drivers/usb/musb/musb_regs.h

   1 /*
   2  * MUSB OTG driver register defines
   3  *
   4  * Copyright 2005 Mentor Graphics Corporation
   5  * Copyright (C) 2005-2006 by Texas Instruments
   6  * Copyright (C) 2006-2007 Nokia Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  25  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34
  35 #ifndef __MUSB_REGS_H__
  36 #define __MUSB_REGS_H__
  37
  38 #define MUSB_EP0_FIFOSIZE       64      /* This is non-configurable */
  39
  40 /*
  41  * MUSB Register bits
  42  */
  43
  44 /* POWER */
  45 #define MUSB_POWER_ISOUPDATE    0x80
  46 #define MUSB_POWER_SOFTCONN     0x40
  47 #define MUSB_POWER_HSENAB       0x20
  48 #define MUSB_POWER_HSMODE       0x10
  49 #define MUSB_POWER_RESET        0x08
  50 #define MUSB_POWER_RESUME       0x04
  51 #define MUSB_POWER_SUSPENDM     0x02
  52 #define MUSB_POWER_ENSUSPEND    0x01
  53
  54 /* INTRUSB */
  55 #define MUSB_INTR_SUSPEND       0x01
  56 #define MUSB_INTR_RESUME        0x02
  57 #define MUSB_INTR_RESET         0x04
  58 #define MUSB_INTR_BABBLE        0x04
  59 #define MUSB_INTR_SOF           0x08
  60 #define MUSB_INTR_CONNECT       0x10
  61 #define MUSB_INTR_DISCONNECT    0x20
  62 #define MUSB_INTR_SESSREQ       0x40
  63 #define MUSB_INTR_VBUSERROR     0x80    /* For SESSION end */
  64
  65 /* DEVCTL */
  66 #define MUSB_DEVCTL_BDEVICE     0x80
  67 #define MUSB_DEVCTL_FSDEV       0x40
  68 #define MUSB_DEVCTL_LSDEV       0x20
  69 #define MUSB_DEVCTL_VBUS        0x18
  70 #define MUSB_DEVCTL_VBUS_SHIFT  3
  71 #define MUSB_DEVCTL_HM          0x04
  72 #define MUSB_DEVCTL_HR          0x02
  73 #define MUSB_DEVCTL_SESSION     0x01
  74
  75 /* MUSB ULPI VBUSCONTROL */
  76 #define MUSB_ULPI_USE_EXTVBUS   0x01
  77 #define MUSB_ULPI_USE_EXTVBUSIND 0x02
  78
  79 /* TESTMODE */
  80 #define MUSB_TEST_FORCE_HOST    0x80
  81 #define MUSB_TEST_FIFO_ACCESS   0x40
  82 #define MUSB_TEST_FORCE_FS      0x20
  83 #define MUSB_TEST_FORCE_HS      0x10
  84 #define MUSB_TEST_PACKET        0x08
  85 #define MUSB_TEST_K             0x04
  86 #define MUSB_TEST_J             0x02
  87 #define MUSB_TEST_SE0_NAK       0x01
  88
  89 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
  90 #define MUSB_FIFOSZ_DPB 0x10
  91 /* Allocation size (8, 16, 32, ... 4096) */
  92 #define MUSB_FIFOSZ_SIZE        0x0f
  93
  94 /* CSR0 */
  95 #define MUSB_CSR0_FLUSHFIFO     0x0100
  96 #define MUSB_CSR0_TXPKTRDY      0x0002
  97 #define MUSB_CSR0_RXPKTRDY      0x0001
  98
  99 /* CSR0 in Peripheral mode */
 100 #define MUSB_CSR0_P_SVDSETUPEND 0x0080
 101 #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
 102 #define MUSB_CSR0_P_SENDSTALL   0x0020
 103 #define MUSB_CSR0_P_SETUPEND    0x0010
 104 #define MUSB_CSR0_P_DATAEND     0x0008
 105 #define MUSB_CSR0_P_SENTSTALL   0x0004
 106
 107 /* CSR0 in Host mode */
 108 #define MUSB_CSR0_H_DIS_PING            0x0800
 109 #define MUSB_CSR0_H_WR_DATATOGGLE       0x0400  /* Set to allow setting: */
 110 #define MUSB_CSR0_H_DATATOGGLE          0x0200  /* Data toggle control */
 111 #define MUSB_CSR0_H_NAKTIMEOUT          0x0080
 112 #define MUSB_CSR0_H_STATUSPKT           0x0040
 113 #define MUSB_CSR0_H_REQPKT              0x0020
 114 #define MUSB_CSR0_H_ERROR               0x0010
 115 #define MUSB_CSR0_H_SETUPPKT            0x0008
 116 #define MUSB_CSR0_H_RXSTALL             0x0004
 117
 118 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
 119 #define MUSB_CSR0_P_WZC_BITS    \
 120         (MUSB_CSR0_P_SENTSTALL)
 121 #define MUSB_CSR0_H_WZC_BITS    \
 122         (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
 123         | MUSB_CSR0_RXPKTRDY)
 124
 125 /* TxType/RxType */
 126 #define MUSB_TYPE_SPEED         0xc0
 127 #define MUSB_TYPE_SPEED_SHIFT   6
 128 #define MUSB_TYPE_PROTO         0x30    /* Implicitly zero for ep0 */
 129 #define MUSB_TYPE_PROTO_SHIFT   4
 130 #define MUSB_TYPE_REMOTE_END    0xf     /* Implicitly zero for ep0 */
 131
 132 /* CONFIGDATA */
 133 #define MUSB_CONFIGDATA_MPRXE           0x80    /* Auto bulk pkt combining */
 134 #define MUSB_CONFIGDATA_MPTXE           0x40    /* Auto bulk pkt splitting */
 135 #define MUSB_CONFIGDATA_BIGENDIAN       0x20
 136 #define MUSB_CONFIGDATA_HBRXE           0x10    /* HB-ISO for RX */
 137 #define MUSB_CONFIGDATA_HBTXE           0x08    /* HB-ISO for TX */
 138 #define MUSB_CONFIGDATA_DYNFIFO         0x04    /* Dynamic FIFO sizing */
 139 #define MUSB_CONFIGDATA_SOFTCONE        0x02    /* SoftConnect */
 140 #define MUSB_CONFIGDATA_UTMIDW          0x01    /* Data width 0/1 => 8/16bits */
 141
 142 /* TXCSR in Peripheral and Host mode */
 143 #define MUSB_TXCSR_AUTOSET              0x8000
 144 #define MUSB_TXCSR_DMAENAB              0x1000
 145 #define MUSB_TXCSR_FRCDATATOG           0x0800
 146 #define MUSB_TXCSR_DMAMODE              0x0400
 147 #define MUSB_TXCSR_CLRDATATOG           0x0040
 148 #define MUSB_TXCSR_FLUSHFIFO            0x0008
 149 #define MUSB_TXCSR_FIFONOTEMPTY         0x0002
 150 #define MUSB_TXCSR_TXPKTRDY             0x0001
 151
 152 /* TXCSR in Peripheral mode */
 153 #define MUSB_TXCSR_P_ISO                0x4000
 154 #define MUSB_TXCSR_P_INCOMPTX           0x0080
 155 #define MUSB_TXCSR_P_SENTSTALL          0x0020
 156 #define MUSB_TXCSR_P_SENDSTALL          0x0010
 157 #define MUSB_TXCSR_P_UNDERRUN           0x0004
 158
 159 /* TXCSR in Host mode */
 160 #define MUSB_TXCSR_H_WR_DATATOGGLE      0x0200
 161 #define MUSB_TXCSR_H_DATATOGGLE         0x0100
 162 #define MUSB_TXCSR_H_NAKTIMEOUT         0x0080
 163 #define MUSB_TXCSR_H_RXSTALL            0x0020
 164 #define MUSB_TXCSR_H_ERROR              0x0004
 165
 166 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
 167 #define MUSB_TXCSR_P_WZC_BITS   \
 168         (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
 169         | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
 170 #define MUSB_TXCSR_H_WZC_BITS   \
 171         (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
 172         | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
 173
 174 /* RXCSR in Peripheral and Host mode */
 175 #define MUSB_RXCSR_AUTOCLEAR            0x8000
 176 #define MUSB_RXCSR_DMAENAB              0x2000
 177 #define MUSB_RXCSR_DISNYET              0x1000
 178 #define MUSB_RXCSR_PID_ERR              0x1000
 179 #define MUSB_RXCSR_DMAMODE              0x0800
 180 #define MUSB_RXCSR_INCOMPRX             0x0100
 181 #define MUSB_RXCSR_CLRDATATOG           0x0080
 182 #define MUSB_RXCSR_FLUSHFIFO            0x0010
 183 #define MUSB_RXCSR_DATAERROR            0x0008
 184 #define MUSB_RXCSR_FIFOFULL             0x0002
 185 #define MUSB_RXCSR_RXPKTRDY             0x0001
 186
 187 /* RXCSR in Peripheral mode */
 188 #define MUSB_RXCSR_P_ISO                0x4000
 189 #define MUSB_RXCSR_P_SENTSTALL          0x0040
 190 #define MUSB_RXCSR_P_SENDSTALL          0x0020
 191 #define MUSB_RXCSR_P_OVERRUN            0x0004
 192
 193 /* RXCSR in Host mode */
 194 #define MUSB_RXCSR_H_AUTOREQ            0x4000
 195 #define MUSB_RXCSR_H_WR_DATATOGGLE      0x0400
 196 #define MUSB_RXCSR_H_DATATOGGLE         0x0200
 197 #define MUSB_RXCSR_H_RXSTALL            0x0040
 198 #define MUSB_RXCSR_H_REQPKT             0x0020
 199 #define MUSB_RXCSR_H_ERROR              0x0004
 200
 201 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
 202 #define MUSB_RXCSR_P_WZC_BITS   \
 203         (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
 204         | MUSB_RXCSR_RXPKTRDY)
 205 #define MUSB_RXCSR_H_WZC_BITS   \
 206         (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
 207         | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
 208
 209 /* HUBADDR */
 210 #define MUSB_HUBADDR_MULTI_TT           0x80
 211
 212
 213 #ifndef CONFIG_BLACKFIN
 214
 215 /*
 216  * Common USB registers
 217  */
 218
 219 #define MUSB_FADDR              0x00    /* 8-bit */
 220 #define MUSB_POWER              0x01    /* 8-bit */
 221
 222 #define MUSB_INTRTX             0x02    /* 16-bit */
 223 #define MUSB_INTRRX             0x04
 224 #define MUSB_INTRTXE            0x06
 225 #define MUSB_INTRRXE            0x08
 226 #define MUSB_INTRUSB            0x0A    /* 8 bit */
 227 #define MUSB_INTRUSBE           0x0B    /* 8 bit */
 228 #define MUSB_FRAME              0x0C
 229 #define MUSB_INDEX              0x0E    /* 8 bit */
 230 #define MUSB_TESTMODE           0x0F    /* 8 bit */
 231
 232 /* Get offset for a given FIFO from musb->mregs */
 233 #ifdef  CONFIG_USB_TUSB6010
 234 #define MUSB_FIFO_OFFSET(epnum) (0x200 + ((epnum) * 0x20))
 235 #else
 236 #define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4))
 237 #endif
 238
 239 /*
 240  * Additional Control Registers
 241  */
 242
 243 #define MUSB_DEVCTL             0x60    /* 8 bit */
 244
 245 /* These are always controlled through the INDEX register */
 246 #define MUSB_TXFIFOSZ           0x62    /* 8-bit (see masks) */
 247 #define MUSB_RXFIFOSZ           0x63    /* 8-bit (see masks) */
 248 #define MUSB_TXFIFOADD          0x64    /* 16-bit offset shifted right 3 */
 249 #define MUSB_RXFIFOADD          0x66    /* 16-bit offset shifted right 3 */
 250
 251 /* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
 252 #define MUSB_HWVERS             0x6C    /* 8 bit */
 253 #define MUSB_ULPI_BUSCONTROL    0x70    /* 8 bit */
 254
 255 #define MUSB_EPINFO             0x78    /* 8 bit */
 256 #define MUSB_RAMINFO            0x79    /* 8 bit */
 257 #define MUSB_LINKINFO           0x7a    /* 8 bit */
 258 #define MUSB_VPLEN              0x7b    /* 8 bit */
 259 #define MUSB_HS_EOF1            0x7c    /* 8 bit */
 260 #define MUSB_FS_EOF1            0x7d    /* 8 bit */
 261 #define MUSB_LS_EOF1            0x7e    /* 8 bit */
 262
 263 /* Offsets to endpoint registers */
 264 #define MUSB_TXMAXP             0x00
 265 #define MUSB_TXCSR              0x02
 266 #define MUSB_CSR0               MUSB_TXCSR      /* Re-used for EP0 */
 267 #define MUSB_RXMAXP             0x04
 268 #define MUSB_RXCSR              0x06
 269 #define MUSB_RXCOUNT            0x08
 270 #define MUSB_COUNT0             MUSB_RXCOUNT    /* Re-used for EP0 */
 271 #define MUSB_TXTYPE             0x0A
 272 #define MUSB_TYPE0              MUSB_TXTYPE     /* Re-used for EP0 */
 273 #define MUSB_TXINTERVAL         0x0B
 274 #define MUSB_NAKLIMIT0          MUSB_TXINTERVAL /* Re-used for EP0 */
 275 #define MUSB_RXTYPE             0x0C
 276 #define MUSB_RXINTERVAL         0x0D
 277 #define MUSB_FIFOSIZE           0x0F
 278 #define MUSB_CONFIGDATA         MUSB_FIFOSIZE   /* Re-used for EP0 */
 279
 280 /* Offsets to endpoint registers in indexed model (using INDEX register) */
 281 #define MUSB_INDEXED_OFFSET(_epnum, _offset)    \
 282         (0x10 + (_offset))
 283
 284 /* Offsets to endpoint registers in flat models */
 285 #define MUSB_FLAT_OFFSET(_epnum, _offset)       \
 286         (0x100 + (0x10*(_epnum)) + (_offset))
 287
 288 #ifdef CONFIG_USB_TUSB6010
 289 /* TUSB6010 EP0 configuration register is special */
 290 #define MUSB_TUSB_OFFSET(_epnum, _offset)       \
 291         (0x10 + _offset)
 292 #include "tusb6010.h"           /* Needed "only" for TUSB_EP0_CONF */
 293 #endif
 294
 295 #define MUSB_TXCSR_MODE                 0x2000
 296
 297 /* "bus control"/target registers, for host side multipoint (external hubs) */
 298 #define MUSB_TXFUNCADDR         0x00
 299 #define MUSB_TXHUBADDR          0x02
 300 #define MUSB_TXHUBPORT          0x03
 301
 302 #define MUSB_RXFUNCADDR         0x04
 303 #define MUSB_RXHUBADDR          0x06
 304 #define MUSB_RXHUBPORT          0x07
 305
 306 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
 307         (0x80 + (8*(_epnum)) + (_offset))
 308
 309 static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
 310 {
 311         musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
 312 }
 313
 314 static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
 315 {
 316         musb_writew(mbase, MUSB_TXFIFOADD, c_off);
 317 }
 318
 319 static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
 320 {
 321         musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
 322 }
 323
 324 static inline void  musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
 325 {
 326         musb_writew(mbase, MUSB_RXFIFOADD, c_off);
 327 }
 328
 329 static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
 330 {
 331         musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val);
 332 }
 333
 334 static inline u8 musb_read_txfifosz(void __iomem *mbase)
 335 {
 336         return musb_readb(mbase, MUSB_TXFIFOSZ);
 337 }
 338
 339 static inline u16 musb_read_txfifoadd(void __iomem *mbase)
 340 {
 341         return musb_readw(mbase, MUSB_TXFIFOADD);
 342 }
 343
 344 static inline u8 musb_read_rxfifosz(void __iomem *mbase)
 345 {
 346         return musb_readb(mbase, MUSB_RXFIFOSZ);
 347 }
 348
 349 static inline u16  musb_read_rxfifoadd(void __iomem *mbase)
 350 {
 351         return musb_readw(mbase, MUSB_RXFIFOADD);
 352 }
 353
 354 static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
 355 {
 356         return musb_readb(mbase, MUSB_ULPI_BUSCONTROL);
 357 }
 358
 359 static inline u8 musb_read_configdata(void __iomem *mbase)
 360 {
 361         musb_writeb(mbase, MUSB_INDEX, 0);
 362         return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
 363 }
 364
 365 static inline u16 musb_read_hwvers(void __iomem *mbase)
 366 {
 367         return musb_readw(mbase, MUSB_HWVERS);
 368 }
 369
 370 static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
 371 {
 372         return (MUSB_BUSCTL_OFFSET(i, 0) + mbase);
 373 }
 374
 375 static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
 376                 u8 qh_addr_reg)
 377 {
 378         musb_writeb(ep_target_regs, MUSB_RXFUNCADDR, qh_addr_reg);
 379 }
 380
 381 static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
 382                 u8 qh_h_addr_reg)
 383 {
 384         musb_writeb(ep_target_regs, MUSB_RXHUBADDR, qh_h_addr_reg);
 385 }
 386
 387 static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
 388                 u8 qh_h_port_reg)
 389 {
 390         musb_writeb(ep_target_regs, MUSB_RXHUBPORT, qh_h_port_reg);
 391 }
 392
 393 static inline void  musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
 394                 u8 qh_addr_reg)
 395 {
 396         musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR),
 397                         qh_addr_reg);
 398 }
 399
 400 static inline void  musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
 401                 u8 qh_addr_reg)
 402 {
 403         musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR),
 404                         qh_addr_reg);
 405 }
 406
 407 static inline void  musb_write_txhubport(void __iomem *mbase, u8 epnum,
 408                 u8 qh_h_port_reg)
 409 {
 410         musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT),
 411                         qh_h_port_reg);
 412 }
 413
 414 static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
 415 {
 416         return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXFUNCADDR));
 417 }
 418
 419 static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
 420 {
 421         return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBADDR));
 422 }
 423
 424 static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
 425 {
 426         return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBPORT));
 427 }
 428
 429 static inline u8  musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
 430 {
 431         return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR));
 432 }
 433
 434 static inline u8  musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
 435 {
 436         return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR));
 437 }
 438
 439 static inline u8  musb_read_txhubport(void __iomem *mbase, u8 epnum)
 440 {
 441         return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT));
 442 }
 443
 444 #else /* CONFIG_BLACKFIN */
 445
 446 #define USB_BASE                USB_FADDR
 447 #define USB_OFFSET(reg)         (reg - USB_BASE)
 448
 449 /*
 450  * Common USB registers
 451  */
 452 #define MUSB_FADDR              USB_OFFSET(USB_FADDR)   /* 8-bit */
 453 #define MUSB_POWER              USB_OFFSET(USB_POWER)   /* 8-bit */
 454 #define MUSB_INTRTX             USB_OFFSET(USB_INTRTX)  /* 16-bit */
 455 #define MUSB_INTRRX             USB_OFFSET(USB_INTRRX)
 456 #define MUSB_INTRTXE            USB_OFFSET(USB_INTRTXE)
 457 #define MUSB_INTRRXE            USB_OFFSET(USB_INTRRXE)
 458 #define MUSB_INTRUSB            USB_OFFSET(USB_INTRUSB) /* 8 bit */
 459 #define MUSB_INTRUSBE           USB_OFFSET(USB_INTRUSBE)/* 8 bit */
 460 #define MUSB_FRAME              USB_OFFSET(USB_FRAME)
 461 #define MUSB_INDEX              USB_OFFSET(USB_INDEX)   /* 8 bit */
 462 #define MUSB_TESTMODE           USB_OFFSET(USB_TESTMODE)/* 8 bit */
 463
 464 /* Get offset for a given FIFO from musb->mregs */
 465 #define MUSB_FIFO_OFFSET(epnum) \
 466         (USB_OFFSET(USB_EP0_FIFO) + ((epnum) * 8))
 467
 468 /*
 469  * Additional Control Registers
 470  */
 471
 472 #define MUSB_DEVCTL             USB_OFFSET(USB_OTG_DEV_CTL)     /* 8 bit */
 473
 474 #define MUSB_LINKINFO           USB_OFFSET(USB_LINKINFO)/* 8 bit */
 475 #define MUSB_VPLEN              USB_OFFSET(USB_VPLEN)   /* 8 bit */
 476 #define MUSB_HS_EOF1            USB_OFFSET(USB_HS_EOF1) /* 8 bit */
 477 #define MUSB_FS_EOF1            USB_OFFSET(USB_FS_EOF1) /* 8 bit */
 478 #define MUSB_LS_EOF1            USB_OFFSET(USB_LS_EOF1) /* 8 bit */
 479
 480 /* Offsets to endpoint registers */
 481 #define MUSB_TXMAXP             0x00
 482 #define MUSB_TXCSR              0x04
 483 #define MUSB_CSR0               MUSB_TXCSR      /* Re-used for EP0 */
 484 #define MUSB_RXMAXP             0x08
 485 #define MUSB_RXCSR              0x0C
 486 #define MUSB_RXCOUNT            0x10
 487 #define MUSB_COUNT0             MUSB_RXCOUNT    /* Re-used for EP0 */
 488 #define MUSB_TXTYPE             0x14
 489 #define MUSB_TYPE0              MUSB_TXTYPE     /* Re-used for EP0 */
 490 #define MUSB_TXINTERVAL         0x18
 491 #define MUSB_NAKLIMIT0          MUSB_TXINTERVAL /* Re-used for EP0 */
 492 #define MUSB_RXTYPE             0x1C
 493 #define MUSB_RXINTERVAL         0x20
 494 #define MUSB_TXCOUNT            0x28
 495
 496 /* Offsets to endpoint registers in indexed model (using INDEX register) */
 497 #define MUSB_INDEXED_OFFSET(_epnum, _offset)    \
 498         (0x40 + (_offset))
 499
 500 /* Offsets to endpoint registers in flat models */
 501 #define MUSB_FLAT_OFFSET(_epnum, _offset)       \
 502         (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
 503
 504 /* Not implemented - HW has separate Tx/Rx FIFO */
 505 #define MUSB_TXCSR_MODE                 0x0000
 506
 507 static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
 508 {
 509 }
 510
 511 static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
 512 {
 513 }
 514
 515 static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
 516 {
 517 }
 518
 519 static inline void  musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
 520 {
 521 }
 522
 523 static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
 524 {
 525 }
 526
 527 static inline u8 musb_read_txfifosz(void __iomem *mbase)
 528 {
 529         return 0;
 530 }
 531
 532 static inline u16 musb_read_txfifoadd(void __iomem *mbase)
 533 {
 534         return 0;
 535 }
 536
 537 static inline u8 musb_read_rxfifosz(void __iomem *mbase)
 538 {
 539         return 0;
 540 }
 541
 542 static inline u16  musb_read_rxfifoadd(void __iomem *mbase)
 543 {
 544         return 0;
 545 }
 546
 547 static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
 548 {
 549         return 0;
 550 }
 551
 552 static inline u8 musb_read_configdata(void __iomem *mbase)
 553 {
 554         return 0;
 555 }
 556
 557 static inline u16 musb_read_hwvers(void __iomem *mbase)
 558 {
 559         /*
 560          * This register is invisible on Blackfin, actually the MUSB
 561          * RTL version of Blackfin is 1.9, so just harcode its value.
 562          */
 563         return MUSB_HWVERS_1900;
 564 }
 565
 566 static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
 567 {
 568         return NULL;
 569 }
 570
 571 static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
 572                 u8 qh_addr_req)
 573 {
 574 }
 575
 576 static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
 577                 u8 qh_h_addr_reg)
 578 {
 579 }
 580
 581 static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
 582                 u8 qh_h_port_reg)
 583 {
 584 }
 585
 586 static inline void  musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
 587                 u8 qh_addr_reg)
 588 {
 589 }
 590
 591 static inline void  musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
 592                 u8 qh_addr_reg)
 593 {
 594 }
 595
 596 static inline void  musb_write_txhubport(void __iomem *mbase, u8 epnum,
 597                 u8 qh_h_port_reg)
 598 {
 599 }
 600
 601 static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
 602 {
 603         return 0;
 604 }
 605
 606 static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
 607 {
 608         return 0;
 609 }
 610
 611 static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
 612 {
 613         return 0;
 614 }
 615
 616 static inline u8  musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
 617 {
 618         return 0;
 619 }
 620
 621 static inline u8  musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
 622 {
 623         return 0;
 624 }
 625
 626 static inline void  musb_read_txhubport(void __iomem *mbase, u8 epnum)
 627 {
 628 }
 629
 630 #endif /* CONFIG_BLACKFIN */
 631
 632 #endif  /* __MUSB_REGS_H__ */