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x86, ioapic: Fix io_apic_redir_entries to return the number of entries.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / serial / mpc52xx_uart.c
bloba176ab4bd65bbf638c7bf81157d6e9d0aa5a4352
1 /*
2 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
3 *
4 * FIXME According to the usermanual the status bits in the status register
5 * are only updated when the peripherals access the FIFO and not when the
6 * CPU access them. So since we use this bits to know when we stop writing
7 * and reading, they may not be updated in-time and a race condition may
8 * exists. But I haven't be able to prove this and I don't care. But if
9 * any problem arises, it might worth checking. The TX/RX FIFO Stats
10 * registers should be used in addition.
11 * Update: Actually, they seem updated ... At least the bits we use.
12 *
13 *
14 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
15 *
16 * Some of the code has been inspired/copied from the 2.4 code written
17 * by Dale Farnsworth <dfarnsworth@mvista.com>.
18 *
19 * Copyright (C) 2008 Freescale Semiconductor Inc.
20 * John Rigby <jrigby@gmail.com>
21 * Added support for MPC5121
22 * Copyright (C) 2006 Secret Lab Technologies Ltd.
23 * Grant Likely <grant.likely@secretlab.ca>
24 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
25 * Copyright (C) 2003 MontaVista, Software, Inc.
26 *
27 * This file is licensed under the terms of the GNU General Public License
28 * version 2. This program is licensed "as is" without any warranty of any
29 * kind, whether express or implied.
30 */
31
32 #undef DEBUG
33
34 #include <linux/device.h>
35 #include <linux/module.h>
36 #include <linux/tty.h>
37 #include <linux/serial.h>
38 #include <linux/sysrq.h>
39 #include <linux/console.h>
40 #include <linux/delay.h>
41 #include <linux/io.h>
42 #include <linux/of.h>
43 #include <linux/of_platform.h>
44 #include <linux/clk.h>
45
46 #include <asm/mpc52xx.h>
47 #include <asm/mpc52xx_psc.h>
48
49 #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
50 #define SUPPORT_SYSRQ
51 #endif
52
53 #include <linux/serial_core.h>
54
55
56 /* We've been assigned a range on the "Low-density serial ports" major */
57 #define SERIAL_PSC_MAJOR 204
58 #define SERIAL_PSC_MINOR 148
59
60
61 #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
62
63
64 static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
65 /* Rem: - We use the read_status_mask as a shadow of
66 * psc->mpc52xx_psc_imr
67 * - It's important that is array is all zero on start as we
68 * use it to know if it's initialized or not ! If it's not sure
69 * it's cleared, then a memset(...,0,...) should be added to
70 * the console_init
71 */
72
73 /* lookup table for matching device nodes to index numbers */
74 static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
75
76 static void mpc52xx_uart_of_enumerate(void);
77
78
79 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
80
81
82 /* Forward declaration of the interruption handling routine */
83 static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
84 static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
85
86
87 /* Simple macro to test if a port is console or not. This one is taken
88 * for serial_core.c and maybe should be moved to serial_core.h ? */
89 #ifdef CONFIG_SERIAL_CORE_CONSOLE
90 #define uart_console(port) \
91 ((port)->cons && (port)->cons->index == (port)->line)
92 #else
93 #define uart_console(port) (0)
94 #endif
95
96 /* ======================================================================== */
97 /* PSC fifo operations for isolating differences between 52xx and 512x */
98 /* ======================================================================== */
99
100 struct psc_ops {
101 void (*fifo_init)(struct uart_port *port);
102 int (*raw_rx_rdy)(struct uart_port *port);
103 int (*raw_tx_rdy)(struct uart_port *port);
104 int (*rx_rdy)(struct uart_port *port);
105 int (*tx_rdy)(struct uart_port *port);
106 int (*tx_empty)(struct uart_port *port);
107 void (*stop_rx)(struct uart_port *port);
108 void (*start_tx)(struct uart_port *port);
109 void (*stop_tx)(struct uart_port *port);
110 void (*rx_clr_irq)(struct uart_port *port);
111 void (*tx_clr_irq)(struct uart_port *port);
112 void (*write_char)(struct uart_port *port, unsigned char c);
113 unsigned char (*read_char)(struct uart_port *port);
114 void (*cw_disable_ints)(struct uart_port *port);
115 void (*cw_restore_ints)(struct uart_port *port);
116 unsigned long (*getuartclk)(void *p);
117 int (*clock)(struct uart_port *port, int enable);
118 int (*fifoc_init)(void);
119 void (*fifoc_uninit)(void);
120 void (*get_irq)(struct uart_port *, struct device_node *);
121 irqreturn_t (*handle_irq)(struct uart_port *port);
122 };
123
124 #ifdef CONFIG_PPC_MPC52xx
125 #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
126 static void mpc52xx_psc_fifo_init(struct uart_port *port)
127 {
128 struct mpc52xx_psc __iomem *psc = PSC(port);
129 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
130
131 /* /32 prescaler */
132 out_be16(&psc->mpc52xx_psc_clock_select, 0xdd00);
133
134 out_8(&fifo->rfcntl, 0x00);
135 out_be16(&fifo->rfalarm, 0x1ff);
136 out_8(&fifo->tfcntl, 0x07);
137 out_be16(&fifo->tfalarm, 0x80);
138
139 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
140 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
141 }
142
143 static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
144 {
145 return in_be16(&PSC(port)->mpc52xx_psc_status)
146 & MPC52xx_PSC_SR_RXRDY;
147 }
148
149 static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
150 {
151 return in_be16(&PSC(port)->mpc52xx_psc_status)
152 & MPC52xx_PSC_SR_TXRDY;
153 }
154
155
156 static int mpc52xx_psc_rx_rdy(struct uart_port *port)
157 {
158 return in_be16(&PSC(port)->mpc52xx_psc_isr)
159 & port->read_status_mask
160 & MPC52xx_PSC_IMR_RXRDY;
161 }
162
163 static int mpc52xx_psc_tx_rdy(struct uart_port *port)
164 {
165 return in_be16(&PSC(port)->mpc52xx_psc_isr)
166 & port->read_status_mask
167 & MPC52xx_PSC_IMR_TXRDY;
168 }
169
170 static int mpc52xx_psc_tx_empty(struct uart_port *port)
171 {
172 return in_be16(&PSC(port)->mpc52xx_psc_status)
173 & MPC52xx_PSC_SR_TXEMP;
174 }
175
176 static void mpc52xx_psc_start_tx(struct uart_port *port)
177 {
178 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
179 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
180 }
181
182 static void mpc52xx_psc_stop_tx(struct uart_port *port)
183 {
184 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
185 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
186 }
187
188 static void mpc52xx_psc_stop_rx(struct uart_port *port)
189 {
190 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
191 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
192 }
193
194 static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
195 {
196 }
197
198 static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
199 {
200 }
201
202 static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
203 {
204 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
205 }
206
207 static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
208 {
209 return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
210 }
211
212 static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
213 {
214 out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
215 }
216
217 static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
218 {
219 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
220 }
221
222 /* Search for bus-frequency property in this node or a parent */
223 static unsigned long mpc52xx_getuartclk(void *p)
224 {
225 /*
226 * 5200 UARTs have a / 32 prescaler
227 * but the generic serial code assumes 16
228 * so return ipb freq / 2
229 */
230 return mpc5xxx_get_bus_frequency(p) / 2;
231 }
232
233 static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
234 {
235 port->irqflags = IRQF_DISABLED;
236 port->irq = irq_of_parse_and_map(np, 0);
237 }
238
239 /* 52xx specific interrupt handler. The caller holds the port lock */
240 static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
241 {
242 return mpc5xxx_uart_process_int(port);
243 }
244
245 static struct psc_ops mpc52xx_psc_ops = {
246 .fifo_init = mpc52xx_psc_fifo_init,
247 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
248 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
249 .rx_rdy = mpc52xx_psc_rx_rdy,
250 .tx_rdy = mpc52xx_psc_tx_rdy,
251 .tx_empty = mpc52xx_psc_tx_empty,
252 .stop_rx = mpc52xx_psc_stop_rx,
253 .start_tx = mpc52xx_psc_start_tx,
254 .stop_tx = mpc52xx_psc_stop_tx,
255 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
256 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
257 .write_char = mpc52xx_psc_write_char,
258 .read_char = mpc52xx_psc_read_char,
259 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
260 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
261 .getuartclk = mpc52xx_getuartclk,
262 .get_irq = mpc52xx_psc_get_irq,
263 .handle_irq = mpc52xx_psc_handle_irq,
264 };
265
266 #endif /* CONFIG_MPC52xx */
267
268 #ifdef CONFIG_PPC_MPC512x
269 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
270
271 /* PSC FIFO Controller for mpc512x */
272 struct psc_fifoc {
273 u32 fifoc_cmd;
274 u32 fifoc_int;
275 u32 fifoc_dma;
276 u32 fifoc_axe;
277 u32 fifoc_debug;
278 };
279
280 static struct psc_fifoc __iomem *psc_fifoc;
281 static unsigned int psc_fifoc_irq;
282
283 static void mpc512x_psc_fifo_init(struct uart_port *port)
284 {
285 /* /32 prescaler */
286 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
287
288 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
289 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
290 out_be32(&FIFO_512x(port)->txalarm, 1);
291 out_be32(&FIFO_512x(port)->tximr, 0);
292
293 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
294 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
295 out_be32(&FIFO_512x(port)->rxalarm, 1);
296 out_be32(&FIFO_512x(port)->rximr, 0);
297
298 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
299 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
300 }
301
302 static int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
303 {
304 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
305 }
306
307 static int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
308 {
309 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
310 }
311
312 static int mpc512x_psc_rx_rdy(struct uart_port *port)
313 {
314 return in_be32(&FIFO_512x(port)->rxsr)
315 & in_be32(&FIFO_512x(port)->rximr)
316 & MPC512x_PSC_FIFO_ALARM;
317 }
318
319 static int mpc512x_psc_tx_rdy(struct uart_port *port)
320 {
321 return in_be32(&FIFO_512x(port)->txsr)
322 & in_be32(&FIFO_512x(port)->tximr)
323 & MPC512x_PSC_FIFO_ALARM;
324 }
325
326 static int mpc512x_psc_tx_empty(struct uart_port *port)
327 {
328 return in_be32(&FIFO_512x(port)->txsr)
329 & MPC512x_PSC_FIFO_EMPTY;
330 }
331
332 static void mpc512x_psc_stop_rx(struct uart_port *port)
333 {
334 unsigned long rx_fifo_imr;
335
336 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
337 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
338 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
339 }
340
341 static void mpc512x_psc_start_tx(struct uart_port *port)
342 {
343 unsigned long tx_fifo_imr;
344
345 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
346 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
347 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
348 }
349
350 static void mpc512x_psc_stop_tx(struct uart_port *port)
351 {
352 unsigned long tx_fifo_imr;
353
354 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
355 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
356 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
357 }
358
359 static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
360 {
361 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
362 }
363
364 static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
365 {
366 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
367 }
368
369 static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
370 {
371 out_8(&FIFO_512x(port)->txdata_8, c);
372 }
373
374 static unsigned char mpc512x_psc_read_char(struct uart_port *port)
375 {
376 return in_8(&FIFO_512x(port)->rxdata_8);
377 }
378
379 static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
380 {
381 port->read_status_mask =
382 in_be32(&FIFO_512x(port)->tximr) << 16 |
383 in_be32(&FIFO_512x(port)->rximr);
384 out_be32(&FIFO_512x(port)->tximr, 0);
385 out_be32(&FIFO_512x(port)->rximr, 0);
386 }
387
388 static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
389 {
390 out_be32(&FIFO_512x(port)->tximr,
391 (port->read_status_mask >> 16) & 0x7f);
392 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
393 }
394
395 static unsigned long mpc512x_getuartclk(void *p)
396 {
397 return mpc5xxx_get_bus_frequency(p);
398 }
399
400 #define DEFAULT_FIFO_SIZE 16
401
402 static unsigned int __init get_fifo_size(struct device_node *np,
403 char *fifo_name)
404 {
405 const unsigned int *fp;
406
407 fp = of_get_property(np, fifo_name, NULL);
408 if (fp)
409 return *fp;
410
411 pr_warning("no %s property in %s node, defaulting to %d\n",
412 fifo_name, np->full_name, DEFAULT_FIFO_SIZE);
413
414 return DEFAULT_FIFO_SIZE;
415 }
416
417 #define FIFOC(_base) ((struct mpc512x_psc_fifo __iomem *) \
418 ((u32)(_base) + sizeof(struct mpc52xx_psc)))
419
420 /* Init PSC FIFO Controller */
421 static int __init mpc512x_psc_fifoc_init(void)
422 {
423 struct device_node *np;
424 void __iomem *psc;
425 unsigned int tx_fifo_size;
426 unsigned int rx_fifo_size;
427 int fifobase = 0; /* current fifo address in 32 bit words */
428
429 np = of_find_compatible_node(NULL, NULL,
430 "fsl,mpc5121-psc-fifo");
431 if (!np) {
432 pr_err("%s: Can't find FIFOC node\n", __func__);
433 return -ENODEV;
434 }
435
436 psc_fifoc = of_iomap(np, 0);
437 if (!psc_fifoc) {
438 pr_err("%s: Can't map FIFOC\n", __func__);
439 return -ENODEV;
440 }
441
442 psc_fifoc_irq = irq_of_parse_and_map(np, 0);
443 of_node_put(np);
444 if (psc_fifoc_irq == NO_IRQ) {
445 pr_err("%s: Can't get FIFOC irq\n", __func__);
446 iounmap(psc_fifoc);
447 return -ENODEV;
448 }
449
450 for_each_compatible_node(np, NULL, "fsl,mpc5121-psc-uart") {
451 tx_fifo_size = get_fifo_size(np, "fsl,tx-fifo-size");
452 rx_fifo_size = get_fifo_size(np, "fsl,rx-fifo-size");
453
454 /* size in register is in 4 byte units */
455 tx_fifo_size /= 4;
456 rx_fifo_size /= 4;
457 if (!tx_fifo_size)
458 tx_fifo_size = 1;
459 if (!rx_fifo_size)
460 rx_fifo_size = 1;
461
462 psc = of_iomap(np, 0);
463 if (!psc) {
464 pr_err("%s: Can't map %s device\n",
465 __func__, np->full_name);
466 continue;
467 }
468
469 /* FIFO space is 4KiB, check if requested size is available */
470 if ((fifobase + tx_fifo_size + rx_fifo_size) > 0x1000) {
471 pr_err("%s: no fifo space available for %s\n",
472 __func__, np->full_name);
473 iounmap(psc);
474 /*
475 * chances are that another device requests less
476 * fifo space, so we continue.
477 */
478 continue;
479 }
480 /* set tx and rx fifo size registers */
481 out_be32(&FIFOC(psc)->txsz, (fifobase << 16) | tx_fifo_size);
482 fifobase += tx_fifo_size;
483 out_be32(&FIFOC(psc)->rxsz, (fifobase << 16) | rx_fifo_size);
484 fifobase += rx_fifo_size;
485
486 /* reset and enable the slices */
487 out_be32(&FIFOC(psc)->txcmd, 0x80);
488 out_be32(&FIFOC(psc)->txcmd, 0x01);
489 out_be32(&FIFOC(psc)->rxcmd, 0x80);
490 out_be32(&FIFOC(psc)->rxcmd, 0x01);
491
492 iounmap(psc);
493 }
494
495 return 0;
496 }
497
498 static void __exit mpc512x_psc_fifoc_uninit(void)
499 {
500 iounmap(psc_fifoc);
501 }
502
503 /* 512x specific interrupt handler. The caller holds the port lock */
504 static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
505 {
506 unsigned long fifoc_int;
507 int psc_num;
508
509 /* Read pending PSC FIFOC interrupts */
510 fifoc_int = in_be32(&psc_fifoc->fifoc_int);
511
512 /* Check if it is an interrupt for this port */
513 psc_num = (port->mapbase & 0xf00) >> 8;
514 if (test_bit(psc_num, &fifoc_int) ||
515 test_bit(psc_num + 16, &fifoc_int))
516 return mpc5xxx_uart_process_int(port);
517
518 return IRQ_NONE;
519 }
520
521 static int mpc512x_psc_clock(struct uart_port *port, int enable)
522 {
523 struct clk *psc_clk;
524 int psc_num;
525 char clk_name[10];
526
527 if (uart_console(port))
528 return 0;
529
530 psc_num = (port->mapbase & 0xf00) >> 8;
531 snprintf(clk_name, sizeof(clk_name), "psc%d_clk", psc_num);
532 psc_clk = clk_get(port->dev, clk_name);
533 if (IS_ERR(psc_clk)) {
534 dev_err(port->dev, "Failed to get PSC clock entry!\n");
535 return -ENODEV;
536 }
537
538 dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis");
539
540 if (enable)
541 clk_enable(psc_clk);
542 else
543 clk_disable(psc_clk);
544
545 return 0;
546 }
547
548 static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
549 {
550 port->irqflags = IRQF_SHARED;
551 port->irq = psc_fifoc_irq;
552 }
553
554 static struct psc_ops mpc512x_psc_ops = {
555 .fifo_init = mpc512x_psc_fifo_init,
556 .raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
557 .raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
558 .rx_rdy = mpc512x_psc_rx_rdy,
559 .tx_rdy = mpc512x_psc_tx_rdy,
560 .tx_empty = mpc512x_psc_tx_empty,
561 .stop_rx = mpc512x_psc_stop_rx,
562 .start_tx = mpc512x_psc_start_tx,
563 .stop_tx = mpc512x_psc_stop_tx,
564 .rx_clr_irq = mpc512x_psc_rx_clr_irq,
565 .tx_clr_irq = mpc512x_psc_tx_clr_irq,
566 .write_char = mpc512x_psc_write_char,
567 .read_char = mpc512x_psc_read_char,
568 .cw_disable_ints = mpc512x_psc_cw_disable_ints,
569 .cw_restore_ints = mpc512x_psc_cw_restore_ints,
570 .getuartclk = mpc512x_getuartclk,
571 .clock = mpc512x_psc_clock,
572 .fifoc_init = mpc512x_psc_fifoc_init,
573 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
574 .get_irq = mpc512x_psc_get_irq,
575 .handle_irq = mpc512x_psc_handle_irq,
576 };
577 #endif
578
579 static struct psc_ops *psc_ops;
580
581 /* ======================================================================== */
582 /* UART operations */
583 /* ======================================================================== */
584
585 static unsigned int
586 mpc52xx_uart_tx_empty(struct uart_port *port)
587 {
588 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
589 }
590
591 static void
592 mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
593 {
594 if (mctrl & TIOCM_RTS)
595 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
596 else
597 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
598 }
599
600 static unsigned int
601 mpc52xx_uart_get_mctrl(struct uart_port *port)
602 {
603 unsigned int ret = TIOCM_DSR;
604 u8 status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
605
606 if (!(status & MPC52xx_PSC_CTS))
607 ret |= TIOCM_CTS;
608 if (!(status & MPC52xx_PSC_DCD))
609 ret |= TIOCM_CAR;
610
611 return ret;
612 }
613
614 static void
615 mpc52xx_uart_stop_tx(struct uart_port *port)
616 {
617 /* port->lock taken by caller */
618 psc_ops->stop_tx(port);
619 }
620
621 static void
622 mpc52xx_uart_start_tx(struct uart_port *port)
623 {
624 /* port->lock taken by caller */
625 psc_ops->start_tx(port);
626 }
627
628 static void
629 mpc52xx_uart_send_xchar(struct uart_port *port, char ch)
630 {
631 unsigned long flags;
632 spin_lock_irqsave(&port->lock, flags);
633
634 port->x_char = ch;
635 if (ch) {
636 /* Make sure tx interrupts are on */
637 /* Truly necessary ??? They should be anyway */
638 psc_ops->start_tx(port);
639 }
640
641 spin_unlock_irqrestore(&port->lock, flags);
642 }
643
644 static void
645 mpc52xx_uart_stop_rx(struct uart_port *port)
646 {
647 /* port->lock taken by caller */
648 psc_ops->stop_rx(port);
649 }
650
651 static void
652 mpc52xx_uart_enable_ms(struct uart_port *port)
653 {
654 struct mpc52xx_psc __iomem *psc = PSC(port);
655
656 /* clear D_*-bits by reading them */
657 in_8(&psc->mpc52xx_psc_ipcr);
658 /* enable CTS and DCD as IPC interrupts */
659 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
660
661 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
662 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
663 }
664
665 static void
666 mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
667 {
668 unsigned long flags;
669 spin_lock_irqsave(&port->lock, flags);
670
671 if (ctl == -1)
672 out_8(&PSC(port)->command, MPC52xx_PSC_START_BRK);
673 else
674 out_8(&PSC(port)->command, MPC52xx_PSC_STOP_BRK);
675
676 spin_unlock_irqrestore(&port->lock, flags);
677 }
678
679 static int
680 mpc52xx_uart_startup(struct uart_port *port)
681 {
682 struct mpc52xx_psc __iomem *psc = PSC(port);
683 int ret;
684
685 if (psc_ops->clock) {
686 ret = psc_ops->clock(port, 1);
687 if (ret)
688 return ret;
689 }
690
691 /* Request IRQ */
692 ret = request_irq(port->irq, mpc52xx_uart_int,
693 port->irqflags, "mpc52xx_psc_uart", port);
694 if (ret)
695 return ret;
696
697 /* Reset/activate the port, clear and enable interrupts */
698 out_8(&psc->command, MPC52xx_PSC_RST_RX);
699 out_8(&psc->command, MPC52xx_PSC_RST_TX);
700
701 out_be32(&psc->sicr, 0); /* UART mode DCD ignored */
702
703 psc_ops->fifo_init(port);
704
705 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
706 out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
707
708 return 0;
709 }
710
711 static void
712 mpc52xx_uart_shutdown(struct uart_port *port)
713 {
714 struct mpc52xx_psc __iomem *psc = PSC(port);
715
716 /* Shut down the port. Leave TX active if on a console port */
717 out_8(&psc->command, MPC52xx_PSC_RST_RX);
718 if (!uart_console(port))
719 out_8(&psc->command, MPC52xx_PSC_RST_TX);
720
721 port->read_status_mask = 0;
722 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
723
724 if (psc_ops->clock)
725 psc_ops->clock(port, 0);
726
727 /* Release interrupt */
728 free_irq(port->irq, port);
729 }
730
731 static void
732 mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
733 struct ktermios *old)
734 {
735 struct mpc52xx_psc __iomem *psc = PSC(port);
736 unsigned long flags;
737 unsigned char mr1, mr2;
738 unsigned short ctr;
739 unsigned int j, baud, quot;
740
741 /* Prepare what we're gonna write */
742 mr1 = 0;
743
744 switch (new->c_cflag & CSIZE) {
745 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
746 break;
747 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
748 break;
749 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
750 break;
751 case CS8:
752 default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
753 }
754
755 if (new->c_cflag & PARENB) {
756 mr1 |= (new->c_cflag & PARODD) ?
757 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
758 } else
759 mr1 |= MPC52xx_PSC_MODE_PARNONE;
760
761
762 mr2 = 0;
763
764 if (new->c_cflag & CSTOPB)
765 mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
766 else
767 mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
768 MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
769 MPC52xx_PSC_MODE_ONE_STOP;
770
771 if (new->c_cflag & CRTSCTS) {
772 mr1 |= MPC52xx_PSC_MODE_RXRTS;
773 mr2 |= MPC52xx_PSC_MODE_TXCTS;
774 }
775
776 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16);
777 quot = uart_get_divisor(port, baud);
778 ctr = quot & 0xffff;
779
780 /* Get the lock */
781 spin_lock_irqsave(&port->lock, flags);
782
783 /* Update the per-port timeout */
784 uart_update_timeout(port, new->c_cflag, baud);
785
786 /* Do our best to flush TX & RX, so we don't lose anything */
787 /* But we don't wait indefinitely ! */
788 j = 5000000; /* Maximum wait */
789 /* FIXME Can't receive chars since set_termios might be called at early
790 * boot for the console, all stuff is not yet ready to receive at that
791 * time and that just makes the kernel oops */
792 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
793 while (!mpc52xx_uart_tx_empty(port) && --j)
794 udelay(1);
795
796 if (!j)
797 printk(KERN_ERR "mpc52xx_uart.c: "
798 "Unable to flush RX & TX fifos in-time in set_termios."
799 "Some chars may have been lost.\n");
800
801 /* Reset the TX & RX */
802 out_8(&psc->command, MPC52xx_PSC_RST_RX);
803 out_8(&psc->command, MPC52xx_PSC_RST_TX);
804
805 /* Send new mode settings */
806 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
807 out_8(&psc->mode, mr1);
808 out_8(&psc->mode, mr2);
809 out_8(&psc->ctur, ctr >> 8);
810 out_8(&psc->ctlr, ctr & 0xff);
811
812 if (UART_ENABLE_MS(port, new->c_cflag))
813 mpc52xx_uart_enable_ms(port);
814
815 /* Reenable TX & RX */
816 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
817 out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
818
819 /* We're all set, release the lock */
820 spin_unlock_irqrestore(&port->lock, flags);
821 }
822
823 static const char *
824 mpc52xx_uart_type(struct uart_port *port)
825 {
826 return port->type == PORT_MPC52xx ? "MPC52xx PSC" : NULL;
827 }
828
829 static void
830 mpc52xx_uart_release_port(struct uart_port *port)
831 {
832 /* remapped by us ? */
833 if (port->flags & UPF_IOREMAP) {
834 iounmap(port->membase);
835 port->membase = NULL;
836 }
837
838 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
839 }
840
841 static int
842 mpc52xx_uart_request_port(struct uart_port *port)
843 {
844 int err;
845
846 if (port->flags & UPF_IOREMAP) /* Need to remap ? */
847 port->membase = ioremap(port->mapbase,
848 sizeof(struct mpc52xx_psc));
849
850 if (!port->membase)
851 return -EINVAL;
852
853 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
854 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
855
856 if (err && (port->flags & UPF_IOREMAP)) {
857 iounmap(port->membase);
858 port->membase = NULL;
859 }
860
861 return err;
862 }
863
864 static void
865 mpc52xx_uart_config_port(struct uart_port *port, int flags)
866 {
867 if ((flags & UART_CONFIG_TYPE)
868 && (mpc52xx_uart_request_port(port) == 0))
869 port->type = PORT_MPC52xx;
870 }
871
872 static int
873 mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
874 {
875 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
876 return -EINVAL;
877
878 if ((ser->irq != port->irq) ||
879 (ser->io_type != UPIO_MEM) ||
880 (ser->baud_base != port->uartclk) ||
881 (ser->iomem_base != (void *)port->mapbase) ||
882 (ser->hub6 != 0))
883 return -EINVAL;
884
885 return 0;
886 }
887
888
889 static struct uart_ops mpc52xx_uart_ops = {
890 .tx_empty = mpc52xx_uart_tx_empty,
891 .set_mctrl = mpc52xx_uart_set_mctrl,
892 .get_mctrl = mpc52xx_uart_get_mctrl,
893 .stop_tx = mpc52xx_uart_stop_tx,
894 .start_tx = mpc52xx_uart_start_tx,
895 .send_xchar = mpc52xx_uart_send_xchar,
896 .stop_rx = mpc52xx_uart_stop_rx,
897 .enable_ms = mpc52xx_uart_enable_ms,
898 .break_ctl = mpc52xx_uart_break_ctl,
899 .startup = mpc52xx_uart_startup,
900 .shutdown = mpc52xx_uart_shutdown,
901 .set_termios = mpc52xx_uart_set_termios,
902 /* .pm = mpc52xx_uart_pm, Not supported yet */
903 /* .set_wake = mpc52xx_uart_set_wake, Not supported yet */
904 .type = mpc52xx_uart_type,
905 .release_port = mpc52xx_uart_release_port,
906 .request_port = mpc52xx_uart_request_port,
907 .config_port = mpc52xx_uart_config_port,
908 .verify_port = mpc52xx_uart_verify_port
909 };
910
911
912 /* ======================================================================== */
913 /* Interrupt handling */
914 /* ======================================================================== */
915
916 static inline int
917 mpc52xx_uart_int_rx_chars(struct uart_port *port)
918 {
919 struct tty_struct *tty = port->state->port.tty;
920 unsigned char ch, flag;
921 unsigned short status;
922
923 /* While we can read, do so ! */
924 while (psc_ops->raw_rx_rdy(port)) {
925 /* Get the char */
926 ch = psc_ops->read_char(port);
927
928 /* Handle sysreq char */
929 #ifdef SUPPORT_SYSRQ
930 if (uart_handle_sysrq_char(port, ch)) {
931 port->sysrq = 0;
932 continue;
933 }
934 #endif
935
936 /* Store it */
937
938 flag = TTY_NORMAL;
939 port->icount.rx++;
940
941 status = in_be16(&PSC(port)->mpc52xx_psc_status);
942
943 if (status & (MPC52xx_PSC_SR_PE |
944 MPC52xx_PSC_SR_FE |
945 MPC52xx_PSC_SR_RB)) {
946
947 if (status & MPC52xx_PSC_SR_RB) {
948 flag = TTY_BREAK;
949 uart_handle_break(port);
950 port->icount.brk++;
951 } else if (status & MPC52xx_PSC_SR_PE) {
952 flag = TTY_PARITY;
953 port->icount.parity++;
954 }
955 else if (status & MPC52xx_PSC_SR_FE) {
956 flag = TTY_FRAME;
957 port->icount.frame++;
958 }
959
960 /* Clear error condition */
961 out_8(&PSC(port)->command, MPC52xx_PSC_RST_ERR_STAT);
962
963 }
964 tty_insert_flip_char(tty, ch, flag);
965 if (status & MPC52xx_PSC_SR_OE) {
966 /*
967 * Overrun is special, since it's
968 * reported immediately, and doesn't
969 * affect the current character
970 */
971 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
972 port->icount.overrun++;
973 }
974 }
975
976 spin_unlock(&port->lock);
977 tty_flip_buffer_push(tty);
978 spin_lock(&port->lock);
979
980 return psc_ops->raw_rx_rdy(port);
981 }
982
983 static inline int
984 mpc52xx_uart_int_tx_chars(struct uart_port *port)
985 {
986 struct circ_buf *xmit = &port->state->xmit;
987
988 /* Process out of band chars */
989 if (port->x_char) {
990 psc_ops->write_char(port, port->x_char);
991 port->icount.tx++;
992 port->x_char = 0;
993 return 1;
994 }
995
996 /* Nothing to do ? */
997 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
998 mpc52xx_uart_stop_tx(port);
999 return 0;
1000 }
1001
1002 /* Send chars */
1003 while (psc_ops->raw_tx_rdy(port)) {
1004 psc_ops->write_char(port, xmit->buf[xmit->tail]);
1005 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1006 port->icount.tx++;
1007 if (uart_circ_empty(xmit))
1008 break;
1009 }
1010
1011 /* Wake up */
1012 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1013 uart_write_wakeup(port);
1014
1015 /* Maybe we're done after all */
1016 if (uart_circ_empty(xmit)) {
1017 mpc52xx_uart_stop_tx(port);
1018 return 0;
1019 }
1020
1021 return 1;
1022 }
1023
1024 static irqreturn_t
1025 mpc5xxx_uart_process_int(struct uart_port *port)
1026 {
1027 unsigned long pass = ISR_PASS_LIMIT;
1028 unsigned int keepgoing;
1029 u8 status;
1030
1031 /* While we have stuff to do, we continue */
1032 do {
1033 /* If we don't find anything to do, we stop */
1034 keepgoing = 0;
1035
1036 psc_ops->rx_clr_irq(port);
1037 if (psc_ops->rx_rdy(port))
1038 keepgoing |= mpc52xx_uart_int_rx_chars(port);
1039
1040 psc_ops->tx_clr_irq(port);
1041 if (psc_ops->tx_rdy(port))
1042 keepgoing |= mpc52xx_uart_int_tx_chars(port);
1043
1044 status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
1045 if (status & MPC52xx_PSC_D_DCD)
1046 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
1047
1048 if (status & MPC52xx_PSC_D_CTS)
1049 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
1050
1051 /* Limit number of iteration */
1052 if (!(--pass))
1053 keepgoing = 0;
1054
1055 } while (keepgoing);
1056
1057 return IRQ_HANDLED;
1058 }
1059
1060 static irqreturn_t
1061 mpc52xx_uart_int(int irq, void *dev_id)
1062 {
1063 struct uart_port *port = dev_id;
1064 irqreturn_t ret;
1065
1066 spin_lock(&port->lock);
1067
1068 ret = psc_ops->handle_irq(port);
1069
1070 spin_unlock(&port->lock);
1071
1072 return ret;
1073 }
1074
1075 /* ======================================================================== */
1076 /* Console ( if applicable ) */
1077 /* ======================================================================== */
1078
1079 #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
1080
1081 static void __init
1082 mpc52xx_console_get_options(struct uart_port *port,
1083 int *baud, int *parity, int *bits, int *flow)
1084 {
1085 struct mpc52xx_psc __iomem *psc = PSC(port);
1086 unsigned char mr1;
1087
1088 pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
1089
1090 /* Read the mode registers */
1091 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
1092 mr1 = in_8(&psc->mode);
1093
1094 /* CT{U,L}R are write-only ! */
1095 *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1096
1097 /* Parse them */
1098 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
1099 case MPC52xx_PSC_MODE_5_BITS:
1100 *bits = 5;
1101 break;
1102 case MPC52xx_PSC_MODE_6_BITS:
1103 *bits = 6;
1104 break;
1105 case MPC52xx_PSC_MODE_7_BITS:
1106 *bits = 7;
1107 break;
1108 case MPC52xx_PSC_MODE_8_BITS:
1109 default:
1110 *bits = 8;
1111 }
1112
1113 if (mr1 & MPC52xx_PSC_MODE_PARNONE)
1114 *parity = 'n';
1115 else
1116 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
1117 }
1118
1119 static void
1120 mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
1121 {
1122 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1123 unsigned int i, j;
1124
1125 /* Disable interrupts */
1126 psc_ops->cw_disable_ints(port);
1127
1128 /* Wait the TX buffer to be empty */
1129 j = 5000000; /* Maximum wait */
1130 while (!mpc52xx_uart_tx_empty(port) && --j)
1131 udelay(1);
1132
1133 /* Write all the chars */
1134 for (i = 0; i < count; i++, s++) {
1135 /* Line return handling */
1136 if (*s == '\n')
1137 psc_ops->write_char(port, '\r');
1138
1139 /* Send the char */
1140 psc_ops->write_char(port, *s);
1141
1142 /* Wait the TX buffer to be empty */
1143 j = 20000; /* Maximum wait */
1144 while (!mpc52xx_uart_tx_empty(port) && --j)
1145 udelay(1);
1146 }
1147
1148 /* Restore interrupt state */
1149 psc_ops->cw_restore_ints(port);
1150 }
1151
1152
1153 static int __init
1154 mpc52xx_console_setup(struct console *co, char *options)
1155 {
1156 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1157 struct device_node *np = mpc52xx_uart_nodes[co->index];
1158 unsigned int uartclk;
1159 struct resource res;
1160 int ret;
1161
1162 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1163 int bits = 8;
1164 int parity = 'n';
1165 int flow = 'n';
1166
1167 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
1168 co, co->index, options);
1169
1170 if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) {
1171 pr_debug("PSC%x out of range\n", co->index);
1172 return -EINVAL;
1173 }
1174
1175 if (!np) {
1176 pr_debug("PSC%x not found in device tree\n", co->index);
1177 return -EINVAL;
1178 }
1179
1180 pr_debug("Console on ttyPSC%x is %s\n",
1181 co->index, mpc52xx_uart_nodes[co->index]->full_name);
1182
1183 /* Fetch register locations */
1184 ret = of_address_to_resource(np, 0, &res);
1185 if (ret) {
1186 pr_debug("Could not get resources for PSC%x\n", co->index);
1187 return ret;
1188 }
1189
1190 uartclk = psc_ops->getuartclk(np);
1191 if (uartclk == 0) {
1192 pr_debug("Could not find uart clock frequency!\n");
1193 return -EINVAL;
1194 }
1195
1196 /* Basic port init. Needed since we use some uart_??? func before
1197 * real init for early access */
1198 spin_lock_init(&port->lock);
1199 port->uartclk = uartclk;
1200 port->ops = &mpc52xx_uart_ops;
1201 port->mapbase = res.start;
1202 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
1203 port->irq = irq_of_parse_and_map(np, 0);
1204
1205 if (port->membase == NULL)
1206 return -EINVAL;
1207
1208 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1209 (void *)port->mapbase, port->membase,
1210 port->irq, port->uartclk);
1211
1212 /* Setup the port parameters accoding to options */
1213 if (options)
1214 uart_parse_options(options, &baud, &parity, &bits, &flow);
1215 else
1216 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
1217
1218 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
1219 baud, bits, parity, flow);
1220
1221 return uart_set_options(port, co, baud, parity, bits, flow);
1222 }
1223
1224
1225 static struct uart_driver mpc52xx_uart_driver;
1226
1227 static struct console mpc52xx_console = {
1228 .name = "ttyPSC",
1229 .write = mpc52xx_console_write,
1230 .device = uart_console_device,
1231 .setup = mpc52xx_console_setup,
1232 .flags = CON_PRINTBUFFER,
1233 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */
1234 .data = &mpc52xx_uart_driver,
1235 };
1236
1237
1238 static int __init
1239 mpc52xx_console_init(void)
1240 {
1241 mpc52xx_uart_of_enumerate();
1242 register_console(&mpc52xx_console);
1243 return 0;
1244 }
1245
1246 console_initcall(mpc52xx_console_init);
1247
1248 #define MPC52xx_PSC_CONSOLE &mpc52xx_console
1249 #else
1250 #define MPC52xx_PSC_CONSOLE NULL
1251 #endif
1252
1253
1254 /* ======================================================================== */
1255 /* UART Driver */
1256 /* ======================================================================== */
1257
1258 static struct uart_driver mpc52xx_uart_driver = {
1259 .driver_name = "mpc52xx_psc_uart",
1260 .dev_name = "ttyPSC",
1261 .major = SERIAL_PSC_MAJOR,
1262 .minor = SERIAL_PSC_MINOR,
1263 .nr = MPC52xx_PSC_MAXNUM,
1264 .cons = MPC52xx_PSC_CONSOLE,
1265 };
1266
1267 /* ======================================================================== */
1268 /* OF Platform Driver */
1269 /* ======================================================================== */
1270
1271 static struct of_device_id mpc52xx_uart_of_match[] = {
1272 #ifdef CONFIG_PPC_MPC52xx
1273 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1274 /* binding used by old lite5200 device trees: */
1275 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1276 /* binding used by efika: */
1277 { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
1278 #endif
1279 #ifdef CONFIG_PPC_MPC512x
1280 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1281 #endif
1282 {},
1283 };
1284
1285 static int __devinit
1286 mpc52xx_uart_of_probe(struct of_device *op, const struct of_device_id *match)
1287 {
1288 int idx = -1;
1289 unsigned int uartclk;
1290 struct uart_port *port = NULL;
1291 struct resource res;
1292 int ret;
1293
1294 dev_dbg(&op->dev, "mpc52xx_uart_probe(op=%p, match=%p)\n", op, match);
1295
1296 /* Check validity & presence */
1297 for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
1298 if (mpc52xx_uart_nodes[idx] == op->node)
1299 break;
1300 if (idx >= MPC52xx_PSC_MAXNUM)
1301 return -EINVAL;
1302 pr_debug("Found %s assigned to ttyPSC%x\n",
1303 mpc52xx_uart_nodes[idx]->full_name, idx);
1304
1305 uartclk = psc_ops->getuartclk(op->node);
1306 if (uartclk == 0) {
1307 dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
1308 return -EINVAL;
1309 }
1310
1311 /* Init the port structure */
1312 port = &mpc52xx_uart_ports[idx];
1313
1314 spin_lock_init(&port->lock);
1315 port->uartclk = uartclk;
1316 port->fifosize = 512;
1317 port->iotype = UPIO_MEM;
1318 port->flags = UPF_BOOT_AUTOCONF |
1319 (uart_console(port) ? 0 : UPF_IOREMAP);
1320 port->line = idx;
1321 port->ops = &mpc52xx_uart_ops;
1322 port->dev = &op->dev;
1323
1324 /* Search for IRQ and mapbase */
1325 ret = of_address_to_resource(op->node, 0, &res);
1326 if (ret)
1327 return ret;
1328
1329 port->mapbase = res.start;
1330 if (!port->mapbase) {
1331 dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1332 return -EINVAL;
1333 }
1334
1335 psc_ops->get_irq(port, op->node);
1336 if (port->irq == NO_IRQ) {
1337 dev_dbg(&op->dev, "Could not get irq\n");
1338 return -EINVAL;
1339 }
1340
1341 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1342 (void *)port->mapbase, port->irq, port->uartclk);
1343
1344 /* Add the port to the uart sub-system */
1345 ret = uart_add_one_port(&mpc52xx_uart_driver, port);
1346 if (ret)
1347 return ret;
1348
1349 dev_set_drvdata(&op->dev, (void *)port);
1350 return 0;
1351 }
1352
1353 static int
1354 mpc52xx_uart_of_remove(struct of_device *op)
1355 {
1356 struct uart_port *port = dev_get_drvdata(&op->dev);
1357 dev_set_drvdata(&op->dev, NULL);
1358
1359 if (port)
1360 uart_remove_one_port(&mpc52xx_uart_driver, port);
1361
1362 return 0;
1363 }
1364
1365 #ifdef CONFIG_PM
1366 static int
1367 mpc52xx_uart_of_suspend(struct of_device *op, pm_message_t state)
1368 {
1369 struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev);
1370
1371 if (port)
1372 uart_suspend_port(&mpc52xx_uart_driver, port);
1373
1374 return 0;
1375 }
1376
1377 static int
1378 mpc52xx_uart_of_resume(struct of_device *op)
1379 {
1380 struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev);
1381
1382 if (port)
1383 uart_resume_port(&mpc52xx_uart_driver, port);
1384
1385 return 0;
1386 }
1387 #endif
1388
1389 static void
1390 mpc52xx_uart_of_assign(struct device_node *np)
1391 {
1392 int i;
1393
1394 /* Find the first free PSC number */
1395 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1396 if (mpc52xx_uart_nodes[i] == NULL) {
1397 of_node_get(np);
1398 mpc52xx_uart_nodes[i] = np;
1399 return;
1400 }
1401 }
1402 }
1403
1404 static void
1405 mpc52xx_uart_of_enumerate(void)
1406 {
1407 static int enum_done;
1408 struct device_node *np;
1409 const struct of_device_id *match;
1410 int i;
1411
1412 if (enum_done)
1413 return;
1414
1415 /* Assign index to each PSC in device tree */
1416 for_each_matching_node(np, mpc52xx_uart_of_match) {
1417 match = of_match_node(mpc52xx_uart_of_match, np);
1418 psc_ops = match->data;
1419 mpc52xx_uart_of_assign(np);
1420 }
1421
1422 enum_done = 1;
1423
1424 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1425 if (mpc52xx_uart_nodes[i])
1426 pr_debug("%s assigned to ttyPSC%x\n",
1427 mpc52xx_uart_nodes[i]->full_name, i);
1428 }
1429 }
1430
1431 MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
1432
1433 static struct of_platform_driver mpc52xx_uart_of_driver = {
1434 .match_table = mpc52xx_uart_of_match,
1435 .probe = mpc52xx_uart_of_probe,
1436 .remove = mpc52xx_uart_of_remove,
1437 #ifdef CONFIG_PM
1438 .suspend = mpc52xx_uart_of_suspend,
1439 .resume = mpc52xx_uart_of_resume,
1440 #endif
1441 .driver = {
1442 .name = "mpc52xx-psc-uart",
1443 },
1444 };
1445
1446
1447 /* ======================================================================== */
1448 /* Module */
1449 /* ======================================================================== */
1450
1451 static int __init
1452 mpc52xx_uart_init(void)
1453 {
1454 int ret;
1455
1456 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1457
1458 ret = uart_register_driver(&mpc52xx_uart_driver);
1459 if (ret) {
1460 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
1461 __FILE__, ret);
1462 return ret;
1463 }
1464
1465 mpc52xx_uart_of_enumerate();
1466
1467 /*
1468 * Map the PSC FIFO Controller and init if on MPC512x.
1469 */
1470 if (psc_ops->fifoc_init) {
1471 ret = psc_ops->fifoc_init();
1472 if (ret)
1473 return ret;
1474 }
1475
1476 ret = of_register_platform_driver(&mpc52xx_uart_of_driver);
1477 if (ret) {
1478 printk(KERN_ERR "%s: of_register_platform_driver failed (%i)\n",
1479 __FILE__, ret);
1480 uart_unregister_driver(&mpc52xx_uart_driver);
1481 return ret;
1482 }
1483
1484 return 0;
1485 }
1486
1487 static void __exit
1488 mpc52xx_uart_exit(void)
1489 {
1490 if (psc_ops->fifoc_uninit)
1491 psc_ops->fifoc_uninit();
1492
1493 of_unregister_platform_driver(&mpc52xx_uart_of_driver);
1494 uart_unregister_driver(&mpc52xx_uart_driver);
1495 }
1496
1497
1498 module_init(mpc52xx_uart_init);
1499 module_exit(mpc52xx_uart_exit);
1500
1501 MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
1502 MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
1503 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree