2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/highmem.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
29 #include <asm/stacktrace.h>
34 #define wrmsrl(msr, val) \
36 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
37 (unsigned long)(val)); \
38 native_write_msr((msr), (u32)((u64)(val)), \
39 (u32)((u64)(val) >> 32)); \
44 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
47 copy_from_user_nmi(void *to
, const void __user
*from
, unsigned long n
)
49 unsigned long offset
, addr
= (unsigned long)from
;
50 int type
= in_nmi() ? KM_NMI
: KM_IRQ0
;
51 unsigned long size
, len
= 0;
57 ret
= __get_user_pages_fast(addr
, 1, 0, &page
);
61 offset
= addr
& (PAGE_SIZE
- 1);
62 size
= min(PAGE_SIZE
- offset
, n
- len
);
64 map
= kmap_atomic(page
, type
);
65 memcpy(to
, map
+offset
, size
);
66 kunmap_atomic(map
, type
);
78 struct event_constraint
{
80 unsigned long idxmsk
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
89 int nb_id
; /* NorthBridge id */
90 int refcnt
; /* reference count */
91 struct perf_event
*owners
[X86_PMC_IDX_MAX
];
92 struct event_constraint event_constraints
[X86_PMC_IDX_MAX
];
95 #define MAX_LBR_ENTRIES 16
97 struct cpu_hw_events
{
99 * Generic x86 PMC bits
101 struct perf_event
*events
[X86_PMC_IDX_MAX
]; /* in counter order */
102 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
107 int assign
[X86_PMC_IDX_MAX
]; /* event to counter assignment */
108 u64 tags
[X86_PMC_IDX_MAX
];
109 struct perf_event
*event_list
[X86_PMC_IDX_MAX
]; /* in enabled order */
112 * Intel DebugStore bits
114 struct debug_store
*ds
;
122 struct perf_branch_stack lbr_stack
;
123 struct perf_branch_entry lbr_entries
[MAX_LBR_ENTRIES
];
128 struct amd_nb
*amd_nb
;
131 #define __EVENT_CONSTRAINT(c, n, m, w) {\
132 { .idxmsk64 = (n) }, \
138 #define EVENT_CONSTRAINT(c, n, m) \
139 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
142 * Constraint on the Event code.
144 #define INTEL_EVENT_CONSTRAINT(c, n) \
145 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK)
148 * Constraint on the Event code + UMask + fixed-mask
150 #define FIXED_EVENT_CONSTRAINT(c, n) \
151 EVENT_CONSTRAINT(c, (1ULL << (32+n)), INTEL_ARCH_FIXED_MASK)
154 * Constraint on the Event code + UMask
156 #define PEBS_EVENT_CONSTRAINT(c, n) \
157 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
159 #define EVENT_CONSTRAINT_END \
160 EVENT_CONSTRAINT(0, 0, 0)
162 #define for_each_event_constraint(e, c) \
163 for ((e) = (c); (e)->cmask; (e)++)
165 union perf_capabilities
{
169 u64 pebs_arch_reg
: 1;
177 * struct x86_pmu - generic x86 pmu
181 * Generic x86 PMC bits
185 int (*handle_irq
)(struct pt_regs
*);
186 void (*disable_all
)(void);
187 void (*enable_all
)(void);
188 void (*enable
)(struct perf_event
*);
189 void (*disable
)(struct perf_event
*);
190 int (*hw_config
)(struct perf_event_attr
*attr
, struct hw_perf_event
*hwc
);
191 int (*schedule_events
)(struct cpu_hw_events
*cpuc
, int n
, int *assign
);
194 u64 (*event_map
)(int);
195 u64 (*raw_event
)(u64
);
198 int num_events_fixed
;
203 struct event_constraint
*
204 (*get_event_constraints
)(struct cpu_hw_events
*cpuc
,
205 struct perf_event
*event
);
207 void (*put_event_constraints
)(struct cpu_hw_events
*cpuc
,
208 struct perf_event
*event
);
209 struct event_constraint
*event_constraints
;
210 void (*quirks
)(void);
212 void (*cpu_prepare
)(int cpu
);
213 void (*cpu_starting
)(int cpu
);
214 void (*cpu_dying
)(int cpu
);
215 void (*cpu_dead
)(int cpu
);
218 * Intel Arch Perfmon v2+
221 union perf_capabilities intel_cap
;
224 * Intel DebugStore bits
227 int pebs_record_size
;
228 void (*drain_pebs
)(struct pt_regs
*regs
);
229 struct event_constraint
*pebs_constraints
;
234 unsigned long lbr_tos
, lbr_from
, lbr_to
; /* MSR base regs */
235 int lbr_nr
; /* hardware stack size */
238 static struct x86_pmu x86_pmu __read_mostly
;
240 static DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
244 static int x86_perf_event_set_period(struct perf_event
*event
);
247 * Generalized hw caching related hw_event table, filled
248 * in on a per model basis. A value of 0 means
249 * 'not supported', -1 means 'hw_event makes no sense on
250 * this CPU', any other value means the raw hw_event
254 #define C(x) PERF_COUNT_HW_CACHE_##x
256 static u64 __read_mostly hw_cache_event_ids
257 [PERF_COUNT_HW_CACHE_MAX
]
258 [PERF_COUNT_HW_CACHE_OP_MAX
]
259 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
262 * Propagate event elapsed time into the generic event.
263 * Can only be executed on the CPU where the event is active.
264 * Returns the delta events processed.
267 x86_perf_event_update(struct perf_event
*event
)
269 struct hw_perf_event
*hwc
= &event
->hw
;
270 int shift
= 64 - x86_pmu
.event_bits
;
271 u64 prev_raw_count
, new_raw_count
;
275 if (idx
== X86_PMC_IDX_FIXED_BTS
)
279 * Careful: an NMI might modify the previous event value.
281 * Our tactic to handle this is to first atomically read and
282 * exchange a new raw count - then add that new-prev delta
283 * count to the generic event atomically:
286 prev_raw_count
= atomic64_read(&hwc
->prev_count
);
287 rdmsrl(hwc
->event_base
+ idx
, new_raw_count
);
289 if (atomic64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
290 new_raw_count
) != prev_raw_count
)
294 * Now we have the new raw value and have updated the prev
295 * timestamp already. We can now calculate the elapsed delta
296 * (event-)time and add that to the generic event.
298 * Careful, not all hw sign-extends above the physical width
301 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
304 atomic64_add(delta
, &event
->count
);
305 atomic64_sub(delta
, &hwc
->period_left
);
307 return new_raw_count
;
310 static atomic_t active_events
;
311 static DEFINE_MUTEX(pmc_reserve_mutex
);
313 #ifdef CONFIG_X86_LOCAL_APIC
315 static bool reserve_pmc_hardware(void)
319 if (nmi_watchdog
== NMI_LOCAL_APIC
)
320 disable_lapic_nmi_watchdog();
322 for (i
= 0; i
< x86_pmu
.num_events
; i
++) {
323 if (!reserve_perfctr_nmi(x86_pmu
.perfctr
+ i
))
327 for (i
= 0; i
< x86_pmu
.num_events
; i
++) {
328 if (!reserve_evntsel_nmi(x86_pmu
.eventsel
+ i
))
335 for (i
--; i
>= 0; i
--)
336 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
338 i
= x86_pmu
.num_events
;
341 for (i
--; i
>= 0; i
--)
342 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
344 if (nmi_watchdog
== NMI_LOCAL_APIC
)
345 enable_lapic_nmi_watchdog();
350 static void release_pmc_hardware(void)
354 for (i
= 0; i
< x86_pmu
.num_events
; i
++) {
355 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
356 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
359 if (nmi_watchdog
== NMI_LOCAL_APIC
)
360 enable_lapic_nmi_watchdog();
365 static bool reserve_pmc_hardware(void) { return true; }
366 static void release_pmc_hardware(void) {}
370 static int reserve_ds_buffers(void);
371 static void release_ds_buffers(void);
373 static void hw_perf_event_destroy(struct perf_event
*event
)
375 if (atomic_dec_and_mutex_lock(&active_events
, &pmc_reserve_mutex
)) {
376 release_pmc_hardware();
377 release_ds_buffers();
378 mutex_unlock(&pmc_reserve_mutex
);
382 static inline int x86_pmu_initialized(void)
384 return x86_pmu
.handle_irq
!= NULL
;
388 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event_attr
*attr
)
390 unsigned int cache_type
, cache_op
, cache_result
;
393 config
= attr
->config
;
395 cache_type
= (config
>> 0) & 0xff;
396 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
399 cache_op
= (config
>> 8) & 0xff;
400 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
403 cache_result
= (config
>> 16) & 0xff;
404 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
407 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
420 static int x86_hw_config(struct perf_event_attr
*attr
, struct hw_perf_event
*hwc
)
424 * (keep 'enabled' bit clear for now)
426 hwc
->config
= ARCH_PERFMON_EVENTSEL_INT
;
429 * Count user and OS events unless requested not to
431 if (!attr
->exclude_user
)
432 hwc
->config
|= ARCH_PERFMON_EVENTSEL_USR
;
433 if (!attr
->exclude_kernel
)
434 hwc
->config
|= ARCH_PERFMON_EVENTSEL_OS
;
440 * Setup the hardware configuration for a given attr_type
442 static int __hw_perf_event_init(struct perf_event
*event
)
444 struct perf_event_attr
*attr
= &event
->attr
;
445 struct hw_perf_event
*hwc
= &event
->hw
;
449 if (!x86_pmu_initialized())
453 if (!atomic_inc_not_zero(&active_events
)) {
454 mutex_lock(&pmc_reserve_mutex
);
455 if (atomic_read(&active_events
) == 0) {
456 if (!reserve_pmc_hardware())
459 err
= reserve_ds_buffers();
461 release_pmc_hardware();
465 atomic_inc(&active_events
);
466 mutex_unlock(&pmc_reserve_mutex
);
471 event
->destroy
= hw_perf_event_destroy
;
475 hwc
->last_tag
= ~0ULL;
477 /* Processor specifics */
478 err
= x86_pmu
.hw_config(attr
, hwc
);
482 if (!hwc
->sample_period
) {
483 hwc
->sample_period
= x86_pmu
.max_period
;
484 hwc
->last_period
= hwc
->sample_period
;
485 atomic64_set(&hwc
->period_left
, hwc
->sample_period
);
488 * If we have a PMU initialized but no APIC
489 * interrupts, we cannot sample hardware
490 * events (user-space has to fall back and
491 * sample via a hrtimer based software event):
498 * Raw hw_event type provide the config in the hw_event structure
500 if (attr
->type
== PERF_TYPE_RAW
) {
501 hwc
->config
|= x86_pmu
.raw_event(attr
->config
);
502 if ((hwc
->config
& ARCH_PERFMON_EVENTSEL_ANY
) &&
503 perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN
))
508 if (attr
->type
== PERF_TYPE_HW_CACHE
)
509 return set_ext_hw_attr(hwc
, attr
);
511 if (attr
->config
>= x86_pmu
.max_events
)
517 config
= x86_pmu
.event_map(attr
->config
);
528 if ((attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
) &&
529 (hwc
->sample_period
== 1)) {
530 /* BTS is not supported by this architecture. */
534 /* BTS is currently only allowed for user-mode. */
535 if (!attr
->exclude_kernel
)
539 hwc
->config
|= config
;
544 static void x86_pmu_disable_all(void)
546 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
549 for (idx
= 0; idx
< x86_pmu
.num_events
; idx
++) {
552 if (!test_bit(idx
, cpuc
->active_mask
))
554 rdmsrl(x86_pmu
.eventsel
+ idx
, val
);
555 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
557 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
558 wrmsrl(x86_pmu
.eventsel
+ idx
, val
);
562 void hw_perf_disable(void)
564 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
566 if (!x86_pmu_initialized())
576 x86_pmu
.disable_all();
579 static void x86_pmu_enable_all(void)
581 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
584 for (idx
= 0; idx
< x86_pmu
.num_events
; idx
++) {
585 struct perf_event
*event
= cpuc
->events
[idx
];
588 if (!test_bit(idx
, cpuc
->active_mask
))
591 val
= event
->hw
.config
;
592 val
|= ARCH_PERFMON_EVENTSEL_ENABLE
;
593 wrmsrl(x86_pmu
.eventsel
+ idx
, val
);
597 static const struct pmu pmu
;
599 static inline int is_x86_event(struct perf_event
*event
)
601 return event
->pmu
== &pmu
;
604 static int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
606 struct event_constraint
*c
, *constraints
[X86_PMC_IDX_MAX
];
607 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
608 int i
, j
, w
, wmax
, num
= 0;
609 struct hw_perf_event
*hwc
;
611 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
613 for (i
= 0; i
< n
; i
++) {
614 c
= x86_pmu
.get_event_constraints(cpuc
, cpuc
->event_list
[i
]);
619 * fastpath, try to reuse previous register
621 for (i
= 0; i
< n
; i
++) {
622 hwc
= &cpuc
->event_list
[i
]->hw
;
629 /* constraint still honored */
630 if (!test_bit(hwc
->idx
, c
->idxmsk
))
633 /* not already used */
634 if (test_bit(hwc
->idx
, used_mask
))
637 __set_bit(hwc
->idx
, used_mask
);
639 assign
[i
] = hwc
->idx
;
648 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
651 * weight = number of possible counters
653 * 1 = most constrained, only works on one counter
654 * wmax = least constrained, works on any counter
656 * assign events to counters starting with most
657 * constrained events.
659 wmax
= x86_pmu
.num_events
;
662 * when fixed event counters are present,
663 * wmax is incremented by 1 to account
664 * for one more choice
666 if (x86_pmu
.num_events_fixed
)
669 for (w
= 1, num
= n
; num
&& w
<= wmax
; w
++) {
671 for (i
= 0; num
&& i
< n
; i
++) {
673 hwc
= &cpuc
->event_list
[i
]->hw
;
678 for_each_set_bit(j
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
679 if (!test_bit(j
, used_mask
))
683 if (j
== X86_PMC_IDX_MAX
)
686 __set_bit(j
, used_mask
);
695 * scheduling failed or is just a simulation,
696 * free resources if necessary
698 if (!assign
|| num
) {
699 for (i
= 0; i
< n
; i
++) {
700 if (x86_pmu
.put_event_constraints
)
701 x86_pmu
.put_event_constraints(cpuc
, cpuc
->event_list
[i
]);
704 return num
? -ENOSPC
: 0;
708 * dogrp: true if must collect siblings events (group)
709 * returns total number of events and error code
711 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
713 struct perf_event
*event
;
716 max_count
= x86_pmu
.num_events
+ x86_pmu
.num_events_fixed
;
718 /* current number of events already accepted */
721 if (is_x86_event(leader
)) {
724 cpuc
->event_list
[n
] = leader
;
730 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
731 if (!is_x86_event(event
) ||
732 event
->state
<= PERF_EVENT_STATE_OFF
)
738 cpuc
->event_list
[n
] = event
;
744 static inline void x86_assign_hw_event(struct perf_event
*event
,
745 struct cpu_hw_events
*cpuc
, int i
)
747 struct hw_perf_event
*hwc
= &event
->hw
;
749 hwc
->idx
= cpuc
->assign
[i
];
750 hwc
->last_cpu
= smp_processor_id();
751 hwc
->last_tag
= ++cpuc
->tags
[i
];
753 if (hwc
->idx
== X86_PMC_IDX_FIXED_BTS
) {
754 hwc
->config_base
= 0;
756 } else if (hwc
->idx
>= X86_PMC_IDX_FIXED
) {
757 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
759 * We set it so that event_base + idx in wrmsr/rdmsr maps to
760 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
763 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
765 hwc
->config_base
= x86_pmu
.eventsel
;
766 hwc
->event_base
= x86_pmu
.perfctr
;
770 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
771 struct cpu_hw_events
*cpuc
,
774 return hwc
->idx
== cpuc
->assign
[i
] &&
775 hwc
->last_cpu
== smp_processor_id() &&
776 hwc
->last_tag
== cpuc
->tags
[i
];
779 static int x86_pmu_start(struct perf_event
*event
);
780 static void x86_pmu_stop(struct perf_event
*event
);
782 void hw_perf_enable(void)
784 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
785 struct perf_event
*event
;
786 struct hw_perf_event
*hwc
;
789 if (!x86_pmu_initialized())
796 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
798 * apply assignment obtained either from
799 * hw_perf_group_sched_in() or x86_pmu_enable()
801 * step1: save events moving to new counters
802 * step2: reprogram moved events into new counters
804 for (i
= 0; i
< n_running
; i
++) {
805 event
= cpuc
->event_list
[i
];
809 * we can avoid reprogramming counter if:
810 * - assigned same counter as last time
811 * - running on same CPU as last time
812 * - no other event has used the counter since
814 if (hwc
->idx
== -1 ||
815 match_prev_assignment(hwc
, cpuc
, i
))
821 for (i
= 0; i
< cpuc
->n_events
; i
++) {
822 event
= cpuc
->event_list
[i
];
825 if (!match_prev_assignment(hwc
, cpuc
, i
))
826 x86_assign_hw_event(event
, cpuc
, i
);
827 else if (i
< n_running
)
830 x86_pmu_start(event
);
833 perf_events_lapic_init();
839 x86_pmu
.enable_all();
842 static inline void __x86_pmu_enable_event(struct hw_perf_event
*hwc
)
844 wrmsrl(hwc
->config_base
+ hwc
->idx
,
845 hwc
->config
| ARCH_PERFMON_EVENTSEL_ENABLE
);
848 static inline void x86_pmu_disable_event(struct perf_event
*event
)
850 struct hw_perf_event
*hwc
= &event
->hw
;
852 wrmsrl(hwc
->config_base
+ hwc
->idx
, hwc
->config
);
855 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
858 * Set the next IRQ period, based on the hwc->period_left value.
859 * To be called with the event disabled in hw:
862 x86_perf_event_set_period(struct perf_event
*event
)
864 struct hw_perf_event
*hwc
= &event
->hw
;
865 s64 left
= atomic64_read(&hwc
->period_left
);
866 s64 period
= hwc
->sample_period
;
867 int ret
= 0, idx
= hwc
->idx
;
869 if (idx
== X86_PMC_IDX_FIXED_BTS
)
873 * If we are way outside a reasonable range then just skip forward:
875 if (unlikely(left
<= -period
)) {
877 atomic64_set(&hwc
->period_left
, left
);
878 hwc
->last_period
= period
;
882 if (unlikely(left
<= 0)) {
884 atomic64_set(&hwc
->period_left
, left
);
885 hwc
->last_period
= period
;
889 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
891 if (unlikely(left
< 2))
894 if (left
> x86_pmu
.max_period
)
895 left
= x86_pmu
.max_period
;
897 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
900 * The hw event starts counting from this event offset,
901 * mark it to be able to extra future deltas:
903 atomic64_set(&hwc
->prev_count
, (u64
)-left
);
905 wrmsrl(hwc
->event_base
+ idx
,
906 (u64
)(-left
) & x86_pmu
.event_mask
);
908 perf_event_update_userpage(event
);
913 static void x86_pmu_enable_event(struct perf_event
*event
)
915 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
917 __x86_pmu_enable_event(&event
->hw
);
921 * activate a single event
923 * The event is added to the group of enabled events
924 * but only if it can be scehduled with existing events.
926 * Called with PMU disabled. If successful and return value 1,
927 * then guaranteed to call perf_enable() and hw_perf_enable()
929 static int x86_pmu_enable(struct perf_event
*event
)
931 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
932 struct hw_perf_event
*hwc
;
933 int assign
[X86_PMC_IDX_MAX
];
939 n
= collect_events(cpuc
, event
, false);
943 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
947 * copy new assignment, now we know it is possible
948 * will be used by hw_perf_enable()
950 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
953 cpuc
->n_added
+= n
- n0
;
958 static int x86_pmu_start(struct perf_event
*event
)
960 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
961 int idx
= event
->hw
.idx
;
966 x86_perf_event_set_period(event
);
967 cpuc
->events
[idx
] = event
;
968 __set_bit(idx
, cpuc
->active_mask
);
969 x86_pmu
.enable(event
);
970 perf_event_update_userpage(event
);
975 static void x86_pmu_unthrottle(struct perf_event
*event
)
977 int ret
= x86_pmu_start(event
);
981 void perf_event_print_debug(void)
983 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
985 struct cpu_hw_events
*cpuc
;
989 if (!x86_pmu
.num_events
)
992 local_irq_save(flags
);
994 cpu
= smp_processor_id();
995 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
997 if (x86_pmu
.version
>= 2) {
998 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
999 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1000 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1001 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1002 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1005 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1006 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1007 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1008 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1009 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1011 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1013 for (idx
= 0; idx
< x86_pmu
.num_events
; idx
++) {
1014 rdmsrl(x86_pmu
.eventsel
+ idx
, pmc_ctrl
);
1015 rdmsrl(x86_pmu
.perfctr
+ idx
, pmc_count
);
1017 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1019 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1020 cpu
, idx
, pmc_ctrl
);
1021 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1022 cpu
, idx
, pmc_count
);
1023 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1024 cpu
, idx
, prev_left
);
1026 for (idx
= 0; idx
< x86_pmu
.num_events_fixed
; idx
++) {
1027 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1029 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1030 cpu
, idx
, pmc_count
);
1032 local_irq_restore(flags
);
1035 static void x86_pmu_stop(struct perf_event
*event
)
1037 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1038 struct hw_perf_event
*hwc
= &event
->hw
;
1041 if (!__test_and_clear_bit(idx
, cpuc
->active_mask
))
1044 x86_pmu
.disable(event
);
1047 * Drain the remaining delta count out of a event
1048 * that we are disabling:
1050 x86_perf_event_update(event
);
1052 cpuc
->events
[idx
] = NULL
;
1055 static void x86_pmu_disable(struct perf_event
*event
)
1057 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1060 x86_pmu_stop(event
);
1062 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1063 if (event
== cpuc
->event_list
[i
]) {
1065 if (x86_pmu
.put_event_constraints
)
1066 x86_pmu
.put_event_constraints(cpuc
, event
);
1068 while (++i
< cpuc
->n_events
)
1069 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1075 perf_event_update_userpage(event
);
1078 static int x86_pmu_handle_irq(struct pt_regs
*regs
)
1080 struct perf_sample_data data
;
1081 struct cpu_hw_events
*cpuc
;
1082 struct perf_event
*event
;
1083 struct hw_perf_event
*hwc
;
1084 int idx
, handled
= 0;
1087 perf_sample_data_init(&data
, 0);
1089 cpuc
= &__get_cpu_var(cpu_hw_events
);
1091 for (idx
= 0; idx
< x86_pmu
.num_events
; idx
++) {
1092 if (!test_bit(idx
, cpuc
->active_mask
))
1095 event
= cpuc
->events
[idx
];
1098 val
= x86_perf_event_update(event
);
1099 if (val
& (1ULL << (x86_pmu
.event_bits
- 1)))
1106 data
.period
= event
->hw
.last_period
;
1108 if (!x86_perf_event_set_period(event
))
1111 if (perf_event_overflow(event
, 1, &data
, regs
))
1112 x86_pmu_stop(event
);
1116 inc_irq_stat(apic_perf_irqs
);
1121 void smp_perf_pending_interrupt(struct pt_regs
*regs
)
1125 inc_irq_stat(apic_pending_irqs
);
1126 perf_event_do_pending();
1130 void set_perf_event_pending(void)
1132 #ifdef CONFIG_X86_LOCAL_APIC
1133 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1136 apic
->send_IPI_self(LOCAL_PENDING_VECTOR
);
1140 void perf_events_lapic_init(void)
1142 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1146 * Always use NMI for PMU
1148 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1151 static int __kprobes
1152 perf_event_nmi_handler(struct notifier_block
*self
,
1153 unsigned long cmd
, void *__args
)
1155 struct die_args
*args
= __args
;
1156 struct pt_regs
*regs
;
1158 if (!atomic_read(&active_events
))
1172 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1174 * Can't rely on the handled return value to say it was our NMI, two
1175 * events could trigger 'simultaneously' raising two back-to-back NMIs.
1177 * If the first NMI handles both, the latter will be empty and daze
1180 x86_pmu
.handle_irq(regs
);
1185 static __read_mostly
struct notifier_block perf_event_nmi_notifier
= {
1186 .notifier_call
= perf_event_nmi_handler
,
1191 static struct event_constraint unconstrained
;
1192 static struct event_constraint emptyconstraint
;
1194 static struct event_constraint
*
1195 x86_get_event_constraints(struct cpu_hw_events
*cpuc
, struct perf_event
*event
)
1197 struct event_constraint
*c
;
1199 if (x86_pmu
.event_constraints
) {
1200 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1201 if ((event
->hw
.config
& c
->cmask
) == c
->code
)
1206 return &unconstrained
;
1209 static int x86_event_sched_in(struct perf_event
*event
,
1210 struct perf_cpu_context
*cpuctx
)
1214 event
->state
= PERF_EVENT_STATE_ACTIVE
;
1215 event
->oncpu
= smp_processor_id();
1216 event
->tstamp_running
+= event
->ctx
->time
- event
->tstamp_stopped
;
1218 if (!is_x86_event(event
))
1219 ret
= event
->pmu
->enable(event
);
1221 if (!ret
&& !is_software_event(event
))
1222 cpuctx
->active_oncpu
++;
1224 if (!ret
&& event
->attr
.exclusive
)
1225 cpuctx
->exclusive
= 1;
1230 static void x86_event_sched_out(struct perf_event
*event
,
1231 struct perf_cpu_context
*cpuctx
)
1233 event
->state
= PERF_EVENT_STATE_INACTIVE
;
1236 if (!is_x86_event(event
))
1237 event
->pmu
->disable(event
);
1239 event
->tstamp_running
-= event
->ctx
->time
- event
->tstamp_stopped
;
1241 if (!is_software_event(event
))
1242 cpuctx
->active_oncpu
--;
1244 if (event
->attr
.exclusive
|| !cpuctx
->active_oncpu
)
1245 cpuctx
->exclusive
= 0;
1249 * Called to enable a whole group of events.
1250 * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1251 * Assumes the caller has disabled interrupts and has
1252 * frozen the PMU with hw_perf_save_disable.
1254 * called with PMU disabled. If successful and return value 1,
1255 * then guaranteed to call perf_enable() and hw_perf_enable()
1257 int hw_perf_group_sched_in(struct perf_event
*leader
,
1258 struct perf_cpu_context
*cpuctx
,
1259 struct perf_event_context
*ctx
)
1261 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1262 struct perf_event
*sub
;
1263 int assign
[X86_PMC_IDX_MAX
];
1266 if (!x86_pmu_initialized())
1269 /* n0 = total number of events */
1270 n0
= collect_events(cpuc
, leader
, true);
1274 ret
= x86_pmu
.schedule_events(cpuc
, n0
, assign
);
1278 ret
= x86_event_sched_in(leader
, cpuctx
);
1283 list_for_each_entry(sub
, &leader
->sibling_list
, group_entry
) {
1284 if (sub
->state
> PERF_EVENT_STATE_OFF
) {
1285 ret
= x86_event_sched_in(sub
, cpuctx
);
1292 * copy new assignment, now we know it is possible
1293 * will be used by hw_perf_enable()
1295 memcpy(cpuc
->assign
, assign
, n0
*sizeof(int));
1297 cpuc
->n_events
= n0
;
1298 cpuc
->n_added
+= n1
;
1299 ctx
->nr_active
+= n1
;
1302 * 1 means successful and events are active
1303 * This is not quite true because we defer
1304 * actual activation until hw_perf_enable() but
1305 * this way we* ensure caller won't try to enable
1310 x86_event_sched_out(leader
, cpuctx
);
1312 list_for_each_entry(sub
, &leader
->sibling_list
, group_entry
) {
1313 if (sub
->state
== PERF_EVENT_STATE_ACTIVE
) {
1314 x86_event_sched_out(sub
, cpuctx
);
1322 #include "perf_event_amd.c"
1323 #include "perf_event_p6.c"
1324 #include "perf_event_p4.c"
1325 #include "perf_event_intel_lbr.c"
1326 #include "perf_event_intel_ds.c"
1327 #include "perf_event_intel.c"
1329 static int __cpuinit
1330 x86_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1332 unsigned int cpu
= (long)hcpu
;
1334 switch (action
& ~CPU_TASKS_FROZEN
) {
1335 case CPU_UP_PREPARE
:
1336 if (x86_pmu
.cpu_prepare
)
1337 x86_pmu
.cpu_prepare(cpu
);
1341 if (x86_pmu
.cpu_starting
)
1342 x86_pmu
.cpu_starting(cpu
);
1346 if (x86_pmu
.cpu_dying
)
1347 x86_pmu
.cpu_dying(cpu
);
1351 if (x86_pmu
.cpu_dead
)
1352 x86_pmu
.cpu_dead(cpu
);
1362 static void __init
pmu_check_apic(void)
1368 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1369 pr_info("no hardware sampling interrupt available.\n");
1372 void __init
init_hw_perf_events(void)
1374 struct event_constraint
*c
;
1377 pr_info("Performance Events: ");
1379 switch (boot_cpu_data
.x86_vendor
) {
1380 case X86_VENDOR_INTEL
:
1381 err
= intel_pmu_init();
1383 case X86_VENDOR_AMD
:
1384 err
= amd_pmu_init();
1390 pr_cont("no PMU driver, software events only.\n");
1396 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1401 if (x86_pmu
.num_events
> X86_PMC_MAX_GENERIC
) {
1402 WARN(1, KERN_ERR
"hw perf events %d > max(%d), clipping!",
1403 x86_pmu
.num_events
, X86_PMC_MAX_GENERIC
);
1404 x86_pmu
.num_events
= X86_PMC_MAX_GENERIC
;
1406 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_events
) - 1;
1407 perf_max_events
= x86_pmu
.num_events
;
1409 if (x86_pmu
.num_events_fixed
> X86_PMC_MAX_FIXED
) {
1410 WARN(1, KERN_ERR
"hw perf events fixed %d > max(%d), clipping!",
1411 x86_pmu
.num_events_fixed
, X86_PMC_MAX_FIXED
);
1412 x86_pmu
.num_events_fixed
= X86_PMC_MAX_FIXED
;
1415 x86_pmu
.intel_ctrl
|=
1416 ((1LL << x86_pmu
.num_events_fixed
)-1) << X86_PMC_IDX_FIXED
;
1418 perf_events_lapic_init();
1419 register_die_notifier(&perf_event_nmi_notifier
);
1421 unconstrained
= (struct event_constraint
)
1422 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_events
) - 1,
1423 0, x86_pmu
.num_events
);
1425 if (x86_pmu
.event_constraints
) {
1426 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1427 if (c
->cmask
!= INTEL_ARCH_FIXED_MASK
)
1430 c
->idxmsk64
|= (1ULL << x86_pmu
.num_events
) - 1;
1431 c
->weight
+= x86_pmu
.num_events
;
1435 pr_info("... version: %d\n", x86_pmu
.version
);
1436 pr_info("... bit width: %d\n", x86_pmu
.event_bits
);
1437 pr_info("... generic registers: %d\n", x86_pmu
.num_events
);
1438 pr_info("... value mask: %016Lx\n", x86_pmu
.event_mask
);
1439 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1440 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_events_fixed
);
1441 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1443 perf_cpu_notifier(x86_pmu_notifier
);
1446 static inline void x86_pmu_read(struct perf_event
*event
)
1448 x86_perf_event_update(event
);
1451 static const struct pmu pmu
= {
1452 .enable
= x86_pmu_enable
,
1453 .disable
= x86_pmu_disable
,
1454 .start
= x86_pmu_start
,
1455 .stop
= x86_pmu_stop
,
1456 .read
= x86_pmu_read
,
1457 .unthrottle
= x86_pmu_unthrottle
,
1461 * validate that we can schedule this event
1463 static int validate_event(struct perf_event
*event
)
1465 struct cpu_hw_events
*fake_cpuc
;
1466 struct event_constraint
*c
;
1469 fake_cpuc
= kmalloc(sizeof(*fake_cpuc
), GFP_KERNEL
| __GFP_ZERO
);
1473 c
= x86_pmu
.get_event_constraints(fake_cpuc
, event
);
1475 if (!c
|| !c
->weight
)
1478 if (x86_pmu
.put_event_constraints
)
1479 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
1487 * validate a single event group
1489 * validation include:
1490 * - check events are compatible which each other
1491 * - events do not compete for the same counter
1492 * - number of events <= number of counters
1494 * validation ensures the group can be loaded onto the
1495 * PMU if it was the only group available.
1497 static int validate_group(struct perf_event
*event
)
1499 struct perf_event
*leader
= event
->group_leader
;
1500 struct cpu_hw_events
*fake_cpuc
;
1504 fake_cpuc
= kmalloc(sizeof(*fake_cpuc
), GFP_KERNEL
| __GFP_ZERO
);
1509 * the event is not yet connected with its
1510 * siblings therefore we must first collect
1511 * existing siblings, then add the new event
1512 * before we can simulate the scheduling
1515 n
= collect_events(fake_cpuc
, leader
, true);
1519 fake_cpuc
->n_events
= n
;
1520 n
= collect_events(fake_cpuc
, event
, false);
1524 fake_cpuc
->n_events
= n
;
1526 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
1534 const struct pmu
*hw_perf_event_init(struct perf_event
*event
)
1536 const struct pmu
*tmp
;
1539 err
= __hw_perf_event_init(event
);
1542 * we temporarily connect event to its pmu
1543 * such that validate_group() can classify
1544 * it as an x86 event using is_x86_event()
1549 if (event
->group_leader
!= event
)
1550 err
= validate_group(event
);
1552 err
= validate_event(event
);
1558 event
->destroy(event
);
1559 return ERR_PTR(err
);
1570 void callchain_store(struct perf_callchain_entry
*entry
, u64 ip
)
1572 if (entry
->nr
< PERF_MAX_STACK_DEPTH
)
1573 entry
->ip
[entry
->nr
++] = ip
;
1576 static DEFINE_PER_CPU(struct perf_callchain_entry
, pmc_irq_entry
);
1577 static DEFINE_PER_CPU(struct perf_callchain_entry
, pmc_nmi_entry
);
1581 backtrace_warning_symbol(void *data
, char *msg
, unsigned long symbol
)
1583 /* Ignore warnings */
1586 static void backtrace_warning(void *data
, char *msg
)
1588 /* Ignore warnings */
1591 static int backtrace_stack(void *data
, char *name
)
1596 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1598 struct perf_callchain_entry
*entry
= data
;
1601 callchain_store(entry
, addr
);
1604 static const struct stacktrace_ops backtrace_ops
= {
1605 .warning
= backtrace_warning
,
1606 .warning_symbol
= backtrace_warning_symbol
,
1607 .stack
= backtrace_stack
,
1608 .address
= backtrace_address
,
1609 .walk_stack
= print_context_stack_bp
,
1612 #include "../dumpstack.h"
1615 perf_callchain_kernel(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1617 callchain_store(entry
, PERF_CONTEXT_KERNEL
);
1618 callchain_store(entry
, regs
->ip
);
1620 dump_trace(NULL
, regs
, NULL
, regs
->bp
, &backtrace_ops
, entry
);
1623 static int copy_stack_frame(const void __user
*fp
, struct stack_frame
*frame
)
1625 unsigned long bytes
;
1627 bytes
= copy_from_user_nmi(frame
, fp
, sizeof(*frame
));
1629 return bytes
== sizeof(*frame
);
1633 perf_callchain_user(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1635 struct stack_frame frame
;
1636 const void __user
*fp
;
1638 if (!user_mode(regs
))
1639 regs
= task_pt_regs(current
);
1641 fp
= (void __user
*)regs
->bp
;
1643 callchain_store(entry
, PERF_CONTEXT_USER
);
1644 callchain_store(entry
, regs
->ip
);
1646 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1647 frame
.next_frame
= NULL
;
1648 frame
.return_address
= 0;
1650 if (!copy_stack_frame(fp
, &frame
))
1653 if ((unsigned long)fp
< regs
->sp
)
1656 callchain_store(entry
, frame
.return_address
);
1657 fp
= frame
.next_frame
;
1662 perf_do_callchain(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1669 is_user
= user_mode(regs
);
1671 if (is_user
&& current
->state
!= TASK_RUNNING
)
1675 perf_callchain_kernel(regs
, entry
);
1678 perf_callchain_user(regs
, entry
);
1681 struct perf_callchain_entry
*perf_callchain(struct pt_regs
*regs
)
1683 struct perf_callchain_entry
*entry
;
1686 entry
= &__get_cpu_var(pmc_nmi_entry
);
1688 entry
= &__get_cpu_var(pmc_irq_entry
);
1692 perf_do_callchain(regs
, entry
);
1697 #ifdef CONFIG_EVENT_TRACING
1698 void perf_arch_fetch_caller_regs(struct pt_regs
*regs
, unsigned long ip
, int skip
)
1702 * perf_arch_fetch_caller_regs adds another call, we need to increment
1705 regs
->bp
= rewind_frame_pointer(skip
+ 1);
1706 regs
->cs
= __KERNEL_CS
;
1707 local_save_flags(regs
->flags
);