drivers/gpu/drm/radeon/r520.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "radeon_reg.h"
  30 #include "radeon.h"
  31
  32 /* r520,rv530,rv560,rv570,r580 depends on : */
  33 void r100_hdp_reset(struct radeon_device *rdev);
  34 void r420_pipes_init(struct radeon_device *rdev);
  35 void rs600_mc_disable_clients(struct radeon_device *rdev);
  36 void rs600_disable_vga(struct radeon_device *rdev);
  37 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
  38 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
  39
  40 /* This files gather functions specifics to:
  41  * r520,rv530,rv560,rv570,r580
  42  *
  43  * Some of these functions might be used by newer ASICs.
  44  */
  45 void r520_gpu_init(struct radeon_device *rdev);
  46 int r520_mc_wait_for_idle(struct radeon_device *rdev);
  47
  48
  49 /*
  50  * MC
  51  */
  52 int r520_mc_init(struct radeon_device *rdev)
  53 {
  54         uint32_t tmp;
  55         int r;
  56
  57         if (r100_debugfs_rbbm_init(rdev)) {
  58                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  59         }
  60         if (rv515_debugfs_pipes_info_init(rdev)) {
  61                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  62         }
  63         if (rv515_debugfs_ga_info_init(rdev)) {
  64                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  65         }
  66
  67         r520_gpu_init(rdev);
  68         rv370_pcie_gart_disable(rdev);
  69
  70         /* Setup GPU memory space */
  71         rdev->mc.vram_location = 0xFFFFFFFFUL;
  72         rdev->mc.gtt_location = 0xFFFFFFFFUL;
  73         if (rdev->flags & RADEON_IS_AGP) {
  74                 r = radeon_agp_init(rdev);
  75                 if (r) {
  76                         printk(KERN_WARNING "[drm] Disabling AGP\n");
  77                         rdev->flags &= ~RADEON_IS_AGP;
  78                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  79                 } else {
  80                         rdev->mc.gtt_location = rdev->mc.agp_base;
  81                 }
  82         }
  83         r = radeon_mc_setup(rdev);
  84         if (r) {
  85                 return r;
  86         }
  87
  88         /* Program GPU memory space */
  89         rs600_mc_disable_clients(rdev);
  90         if (r520_mc_wait_for_idle(rdev)) {
  91                 printk(KERN_WARNING "Failed to wait MC idle while "
  92                        "programming pipes. Bad things might happen.\n");
  93         }
  94         /* Write VRAM size in case we are limiting it */
  95         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
  96         tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
  97         tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16);
  98         tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16);
  99         WREG32_MC(R520_MC_FB_LOCATION, tmp);
 100         WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
 101         WREG32(0x310, rdev->mc.vram_location);
 102         if (rdev->flags & RADEON_IS_AGP) {
 103                 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 104                 tmp = REG_SET(R520_MC_AGP_TOP, tmp >> 16);
 105                 tmp |= REG_SET(R520_MC_AGP_START, rdev->mc.gtt_location >> 16);
 106                 WREG32_MC(R520_MC_AGP_LOCATION, tmp);
 107                 WREG32_MC(R520_MC_AGP_BASE, rdev->mc.agp_base);
 108                 WREG32_MC(R520_MC_AGP_BASE_2, 0);
 109         } else {
 110                 WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF);
 111                 WREG32_MC(R520_MC_AGP_BASE, 0);
 112                 WREG32_MC(R520_MC_AGP_BASE_2, 0);
 113         }
 114         return 0;
 115 }
 116
 117 void r520_mc_fini(struct radeon_device *rdev)
 118 {
 119 }
 120
 121
 122 /*
 123  * Global GPU functions
 124  */
 125 void r520_errata(struct radeon_device *rdev)
 126 {
 127         rdev->pll_errata = 0;
 128 }
 129
 130 int r520_mc_wait_for_idle(struct radeon_device *rdev)
 131 {
 132         unsigned i;
 133         uint32_t tmp;
 134
 135         for (i = 0; i < rdev->usec_timeout; i++) {
 136                 /* read MC_STATUS */
 137                 tmp = RREG32_MC(R520_MC_STATUS);
 138                 if (tmp & R520_MC_STATUS_IDLE) {
 139                         return 0;
 140                 }
 141                 DRM_UDELAY(1);
 142         }
 143         return -1;
 144 }
 145
 146 void r520_gpu_init(struct radeon_device *rdev)
 147 {
 148         unsigned pipe_select_current, gb_pipe_select, tmp;
 149
 150         r100_hdp_reset(rdev);
 151         rs600_disable_vga(rdev);
 152         /*
 153          * DST_PIPE_CONFIG              0x170C
 154          * GB_TILE_CONFIG               0x4018
 155          * GB_FIFO_SIZE                 0x4024
 156          * GB_PIPE_SELECT               0x402C
 157          * GB_PIPE_SELECT2              0x4124
 158          *      Z_PIPE_SHIFT                    0
 159          *      Z_PIPE_MASK                     0x000000003
 160          * GB_FIFO_SIZE2                0x4128
 161          *      SC_SFIFO_SIZE_SHIFT             0
 162          *      SC_SFIFO_SIZE_MASK              0x000000003
 163          *      SC_MFIFO_SIZE_SHIFT             2
 164          *      SC_MFIFO_SIZE_MASK              0x00000000C
 165          *      FG_SFIFO_SIZE_SHIFT             4
 166          *      FG_SFIFO_SIZE_MASK              0x000000030
 167          *      ZB_MFIFO_SIZE_SHIFT             6
 168          *      ZB_MFIFO_SIZE_MASK              0x0000000C0
 169          * GA_ENHANCE                   0x4274
 170          * SU_REG_DEST                  0x42C8
 171          */
 172         /* workaround for RV530 */
 173         if (rdev->family == CHIP_RV530) {
 174                 WREG32(0x4128, 0xFF);
 175         }
 176         r420_pipes_init(rdev);
 177         gb_pipe_select = RREG32(0x402C);
 178         tmp = RREG32(0x170C);
 179         pipe_select_current = (tmp >> 2) & 3;
 180         tmp = (1 << pipe_select_current) |
 181               (((gb_pipe_select >> 8) & 0xF) << 4);
 182         WREG32_PLL(0x000D, tmp);
 183         if (r520_mc_wait_for_idle(rdev)) {
 184                 printk(KERN_WARNING "Failed to wait MC idle while "
 185                        "programming pipes. Bad things might happen.\n");
 186         }
 187 }
 188
 189
 190 /*
 191  * VRAM info
 192  */
 193 static void r520_vram_get_type(struct radeon_device *rdev)
 194 {
 195         uint32_t tmp;
 196
 197         rdev->mc.vram_width = 128;
 198         rdev->mc.vram_is_ddr = true;
 199         tmp = RREG32_MC(R520_MC_CNTL0);
 200         switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
 201         case 0:
 202                 rdev->mc.vram_width = 32;
 203                 break;
 204         case 1:
 205                 rdev->mc.vram_width = 64;
 206                 break;
 207         case 2:
 208                 rdev->mc.vram_width = 128;
 209                 break;
 210         case 3:
 211                 rdev->mc.vram_width = 256;
 212                 break;
 213         default:
 214                 rdev->mc.vram_width = 128;
 215                 break;
 216         }
 217         if (tmp & R520_MC_CHANNEL_SIZE)
 218                 rdev->mc.vram_width *= 2;
 219 }
 220
 221 void r520_vram_info(struct radeon_device *rdev)
 222 {
 223         fixed20_12 a;
 224
 225         r520_vram_get_type(rdev);
 226
 227         r100_vram_init_sizes(rdev);
 228         /* FIXME: we should enforce default clock in case GPU is not in
 229          * default setup
 230          */
 231         a.full = rfixed_const(100);
 232         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 233         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 234 }
 235
 236 void r520_bandwidth_update(struct radeon_device *rdev)
 237 {
 238         rv515_bandwidth_avivo_update(rdev);
 239 }