2 * Device driver for the PMU on 68K-based Apple PowerBooks
4 * The VIA (versatile interface adapter) interfaces to the PMU,
5 * a 6805 microprocessor core whose primary function is to control
6 * battery charging and system power on the PowerBooks.
7 * The PMU also controls the ADB (Apple Desktop Bus) which connects
8 * to the keyboard and mouse, as well as the non-volatile RAM
9 * and the RTC (real time clock) chip.
11 * Adapted for 68K PMU by Joshua M. Thompson
13 * Based largely on the PowerMac PMU code by Paul Mackerras and
16 * Also based on the PMU driver from MkLinux by Apple Computer, Inc.
17 * and the Open Software Foundation, Inc.
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/kernel.h>
24 #include <linux/delay.h>
25 #include <linux/miscdevice.h>
26 #include <linux/blkdev.h>
27 #include <linux/pci.h>
28 #include <linux/slab.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
32 #include <linux/adb.h>
33 #include <linux/pmu.h>
34 #include <linux/cuda.h>
36 #include <asm/macintosh.h>
37 #include <asm/macints.h>
38 #include <asm/mac_via.h>
40 #include <asm/pgtable.h>
41 #include <asm/system.h>
43 #include <asm/uaccess.h>
45 /* Misc minor number allocated for /dev/pmu */
48 /* VIA registers - spaced 0x200 bytes apart */
49 #define RS 0x200 /* skip between registers */
50 #define B 0 /* B-side data */
51 #define A RS /* A-side data */
52 #define DIRB (2*RS) /* B-side direction (1=output) */
53 #define DIRA (3*RS) /* A-side direction (1=output) */
54 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
55 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
56 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
57 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
58 #define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */
59 #define T2CH (9*RS) /* Timer 2 counter (high 8 bits) */
60 #define SR (10*RS) /* Shift register */
61 #define ACR (11*RS) /* Auxiliary control register */
62 #define PCR (12*RS) /* Peripheral control register */
63 #define IFR (13*RS) /* Interrupt flag register */
64 #define IER (14*RS) /* Interrupt enable register */
65 #define ANH (15*RS) /* A-side data, no handshake */
67 /* Bits in B data register: both active low */
68 #define TACK 0x02 /* Transfer acknowledge (input) */
69 #define TREQ 0x04 /* Transfer request (output) */
72 #define SR_CTRL 0x1c /* Shift register control bits */
73 #define SR_EXT 0x0c /* Shift on external clock */
74 #define SR_OUT 0x10 /* Shift out if 1 */
76 /* Bits in IFR and IER */
77 #define SR_INT 0x04 /* Shift register full/empty */
78 #define CB1_INT 0x10 /* transition on CB1 input */
80 static enum pmu_state
{
88 static struct adb_request
*current_req
;
89 static struct adb_request
*last_req
;
90 static struct adb_request
*req_awaiting_reply
;
91 static unsigned char interrupt_data
[32];
92 static unsigned char *reply_ptr
;
93 static int data_index
;
95 static int adb_int_pending
;
96 static int pmu_adb_flags
;
97 static int adb_dev_map
;
98 static struct adb_request bright_req_1
, bright_req_2
, bright_req_3
;
99 static int pmu_kind
= PMU_UNKNOWN
;
100 static int pmu_fully_inited
;
104 static int pmu_probe(void);
105 static int pmu_init(void);
106 static void pmu_start(void);
107 static irqreturn_t
pmu_interrupt(int irq
, void *arg
);
108 static int pmu_send_request(struct adb_request
*req
, int sync
);
109 static int pmu_autopoll(int devs
);
111 static int pmu_reset_bus(void);
113 static void pmu_start(void);
114 static void send_byte(int x
);
115 static void recv_byte(void);
116 static void pmu_done(struct adb_request
*req
);
117 static void pmu_handle_data(unsigned char *data
, int len
);
118 static void set_volume(int level
);
119 static void pmu_enable_backlight(int on
);
120 static void pmu_set_brightness(int level
);
122 struct adb_driver via_pmu_driver
= {
133 * This table indicates for each PMU opcode:
134 * - the number of data bytes to be sent with the command, or -1
135 * if a length byte should be sent,
136 * - the number of response bytes which the PMU will return, or
137 * -1 if it will send a length byte.
139 static s8 pmu_data_len
[256][2] = {
140 /* 0 1 2 3 4 5 6 7 */
141 /*00*/ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
142 /*08*/ {-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
143 /*10*/ { 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
144 /*18*/ { 0, 1},{ 0, 1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{ 0, 0},
145 /*20*/ {-1, 0},{ 0, 0},{ 2, 0},{ 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},
146 /*28*/ { 0,-1},{ 0,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{ 0,-1},
147 /*30*/ { 4, 0},{20, 0},{-1, 0},{ 3, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
148 /*38*/ { 0, 4},{ 0,20},{ 2,-1},{ 2, 1},{ 3,-1},{-1,-1},{-1,-1},{ 4, 0},
149 /*40*/ { 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
150 /*48*/ { 0, 1},{ 0, 1},{-1,-1},{ 1, 0},{ 1, 0},{-1,-1},{-1,-1},{-1,-1},
151 /*50*/ { 1, 0},{ 0, 0},{ 2, 0},{ 2, 0},{-1, 0},{ 1, 0},{ 3, 0},{ 1, 0},
152 /*58*/ { 0, 1},{ 1, 0},{ 0, 2},{ 0, 2},{ 0,-1},{-1,-1},{-1,-1},{-1,-1},
153 /*60*/ { 2, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
154 /*68*/ { 0, 3},{ 0, 3},{ 0, 2},{ 0, 8},{ 0,-1},{ 0,-1},{-1,-1},{-1,-1},
155 /*70*/ { 1, 0},{ 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
156 /*78*/ { 0,-1},{ 0,-1},{-1,-1},{-1,-1},{-1,-1},{ 5, 1},{ 4, 1},{ 4, 1},
157 /*80*/ { 4, 0},{-1, 0},{ 0, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
158 /*88*/ { 0, 5},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
159 /*90*/ { 1, 0},{ 2, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
160 /*98*/ { 0, 1},{ 0, 1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
161 /*a0*/ { 2, 0},{ 2, 0},{ 2, 0},{ 4, 0},{-1, 0},{ 0, 0},{-1, 0},{-1, 0},
162 /*a8*/ { 1, 1},{ 1, 0},{ 3, 0},{ 2, 0},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
163 /*b0*/ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
164 /*b8*/ {-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
165 /*c0*/ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
166 /*c8*/ {-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
167 /*d0*/ { 0, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
168 /*d8*/ { 1, 1},{ 1, 1},{-1,-1},{-1,-1},{ 0, 1},{ 0,-1},{-1,-1},{-1,-1},
169 /*e0*/ {-1, 0},{ 4, 0},{ 0, 1},{-1, 0},{-1, 0},{ 4, 0},{-1, 0},{-1, 0},
170 /*e8*/ { 3,-1},{-1,-1},{ 0, 1},{-1,-1},{ 0,-1},{-1,-1},{-1,-1},{ 0, 0},
171 /*f0*/ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
172 /*f8*/ {-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
177 if (macintosh_config
->adb_type
== MAC_ADB_PB1
) {
178 pmu_kind
= PMU_68K_V1
;
179 } else if (macintosh_config
->adb_type
== MAC_ADB_PB2
) {
180 pmu_kind
= PMU_68K_V2
;
194 volatile struct adb_request req
;
196 via2
[B
] |= TREQ
; /* negate TREQ */
197 via2
[DIRB
] = (via2
[DIRB
] | TREQ
) & ~TACK
; /* TACK in, TREQ out */
199 pmu_request((struct adb_request
*) &req
, NULL
, 2, PMU_SET_INTR_MASK
, PMU_INT_ADB
);
201 while (!req
.complete
) {
203 printk(KERN_ERR
"pmu_init: no response from PMU\n");
210 /* ack all pending interrupts */
212 interrupt_data
[0] = 1;
213 while (interrupt_data
[0] || pmu_state
!= idle
) {
215 printk(KERN_ERR
"pmu_init: timed out acking intrs\n");
218 if (pmu_state
== idle
) {
220 pmu_interrupt(0, NULL
);
226 pmu_request((struct adb_request
*) &req
, NULL
, 2, PMU_SET_INTR_MASK
,
227 PMU_INT_ADB_AUTO
|PMU_INT_SNDBRT
|PMU_INT_ADB
);
229 while (!req
.complete
) {
231 printk(KERN_ERR
"pmu_init: no response from PMU\n");
238 bright_req_1
.complete
= 1;
239 bright_req_2
.complete
= 1;
240 bright_req_3
.complete
= 1;
242 if (request_irq(IRQ_MAC_ADB_SR
, pmu_interrupt
, 0, "pmu-shift",
244 printk(KERN_ERR
"pmu_init: can't get irq %d\n",
248 if (request_irq(IRQ_MAC_ADB_CL
, pmu_interrupt
, 0, "pmu-clock",
250 printk(KERN_ERR
"pmu_init: can't get irq %d\n",
252 free_irq(IRQ_MAC_ADB_SR
, pmu_interrupt
);
256 pmu_fully_inited
= 1;
258 /* Enable backlight */
259 pmu_enable_backlight(1);
261 printk("adb: PMU 68K driver v0.5 for Unified ADB.\n");
272 /* Send an ADB command */
274 pmu_send_request(struct adb_request
*req
, int sync
)
278 if (!pmu_fully_inited
)
286 switch (req
->data
[0]) {
288 for (i
= 0; i
< req
->nbytes
- 1; ++i
)
289 req
->data
[i
] = req
->data
[i
+1];
291 if (pmu_data_len
[req
->data
[0]][1] != 0) {
292 req
->reply
[0] = ADB_RET_OK
;
296 ret
= pmu_queue_request(req
);
299 switch (req
->data
[1]) {
301 if (req
->nbytes
!= 2)
303 req
->data
[0] = PMU_READ_RTC
;
306 req
->reply
[0] = CUDA_PACKET
;
308 req
->reply
[2] = CUDA_GET_TIME
;
309 ret
= pmu_queue_request(req
);
312 if (req
->nbytes
!= 6)
314 req
->data
[0] = PMU_SET_RTC
;
316 for (i
= 1; i
<= 4; ++i
)
317 req
->data
[i
] = req
->data
[i
+1];
319 req
->reply
[0] = CUDA_PACKET
;
321 req
->reply
[2] = CUDA_SET_TIME
;
322 ret
= pmu_queue_request(req
);
325 if (req
->nbytes
!= 4)
327 req
->data
[0] = PMU_READ_NVRAM
;
328 req
->data
[1] = req
->data
[2];
329 req
->data
[2] = req
->data
[3];
332 req
->reply
[0] = CUDA_PACKET
;
334 req
->reply
[2] = CUDA_GET_PRAM
;
335 ret
= pmu_queue_request(req
);
338 if (req
->nbytes
!= 5)
340 req
->data
[0] = PMU_WRITE_NVRAM
;
341 req
->data
[1] = req
->data
[2];
342 req
->data
[2] = req
->data
[3];
343 req
->data
[3] = req
->data
[4];
346 req
->reply
[0] = CUDA_PACKET
;
348 req
->reply
[2] = CUDA_SET_PRAM
;
349 ret
= pmu_queue_request(req
);
354 for (i
= req
->nbytes
- 1; i
> 1; --i
)
355 req
->data
[i
+2] = req
->data
[i
];
356 req
->data
[3] = req
->nbytes
- 2;
357 req
->data
[2] = pmu_adb_flags
;
358 /*req->data[1] = req->data[1];*/
359 req
->data
[0] = PMU_ADB_CMD
;
361 req
->reply_expected
= 1;
363 ret
= pmu_queue_request(req
);
373 while (!req
->complete
)
380 /* Enable/disable autopolling */
382 pmu_autopoll(int devs
)
384 struct adb_request req
;
386 if (!pmu_fully_inited
) return -ENXIO
;
390 pmu_request(&req
, NULL
, 5, PMU_ADB_CMD
, 0, 0x86,
391 adb_dev_map
>> 8, adb_dev_map
);
394 pmu_request(&req
, NULL
, 1, PMU_ADB_POLL_OFF
);
397 while (!req
.complete
)
402 /* Reset the ADB bus */
406 struct adb_request req
;
408 int save_autopoll
= adb_dev_map
;
410 if (!pmu_fully_inited
) return -ENXIO
;
412 /* anyone got a better idea?? */
417 req
.data
[0] = PMU_ADB_CMD
;
419 req
.data
[2] = 3; /* ADB_BUSRESET ??? */
423 req
.reply_expected
= 1;
424 if (pmu_queue_request(&req
) != 0)
426 printk(KERN_ERR
"pmu_adb_reset_bus: pmu_queue_request failed\n");
429 while (!req
.complete
)
432 while (!req
.complete
) {
434 printk(KERN_ERR
"pmu_adb_reset_bus (reset): no response from PMU\n");
441 if (save_autopoll
!= 0)
442 pmu_autopoll(save_autopoll
);
447 /* Construct and send a pmu request */
449 pmu_request(struct adb_request
*req
, void (*done
)(struct adb_request
*),
455 if (nbytes
< 0 || nbytes
> 32) {
456 printk(KERN_ERR
"pmu_request: bad nbytes (%d)\n", nbytes
);
460 req
->nbytes
= nbytes
;
462 va_start(list
, nbytes
);
463 for (i
= 0; i
< nbytes
; ++i
)
464 req
->data
[i
] = va_arg(list
, int);
466 if (pmu_data_len
[req
->data
[0]][1] != 0) {
467 req
->reply
[0] = ADB_RET_OK
;
471 req
->reply_expected
= 0;
472 return pmu_queue_request(req
);
476 pmu_queue_request(struct adb_request
*req
)
481 if (req
->nbytes
<= 0) {
485 nsend
= pmu_data_len
[req
->data
[0]][0];
486 if (nsend
>= 0 && req
->nbytes
!= nsend
+ 1) {
494 local_irq_save(flags
);
496 if (current_req
!= 0) {
497 last_req
->next
= req
;
502 if (pmu_state
== idle
)
506 local_irq_restore(flags
);
513 via1
[ACR
] |= SR_CTRL
;
515 via2
[B
] &= ~TREQ
; /* assert TREQ */
523 via1
[ACR
] = (via1
[ACR
] | SR_EXT
) & ~SR_OUT
;
524 c
= via1
[SR
]; /* resets SR */
532 struct adb_request
*req
;
534 /* assert pmu_state == idle */
535 /* get the packet to send */
536 local_irq_save(flags
);
538 if (req
== 0 || pmu_state
!= idle
539 || (req
->reply_expected
&& req_awaiting_reply
))
544 data_len
= pmu_data_len
[req
->data
[0]][0];
546 /* set the shift register to shift out and send a byte */
547 send_byte(req
->data
[0]);
550 local_irq_restore(flags
);
558 local_irq_save(flags
);
559 if (via1
[IFR
] & SR_INT
) {
561 pmu_interrupt(IRQ_MAC_ADB_SR
, NULL
);
563 if (via1
[IFR
] & CB1_INT
) {
565 pmu_interrupt(IRQ_MAC_ADB_CL
, NULL
);
567 local_irq_restore(flags
);
571 pmu_interrupt(int irq
, void *dev_id
)
573 struct adb_request
*req
;
574 int timeout
, bite
= 0; /* to prevent compiler warning */
577 printk("pmu_interrupt: irq %d state %d acr %02X, b %02X data_index %d/%d adb_int_pending %d\n",
578 irq
, pmu_state
, (uint
) via1
[ACR
], (uint
) via2
[B
], data_index
, data_len
, adb_int_pending
);
581 if (irq
== IRQ_MAC_ADB_CL
) { /* CB1 interrupt */
583 } else if (irq
== IRQ_MAC_ADB_SR
) { /* SR interrupt */
584 if (via2
[B
] & TACK
) {
585 printk(KERN_DEBUG
"PMU: SR_INT but ack still high! (%x)\n", via2
[B
]);
588 /* if reading grab the byte */
589 if ((via1
[ACR
] & SR_OUT
) == 0) bite
= via1
[SR
];
591 /* reset TREQ and wait for TACK to go high */
594 while (!(via2
[B
] & TACK
)) {
596 printk(KERN_ERR
"PMU not responding (!ack)\n");
606 data_len
= req
->nbytes
- 1;
610 if (data_index
<= data_len
) {
611 send_byte(req
->data
[data_index
++]);
615 data_len
= pmu_data_len
[req
->data
[0]][1];
618 current_req
= req
->next
;
619 if (req
->reply_expected
)
620 req_awaiting_reply
= req
;
626 reply_ptr
= req
->reply
+ req
->reply_len
;
634 pmu_state
= reading_intr
;
635 reply_ptr
= interrupt_data
;
641 if (data_len
== -1) {
644 printk(KERN_ERR
"PMU: bad reply len %d\n",
647 reply_ptr
[data_index
++] = bite
;
649 if (data_index
< data_len
) {
654 if (pmu_state
== reading_intr
) {
655 pmu_handle_data(interrupt_data
, data_index
);
658 current_req
= req
->next
;
659 req
->reply_len
+= data_index
;
667 printk(KERN_ERR
"pmu_interrupt: unknown state %d?\n",
672 if (pmu_state
== idle
) {
673 if (adb_int_pending
) {
675 send_byte(PMU_INT_ACK
);
677 } else if (current_req
) {
683 printk("pmu_interrupt: exit state %d acr %02X, b %02X data_index %d/%d adb_int_pending %d\n",
684 pmu_state
, (uint
) via1
[ACR
], (uint
) via2
[B
], data_index
, data_len
, adb_int_pending
);
690 pmu_done(struct adb_request
*req
)
697 /* Interrupt data could be the result data from an ADB cmd */
699 pmu_handle_data(unsigned char *data
, int len
)
701 static int show_pmu_ints
= 1;
708 if (data
[0] & PMU_INT_ADB
) {
709 if ((data
[0] & PMU_INT_ADB_AUTO
) == 0) {
710 struct adb_request
*req
= req_awaiting_reply
;
712 printk(KERN_ERR
"PMU: extra ADB reply\n");
715 req_awaiting_reply
= NULL
;
719 memcpy(req
->reply
, data
+ 1, len
- 1);
720 req
->reply_len
= len
- 1;
724 adb_input(data
+1, len
-1, 1);
727 if (data
[0] == 0x08 && len
== 3) {
728 /* sound/brightness buttons pressed */
729 pmu_set_brightness(data
[1] >> 3);
731 } else if (show_pmu_ints
732 && !(data
[0] == PMU_INT_TICK
&& len
== 1)) {
734 printk(KERN_DEBUG
"pmu intr");
735 for (i
= 0; i
< len
; ++i
)
736 printk(" %.2x", data
[i
]);
742 static int backlight_level
= -1;
743 static int backlight_enabled
= 0;
745 #define LEVEL_TO_BRIGHT(lev) ((lev) < 1? 0x7f: 0x4a - ((lev) << 1))
748 pmu_enable_backlight(int on
)
750 struct adb_request req
;
753 /* first call: get current backlight value */
754 if (backlight_level
< 0) {
758 pmu_request(&req
, NULL
, 3, PMU_READ_NVRAM
, 0x14, 0xe);
759 while (!req
.complete
)
761 printk(KERN_DEBUG
"pmu: nvram returned bright: %d\n", (int)req
.reply
[1]);
762 backlight_level
= req
.reply
[1];
765 backlight_enabled
= 0;
769 pmu_request(&req
, NULL
, 2, PMU_BACKLIGHT_BRIGHT
,
770 LEVEL_TO_BRIGHT(backlight_level
));
771 while (!req
.complete
)
774 pmu_request(&req
, NULL
, 2, PMU_POWER_CTRL
,
775 PMU_POW_BACKLIGHT
| (on
? PMU_POW_ON
: PMU_POW_OFF
));
776 while (!req
.complete
)
778 backlight_enabled
= on
;
782 pmu_set_brightness(int level
)
786 backlight_level
= level
;
787 bright
= LEVEL_TO_BRIGHT(level
);
788 if (!backlight_enabled
)
790 if (bright_req_1
.complete
)
791 pmu_request(&bright_req_1
, NULL
, 2, PMU_BACKLIGHT_BRIGHT
,
793 if (bright_req_2
.complete
)
794 pmu_request(&bright_req_2
, NULL
, 2, PMU_POWER_CTRL
,
795 PMU_POW_BACKLIGHT
| (bright
< 0x7f ? PMU_POW_ON
: PMU_POW_OFF
));
799 pmu_enable_irled(int on
)
801 struct adb_request req
;
803 pmu_request(&req
, NULL
, 2, PMU_POWER_CTRL
, PMU_POW_IRLED
|
804 (on
? PMU_POW_ON
: PMU_POW_OFF
));
805 while (!req
.complete
)
810 set_volume(int level
)
817 return (pmu_kind
!= PMU_UNKNOWN
);