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IPVS: netns, misc init_net removal in core.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / sound / soc / codecs / tlv320dac33.c
blobc5ab8c8057714871e13ad249805f60877ff32f5d
1 /*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/pm.h>
29 #include <linux/i2c.h>
30 #include <linux/platform_device.h>
31 #include <linux/interrupt.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/slab.h>
35 #include <sound/core.h>
36 #include <sound/pcm.h>
37 #include <sound/pcm_params.h>
38 #include <sound/soc.h>
39 #include <sound/soc-dapm.h>
40 #include <sound/initval.h>
41 #include <sound/tlv.h>
42
43 #include <sound/tlv320dac33-plat.h>
44 #include "tlv320dac33.h"
45
46 #define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
47 * 6144 stereo */
48 #define DAC33_BUFFER_SIZE_SAMPLES 6144
49
50 #define NSAMPLE_MAX 5700
51
52 #define MODE7_LTHR 10
53 #define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
54
55 #define BURST_BASEFREQ_HZ 49152000
56
57 #define SAMPLES_TO_US(rate, samples) \
58 (1000000000 / ((rate * 1000) / samples))
59
60 #define US_TO_SAMPLES(rate, us) \
61 (rate / (1000000 / (us < 1000000 ? us : 1000000)))
62
63 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
64 ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
65
66 static void dac33_calculate_times(struct snd_pcm_substream *substream);
67 static int dac33_prepare_chip(struct snd_pcm_substream *substream);
68
69 enum dac33_state {
70 DAC33_IDLE = 0,
71 DAC33_PREFILL,
72 DAC33_PLAYBACK,
73 DAC33_FLUSH,
74 };
75
76 enum dac33_fifo_modes {
77 DAC33_FIFO_BYPASS = 0,
78 DAC33_FIFO_MODE1,
79 DAC33_FIFO_MODE7,
80 DAC33_FIFO_LAST_MODE,
81 };
82
83 #define DAC33_NUM_SUPPLIES 3
84 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
85 "AVDD",
86 "DVDD",
87 "IOVDD",
88 };
89
90 struct tlv320dac33_priv {
91 struct mutex mutex;
92 struct workqueue_struct *dac33_wq;
93 struct work_struct work;
94 struct snd_soc_codec *codec;
95 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
96 struct snd_pcm_substream *substream;
97 int power_gpio;
98 int chip_power;
99 int irq;
100 unsigned int refclk;
101
102 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
103 unsigned int nsample_min; /* nsample should not be lower than
104 * this */
105 unsigned int nsample_max; /* nsample should not be higher than
106 * this */
107 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
108 unsigned int nsample; /* burst read amount from host */
109 int mode1_latency; /* latency caused by the i2c writes in
110 * us */
111 int auto_fifo_config; /* Configure the FIFO based on the
112 * period size */
113 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
114 unsigned int burst_rate; /* Interface speed in Burst modes */
115
116 int keep_bclk; /* Keep the BCLK continuously running
117 * in FIFO modes */
118 spinlock_t lock;
119 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
120 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
121
122 unsigned int mode1_us_burst; /* Time to burst read n number of
123 * samples */
124 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
125
126 unsigned int uthr;
127
128 enum dac33_state state;
129 enum snd_soc_control_type control_type;
130 void *control_data;
131 };
132
133 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
134 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
135 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
136 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
137 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
138 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
139 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
140 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
141 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
142 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
143 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
144 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
145 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
146 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
147 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
148 0x00, 0x00, /* 0x38 - 0x39 */
149 /* Registers 0x3a - 0x3f are reserved */
150 0x00, 0x00, /* 0x3a - 0x3b */
151 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
152
153 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
154 0x00, 0x80, /* 0x44 - 0x45 */
155 /* Registers 0x46 - 0x47 are reserved */
156 0x80, 0x80, /* 0x46 - 0x47 */
157
158 0x80, 0x00, 0x00, /* 0x48 - 0x4a */
159 /* Registers 0x4b - 0x7c are reserved */
160 0x00, /* 0x4b */
161 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
162 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
163 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
164 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
165 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
166 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
167 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
168 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
169 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
170 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
171 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
172 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
173 0x00, /* 0x7c */
174
175 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
176 };
177
178 /* Register read and write */
179 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
180 unsigned reg)
181 {
182 u8 *cache = codec->reg_cache;
183 if (reg >= DAC33_CACHEREGNUM)
184 return 0;
185
186 return cache[reg];
187 }
188
189 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
190 u8 reg, u8 value)
191 {
192 u8 *cache = codec->reg_cache;
193 if (reg >= DAC33_CACHEREGNUM)
194 return;
195
196 cache[reg] = value;
197 }
198
199 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
200 u8 *value)
201 {
202 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
203 int val, ret = 0;
204
205 *value = reg & 0xff;
206
207 /* If powered off, return the cached value */
208 if (dac33->chip_power) {
209 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
210 if (val < 0) {
211 dev_err(codec->dev, "Read failed (%d)\n", val);
212 value[0] = dac33_read_reg_cache(codec, reg);
213 ret = val;
214 } else {
215 value[0] = val;
216 dac33_write_reg_cache(codec, reg, val);
217 }
218 } else {
219 value[0] = dac33_read_reg_cache(codec, reg);
220 }
221
222 return ret;
223 }
224
225 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
226 unsigned int value)
227 {
228 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
229 u8 data[2];
230 int ret = 0;
231
232 /*
233 * data is
234 * D15..D8 dac33 register offset
235 * D7...D0 register data
236 */
237 data[0] = reg & 0xff;
238 data[1] = value & 0xff;
239
240 dac33_write_reg_cache(codec, data[0], data[1]);
241 if (dac33->chip_power) {
242 ret = codec->hw_write(codec->control_data, data, 2);
243 if (ret != 2)
244 dev_err(codec->dev, "Write failed (%d)\n", ret);
245 else
246 ret = 0;
247 }
248
249 return ret;
250 }
251
252 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
253 unsigned int value)
254 {
255 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
256 int ret;
257
258 mutex_lock(&dac33->mutex);
259 ret = dac33_write(codec, reg, value);
260 mutex_unlock(&dac33->mutex);
261
262 return ret;
263 }
264
265 #define DAC33_I2C_ADDR_AUTOINC 0x80
266 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
267 unsigned int value)
268 {
269 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
270 u8 data[3];
271 int ret = 0;
272
273 /*
274 * data is
275 * D23..D16 dac33 register offset
276 * D15..D8 register data MSB
277 * D7...D0 register data LSB
278 */
279 data[0] = reg & 0xff;
280 data[1] = (value >> 8) & 0xff;
281 data[2] = value & 0xff;
282
283 dac33_write_reg_cache(codec, data[0], data[1]);
284 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
285
286 if (dac33->chip_power) {
287 /* We need to set autoincrement mode for 16 bit writes */
288 data[0] |= DAC33_I2C_ADDR_AUTOINC;
289 ret = codec->hw_write(codec->control_data, data, 3);
290 if (ret != 3)
291 dev_err(codec->dev, "Write failed (%d)\n", ret);
292 else
293 ret = 0;
294 }
295
296 return ret;
297 }
298
299 static void dac33_init_chip(struct snd_soc_codec *codec)
300 {
301 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
302
303 if (unlikely(!dac33->chip_power))
304 return;
305
306 /* 44-46: DAC Control Registers */
307 /* A : DAC sample rate Fsref/1.5 */
308 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
309 /* B : DAC src=normal, not muted */
310 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
311 DAC33_DACSRCL_LEFT);
312 /* C : (defaults) */
313 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
314
315 /* 73 : volume soft stepping control,
316 clock source = internal osc (?) */
317 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
318
319 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
320
321 /* Restore only selected registers (gains mostly) */
322 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
323 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
324 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
325 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
326
327 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
328 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
329 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
330 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
331 }
332
333 static inline int dac33_read_id(struct snd_soc_codec *codec)
334 {
335 int i, ret = 0;
336 u8 reg;
337
338 for (i = 0; i < 3; i++) {
339 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, &reg);
340 if (ret < 0)
341 break;
342 }
343
344 return ret;
345 }
346
347 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
348 {
349 u8 reg;
350
351 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
352 if (power)
353 reg |= DAC33_PDNALLB;
354 else
355 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
356 DAC33_DACRPDNB | DAC33_DACLPDNB);
357 dac33_write(codec, DAC33_PWR_CTRL, reg);
358 }
359
360 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
361 {
362 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
363 int ret = 0;
364
365 mutex_lock(&dac33->mutex);
366
367 /* Safety check */
368 if (unlikely(power == dac33->chip_power)) {
369 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
370 power ? "ON" : "OFF");
371 goto exit;
372 }
373
374 if (power) {
375 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
376 dac33->supplies);
377 if (ret != 0) {
378 dev_err(codec->dev,
379 "Failed to enable supplies: %d\n", ret);
380 goto exit;
381 }
382
383 if (dac33->power_gpio >= 0)
384 gpio_set_value(dac33->power_gpio, 1);
385
386 dac33->chip_power = 1;
387 } else {
388 dac33_soft_power(codec, 0);
389 if (dac33->power_gpio >= 0)
390 gpio_set_value(dac33->power_gpio, 0);
391
392 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
393 dac33->supplies);
394 if (ret != 0) {
395 dev_err(codec->dev,
396 "Failed to disable supplies: %d\n", ret);
397 goto exit;
398 }
399
400 dac33->chip_power = 0;
401 }
402
403 exit:
404 mutex_unlock(&dac33->mutex);
405 return ret;
406 }
407
408 static int playback_event(struct snd_soc_dapm_widget *w,
409 struct snd_kcontrol *kcontrol, int event)
410 {
411 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
412
413 switch (event) {
414 case SND_SOC_DAPM_PRE_PMU:
415 if (likely(dac33->substream)) {
416 dac33_calculate_times(dac33->substream);
417 dac33_prepare_chip(dac33->substream);
418 }
419 break;
420 }
421 return 0;
422 }
423
424 static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
425 struct snd_ctl_elem_value *ucontrol)
426 {
427 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
428 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
429
430 ucontrol->value.integer.value[0] = dac33->nsample;
431
432 return 0;
433 }
434
435 static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
436 struct snd_ctl_elem_value *ucontrol)
437 {
438 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
439 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
440 int ret = 0;
441
442 if (dac33->nsample == ucontrol->value.integer.value[0])
443 return 0;
444
445 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
446 ucontrol->value.integer.value[0] > dac33->nsample_max) {
447 ret = -EINVAL;
448 } else {
449 dac33->nsample = ucontrol->value.integer.value[0];
450 /* Re calculate the burst time */
451 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
452 dac33->nsample);
453 }
454
455 return ret;
456 }
457
458 static int dac33_get_uthr(struct snd_kcontrol *kcontrol,
459 struct snd_ctl_elem_value *ucontrol)
460 {
461 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
462 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
463
464 ucontrol->value.integer.value[0] = dac33->uthr;
465
466 return 0;
467 }
468
469 static int dac33_set_uthr(struct snd_kcontrol *kcontrol,
470 struct snd_ctl_elem_value *ucontrol)
471 {
472 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
473 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
474 int ret = 0;
475
476 if (dac33->substream)
477 return -EBUSY;
478
479 if (dac33->uthr == ucontrol->value.integer.value[0])
480 return 0;
481
482 if (ucontrol->value.integer.value[0] < (MODE7_LTHR + 10) ||
483 ucontrol->value.integer.value[0] > MODE7_UTHR)
484 ret = -EINVAL;
485 else
486 dac33->uthr = ucontrol->value.integer.value[0];
487
488 return ret;
489 }
490
491 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
492 struct snd_ctl_elem_value *ucontrol)
493 {
494 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
495 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
496
497 ucontrol->value.integer.value[0] = dac33->fifo_mode;
498
499 return 0;
500 }
501
502 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
503 struct snd_ctl_elem_value *ucontrol)
504 {
505 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
506 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
507 int ret = 0;
508
509 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
510 return 0;
511 /* Do not allow changes while stream is running*/
512 if (codec->active)
513 return -EPERM;
514
515 if (ucontrol->value.integer.value[0] < 0 ||
516 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
517 ret = -EINVAL;
518 else
519 dac33->fifo_mode = ucontrol->value.integer.value[0];
520
521 return ret;
522 }
523
524 /* Codec operation modes */
525 static const char *dac33_fifo_mode_texts[] = {
526 "Bypass", "Mode 1", "Mode 7"
527 };
528
529 static const struct soc_enum dac33_fifo_mode_enum =
530 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
531 dac33_fifo_mode_texts);
532
533 /* L/R Line Output Gain */
534 static const char *lr_lineout_gain_texts[] = {
535 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
536 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
537 };
538
539 static const struct soc_enum l_lineout_gain_enum =
540 SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0,
541 ARRAY_SIZE(lr_lineout_gain_texts),
542 lr_lineout_gain_texts);
543
544 static const struct soc_enum r_lineout_gain_enum =
545 SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0,
546 ARRAY_SIZE(lr_lineout_gain_texts),
547 lr_lineout_gain_texts);
548
549 /*
550 * DACL/R digital volume control:
551 * from 0 dB to -63.5 in 0.5 dB steps
552 * Need to be inverted later on:
553 * 0x00 == 0 dB
554 * 0x7f == -63.5 dB
555 */
556 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
557
558 static const struct snd_kcontrol_new dac33_snd_controls[] = {
559 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
560 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
561 0, 0x7f, 1, dac_digivol_tlv),
562 SOC_DOUBLE_R("DAC Digital Playback Switch",
563 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
564 SOC_DOUBLE_R("Line to Line Out Volume",
565 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
566 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
567 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
568 };
569
570 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
571 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
572 dac33_get_fifo_mode, dac33_set_fifo_mode),
573 };
574
575 static const struct snd_kcontrol_new dac33_fifo_snd_controls[] = {
576 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
577 dac33_get_nsample, dac33_set_nsample),
578 SOC_SINGLE_EXT("UTHR", 0, 0, MODE7_UTHR, 0,
579 dac33_get_uthr, dac33_set_uthr),
580 };
581
582 /* Analog bypass */
583 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
584 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
585
586 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
587 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
588
589 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
590 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
591 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
592
593 SND_SOC_DAPM_INPUT("LINEL"),
594 SND_SOC_DAPM_INPUT("LINER"),
595
596 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
597 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
598
599 /* Analog bypass */
600 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
601 &dac33_dapm_abypassl_control),
602 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
603 &dac33_dapm_abypassr_control),
604
605 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
606 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
607 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
608 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
609
610 SND_SOC_DAPM_PRE("Prepare Playback", playback_event),
611 };
612
613 static const struct snd_soc_dapm_route audio_map[] = {
614 /* Analog bypass */
615 {"Analog Left Bypass", "Switch", "LINEL"},
616 {"Analog Right Bypass", "Switch", "LINER"},
617
618 {"Output Left Amp Power", NULL, "DACL"},
619 {"Output Right Amp Power", NULL, "DACR"},
620
621 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
622 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
623
624 /* output */
625 {"LEFT_LO", NULL, "Output Left Amp Power"},
626 {"RIGHT_LO", NULL, "Output Right Amp Power"},
627 };
628
629 static int dac33_add_widgets(struct snd_soc_codec *codec)
630 {
631 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
632 ARRAY_SIZE(dac33_dapm_widgets));
633
634 /* set up audio path interconnects */
635 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
636
637 return 0;
638 }
639
640 static int dac33_set_bias_level(struct snd_soc_codec *codec,
641 enum snd_soc_bias_level level)
642 {
643 int ret;
644
645 switch (level) {
646 case SND_SOC_BIAS_ON:
647 dac33_soft_power(codec, 1);
648 break;
649 case SND_SOC_BIAS_PREPARE:
650 break;
651 case SND_SOC_BIAS_STANDBY:
652 if (codec->bias_level == SND_SOC_BIAS_OFF) {
653 /* Coming from OFF, switch on the codec */
654 ret = dac33_hard_power(codec, 1);
655 if (ret != 0)
656 return ret;
657
658 dac33_init_chip(codec);
659 }
660 break;
661 case SND_SOC_BIAS_OFF:
662 /* Do not power off, when the codec is already off */
663 if (codec->bias_level == SND_SOC_BIAS_OFF)
664 return 0;
665 ret = dac33_hard_power(codec, 0);
666 if (ret != 0)
667 return ret;
668 break;
669 }
670 codec->bias_level = level;
671
672 return 0;
673 }
674
675 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
676 {
677 struct snd_soc_codec *codec = dac33->codec;
678 unsigned int delay;
679
680 switch (dac33->fifo_mode) {
681 case DAC33_FIFO_MODE1:
682 dac33_write16(codec, DAC33_NSAMPLE_MSB,
683 DAC33_THRREG(dac33->nsample));
684
685 /* Take the timestamps */
686 spin_lock_irq(&dac33->lock);
687 dac33->t_stamp2 = ktime_to_us(ktime_get());
688 dac33->t_stamp1 = dac33->t_stamp2;
689 spin_unlock_irq(&dac33->lock);
690
691 dac33_write16(codec, DAC33_PREFILL_MSB,
692 DAC33_THRREG(dac33->alarm_threshold));
693 /* Enable Alarm Threshold IRQ with a delay */
694 delay = SAMPLES_TO_US(dac33->burst_rate,
695 dac33->alarm_threshold) + 1000;
696 usleep_range(delay, delay + 500);
697 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
698 break;
699 case DAC33_FIFO_MODE7:
700 /* Take the timestamp */
701 spin_lock_irq(&dac33->lock);
702 dac33->t_stamp1 = ktime_to_us(ktime_get());
703 /* Move back the timestamp with drain time */
704 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
705 spin_unlock_irq(&dac33->lock);
706
707 dac33_write16(codec, DAC33_PREFILL_MSB,
708 DAC33_THRREG(MODE7_LTHR));
709
710 /* Enable Upper Threshold IRQ */
711 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
712 break;
713 default:
714 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
715 dac33->fifo_mode);
716 break;
717 }
718 }
719
720 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
721 {
722 struct snd_soc_codec *codec = dac33->codec;
723
724 switch (dac33->fifo_mode) {
725 case DAC33_FIFO_MODE1:
726 /* Take the timestamp */
727 spin_lock_irq(&dac33->lock);
728 dac33->t_stamp2 = ktime_to_us(ktime_get());
729 spin_unlock_irq(&dac33->lock);
730
731 dac33_write16(codec, DAC33_NSAMPLE_MSB,
732 DAC33_THRREG(dac33->nsample));
733 break;
734 case DAC33_FIFO_MODE7:
735 /* At the moment we are not using interrupts in mode7 */
736 break;
737 default:
738 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
739 dac33->fifo_mode);
740 break;
741 }
742 }
743
744 static void dac33_work(struct work_struct *work)
745 {
746 struct snd_soc_codec *codec;
747 struct tlv320dac33_priv *dac33;
748 u8 reg;
749
750 dac33 = container_of(work, struct tlv320dac33_priv, work);
751 codec = dac33->codec;
752
753 mutex_lock(&dac33->mutex);
754 switch (dac33->state) {
755 case DAC33_PREFILL:
756 dac33->state = DAC33_PLAYBACK;
757 dac33_prefill_handler(dac33);
758 break;
759 case DAC33_PLAYBACK:
760 dac33_playback_handler(dac33);
761 break;
762 case DAC33_IDLE:
763 break;
764 case DAC33_FLUSH:
765 dac33->state = DAC33_IDLE;
766 /* Mask all interrupts from dac33 */
767 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
768
769 /* flush fifo */
770 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
771 reg |= DAC33_FIFOFLUSH;
772 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
773 break;
774 }
775 mutex_unlock(&dac33->mutex);
776 }
777
778 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
779 {
780 struct snd_soc_codec *codec = dev;
781 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
782
783 spin_lock(&dac33->lock);
784 dac33->t_stamp1 = ktime_to_us(ktime_get());
785 spin_unlock(&dac33->lock);
786
787 /* Do not schedule the workqueue in Mode7 */
788 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
789 queue_work(dac33->dac33_wq, &dac33->work);
790
791 return IRQ_HANDLED;
792 }
793
794 static void dac33_oscwait(struct snd_soc_codec *codec)
795 {
796 int timeout = 60;
797 u8 reg;
798
799 do {
800 usleep_range(1000, 2000);
801 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
802 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
803 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
804 dev_err(codec->dev,
805 "internal oscillator calibration failed\n");
806 }
807
808 static int dac33_startup(struct snd_pcm_substream *substream,
809 struct snd_soc_dai *dai)
810 {
811 struct snd_soc_pcm_runtime *rtd = substream->private_data;
812 struct snd_soc_codec *codec = rtd->codec;
813 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
814
815 /* Stream started, save the substream pointer */
816 dac33->substream = substream;
817
818 return 0;
819 }
820
821 static void dac33_shutdown(struct snd_pcm_substream *substream,
822 struct snd_soc_dai *dai)
823 {
824 struct snd_soc_pcm_runtime *rtd = substream->private_data;
825 struct snd_soc_codec *codec = rtd->codec;
826 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
827
828 dac33->substream = NULL;
829
830 /* Reset the nSample restrictions */
831 dac33->nsample_min = 0;
832 dac33->nsample_max = NSAMPLE_MAX;
833 }
834
835 static int dac33_hw_params(struct snd_pcm_substream *substream,
836 struct snd_pcm_hw_params *params,
837 struct snd_soc_dai *dai)
838 {
839 struct snd_soc_pcm_runtime *rtd = substream->private_data;
840 struct snd_soc_codec *codec = rtd->codec;
841
842 /* Check parameters for validity */
843 switch (params_rate(params)) {
844 case 44100:
845 case 48000:
846 break;
847 default:
848 dev_err(codec->dev, "unsupported rate %d\n",
849 params_rate(params));
850 return -EINVAL;
851 }
852
853 switch (params_format(params)) {
854 case SNDRV_PCM_FORMAT_S16_LE:
855 break;
856 default:
857 dev_err(codec->dev, "unsupported format %d\n",
858 params_format(params));
859 return -EINVAL;
860 }
861
862 return 0;
863 }
864
865 #define CALC_OSCSET(rate, refclk) ( \
866 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
867 #define CALC_RATIOSET(rate, refclk) ( \
868 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
869
870 /*
871 * tlv320dac33 is strict on the sequence of the register writes, if the register
872 * writes happens in different order, than dac33 might end up in unknown state.
873 * Use the known, working sequence of register writes to initialize the dac33.
874 */
875 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
876 {
877 struct snd_soc_pcm_runtime *rtd = substream->private_data;
878 struct snd_soc_codec *codec = rtd->codec;
879 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
880 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
881 u8 aictrl_a, aictrl_b, fifoctrl_a;
882
883 switch (substream->runtime->rate) {
884 case 44100:
885 case 48000:
886 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
887 ratioset = CALC_RATIOSET(substream->runtime->rate,
888 dac33->refclk);
889 break;
890 default:
891 dev_err(codec->dev, "unsupported rate %d\n",
892 substream->runtime->rate);
893 return -EINVAL;
894 }
895
896
897 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
898 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
899 /* Read FIFO control A, and clear FIFO flush bit */
900 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
901 fifoctrl_a &= ~DAC33_FIFOFLUSH;
902
903 fifoctrl_a &= ~DAC33_WIDTH;
904 switch (substream->runtime->format) {
905 case SNDRV_PCM_FORMAT_S16_LE:
906 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
907 fifoctrl_a |= DAC33_WIDTH;
908 break;
909 default:
910 dev_err(codec->dev, "unsupported format %d\n",
911 substream->runtime->format);
912 return -EINVAL;
913 }
914
915 mutex_lock(&dac33->mutex);
916
917 if (!dac33->chip_power) {
918 /*
919 * Chip is not powered yet.
920 * Do the init in the dac33_set_bias_level later.
921 */
922 mutex_unlock(&dac33->mutex);
923 return 0;
924 }
925
926 dac33_soft_power(codec, 0);
927 dac33_soft_power(codec, 1);
928
929 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
930 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
931
932 /* Write registers 0x08 and 0x09 (MSB, LSB) */
933 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
934
935 /* calib time: 128 is a nice number ;) */
936 dac33_write(codec, DAC33_CALIB_TIME, 128);
937
938 /* adjustment treshold & step */
939 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
940 DAC33_ADJSTEP(1));
941
942 /* div=4 / gain=1 / div */
943 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
944
945 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
946 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
947 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
948
949 dac33_oscwait(codec);
950
951 if (dac33->fifo_mode) {
952 /* Generic for all FIFO modes */
953 /* 50-51 : ASRC Control registers */
954 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
955 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
956
957 /* Write registers 0x34 and 0x35 (MSB, LSB) */
958 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
959
960 /* Set interrupts to high active */
961 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
962 } else {
963 /* FIFO bypass mode */
964 /* 50-51 : ASRC Control registers */
965 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
966 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
967 }
968
969 /* Interrupt behaviour configuration */
970 switch (dac33->fifo_mode) {
971 case DAC33_FIFO_MODE1:
972 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
973 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
974 break;
975 case DAC33_FIFO_MODE7:
976 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
977 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
978 break;
979 default:
980 /* in FIFO bypass mode, the interrupts are not used */
981 break;
982 }
983
984 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
985
986 switch (dac33->fifo_mode) {
987 case DAC33_FIFO_MODE1:
988 /*
989 * For mode1:
990 * Disable the FIFO bypass (Enable the use of FIFO)
991 * Select nSample mode
992 * BCLK is only running when data is needed by DAC33
993 */
994 fifoctrl_a &= ~DAC33_FBYPAS;
995 fifoctrl_a &= ~DAC33_FAUTO;
996 if (dac33->keep_bclk)
997 aictrl_b |= DAC33_BCLKON;
998 else
999 aictrl_b &= ~DAC33_BCLKON;
1000 break;
1001 case DAC33_FIFO_MODE7:
1002 /*
1003 * For mode1:
1004 * Disable the FIFO bypass (Enable the use of FIFO)
1005 * Select Threshold mode
1006 * BCLK is only running when data is needed by DAC33
1007 */
1008 fifoctrl_a &= ~DAC33_FBYPAS;
1009 fifoctrl_a |= DAC33_FAUTO;
1010 if (dac33->keep_bclk)
1011 aictrl_b |= DAC33_BCLKON;
1012 else
1013 aictrl_b &= ~DAC33_BCLKON;
1014 break;
1015 default:
1016 /*
1017 * For FIFO bypass mode:
1018 * Enable the FIFO bypass (Disable the FIFO use)
1019 * Set the BCLK as continous
1020 */
1021 fifoctrl_a |= DAC33_FBYPAS;
1022 aictrl_b |= DAC33_BCLKON;
1023 break;
1024 }
1025
1026 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
1027 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1028 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1029
1030 /*
1031 * BCLK divide ratio
1032 * 0: 1.5
1033 * 1: 1
1034 * 2: 2
1035 * ...
1036 * 254: 254
1037 * 255: 255
1038 */
1039 if (dac33->fifo_mode)
1040 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1041 dac33->burst_bclkdiv);
1042 else
1043 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
1044
1045 switch (dac33->fifo_mode) {
1046 case DAC33_FIFO_MODE1:
1047 dac33_write16(codec, DAC33_ATHR_MSB,
1048 DAC33_THRREG(dac33->alarm_threshold));
1049 break;
1050 case DAC33_FIFO_MODE7:
1051 /*
1052 * Configure the threshold levels, and leave 10 sample space
1053 * at the bottom, and also at the top of the FIFO
1054 */
1055 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
1056 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
1057 break;
1058 default:
1059 break;
1060 }
1061
1062 mutex_unlock(&dac33->mutex);
1063
1064 return 0;
1065 }
1066
1067 static void dac33_calculate_times(struct snd_pcm_substream *substream)
1068 {
1069 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1070 struct snd_soc_codec *codec = rtd->codec;
1071 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1072 unsigned int period_size = substream->runtime->period_size;
1073 unsigned int rate = substream->runtime->rate;
1074 unsigned int nsample_limit;
1075
1076 /* In bypass mode we don't need to calculate */
1077 if (!dac33->fifo_mode)
1078 return;
1079
1080 switch (dac33->fifo_mode) {
1081 case DAC33_FIFO_MODE1:
1082 /* Number of samples under i2c latency */
1083 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1084 dac33->mode1_latency);
1085 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES -
1086 dac33->alarm_threshold;
1087
1088 if (dac33->auto_fifo_config) {
1089 if (period_size <= dac33->alarm_threshold)
1090 /*
1091 * Configure nSamaple to number of periods,
1092 * which covers the latency requironment.
1093 */
1094 dac33->nsample = period_size *
1095 ((dac33->alarm_threshold / period_size) +
1096 (dac33->alarm_threshold % period_size ?
1097 1 : 0));
1098 else if (period_size > nsample_limit)
1099 dac33->nsample = nsample_limit;
1100 else
1101 dac33->nsample = period_size;
1102 } else {
1103 /* nSample time shall not be shorter than i2c latency */
1104 dac33->nsample_min = dac33->alarm_threshold;
1105 /*
1106 * nSample should not be bigger than alsa buffer minus
1107 * size of one period to avoid overruns
1108 */
1109 dac33->nsample_max = substream->runtime->buffer_size -
1110 period_size;
1111
1112 if (dac33->nsample_max > nsample_limit)
1113 dac33->nsample_max = nsample_limit;
1114
1115 /* Correct the nSample if it is outside of the ranges */
1116 if (dac33->nsample < dac33->nsample_min)
1117 dac33->nsample = dac33->nsample_min;
1118 if (dac33->nsample > dac33->nsample_max)
1119 dac33->nsample = dac33->nsample_max;
1120 }
1121
1122 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1123 dac33->nsample);
1124 dac33->t_stamp1 = 0;
1125 dac33->t_stamp2 = 0;
1126 break;
1127 case DAC33_FIFO_MODE7:
1128 if (dac33->auto_fifo_config) {
1129 dac33->uthr = UTHR_FROM_PERIOD_SIZE(
1130 period_size,
1131 rate,
1132 dac33->burst_rate) + 9;
1133 if (dac33->uthr > MODE7_UTHR)
1134 dac33->uthr = MODE7_UTHR;
1135 if (dac33->uthr < (MODE7_LTHR + 10))
1136 dac33->uthr = (MODE7_LTHR + 10);
1137 }
1138 dac33->mode7_us_to_lthr =
1139 SAMPLES_TO_US(substream->runtime->rate,
1140 dac33->uthr - MODE7_LTHR + 1);
1141 dac33->t_stamp1 = 0;
1142 break;
1143 default:
1144 break;
1145 }
1146
1147 }
1148
1149 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1150 struct snd_soc_dai *dai)
1151 {
1152 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1153 struct snd_soc_codec *codec = rtd->codec;
1154 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1155 int ret = 0;
1156
1157 switch (cmd) {
1158 case SNDRV_PCM_TRIGGER_START:
1159 case SNDRV_PCM_TRIGGER_RESUME:
1160 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1161 if (dac33->fifo_mode) {
1162 dac33->state = DAC33_PREFILL;
1163 queue_work(dac33->dac33_wq, &dac33->work);
1164 }
1165 break;
1166 case SNDRV_PCM_TRIGGER_STOP:
1167 case SNDRV_PCM_TRIGGER_SUSPEND:
1168 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1169 if (dac33->fifo_mode) {
1170 dac33->state = DAC33_FLUSH;
1171 queue_work(dac33->dac33_wq, &dac33->work);
1172 }
1173 break;
1174 default:
1175 ret = -EINVAL;
1176 }
1177
1178 return ret;
1179 }
1180
1181 static snd_pcm_sframes_t dac33_dai_delay(
1182 struct snd_pcm_substream *substream,
1183 struct snd_soc_dai *dai)
1184 {
1185 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1186 struct snd_soc_codec *codec = rtd->codec;
1187 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1188 unsigned long long t0, t1, t_now;
1189 unsigned int time_delta, uthr;
1190 int samples_out, samples_in, samples;
1191 snd_pcm_sframes_t delay = 0;
1192
1193 switch (dac33->fifo_mode) {
1194 case DAC33_FIFO_BYPASS:
1195 break;
1196 case DAC33_FIFO_MODE1:
1197 spin_lock(&dac33->lock);
1198 t0 = dac33->t_stamp1;
1199 t1 = dac33->t_stamp2;
1200 spin_unlock(&dac33->lock);
1201 t_now = ktime_to_us(ktime_get());
1202
1203 /* We have not started to fill the FIFO yet, delay is 0 */
1204 if (!t1)
1205 goto out;
1206
1207 if (t0 > t1) {
1208 /*
1209 * Phase 1:
1210 * After Alarm threshold, and before nSample write
1211 */
1212 time_delta = t_now - t0;
1213 samples_out = time_delta ? US_TO_SAMPLES(
1214 substream->runtime->rate,
1215 time_delta) : 0;
1216
1217 if (likely(dac33->alarm_threshold > samples_out))
1218 delay = dac33->alarm_threshold - samples_out;
1219 else
1220 delay = 0;
1221 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1222 /*
1223 * Phase 2:
1224 * After nSample write (during burst operation)
1225 */
1226 time_delta = t_now - t0;
1227 samples_out = time_delta ? US_TO_SAMPLES(
1228 substream->runtime->rate,
1229 time_delta) : 0;
1230
1231 time_delta = t_now - t1;
1232 samples_in = time_delta ? US_TO_SAMPLES(
1233 dac33->burst_rate,
1234 time_delta) : 0;
1235
1236 samples = dac33->alarm_threshold;
1237 samples += (samples_in - samples_out);
1238
1239 if (likely(samples > 0))
1240 delay = samples;
1241 else
1242 delay = 0;
1243 } else {
1244 /*
1245 * Phase 3:
1246 * After burst operation, before next alarm threshold
1247 */
1248 time_delta = t_now - t0;
1249 samples_out = time_delta ? US_TO_SAMPLES(
1250 substream->runtime->rate,
1251 time_delta) : 0;
1252
1253 samples_in = dac33->nsample;
1254 samples = dac33->alarm_threshold;
1255 samples += (samples_in - samples_out);
1256
1257 if (likely(samples > 0))
1258 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1259 DAC33_BUFFER_SIZE_SAMPLES : samples;
1260 else
1261 delay = 0;
1262 }
1263 break;
1264 case DAC33_FIFO_MODE7:
1265 spin_lock(&dac33->lock);
1266 t0 = dac33->t_stamp1;
1267 uthr = dac33->uthr;
1268 spin_unlock(&dac33->lock);
1269 t_now = ktime_to_us(ktime_get());
1270
1271 /* We have not started to fill the FIFO yet, delay is 0 */
1272 if (!t0)
1273 goto out;
1274
1275 if (t_now <= t0) {
1276 /*
1277 * Either the timestamps are messed or equal. Report
1278 * maximum delay
1279 */
1280 delay = uthr;
1281 goto out;
1282 }
1283
1284 time_delta = t_now - t0;
1285 if (time_delta <= dac33->mode7_us_to_lthr) {
1286 /*
1287 * Phase 1:
1288 * After burst (draining phase)
1289 */
1290 samples_out = US_TO_SAMPLES(
1291 substream->runtime->rate,
1292 time_delta);
1293
1294 if (likely(uthr > samples_out))
1295 delay = uthr - samples_out;
1296 else
1297 delay = 0;
1298 } else {
1299 /*
1300 * Phase 2:
1301 * During burst operation
1302 */
1303 time_delta = time_delta - dac33->mode7_us_to_lthr;
1304
1305 samples_out = US_TO_SAMPLES(
1306 substream->runtime->rate,
1307 time_delta);
1308 samples_in = US_TO_SAMPLES(
1309 dac33->burst_rate,
1310 time_delta);
1311 delay = MODE7_LTHR + samples_in - samples_out;
1312
1313 if (unlikely(delay > uthr))
1314 delay = uthr;
1315 }
1316 break;
1317 default:
1318 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1319 dac33->fifo_mode);
1320 break;
1321 }
1322 out:
1323 return delay;
1324 }
1325
1326 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1327 int clk_id, unsigned int freq, int dir)
1328 {
1329 struct snd_soc_codec *codec = codec_dai->codec;
1330 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1331 u8 ioc_reg, asrcb_reg;
1332
1333 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1334 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1335 switch (clk_id) {
1336 case TLV320DAC33_MCLK:
1337 ioc_reg |= DAC33_REFSEL;
1338 asrcb_reg |= DAC33_SRCREFSEL;
1339 break;
1340 case TLV320DAC33_SLEEPCLK:
1341 ioc_reg &= ~DAC33_REFSEL;
1342 asrcb_reg &= ~DAC33_SRCREFSEL;
1343 break;
1344 default:
1345 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1346 break;
1347 }
1348 dac33->refclk = freq;
1349
1350 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1351 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1352
1353 return 0;
1354 }
1355
1356 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1357 unsigned int fmt)
1358 {
1359 struct snd_soc_codec *codec = codec_dai->codec;
1360 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1361 u8 aictrl_a, aictrl_b;
1362
1363 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1364 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1365 /* set master/slave audio interface */
1366 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1367 case SND_SOC_DAIFMT_CBM_CFM:
1368 /* Codec Master */
1369 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1370 break;
1371 case SND_SOC_DAIFMT_CBS_CFS:
1372 /* Codec Slave */
1373 if (dac33->fifo_mode) {
1374 dev_err(codec->dev, "FIFO mode requires master mode\n");
1375 return -EINVAL;
1376 } else
1377 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1378 break;
1379 default:
1380 return -EINVAL;
1381 }
1382
1383 aictrl_a &= ~DAC33_AFMT_MASK;
1384 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1385 case SND_SOC_DAIFMT_I2S:
1386 aictrl_a |= DAC33_AFMT_I2S;
1387 break;
1388 case SND_SOC_DAIFMT_DSP_A:
1389 aictrl_a |= DAC33_AFMT_DSP;
1390 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1391 aictrl_b |= DAC33_DATA_DELAY(0);
1392 break;
1393 case SND_SOC_DAIFMT_RIGHT_J:
1394 aictrl_a |= DAC33_AFMT_RIGHT_J;
1395 break;
1396 case SND_SOC_DAIFMT_LEFT_J:
1397 aictrl_a |= DAC33_AFMT_LEFT_J;
1398 break;
1399 default:
1400 dev_err(codec->dev, "Unsupported format (%u)\n",
1401 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1402 return -EINVAL;
1403 }
1404
1405 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1406 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1407
1408 return 0;
1409 }
1410
1411 static int dac33_soc_probe(struct snd_soc_codec *codec)
1412 {
1413 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1414 int ret = 0;
1415
1416 codec->control_data = dac33->control_data;
1417 codec->hw_write = (hw_write_t) i2c_master_send;
1418 codec->idle_bias_off = 1;
1419 dac33->codec = codec;
1420
1421 /* Read the tlv320dac33 ID registers */
1422 ret = dac33_hard_power(codec, 1);
1423 if (ret != 0) {
1424 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1425 goto err_power;
1426 }
1427 ret = dac33_read_id(codec);
1428 dac33_hard_power(codec, 0);
1429
1430 if (ret < 0) {
1431 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret);
1432 ret = -ENODEV;
1433 goto err_power;
1434 }
1435
1436 /* Check if the IRQ number is valid and request it */
1437 if (dac33->irq >= 0) {
1438 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1439 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1440 codec->name, codec);
1441 if (ret < 0) {
1442 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1443 dac33->irq, ret);
1444 dac33->irq = -1;
1445 }
1446 if (dac33->irq != -1) {
1447 /* Setup work queue */
1448 dac33->dac33_wq =
1449 create_singlethread_workqueue("tlv320dac33");
1450 if (dac33->dac33_wq == NULL) {
1451 free_irq(dac33->irq, codec);
1452 return -ENOMEM;
1453 }
1454
1455 INIT_WORK(&dac33->work, dac33_work);
1456 }
1457 }
1458
1459 snd_soc_add_controls(codec, dac33_snd_controls,
1460 ARRAY_SIZE(dac33_snd_controls));
1461 /* Only add the FIFO controls, if we have valid IRQ number */
1462 if (dac33->irq >= 0) {
1463 snd_soc_add_controls(codec, dac33_mode_snd_controls,
1464 ARRAY_SIZE(dac33_mode_snd_controls));
1465 /* FIFO usage controls only, if autoio config is not selected */
1466 if (!dac33->auto_fifo_config)
1467 snd_soc_add_controls(codec, dac33_fifo_snd_controls,
1468 ARRAY_SIZE(dac33_fifo_snd_controls));
1469 }
1470 dac33_add_widgets(codec);
1471
1472 err_power:
1473 return ret;
1474 }
1475
1476 static int dac33_soc_remove(struct snd_soc_codec *codec)
1477 {
1478 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1479
1480 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1481
1482 if (dac33->irq >= 0) {
1483 free_irq(dac33->irq, dac33->codec);
1484 destroy_workqueue(dac33->dac33_wq);
1485 }
1486 return 0;
1487 }
1488
1489 static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
1490 {
1491 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1492
1493 return 0;
1494 }
1495
1496 static int dac33_soc_resume(struct snd_soc_codec *codec)
1497 {
1498 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1499
1500 return 0;
1501 }
1502
1503 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1504 .read = dac33_read_reg_cache,
1505 .write = dac33_write_locked,
1506 .set_bias_level = dac33_set_bias_level,
1507 .reg_cache_size = ARRAY_SIZE(dac33_reg),
1508 .reg_word_size = sizeof(u8),
1509 .reg_cache_default = dac33_reg,
1510 .probe = dac33_soc_probe,
1511 .remove = dac33_soc_remove,
1512 .suspend = dac33_soc_suspend,
1513 .resume = dac33_soc_resume,
1514 };
1515
1516 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1517 SNDRV_PCM_RATE_48000)
1518 #define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1519
1520 static struct snd_soc_dai_ops dac33_dai_ops = {
1521 .startup = dac33_startup,
1522 .shutdown = dac33_shutdown,
1523 .hw_params = dac33_hw_params,
1524 .trigger = dac33_pcm_trigger,
1525 .delay = dac33_dai_delay,
1526 .set_sysclk = dac33_set_dai_sysclk,
1527 .set_fmt = dac33_set_dai_fmt,
1528 };
1529
1530 static struct snd_soc_dai_driver dac33_dai = {
1531 .name = "tlv320dac33-hifi",
1532 .playback = {
1533 .stream_name = "Playback",
1534 .channels_min = 2,
1535 .channels_max = 2,
1536 .rates = DAC33_RATES,
1537 .formats = DAC33_FORMATS,},
1538 .ops = &dac33_dai_ops,
1539 };
1540
1541 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1542 const struct i2c_device_id *id)
1543 {
1544 struct tlv320dac33_platform_data *pdata;
1545 struct tlv320dac33_priv *dac33;
1546 int ret, i;
1547
1548 if (client->dev.platform_data == NULL) {
1549 dev_err(&client->dev, "Platform data not set\n");
1550 return -ENODEV;
1551 }
1552 pdata = client->dev.platform_data;
1553
1554 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1555 if (dac33 == NULL)
1556 return -ENOMEM;
1557
1558 dac33->control_data = client;
1559 mutex_init(&dac33->mutex);
1560 spin_lock_init(&dac33->lock);
1561
1562 i2c_set_clientdata(client, dac33);
1563
1564 dac33->power_gpio = pdata->power_gpio;
1565 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1566 /* Pre calculate the burst rate */
1567 dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
1568 dac33->keep_bclk = pdata->keep_bclk;
1569 dac33->auto_fifo_config = pdata->auto_fifo_config;
1570 dac33->mode1_latency = pdata->mode1_latency;
1571 if (!dac33->mode1_latency)
1572 dac33->mode1_latency = 10000; /* 10ms */
1573 dac33->irq = client->irq;
1574 dac33->nsample = NSAMPLE_MAX;
1575 dac33->nsample_max = NSAMPLE_MAX;
1576 dac33->uthr = MODE7_UTHR;
1577 /* Disable FIFO use by default */
1578 dac33->fifo_mode = DAC33_FIFO_BYPASS;
1579
1580 /* Check if the reset GPIO number is valid and request it */
1581 if (dac33->power_gpio >= 0) {
1582 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1583 if (ret < 0) {
1584 dev_err(&client->dev,
1585 "Failed to request reset GPIO (%d)\n",
1586 dac33->power_gpio);
1587 goto err_gpio;
1588 }
1589 gpio_direction_output(dac33->power_gpio, 0);
1590 }
1591
1592 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1593 dac33->supplies[i].supply = dac33_supply_names[i];
1594
1595 ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
1596 dac33->supplies);
1597
1598 if (ret != 0) {
1599 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
1600 goto err_get;
1601 }
1602
1603 ret = snd_soc_register_codec(&client->dev,
1604 &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1605 if (ret < 0)
1606 goto err_register;
1607
1608 return ret;
1609 err_register:
1610 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1611 err_get:
1612 if (dac33->power_gpio >= 0)
1613 gpio_free(dac33->power_gpio);
1614 err_gpio:
1615 kfree(dac33);
1616 return ret;
1617 }
1618
1619 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1620 {
1621 struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
1622
1623 if (unlikely(dac33->chip_power))
1624 dac33_hard_power(dac33->codec, 0);
1625
1626 if (dac33->power_gpio >= 0)
1627 gpio_free(dac33->power_gpio);
1628
1629 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1630
1631 snd_soc_unregister_codec(&client->dev);
1632 kfree(dac33);
1633
1634 return 0;
1635 }
1636
1637 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1638 {
1639 .name = "tlv320dac33",
1640 .driver_data = 0,
1641 },
1642 { },
1643 };
1644
1645 static struct i2c_driver tlv320dac33_i2c_driver = {
1646 .driver = {
1647 .name = "tlv320dac33-codec",
1648 .owner = THIS_MODULE,
1649 },
1650 .probe = dac33_i2c_probe,
1651 .remove = __devexit_p(dac33_i2c_remove),
1652 .id_table = tlv320dac33_i2c_id,
1653 };
1654
1655 static int __init dac33_module_init(void)
1656 {
1657 int r;
1658 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1659 if (r < 0) {
1660 printk(KERN_ERR "DAC33: driver registration failed\n");
1661 return r;
1662 }
1663 return 0;
1664 }
1665 module_init(dac33_module_init);
1666
1667 static void __exit dac33_module_exit(void)
1668 {
1669 i2c_del_driver(&tlv320dac33_i2c_driver);
1670 }
1671 module_exit(dac33_module_exit);
1672
1673
1674 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1675 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1676 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree