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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
blob7216db218442b1fb2bdc0eaddb1c8f8927edf8d2
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <scsi/fc/fc_fcoe.h>
44
45 #include "ixgbe.h"
46 #include "ixgbe_common.h"
47 #include "ixgbe_dcb_82599.h"
48 #include "ixgbe_sriov.h"
49
50 char ixgbe_driver_name[] = "ixgbe";
51 static const char ixgbe_driver_string[] =
52 "Intel(R) 10 Gigabit PCI Express Network Driver";
53
54 #define DRV_VERSION "2.0.62-k2"
55 const char ixgbe_driver_version[] = DRV_VERSION;
56 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
57
58 static const struct ixgbe_info *ixgbe_info_tbl[] = {
59 [board_82598] = &ixgbe_82598_info,
60 [board_82599] = &ixgbe_82599_info,
61 };
62
63 /* ixgbe_pci_tbl - PCI Device ID Table
64 *
65 * Wildcard entries (PCI_ANY_ID) should come last
66 * Last entry must be all 0s
67 *
68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
69 * Class, Class Mask, private data (not used) }
70 */
71 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
73 board_82598 },
74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
75 board_82598 },
76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
77 board_82598 },
78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
79 board_82598 },
80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
81 board_82598 },
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
83 board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
85 board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
87 board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
89 board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
91 board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
93 board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
95 board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
97 board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
99 board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
101 board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
103 board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
105 board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
107 board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
109 board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
111 board_82599 },
112
113 /* required last entry */
114 {0, }
115 };
116 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
117
118 #ifdef CONFIG_IXGBE_DCA
119 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
120 void *p);
121 static struct notifier_block dca_notifier = {
122 .notifier_call = ixgbe_notify_dca,
123 .next = NULL,
124 .priority = 0
125 };
126 #endif
127
128 #ifdef CONFIG_PCI_IOV
129 static unsigned int max_vfs;
130 module_param(max_vfs, uint, 0);
131 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
132 "per physical function");
133 #endif /* CONFIG_PCI_IOV */
134
135 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
136 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
137 MODULE_LICENSE("GPL");
138 MODULE_VERSION(DRV_VERSION);
139
140 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
141
142 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
143 {
144 struct ixgbe_hw *hw = &adapter->hw;
145 u32 gcr;
146 u32 gpie;
147 u32 vmdctl;
148
149 #ifdef CONFIG_PCI_IOV
150 /* disable iov and allow time for transactions to clear */
151 pci_disable_sriov(adapter->pdev);
152 #endif
153
154 /* turn off device IOV mode */
155 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
156 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
157 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
158 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
159 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
160 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
161
162 /* set default pool back to 0 */
163 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
164 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
165 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
166
167 /* take a breather then clean up driver data */
168 msleep(100);
169 if (adapter->vfinfo)
170 kfree(adapter->vfinfo);
171 adapter->vfinfo = NULL;
172
173 adapter->num_vfs = 0;
174 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
175 }
176
177 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
178 {
179 u32 ctrl_ext;
180
181 /* Let firmware take over control of h/w */
182 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
183 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
184 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
185 }
186
187 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
188 {
189 u32 ctrl_ext;
190
191 /* Let firmware know the driver has taken over */
192 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
194 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
195 }
196
197 /*
198 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
199 * @adapter: pointer to adapter struct
200 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
201 * @queue: queue to map the corresponding interrupt to
202 * @msix_vector: the vector to map to the corresponding queue
203 *
204 */
205 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
206 u8 queue, u8 msix_vector)
207 {
208 u32 ivar, index;
209 struct ixgbe_hw *hw = &adapter->hw;
210 switch (hw->mac.type) {
211 case ixgbe_mac_82598EB:
212 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
213 if (direction == -1)
214 direction = 0;
215 index = (((direction * 64) + queue) >> 2) & 0x1F;
216 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
217 ivar &= ~(0xFF << (8 * (queue & 0x3)));
218 ivar |= (msix_vector << (8 * (queue & 0x3)));
219 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
220 break;
221 case ixgbe_mac_82599EB:
222 if (direction == -1) {
223 /* other causes */
224 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
225 index = ((queue & 1) * 8);
226 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
227 ivar &= ~(0xFF << index);
228 ivar |= (msix_vector << index);
229 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
230 break;
231 } else {
232 /* tx or rx causes */
233 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
234 index = ((16 * (queue & 1)) + (8 * direction));
235 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
236 ivar &= ~(0xFF << index);
237 ivar |= (msix_vector << index);
238 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
239 break;
240 }
241 default:
242 break;
243 }
244 }
245
246 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
247 u64 qmask)
248 {
249 u32 mask;
250
251 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
252 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
253 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
254 } else {
255 mask = (qmask & 0xFFFFFFFF);
256 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
257 mask = (qmask >> 32);
258 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
259 }
260 }
261
262 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
263 struct ixgbe_tx_buffer
264 *tx_buffer_info)
265 {
266 if (tx_buffer_info->dma) {
267 if (tx_buffer_info->mapped_as_page)
268 pci_unmap_page(adapter->pdev,
269 tx_buffer_info->dma,
270 tx_buffer_info->length,
271 PCI_DMA_TODEVICE);
272 else
273 pci_unmap_single(adapter->pdev,
274 tx_buffer_info->dma,
275 tx_buffer_info->length,
276 PCI_DMA_TODEVICE);
277 tx_buffer_info->dma = 0;
278 }
279 if (tx_buffer_info->skb) {
280 dev_kfree_skb_any(tx_buffer_info->skb);
281 tx_buffer_info->skb = NULL;
282 }
283 tx_buffer_info->time_stamp = 0;
284 /* tx_buffer_info must be completely set up in the transmit path */
285 }
286
287 /**
288 * ixgbe_tx_is_paused - check if the tx ring is paused
289 * @adapter: the ixgbe adapter
290 * @tx_ring: the corresponding tx_ring
291 *
292 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
293 * corresponding TC of this tx_ring when checking TFCS.
294 *
295 * Returns : true if paused
296 */
297 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
298 struct ixgbe_ring *tx_ring)
299 {
300 u32 txoff = IXGBE_TFCS_TXOFF;
301
302 #ifdef CONFIG_IXGBE_DCB
303 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
304 int tc;
305 int reg_idx = tx_ring->reg_idx;
306 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
307
308 switch (adapter->hw.mac.type) {
309 case ixgbe_mac_82598EB:
310 tc = reg_idx >> 2;
311 txoff = IXGBE_TFCS_TXOFF0;
312 break;
313 case ixgbe_mac_82599EB:
314 tc = 0;
315 txoff = IXGBE_TFCS_TXOFF;
316 if (dcb_i == 8) {
317 /* TC0, TC1 */
318 tc = reg_idx >> 5;
319 if (tc == 2) /* TC2, TC3 */
320 tc += (reg_idx - 64) >> 4;
321 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
322 tc += 1 + ((reg_idx - 96) >> 3);
323 } else if (dcb_i == 4) {
324 /* TC0, TC1 */
325 tc = reg_idx >> 6;
326 if (tc == 1) {
327 tc += (reg_idx - 64) >> 5;
328 if (tc == 2) /* TC2, TC3 */
329 tc += (reg_idx - 96) >> 4;
330 }
331 }
332 break;
333 default:
334 tc = 0;
335 }
336 txoff <<= tc;
337 }
338 #endif
339 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
340 }
341
342 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
343 struct ixgbe_ring *tx_ring,
344 unsigned int eop)
345 {
346 struct ixgbe_hw *hw = &adapter->hw;
347
348 /* Detect a transmit hang in hardware, this serializes the
349 * check with the clearing of time_stamp and movement of eop */
350 adapter->detect_tx_hung = false;
351 if (tx_ring->tx_buffer_info[eop].time_stamp &&
352 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
353 !ixgbe_tx_is_paused(adapter, tx_ring)) {
354 /* detected Tx unit hang */
355 union ixgbe_adv_tx_desc *tx_desc;
356 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
357 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
358 " Tx Queue <%d>\n"
359 " TDH, TDT <%x>, <%x>\n"
360 " next_to_use <%x>\n"
361 " next_to_clean <%x>\n"
362 "tx_buffer_info[next_to_clean]\n"
363 " time_stamp <%lx>\n"
364 " jiffies <%lx>\n",
365 tx_ring->queue_index,
366 IXGBE_READ_REG(hw, tx_ring->head),
367 IXGBE_READ_REG(hw, tx_ring->tail),
368 tx_ring->next_to_use, eop,
369 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
370 return true;
371 }
372
373 return false;
374 }
375
376 #define IXGBE_MAX_TXD_PWR 14
377 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
378
379 /* Tx Descriptors needed, worst case */
380 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
381 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
382 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
383 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
384
385 static void ixgbe_tx_timeout(struct net_device *netdev);
386
387 /**
388 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
389 * @q_vector: structure containing interrupt and ring information
390 * @tx_ring: tx ring to clean
391 **/
392 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
393 struct ixgbe_ring *tx_ring)
394 {
395 struct ixgbe_adapter *adapter = q_vector->adapter;
396 struct net_device *netdev = adapter->netdev;
397 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
398 struct ixgbe_tx_buffer *tx_buffer_info;
399 unsigned int i, eop, count = 0;
400 unsigned int total_bytes = 0, total_packets = 0;
401
402 i = tx_ring->next_to_clean;
403 eop = tx_ring->tx_buffer_info[i].next_to_watch;
404 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
405
406 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
407 (count < tx_ring->work_limit)) {
408 bool cleaned = false;
409 for ( ; !cleaned; count++) {
410 struct sk_buff *skb;
411 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
412 tx_buffer_info = &tx_ring->tx_buffer_info[i];
413 cleaned = (i == eop);
414 skb = tx_buffer_info->skb;
415
416 if (cleaned && skb) {
417 unsigned int segs, bytecount;
418 unsigned int hlen = skb_headlen(skb);
419
420 /* gso_segs is currently only valid for tcp */
421 segs = skb_shinfo(skb)->gso_segs ?: 1;
422 #ifdef IXGBE_FCOE
423 /* adjust for FCoE Sequence Offload */
424 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
425 && (skb->protocol == htons(ETH_P_FCOE)) &&
426 skb_is_gso(skb)) {
427 hlen = skb_transport_offset(skb) +
428 sizeof(struct fc_frame_header) +
429 sizeof(struct fcoe_crc_eof);
430 segs = DIV_ROUND_UP(skb->len - hlen,
431 skb_shinfo(skb)->gso_size);
432 }
433 #endif /* IXGBE_FCOE */
434 /* multiply data chunks by size of headers */
435 bytecount = ((segs - 1) * hlen) + skb->len;
436 total_packets += segs;
437 total_bytes += bytecount;
438 }
439
440 ixgbe_unmap_and_free_tx_resource(adapter,
441 tx_buffer_info);
442
443 tx_desc->wb.status = 0;
444
445 i++;
446 if (i == tx_ring->count)
447 i = 0;
448 }
449
450 eop = tx_ring->tx_buffer_info[i].next_to_watch;
451 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
452 }
453
454 tx_ring->next_to_clean = i;
455
456 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
457 if (unlikely(count && netif_carrier_ok(netdev) &&
458 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
459 /* Make sure that anybody stopping the queue after this
460 * sees the new next_to_clean.
461 */
462 smp_mb();
463 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
464 !test_bit(__IXGBE_DOWN, &adapter->state)) {
465 netif_wake_subqueue(netdev, tx_ring->queue_index);
466 ++tx_ring->restart_queue;
467 }
468 }
469
470 if (adapter->detect_tx_hung) {
471 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
472 /* schedule immediate reset if we believe we hung */
473 DPRINTK(PROBE, INFO,
474 "tx hang %d detected, resetting adapter\n",
475 adapter->tx_timeout_count + 1);
476 ixgbe_tx_timeout(adapter->netdev);
477 }
478 }
479
480 /* re-arm the interrupt */
481 if (count >= tx_ring->work_limit)
482 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
483
484 tx_ring->total_bytes += total_bytes;
485 tx_ring->total_packets += total_packets;
486 tx_ring->stats.packets += total_packets;
487 tx_ring->stats.bytes += total_bytes;
488 return (count < tx_ring->work_limit);
489 }
490
491 #ifdef CONFIG_IXGBE_DCA
492 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
493 struct ixgbe_ring *rx_ring)
494 {
495 u32 rxctrl;
496 int cpu = get_cpu();
497 int q = rx_ring->reg_idx;
498
499 if (rx_ring->cpu != cpu) {
500 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
501 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
502 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
503 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
504 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
505 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
506 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
507 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
508 }
509 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
510 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
511 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
512 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
513 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
514 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
515 rx_ring->cpu = cpu;
516 }
517 put_cpu();
518 }
519
520 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
521 struct ixgbe_ring *tx_ring)
522 {
523 u32 txctrl;
524 int cpu = get_cpu();
525 int q = tx_ring->reg_idx;
526 struct ixgbe_hw *hw = &adapter->hw;
527
528 if (tx_ring->cpu != cpu) {
529 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
530 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
531 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
532 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
533 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
534 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
535 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
536 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
537 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
538 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
539 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
540 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
541 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
542 }
543 tx_ring->cpu = cpu;
544 }
545 put_cpu();
546 }
547
548 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
549 {
550 int i;
551
552 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
553 return;
554
555 /* always use CB2 mode, difference is masked in the CB driver */
556 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
557
558 for (i = 0; i < adapter->num_tx_queues; i++) {
559 adapter->tx_ring[i]->cpu = -1;
560 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
561 }
562 for (i = 0; i < adapter->num_rx_queues; i++) {
563 adapter->rx_ring[i]->cpu = -1;
564 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
565 }
566 }
567
568 static int __ixgbe_notify_dca(struct device *dev, void *data)
569 {
570 struct net_device *netdev = dev_get_drvdata(dev);
571 struct ixgbe_adapter *adapter = netdev_priv(netdev);
572 unsigned long event = *(unsigned long *)data;
573
574 switch (event) {
575 case DCA_PROVIDER_ADD:
576 /* if we're already enabled, don't do it again */
577 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
578 break;
579 if (dca_add_requester(dev) == 0) {
580 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
581 ixgbe_setup_dca(adapter);
582 break;
583 }
584 /* Fall Through since DCA is disabled. */
585 case DCA_PROVIDER_REMOVE:
586 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
587 dca_remove_requester(dev);
588 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
589 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
590 }
591 break;
592 }
593
594 return 0;
595 }
596
597 #endif /* CONFIG_IXGBE_DCA */
598 /**
599 * ixgbe_receive_skb - Send a completed packet up the stack
600 * @adapter: board private structure
601 * @skb: packet to send up
602 * @status: hardware indication of status of receive
603 * @rx_ring: rx descriptor ring (for a specific queue) to setup
604 * @rx_desc: rx descriptor
605 **/
606 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
607 struct sk_buff *skb, u8 status,
608 struct ixgbe_ring *ring,
609 union ixgbe_adv_rx_desc *rx_desc)
610 {
611 struct ixgbe_adapter *adapter = q_vector->adapter;
612 struct napi_struct *napi = &q_vector->napi;
613 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
614 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
615
616 skb_record_rx_queue(skb, ring->queue_index);
617 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
618 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
619 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
620 else
621 napi_gro_receive(napi, skb);
622 } else {
623 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
624 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
625 else
626 netif_rx(skb);
627 }
628 }
629
630 /**
631 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
632 * @adapter: address of board private structure
633 * @status_err: hardware indication of status of receive
634 * @skb: skb currently being received and modified
635 **/
636 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
637 union ixgbe_adv_rx_desc *rx_desc,
638 struct sk_buff *skb)
639 {
640 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
641
642 skb->ip_summed = CHECKSUM_NONE;
643
644 /* Rx csum disabled */
645 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
646 return;
647
648 /* if IP and error */
649 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
650 (status_err & IXGBE_RXDADV_ERR_IPE)) {
651 adapter->hw_csum_rx_error++;
652 return;
653 }
654
655 if (!(status_err & IXGBE_RXD_STAT_L4CS))
656 return;
657
658 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
659 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
660
661 /*
662 * 82599 errata, UDP frames with a 0 checksum can be marked as
663 * checksum errors.
664 */
665 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
666 (adapter->hw.mac.type == ixgbe_mac_82599EB))
667 return;
668
669 adapter->hw_csum_rx_error++;
670 return;
671 }
672
673 /* It must be a TCP or UDP packet with a valid checksum */
674 skb->ip_summed = CHECKSUM_UNNECESSARY;
675 }
676
677 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
678 struct ixgbe_ring *rx_ring, u32 val)
679 {
680 /*
681 * Force memory writes to complete before letting h/w
682 * know there are new descriptors to fetch. (Only
683 * applicable for weak-ordered memory model archs,
684 * such as IA-64).
685 */
686 wmb();
687 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
688 }
689
690 /**
691 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
692 * @adapter: address of board private structure
693 **/
694 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
695 struct ixgbe_ring *rx_ring,
696 int cleaned_count)
697 {
698 struct pci_dev *pdev = adapter->pdev;
699 union ixgbe_adv_rx_desc *rx_desc;
700 struct ixgbe_rx_buffer *bi;
701 unsigned int i;
702
703 i = rx_ring->next_to_use;
704 bi = &rx_ring->rx_buffer_info[i];
705
706 while (cleaned_count--) {
707 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
708
709 if (!bi->page_dma &&
710 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
711 if (!bi->page) {
712 bi->page = alloc_page(GFP_ATOMIC);
713 if (!bi->page) {
714 adapter->alloc_rx_page_failed++;
715 goto no_buffers;
716 }
717 bi->page_offset = 0;
718 } else {
719 /* use a half page if we're re-using */
720 bi->page_offset ^= (PAGE_SIZE / 2);
721 }
722
723 bi->page_dma = pci_map_page(pdev, bi->page,
724 bi->page_offset,
725 (PAGE_SIZE / 2),
726 PCI_DMA_FROMDEVICE);
727 }
728
729 if (!bi->skb) {
730 struct sk_buff *skb;
731 /* netdev_alloc_skb reserves 32 bytes up front!! */
732 uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
733 skb = netdev_alloc_skb(adapter->netdev, bufsz);
734
735 if (!skb) {
736 adapter->alloc_rx_buff_failed++;
737 goto no_buffers;
738 }
739
740 /* advance the data pointer to the next cache line */
741 skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
742 - skb->data));
743
744 bi->skb = skb;
745 bi->dma = pci_map_single(pdev, skb->data,
746 rx_ring->rx_buf_len,
747 PCI_DMA_FROMDEVICE);
748 }
749 /* Refresh the desc even if buffer_addrs didn't change because
750 * each write-back erases this info. */
751 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
752 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
753 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
754 } else {
755 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
756 }
757
758 i++;
759 if (i == rx_ring->count)
760 i = 0;
761 bi = &rx_ring->rx_buffer_info[i];
762 }
763
764 no_buffers:
765 if (rx_ring->next_to_use != i) {
766 rx_ring->next_to_use = i;
767 if (i-- == 0)
768 i = (rx_ring->count - 1);
769
770 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
771 }
772 }
773
774 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
775 {
776 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
777 }
778
779 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
780 {
781 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
782 }
783
784 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
785 {
786 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
787 IXGBE_RXDADV_RSCCNT_MASK) >>
788 IXGBE_RXDADV_RSCCNT_SHIFT;
789 }
790
791 /**
792 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
793 * @skb: pointer to the last skb in the rsc queue
794 * @count: pointer to number of packets coalesced in this context
795 *
796 * This function changes a queue full of hw rsc buffers into a completed
797 * packet. It uses the ->prev pointers to find the first packet and then
798 * turns it into the frag list owner.
799 **/
800 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
801 u64 *count)
802 {
803 unsigned int frag_list_size = 0;
804
805 while (skb->prev) {
806 struct sk_buff *prev = skb->prev;
807 frag_list_size += skb->len;
808 skb->prev = NULL;
809 skb = prev;
810 *count += 1;
811 }
812
813 skb_shinfo(skb)->frag_list = skb->next;
814 skb->next = NULL;
815 skb->len += frag_list_size;
816 skb->data_len += frag_list_size;
817 skb->truesize += frag_list_size;
818 return skb;
819 }
820
821 struct ixgbe_rsc_cb {
822 dma_addr_t dma;
823 };
824
825 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
826
827 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
828 struct ixgbe_ring *rx_ring,
829 int *work_done, int work_to_do)
830 {
831 struct ixgbe_adapter *adapter = q_vector->adapter;
832 struct net_device *netdev = adapter->netdev;
833 struct pci_dev *pdev = adapter->pdev;
834 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
835 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
836 struct sk_buff *skb;
837 unsigned int i, rsc_count = 0;
838 u32 len, staterr;
839 u16 hdr_info;
840 bool cleaned = false;
841 int cleaned_count = 0;
842 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
843 #ifdef IXGBE_FCOE
844 int ddp_bytes = 0;
845 #endif /* IXGBE_FCOE */
846
847 i = rx_ring->next_to_clean;
848 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
849 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
850 rx_buffer_info = &rx_ring->rx_buffer_info[i];
851
852 while (staterr & IXGBE_RXD_STAT_DD) {
853 u32 upper_len = 0;
854 if (*work_done >= work_to_do)
855 break;
856 (*work_done)++;
857
858 rmb(); /* read descriptor and rx_buffer_info after status DD */
859 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
860 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
861 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
862 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
863 if (len > IXGBE_RX_HDR_SIZE)
864 len = IXGBE_RX_HDR_SIZE;
865 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
866 } else {
867 len = le16_to_cpu(rx_desc->wb.upper.length);
868 }
869
870 cleaned = true;
871 skb = rx_buffer_info->skb;
872 prefetch(skb->data);
873 rx_buffer_info->skb = NULL;
874
875 if (rx_buffer_info->dma) {
876 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
877 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
878 (!(skb->prev)))
879 /*
880 * When HWRSC is enabled, delay unmapping
881 * of the first packet. It carries the
882 * header information, HW may still
883 * access the header after the writeback.
884 * Only unmap it when EOP is reached
885 */
886 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
887 else
888 pci_unmap_single(pdev, rx_buffer_info->dma,
889 rx_ring->rx_buf_len,
890 PCI_DMA_FROMDEVICE);
891 rx_buffer_info->dma = 0;
892 skb_put(skb, len);
893 }
894
895 if (upper_len) {
896 pci_unmap_page(pdev, rx_buffer_info->page_dma,
897 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
898 rx_buffer_info->page_dma = 0;
899 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
900 rx_buffer_info->page,
901 rx_buffer_info->page_offset,
902 upper_len);
903
904 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
905 (page_count(rx_buffer_info->page) != 1))
906 rx_buffer_info->page = NULL;
907 else
908 get_page(rx_buffer_info->page);
909
910 skb->len += upper_len;
911 skb->data_len += upper_len;
912 skb->truesize += upper_len;
913 }
914
915 i++;
916 if (i == rx_ring->count)
917 i = 0;
918
919 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
920 prefetch(next_rxd);
921 cleaned_count++;
922
923 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
924 rsc_count = ixgbe_get_rsc_count(rx_desc);
925
926 if (rsc_count) {
927 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
928 IXGBE_RXDADV_NEXTP_SHIFT;
929 next_buffer = &rx_ring->rx_buffer_info[nextp];
930 } else {
931 next_buffer = &rx_ring->rx_buffer_info[i];
932 }
933
934 if (staterr & IXGBE_RXD_STAT_EOP) {
935 if (skb->prev)
936 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
937 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
938 if (IXGBE_RSC_CB(skb)->dma) {
939 pci_unmap_single(pdev, IXGBE_RSC_CB(skb)->dma,
940 rx_ring->rx_buf_len,
941 PCI_DMA_FROMDEVICE);
942 IXGBE_RSC_CB(skb)->dma = 0;
943 }
944 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
945 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
946 else
947 rx_ring->rsc_count++;
948 rx_ring->rsc_flush++;
949 }
950 rx_ring->stats.packets++;
951 rx_ring->stats.bytes += skb->len;
952 } else {
953 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
954 rx_buffer_info->skb = next_buffer->skb;
955 rx_buffer_info->dma = next_buffer->dma;
956 next_buffer->skb = skb;
957 next_buffer->dma = 0;
958 } else {
959 skb->next = next_buffer->skb;
960 skb->next->prev = skb;
961 }
962 rx_ring->non_eop_descs++;
963 goto next_desc;
964 }
965
966 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
967 dev_kfree_skb_irq(skb);
968 goto next_desc;
969 }
970
971 ixgbe_rx_checksum(adapter, rx_desc, skb);
972
973 /* probably a little skewed due to removing CRC */
974 total_rx_bytes += skb->len;
975 total_rx_packets++;
976
977 skb->protocol = eth_type_trans(skb, adapter->netdev);
978 #ifdef IXGBE_FCOE
979 /* if ddp, not passing to ULD unless for FCP_RSP or error */
980 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
981 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
982 if (!ddp_bytes)
983 goto next_desc;
984 }
985 #endif /* IXGBE_FCOE */
986 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
987
988 next_desc:
989 rx_desc->wb.upper.status_error = 0;
990
991 /* return some buffers to hardware, one at a time is too slow */
992 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
993 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
994 cleaned_count = 0;
995 }
996
997 /* use prefetched values */
998 rx_desc = next_rxd;
999 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1000
1001 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1002 }
1003
1004 rx_ring->next_to_clean = i;
1005 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1006
1007 if (cleaned_count)
1008 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1009
1010 #ifdef IXGBE_FCOE
1011 /* include DDPed FCoE data */
1012 if (ddp_bytes > 0) {
1013 unsigned int mss;
1014
1015 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1016 sizeof(struct fc_frame_header) -
1017 sizeof(struct fcoe_crc_eof);
1018 if (mss > 512)
1019 mss &= ~511;
1020 total_rx_bytes += ddp_bytes;
1021 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1022 }
1023 #endif /* IXGBE_FCOE */
1024
1025 rx_ring->total_packets += total_rx_packets;
1026 rx_ring->total_bytes += total_rx_bytes;
1027 netdev->stats.rx_bytes += total_rx_bytes;
1028 netdev->stats.rx_packets += total_rx_packets;
1029
1030 return cleaned;
1031 }
1032
1033 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1034 /**
1035 * ixgbe_configure_msix - Configure MSI-X hardware
1036 * @adapter: board private structure
1037 *
1038 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1039 * interrupts.
1040 **/
1041 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1042 {
1043 struct ixgbe_q_vector *q_vector;
1044 int i, j, q_vectors, v_idx, r_idx;
1045 u32 mask;
1046
1047 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1048
1049 /*
1050 * Populate the IVAR table and set the ITR values to the
1051 * corresponding register.
1052 */
1053 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1054 q_vector = adapter->q_vector[v_idx];
1055 /* XXX for_each_set_bit(...) */
1056 r_idx = find_first_bit(q_vector->rxr_idx,
1057 adapter->num_rx_queues);
1058
1059 for (i = 0; i < q_vector->rxr_count; i++) {
1060 j = adapter->rx_ring[r_idx]->reg_idx;
1061 ixgbe_set_ivar(adapter, 0, j, v_idx);
1062 r_idx = find_next_bit(q_vector->rxr_idx,
1063 adapter->num_rx_queues,
1064 r_idx + 1);
1065 }
1066 r_idx = find_first_bit(q_vector->txr_idx,
1067 adapter->num_tx_queues);
1068
1069 for (i = 0; i < q_vector->txr_count; i++) {
1070 j = adapter->tx_ring[r_idx]->reg_idx;
1071 ixgbe_set_ivar(adapter, 1, j, v_idx);
1072 r_idx = find_next_bit(q_vector->txr_idx,
1073 adapter->num_tx_queues,
1074 r_idx + 1);
1075 }
1076
1077 if (q_vector->txr_count && !q_vector->rxr_count)
1078 /* tx only */
1079 q_vector->eitr = adapter->tx_eitr_param;
1080 else if (q_vector->rxr_count)
1081 /* rx or mixed */
1082 q_vector->eitr = adapter->rx_eitr_param;
1083
1084 ixgbe_write_eitr(q_vector);
1085 }
1086
1087 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1088 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1089 v_idx);
1090 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1091 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1092 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1093
1094 /* set up to autoclear timer, and the vectors */
1095 mask = IXGBE_EIMS_ENABLE_MASK;
1096 if (adapter->num_vfs)
1097 mask &= ~(IXGBE_EIMS_OTHER |
1098 IXGBE_EIMS_MAILBOX |
1099 IXGBE_EIMS_LSC);
1100 else
1101 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1102 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1103 }
1104
1105 enum latency_range {
1106 lowest_latency = 0,
1107 low_latency = 1,
1108 bulk_latency = 2,
1109 latency_invalid = 255
1110 };
1111
1112 /**
1113 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1114 * @adapter: pointer to adapter
1115 * @eitr: eitr setting (ints per sec) to give last timeslice
1116 * @itr_setting: current throttle rate in ints/second
1117 * @packets: the number of packets during this measurement interval
1118 * @bytes: the number of bytes during this measurement interval
1119 *
1120 * Stores a new ITR value based on packets and byte
1121 * counts during the last interrupt. The advantage of per interrupt
1122 * computation is faster updates and more accurate ITR for the current
1123 * traffic pattern. Constants in this function were computed
1124 * based on theoretical maximum wire speed and thresholds were set based
1125 * on testing data as well as attempting to minimize response time
1126 * while increasing bulk throughput.
1127 * this functionality is controlled by the InterruptThrottleRate module
1128 * parameter (see ixgbe_param.c)
1129 **/
1130 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1131 u32 eitr, u8 itr_setting,
1132 int packets, int bytes)
1133 {
1134 unsigned int retval = itr_setting;
1135 u32 timepassed_us;
1136 u64 bytes_perint;
1137
1138 if (packets == 0)
1139 goto update_itr_done;
1140
1141
1142 /* simple throttlerate management
1143 * 0-20MB/s lowest (100000 ints/s)
1144 * 20-100MB/s low (20000 ints/s)
1145 * 100-1249MB/s bulk (8000 ints/s)
1146 */
1147 /* what was last interrupt timeslice? */
1148 timepassed_us = 1000000/eitr;
1149 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1150
1151 switch (itr_setting) {
1152 case lowest_latency:
1153 if (bytes_perint > adapter->eitr_low)
1154 retval = low_latency;
1155 break;
1156 case low_latency:
1157 if (bytes_perint > adapter->eitr_high)
1158 retval = bulk_latency;
1159 else if (bytes_perint <= adapter->eitr_low)
1160 retval = lowest_latency;
1161 break;
1162 case bulk_latency:
1163 if (bytes_perint <= adapter->eitr_high)
1164 retval = low_latency;
1165 break;
1166 }
1167
1168 update_itr_done:
1169 return retval;
1170 }
1171
1172 /**
1173 * ixgbe_write_eitr - write EITR register in hardware specific way
1174 * @q_vector: structure containing interrupt and ring information
1175 *
1176 * This function is made to be called by ethtool and by the driver
1177 * when it needs to update EITR registers at runtime. Hardware
1178 * specific quirks/differences are taken care of here.
1179 */
1180 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1181 {
1182 struct ixgbe_adapter *adapter = q_vector->adapter;
1183 struct ixgbe_hw *hw = &adapter->hw;
1184 int v_idx = q_vector->v_idx;
1185 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1186
1187 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1188 /* must write high and low 16 bits to reset counter */
1189 itr_reg |= (itr_reg << 16);
1190 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1191 /*
1192 * set the WDIS bit to not clear the timer bits and cause an
1193 * immediate assertion of the interrupt
1194 */
1195 itr_reg |= IXGBE_EITR_CNT_WDIS;
1196 }
1197 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1198 }
1199
1200 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1201 {
1202 struct ixgbe_adapter *adapter = q_vector->adapter;
1203 u32 new_itr;
1204 u8 current_itr, ret_itr;
1205 int i, r_idx;
1206 struct ixgbe_ring *rx_ring, *tx_ring;
1207
1208 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1209 for (i = 0; i < q_vector->txr_count; i++) {
1210 tx_ring = adapter->tx_ring[r_idx];
1211 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1212 q_vector->tx_itr,
1213 tx_ring->total_packets,
1214 tx_ring->total_bytes);
1215 /* if the result for this queue would decrease interrupt
1216 * rate for this vector then use that result */
1217 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1218 q_vector->tx_itr - 1 : ret_itr);
1219 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1220 r_idx + 1);
1221 }
1222
1223 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1224 for (i = 0; i < q_vector->rxr_count; i++) {
1225 rx_ring = adapter->rx_ring[r_idx];
1226 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1227 q_vector->rx_itr,
1228 rx_ring->total_packets,
1229 rx_ring->total_bytes);
1230 /* if the result for this queue would decrease interrupt
1231 * rate for this vector then use that result */
1232 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1233 q_vector->rx_itr - 1 : ret_itr);
1234 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1235 r_idx + 1);
1236 }
1237
1238 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1239
1240 switch (current_itr) {
1241 /* counts and packets in update_itr are dependent on these numbers */
1242 case lowest_latency:
1243 new_itr = 100000;
1244 break;
1245 case low_latency:
1246 new_itr = 20000; /* aka hwitr = ~200 */
1247 break;
1248 case bulk_latency:
1249 default:
1250 new_itr = 8000;
1251 break;
1252 }
1253
1254 if (new_itr != q_vector->eitr) {
1255 /* do an exponential smoothing */
1256 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1257
1258 /* save the algorithm value here, not the smoothed one */
1259 q_vector->eitr = new_itr;
1260
1261 ixgbe_write_eitr(q_vector);
1262 }
1263
1264 return;
1265 }
1266
1267 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1268 {
1269 struct ixgbe_hw *hw = &adapter->hw;
1270
1271 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1272 (eicr & IXGBE_EICR_GPI_SDP1)) {
1273 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1274 /* write to clear the interrupt */
1275 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1276 }
1277 }
1278
1279 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1280 {
1281 struct ixgbe_hw *hw = &adapter->hw;
1282
1283 if (eicr & IXGBE_EICR_GPI_SDP1) {
1284 /* Clear the interrupt */
1285 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1286 schedule_work(&adapter->multispeed_fiber_task);
1287 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1288 /* Clear the interrupt */
1289 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1290 schedule_work(&adapter->sfp_config_module_task);
1291 } else {
1292 /* Interrupt isn't for us... */
1293 return;
1294 }
1295 }
1296
1297 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1298 {
1299 struct ixgbe_hw *hw = &adapter->hw;
1300
1301 adapter->lsc_int++;
1302 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1303 adapter->link_check_timeout = jiffies;
1304 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1305 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1306 IXGBE_WRITE_FLUSH(hw);
1307 schedule_work(&adapter->watchdog_task);
1308 }
1309 }
1310
1311 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1312 {
1313 struct net_device *netdev = data;
1314 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1315 struct ixgbe_hw *hw = &adapter->hw;
1316 u32 eicr;
1317
1318 /*
1319 * Workaround for Silicon errata. Use clear-by-write instead
1320 * of clear-by-read. Reading with EICS will return the
1321 * interrupt causes without clearing, which later be done
1322 * with the write to EICR.
1323 */
1324 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1325 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1326
1327 if (eicr & IXGBE_EICR_LSC)
1328 ixgbe_check_lsc(adapter);
1329
1330 if (eicr & IXGBE_EICR_MAILBOX)
1331 ixgbe_msg_task(adapter);
1332
1333 if (hw->mac.type == ixgbe_mac_82598EB)
1334 ixgbe_check_fan_failure(adapter, eicr);
1335
1336 if (hw->mac.type == ixgbe_mac_82599EB) {
1337 ixgbe_check_sfp_event(adapter, eicr);
1338
1339 /* Handle Flow Director Full threshold interrupt */
1340 if (eicr & IXGBE_EICR_FLOW_DIR) {
1341 int i;
1342 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1343 /* Disable transmits before FDIR Re-initialization */
1344 netif_tx_stop_all_queues(netdev);
1345 for (i = 0; i < adapter->num_tx_queues; i++) {
1346 struct ixgbe_ring *tx_ring =
1347 adapter->tx_ring[i];
1348 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1349 &tx_ring->reinit_state))
1350 schedule_work(&adapter->fdir_reinit_task);
1351 }
1352 }
1353 }
1354 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1355 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1356
1357 return IRQ_HANDLED;
1358 }
1359
1360 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1361 u64 qmask)
1362 {
1363 u32 mask;
1364
1365 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1366 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1368 } else {
1369 mask = (qmask & 0xFFFFFFFF);
1370 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1371 mask = (qmask >> 32);
1372 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1373 }
1374 /* skip the flush */
1375 }
1376
1377 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1378 u64 qmask)
1379 {
1380 u32 mask;
1381
1382 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1383 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1384 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1385 } else {
1386 mask = (qmask & 0xFFFFFFFF);
1387 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1388 mask = (qmask >> 32);
1389 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1390 }
1391 /* skip the flush */
1392 }
1393
1394 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1395 {
1396 struct ixgbe_q_vector *q_vector = data;
1397 struct ixgbe_adapter *adapter = q_vector->adapter;
1398 struct ixgbe_ring *tx_ring;
1399 int i, r_idx;
1400
1401 if (!q_vector->txr_count)
1402 return IRQ_HANDLED;
1403
1404 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1405 for (i = 0; i < q_vector->txr_count; i++) {
1406 tx_ring = adapter->tx_ring[r_idx];
1407 tx_ring->total_bytes = 0;
1408 tx_ring->total_packets = 0;
1409 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1410 r_idx + 1);
1411 }
1412
1413 /* EIAM disabled interrupts (on this vector) for us */
1414 napi_schedule(&q_vector->napi);
1415
1416 return IRQ_HANDLED;
1417 }
1418
1419 /**
1420 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1421 * @irq: unused
1422 * @data: pointer to our q_vector struct for this interrupt vector
1423 **/
1424 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1425 {
1426 struct ixgbe_q_vector *q_vector = data;
1427 struct ixgbe_adapter *adapter = q_vector->adapter;
1428 struct ixgbe_ring *rx_ring;
1429 int r_idx;
1430 int i;
1431
1432 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1433 for (i = 0; i < q_vector->rxr_count; i++) {
1434 rx_ring = adapter->rx_ring[r_idx];
1435 rx_ring->total_bytes = 0;
1436 rx_ring->total_packets = 0;
1437 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1438 r_idx + 1);
1439 }
1440
1441 if (!q_vector->rxr_count)
1442 return IRQ_HANDLED;
1443
1444 /* disable interrupts on this vector only */
1445 /* EIAM disabled interrupts (on this vector) for us */
1446 napi_schedule(&q_vector->napi);
1447
1448 return IRQ_HANDLED;
1449 }
1450
1451 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1452 {
1453 struct ixgbe_q_vector *q_vector = data;
1454 struct ixgbe_adapter *adapter = q_vector->adapter;
1455 struct ixgbe_ring *ring;
1456 int r_idx;
1457 int i;
1458
1459 if (!q_vector->txr_count && !q_vector->rxr_count)
1460 return IRQ_HANDLED;
1461
1462 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1463 for (i = 0; i < q_vector->txr_count; i++) {
1464 ring = adapter->tx_ring[r_idx];
1465 ring->total_bytes = 0;
1466 ring->total_packets = 0;
1467 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1468 r_idx + 1);
1469 }
1470
1471 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1472 for (i = 0; i < q_vector->rxr_count; i++) {
1473 ring = adapter->rx_ring[r_idx];
1474 ring->total_bytes = 0;
1475 ring->total_packets = 0;
1476 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1477 r_idx + 1);
1478 }
1479
1480 /* EIAM disabled interrupts (on this vector) for us */
1481 napi_schedule(&q_vector->napi);
1482
1483 return IRQ_HANDLED;
1484 }
1485
1486 /**
1487 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1488 * @napi: napi struct with our devices info in it
1489 * @budget: amount of work driver is allowed to do this pass, in packets
1490 *
1491 * This function is optimized for cleaning one queue only on a single
1492 * q_vector!!!
1493 **/
1494 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1495 {
1496 struct ixgbe_q_vector *q_vector =
1497 container_of(napi, struct ixgbe_q_vector, napi);
1498 struct ixgbe_adapter *adapter = q_vector->adapter;
1499 struct ixgbe_ring *rx_ring = NULL;
1500 int work_done = 0;
1501 long r_idx;
1502
1503 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1504 rx_ring = adapter->rx_ring[r_idx];
1505 #ifdef CONFIG_IXGBE_DCA
1506 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1507 ixgbe_update_rx_dca(adapter, rx_ring);
1508 #endif
1509
1510 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1511
1512 /* If all Rx work done, exit the polling mode */
1513 if (work_done < budget) {
1514 napi_complete(napi);
1515 if (adapter->rx_itr_setting & 1)
1516 ixgbe_set_itr_msix(q_vector);
1517 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1518 ixgbe_irq_enable_queues(adapter,
1519 ((u64)1 << q_vector->v_idx));
1520 }
1521
1522 return work_done;
1523 }
1524
1525 /**
1526 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1527 * @napi: napi struct with our devices info in it
1528 * @budget: amount of work driver is allowed to do this pass, in packets
1529 *
1530 * This function will clean more than one rx queue associated with a
1531 * q_vector.
1532 **/
1533 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1534 {
1535 struct ixgbe_q_vector *q_vector =
1536 container_of(napi, struct ixgbe_q_vector, napi);
1537 struct ixgbe_adapter *adapter = q_vector->adapter;
1538 struct ixgbe_ring *ring = NULL;
1539 int work_done = 0, i;
1540 long r_idx;
1541 bool tx_clean_complete = true;
1542
1543 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1544 for (i = 0; i < q_vector->txr_count; i++) {
1545 ring = adapter->tx_ring[r_idx];
1546 #ifdef CONFIG_IXGBE_DCA
1547 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1548 ixgbe_update_tx_dca(adapter, ring);
1549 #endif
1550 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1551 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1552 r_idx + 1);
1553 }
1554
1555 /* attempt to distribute budget to each queue fairly, but don't allow
1556 * the budget to go below 1 because we'll exit polling */
1557 budget /= (q_vector->rxr_count ?: 1);
1558 budget = max(budget, 1);
1559 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1560 for (i = 0; i < q_vector->rxr_count; i++) {
1561 ring = adapter->rx_ring[r_idx];
1562 #ifdef CONFIG_IXGBE_DCA
1563 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1564 ixgbe_update_rx_dca(adapter, ring);
1565 #endif
1566 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1567 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1568 r_idx + 1);
1569 }
1570
1571 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1572 ring = adapter->rx_ring[r_idx];
1573 /* If all Rx work done, exit the polling mode */
1574 if (work_done < budget) {
1575 napi_complete(napi);
1576 if (adapter->rx_itr_setting & 1)
1577 ixgbe_set_itr_msix(q_vector);
1578 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1579 ixgbe_irq_enable_queues(adapter,
1580 ((u64)1 << q_vector->v_idx));
1581 return 0;
1582 }
1583
1584 return work_done;
1585 }
1586
1587 /**
1588 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1589 * @napi: napi struct with our devices info in it
1590 * @budget: amount of work driver is allowed to do this pass, in packets
1591 *
1592 * This function is optimized for cleaning one queue only on a single
1593 * q_vector!!!
1594 **/
1595 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1596 {
1597 struct ixgbe_q_vector *q_vector =
1598 container_of(napi, struct ixgbe_q_vector, napi);
1599 struct ixgbe_adapter *adapter = q_vector->adapter;
1600 struct ixgbe_ring *tx_ring = NULL;
1601 int work_done = 0;
1602 long r_idx;
1603
1604 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1605 tx_ring = adapter->tx_ring[r_idx];
1606 #ifdef CONFIG_IXGBE_DCA
1607 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1608 ixgbe_update_tx_dca(adapter, tx_ring);
1609 #endif
1610
1611 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1612 work_done = budget;
1613
1614 /* If all Tx work done, exit the polling mode */
1615 if (work_done < budget) {
1616 napi_complete(napi);
1617 if (adapter->tx_itr_setting & 1)
1618 ixgbe_set_itr_msix(q_vector);
1619 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1620 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1621 }
1622
1623 return work_done;
1624 }
1625
1626 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1627 int r_idx)
1628 {
1629 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1630
1631 set_bit(r_idx, q_vector->rxr_idx);
1632 q_vector->rxr_count++;
1633 }
1634
1635 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1636 int t_idx)
1637 {
1638 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1639
1640 set_bit(t_idx, q_vector->txr_idx);
1641 q_vector->txr_count++;
1642 }
1643
1644 /**
1645 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1646 * @adapter: board private structure to initialize
1647 * @vectors: allotted vector count for descriptor rings
1648 *
1649 * This function maps descriptor rings to the queue-specific vectors
1650 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1651 * one vector per ring/queue, but on a constrained vector budget, we
1652 * group the rings as "efficiently" as possible. You would add new
1653 * mapping configurations in here.
1654 **/
1655 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1656 int vectors)
1657 {
1658 int v_start = 0;
1659 int rxr_idx = 0, txr_idx = 0;
1660 int rxr_remaining = adapter->num_rx_queues;
1661 int txr_remaining = adapter->num_tx_queues;
1662 int i, j;
1663 int rqpv, tqpv;
1664 int err = 0;
1665
1666 /* No mapping required if MSI-X is disabled. */
1667 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1668 goto out;
1669
1670 /*
1671 * The ideal configuration...
1672 * We have enough vectors to map one per queue.
1673 */
1674 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1675 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1676 map_vector_to_rxq(adapter, v_start, rxr_idx);
1677
1678 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1679 map_vector_to_txq(adapter, v_start, txr_idx);
1680
1681 goto out;
1682 }
1683
1684 /*
1685 * If we don't have enough vectors for a 1-to-1
1686 * mapping, we'll have to group them so there are
1687 * multiple queues per vector.
1688 */
1689 /* Re-adjusting *qpv takes care of the remainder. */
1690 for (i = v_start; i < vectors; i++) {
1691 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1692 for (j = 0; j < rqpv; j++) {
1693 map_vector_to_rxq(adapter, i, rxr_idx);
1694 rxr_idx++;
1695 rxr_remaining--;
1696 }
1697 }
1698 for (i = v_start; i < vectors; i++) {
1699 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1700 for (j = 0; j < tqpv; j++) {
1701 map_vector_to_txq(adapter, i, txr_idx);
1702 txr_idx++;
1703 txr_remaining--;
1704 }
1705 }
1706
1707 out:
1708 return err;
1709 }
1710
1711 /**
1712 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1713 * @adapter: board private structure
1714 *
1715 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1716 * interrupts from the kernel.
1717 **/
1718 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1719 {
1720 struct net_device *netdev = adapter->netdev;
1721 irqreturn_t (*handler)(int, void *);
1722 int i, vector, q_vectors, err;
1723 int ri=0, ti=0;
1724
1725 /* Decrement for Other and TCP Timer vectors */
1726 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1727
1728 /* Map the Tx/Rx rings to the vectors we were allotted. */
1729 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1730 if (err)
1731 goto out;
1732
1733 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1734 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1735 &ixgbe_msix_clean_many)
1736 for (vector = 0; vector < q_vectors; vector++) {
1737 handler = SET_HANDLER(adapter->q_vector[vector]);
1738
1739 if(handler == &ixgbe_msix_clean_rx) {
1740 sprintf(adapter->name[vector], "%s-%s-%d",
1741 netdev->name, "rx", ri++);
1742 }
1743 else if(handler == &ixgbe_msix_clean_tx) {
1744 sprintf(adapter->name[vector], "%s-%s-%d",
1745 netdev->name, "tx", ti++);
1746 }
1747 else
1748 sprintf(adapter->name[vector], "%s-%s-%d",
1749 netdev->name, "TxRx", vector);
1750
1751 err = request_irq(adapter->msix_entries[vector].vector,
1752 handler, 0, adapter->name[vector],
1753 adapter->q_vector[vector]);
1754 if (err) {
1755 DPRINTK(PROBE, ERR,
1756 "request_irq failed for MSIX interrupt "
1757 "Error: %d\n", err);
1758 goto free_queue_irqs;
1759 }
1760 }
1761
1762 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1763 err = request_irq(adapter->msix_entries[vector].vector,
1764 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1765 if (err) {
1766 DPRINTK(PROBE, ERR,
1767 "request_irq for msix_lsc failed: %d\n", err);
1768 goto free_queue_irqs;
1769 }
1770
1771 return 0;
1772
1773 free_queue_irqs:
1774 for (i = vector - 1; i >= 0; i--)
1775 free_irq(adapter->msix_entries[--vector].vector,
1776 adapter->q_vector[i]);
1777 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1778 pci_disable_msix(adapter->pdev);
1779 kfree(adapter->msix_entries);
1780 adapter->msix_entries = NULL;
1781 out:
1782 return err;
1783 }
1784
1785 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1786 {
1787 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1788 u8 current_itr;
1789 u32 new_itr = q_vector->eitr;
1790 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
1791 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
1792
1793 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1794 q_vector->tx_itr,
1795 tx_ring->total_packets,
1796 tx_ring->total_bytes);
1797 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1798 q_vector->rx_itr,
1799 rx_ring->total_packets,
1800 rx_ring->total_bytes);
1801
1802 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1803
1804 switch (current_itr) {
1805 /* counts and packets in update_itr are dependent on these numbers */
1806 case lowest_latency:
1807 new_itr = 100000;
1808 break;
1809 case low_latency:
1810 new_itr = 20000; /* aka hwitr = ~200 */
1811 break;
1812 case bulk_latency:
1813 new_itr = 8000;
1814 break;
1815 default:
1816 break;
1817 }
1818
1819 if (new_itr != q_vector->eitr) {
1820 /* do an exponential smoothing */
1821 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1822
1823 /* save the algorithm value here, not the smoothed one */
1824 q_vector->eitr = new_itr;
1825
1826 ixgbe_write_eitr(q_vector);
1827 }
1828
1829 return;
1830 }
1831
1832 /**
1833 * ixgbe_irq_enable - Enable default interrupt generation settings
1834 * @adapter: board private structure
1835 **/
1836 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1837 {
1838 u32 mask;
1839
1840 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1841 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1842 mask |= IXGBE_EIMS_GPI_SDP1;
1843 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1844 mask |= IXGBE_EIMS_ECC;
1845 mask |= IXGBE_EIMS_GPI_SDP1;
1846 mask |= IXGBE_EIMS_GPI_SDP2;
1847 if (adapter->num_vfs)
1848 mask |= IXGBE_EIMS_MAILBOX;
1849 }
1850 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1851 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1852 mask |= IXGBE_EIMS_FLOW_DIR;
1853
1854 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1855 ixgbe_irq_enable_queues(adapter, ~0);
1856 IXGBE_WRITE_FLUSH(&adapter->hw);
1857
1858 if (adapter->num_vfs > 32) {
1859 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1860 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1861 }
1862 }
1863
1864 /**
1865 * ixgbe_intr - legacy mode Interrupt Handler
1866 * @irq: interrupt number
1867 * @data: pointer to a network interface device structure
1868 **/
1869 static irqreturn_t ixgbe_intr(int irq, void *data)
1870 {
1871 struct net_device *netdev = data;
1872 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1873 struct ixgbe_hw *hw = &adapter->hw;
1874 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1875 u32 eicr;
1876
1877 /*
1878 * Workaround for silicon errata. Mask the interrupts
1879 * before the read of EICR.
1880 */
1881 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1882
1883 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1884 * therefore no explict interrupt disable is necessary */
1885 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1886 if (!eicr) {
1887 /* shared interrupt alert!
1888 * make sure interrupts are enabled because the read will
1889 * have disabled interrupts due to EIAM */
1890 ixgbe_irq_enable(adapter);
1891 return IRQ_NONE; /* Not our interrupt */
1892 }
1893
1894 if (eicr & IXGBE_EICR_LSC)
1895 ixgbe_check_lsc(adapter);
1896
1897 if (hw->mac.type == ixgbe_mac_82599EB)
1898 ixgbe_check_sfp_event(adapter, eicr);
1899
1900 ixgbe_check_fan_failure(adapter, eicr);
1901
1902 if (napi_schedule_prep(&(q_vector->napi))) {
1903 adapter->tx_ring[0]->total_packets = 0;
1904 adapter->tx_ring[0]->total_bytes = 0;
1905 adapter->rx_ring[0]->total_packets = 0;
1906 adapter->rx_ring[0]->total_bytes = 0;
1907 /* would disable interrupts here but EIAM disabled it */
1908 __napi_schedule(&(q_vector->napi));
1909 }
1910
1911 return IRQ_HANDLED;
1912 }
1913
1914 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1915 {
1916 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1917
1918 for (i = 0; i < q_vectors; i++) {
1919 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1920 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1921 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1922 q_vector->rxr_count = 0;
1923 q_vector->txr_count = 0;
1924 }
1925 }
1926
1927 /**
1928 * ixgbe_request_irq - initialize interrupts
1929 * @adapter: board private structure
1930 *
1931 * Attempts to configure interrupts using the best available
1932 * capabilities of the hardware and kernel.
1933 **/
1934 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1935 {
1936 struct net_device *netdev = adapter->netdev;
1937 int err;
1938
1939 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1940 err = ixgbe_request_msix_irqs(adapter);
1941 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1942 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
1943 netdev->name, netdev);
1944 } else {
1945 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
1946 netdev->name, netdev);
1947 }
1948
1949 if (err)
1950 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1951
1952 return err;
1953 }
1954
1955 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1956 {
1957 struct net_device *netdev = adapter->netdev;
1958
1959 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1960 int i, q_vectors;
1961
1962 q_vectors = adapter->num_msix_vectors;
1963
1964 i = q_vectors - 1;
1965 free_irq(adapter->msix_entries[i].vector, netdev);
1966
1967 i--;
1968 for (; i >= 0; i--) {
1969 free_irq(adapter->msix_entries[i].vector,
1970 adapter->q_vector[i]);
1971 }
1972
1973 ixgbe_reset_q_vectors(adapter);
1974 } else {
1975 free_irq(adapter->pdev->irq, netdev);
1976 }
1977 }
1978
1979 /**
1980 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1981 * @adapter: board private structure
1982 **/
1983 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1984 {
1985 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1986 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1987 } else {
1988 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1989 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1990 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1991 if (adapter->num_vfs > 32)
1992 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
1993 }
1994 IXGBE_WRITE_FLUSH(&adapter->hw);
1995 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1996 int i;
1997 for (i = 0; i < adapter->num_msix_vectors; i++)
1998 synchronize_irq(adapter->msix_entries[i].vector);
1999 } else {
2000 synchronize_irq(adapter->pdev->irq);
2001 }
2002 }
2003
2004 /**
2005 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2006 *
2007 **/
2008 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2009 {
2010 struct ixgbe_hw *hw = &adapter->hw;
2011
2012 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2013 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2014
2015 ixgbe_set_ivar(adapter, 0, 0, 0);
2016 ixgbe_set_ivar(adapter, 1, 0, 0);
2017
2018 map_vector_to_rxq(adapter, 0, 0);
2019 map_vector_to_txq(adapter, 0, 0);
2020
2021 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
2022 }
2023
2024 /**
2025 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2026 * @adapter: board private structure
2027 *
2028 * Configure the Tx unit of the MAC after a reset.
2029 **/
2030 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2031 {
2032 u64 tdba;
2033 struct ixgbe_hw *hw = &adapter->hw;
2034 u32 i, j, tdlen, txctrl;
2035
2036 /* Setup the HW Tx Head and Tail descriptor pointers */
2037 for (i = 0; i < adapter->num_tx_queues; i++) {
2038 struct ixgbe_ring *ring = adapter->tx_ring[i];
2039 j = ring->reg_idx;
2040 tdba = ring->dma;
2041 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
2042 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
2043 (tdba & DMA_BIT_MASK(32)));
2044 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2045 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2046 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2047 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
2048 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2049 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
2050 /*
2051 * Disable Tx Head Writeback RO bit, since this hoses
2052 * bookkeeping if things aren't delivered in order.
2053 */
2054 switch (hw->mac.type) {
2055 case ixgbe_mac_82598EB:
2056 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2057 break;
2058 case ixgbe_mac_82599EB:
2059 default:
2060 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2061 break;
2062 }
2063 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2064 switch (hw->mac.type) {
2065 case ixgbe_mac_82598EB:
2066 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2067 break;
2068 case ixgbe_mac_82599EB:
2069 default:
2070 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2071 break;
2072 }
2073 }
2074
2075 if (hw->mac.type == ixgbe_mac_82599EB) {
2076 u32 rttdcs;
2077 u32 mask;
2078
2079 /* disable the arbiter while setting MTQC */
2080 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2081 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2082 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2083
2084 /* set transmit pool layout */
2085 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2086 switch (adapter->flags & mask) {
2087
2088 case (IXGBE_FLAG_SRIOV_ENABLED):
2089 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2090 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2091 break;
2092
2093 case (IXGBE_FLAG_DCB_ENABLED):
2094 /* We enable 8 traffic classes, DCB only */
2095 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2096 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2097 break;
2098
2099 default:
2100 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2101 break;
2102 }
2103
2104 /* re-eable the arbiter */
2105 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2106 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2107 }
2108 }
2109
2110 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2111
2112 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2113 struct ixgbe_ring *rx_ring)
2114 {
2115 u32 srrctl;
2116 int index;
2117 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2118
2119 index = rx_ring->reg_idx;
2120 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2121 unsigned long mask;
2122 mask = (unsigned long) feature[RING_F_RSS].mask;
2123 index = index & mask;
2124 }
2125 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2126
2127 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2128 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2129
2130 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2131 IXGBE_SRRCTL_BSIZEHDR_MASK;
2132
2133 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2134 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2135 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2136 #else
2137 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2138 #endif
2139 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2140 } else {
2141 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2142 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2143 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2144 }
2145
2146 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2147 }
2148
2149 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2150 {
2151 u32 mrqc = 0;
2152 int mask;
2153
2154 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2155 return mrqc;
2156
2157 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2158 #ifdef CONFIG_IXGBE_DCB
2159 | IXGBE_FLAG_DCB_ENABLED
2160 #endif
2161 | IXGBE_FLAG_SRIOV_ENABLED
2162 );
2163
2164 switch (mask) {
2165 case (IXGBE_FLAG_RSS_ENABLED):
2166 mrqc = IXGBE_MRQC_RSSEN;
2167 break;
2168 case (IXGBE_FLAG_SRIOV_ENABLED):
2169 mrqc = IXGBE_MRQC_VMDQEN;
2170 break;
2171 #ifdef CONFIG_IXGBE_DCB
2172 case (IXGBE_FLAG_DCB_ENABLED):
2173 mrqc = IXGBE_MRQC_RT8TCEN;
2174 break;
2175 #endif /* CONFIG_IXGBE_DCB */
2176 default:
2177 break;
2178 }
2179
2180 return mrqc;
2181 }
2182
2183 /**
2184 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2185 * @adapter: address of board private structure
2186 * @index: index of ring to set
2187 **/
2188 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2189 {
2190 struct ixgbe_ring *rx_ring;
2191 struct ixgbe_hw *hw = &adapter->hw;
2192 int j;
2193 u32 rscctrl;
2194 int rx_buf_len;
2195
2196 rx_ring = adapter->rx_ring[index];
2197 j = rx_ring->reg_idx;
2198 rx_buf_len = rx_ring->rx_buf_len;
2199 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2200 rscctrl |= IXGBE_RSCCTL_RSCEN;
2201 /*
2202 * we must limit the number of descriptors so that the
2203 * total size of max desc * buf_len is not greater
2204 * than 65535
2205 */
2206 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2207 #if (MAX_SKB_FRAGS > 16)
2208 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2209 #elif (MAX_SKB_FRAGS > 8)
2210 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2211 #elif (MAX_SKB_FRAGS > 4)
2212 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2213 #else
2214 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2215 #endif
2216 } else {
2217 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2218 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2219 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2220 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2221 else
2222 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2223 }
2224 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2225 }
2226
2227 /**
2228 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2229 * @adapter: board private structure
2230 *
2231 * Configure the Rx unit of the MAC after a reset.
2232 **/
2233 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2234 {
2235 u64 rdba;
2236 struct ixgbe_hw *hw = &adapter->hw;
2237 struct ixgbe_ring *rx_ring;
2238 struct net_device *netdev = adapter->netdev;
2239 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2240 int i, j;
2241 u32 rdlen, rxctrl, rxcsum;
2242 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2243 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2244 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2245 u32 fctrl, hlreg0;
2246 u32 reta = 0, mrqc = 0;
2247 u32 rdrxctl;
2248 int rx_buf_len;
2249
2250 /* Decide whether to use packet split mode or not */
2251 /* Do not use packet split if we're in SR-IOV Mode */
2252 if (!adapter->num_vfs)
2253 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2254
2255 /* Set the RX buffer length according to the mode */
2256 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2257 rx_buf_len = IXGBE_RX_HDR_SIZE;
2258 if (hw->mac.type == ixgbe_mac_82599EB) {
2259 /* PSRTYPE must be initialized in 82599 */
2260 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2261 IXGBE_PSRTYPE_UDPHDR |
2262 IXGBE_PSRTYPE_IPV4HDR |
2263 IXGBE_PSRTYPE_IPV6HDR |
2264 IXGBE_PSRTYPE_L2HDR;
2265 IXGBE_WRITE_REG(hw,
2266 IXGBE_PSRTYPE(adapter->num_vfs),
2267 psrtype);
2268 }
2269 } else {
2270 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2271 (netdev->mtu <= ETH_DATA_LEN))
2272 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2273 else
2274 rx_buf_len = ALIGN(max_frame, 1024);
2275 }
2276
2277 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2278 fctrl |= IXGBE_FCTRL_BAM;
2279 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2280 fctrl |= IXGBE_FCTRL_PMCF;
2281 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2282
2283 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2284 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2285 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2286 else
2287 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2288 #ifdef IXGBE_FCOE
2289 if (netdev->features & NETIF_F_FCOE_MTU)
2290 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2291 #endif
2292 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2293
2294 rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
2295 /* disable receives while setting up the descriptors */
2296 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2297 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2298
2299 /*
2300 * Setup the HW Rx Head and Tail Descriptor Pointers and
2301 * the Base and Length of the Rx Descriptor Ring
2302 */
2303 for (i = 0; i < adapter->num_rx_queues; i++) {
2304 rx_ring = adapter->rx_ring[i];
2305 rdba = rx_ring->dma;
2306 j = rx_ring->reg_idx;
2307 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2308 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2309 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2310 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2311 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2312 rx_ring->head = IXGBE_RDH(j);
2313 rx_ring->tail = IXGBE_RDT(j);
2314 rx_ring->rx_buf_len = rx_buf_len;
2315
2316 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2317 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2318 else
2319 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2320
2321 #ifdef IXGBE_FCOE
2322 if (netdev->features & NETIF_F_FCOE_MTU) {
2323 struct ixgbe_ring_feature *f;
2324 f = &adapter->ring_feature[RING_F_FCOE];
2325 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2326 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2327 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2328 rx_ring->rx_buf_len =
2329 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2330 }
2331 }
2332
2333 #endif /* IXGBE_FCOE */
2334 ixgbe_configure_srrctl(adapter, rx_ring);
2335 }
2336
2337 if (hw->mac.type == ixgbe_mac_82598EB) {
2338 /*
2339 * For VMDq support of different descriptor types or
2340 * buffer sizes through the use of multiple SRRCTL
2341 * registers, RDRXCTL.MVMEN must be set to 1
2342 *
2343 * also, the manual doesn't mention it clearly but DCA hints
2344 * will only use queue 0's tags unless this bit is set. Side
2345 * effects of setting this bit are only that SRRCTL must be
2346 * fully programmed [0..15]
2347 */
2348 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2349 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2350 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2351 }
2352
2353 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2354 u32 vt_reg_bits;
2355 u32 reg_offset, vf_shift;
2356 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2357 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2358 | IXGBE_VT_CTL_REPLEN;
2359 vt_reg_bits |= (adapter->num_vfs <<
2360 IXGBE_VT_CTL_POOL_SHIFT);
2361 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2362 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2363
2364 vf_shift = adapter->num_vfs % 32;
2365 reg_offset = adapter->num_vfs / 32;
2366 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2367 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2368 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2369 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2370 /* Enable only the PF's pool for Tx/Rx */
2371 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2372 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2373 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2374 ixgbe_set_vmolr(hw, adapter->num_vfs);
2375 }
2376
2377 /* Program MRQC for the distribution of queues */
2378 mrqc = ixgbe_setup_mrqc(adapter);
2379
2380 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2381 /* Fill out redirection table */
2382 for (i = 0, j = 0; i < 128; i++, j++) {
2383 if (j == adapter->ring_feature[RING_F_RSS].indices)
2384 j = 0;
2385 /* reta = 4-byte sliding window of
2386 * 0x00..(indices-1)(indices-1)00..etc. */
2387 reta = (reta << 8) | (j * 0x11);
2388 if ((i & 3) == 3)
2389 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2390 }
2391
2392 /* Fill out hash function seeds */
2393 for (i = 0; i < 10; i++)
2394 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2395
2396 if (hw->mac.type == ixgbe_mac_82598EB)
2397 mrqc |= IXGBE_MRQC_RSSEN;
2398 /* Perform hash on these packet types */
2399 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2400 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2401 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2402 | IXGBE_MRQC_RSS_FIELD_IPV6
2403 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2404 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2405 }
2406 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2407
2408 if (adapter->num_vfs) {
2409 u32 reg;
2410
2411 /* Map PF MAC address in RAR Entry 0 to first pool
2412 * following VFs */
2413 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2414
2415 /* Set up VF register offsets for selected VT Mode, i.e.
2416 * 64 VFs for SR-IOV */
2417 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2418 reg |= IXGBE_GCR_EXT_SRIOV;
2419 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2420 }
2421
2422 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2423
2424 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2425 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2426 /* Disable indicating checksum in descriptor, enables
2427 * RSS hash */
2428 rxcsum |= IXGBE_RXCSUM_PCSD;
2429 }
2430 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2431 /* Enable IPv4 payload checksum for UDP fragments
2432 * if PCSD is not set */
2433 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2434 }
2435
2436 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2437
2438 if (hw->mac.type == ixgbe_mac_82599EB) {
2439 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2440 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2441 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2442 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2443 }
2444
2445 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2446 /* Enable 82599 HW-RSC */
2447 for (i = 0; i < adapter->num_rx_queues; i++)
2448 ixgbe_configure_rscctl(adapter, i);
2449
2450 /* Disable RSC for ACK packets */
2451 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2452 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2453 }
2454 }
2455
2456 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2457 {
2458 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2459 struct ixgbe_hw *hw = &adapter->hw;
2460 int pool_ndx = adapter->num_vfs;
2461
2462 /* add VID to filter table */
2463 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
2464 }
2465
2466 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2467 {
2468 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2469 struct ixgbe_hw *hw = &adapter->hw;
2470 int pool_ndx = adapter->num_vfs;
2471
2472 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2473 ixgbe_irq_disable(adapter);
2474
2475 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2476
2477 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2478 ixgbe_irq_enable(adapter);
2479
2480 /* remove VID from filter table */
2481 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
2482 }
2483
2484 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2485 struct vlan_group *grp)
2486 {
2487 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2488 u32 ctrl;
2489 int i, j;
2490
2491 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2492 ixgbe_irq_disable(adapter);
2493 adapter->vlgrp = grp;
2494
2495 /*
2496 * For a DCB driver, always enable VLAN tag stripping so we can
2497 * still receive traffic from a DCB-enabled host even if we're
2498 * not in DCB mode.
2499 */
2500 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2501
2502 /* Disable CFI check */
2503 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2504
2505 /* enable VLAN tag stripping */
2506 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2507 ctrl |= IXGBE_VLNCTRL_VME;
2508 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2509 for (i = 0; i < adapter->num_rx_queues; i++) {
2510 u32 ctrl;
2511 j = adapter->rx_ring[i]->reg_idx;
2512 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2513 ctrl |= IXGBE_RXDCTL_VME;
2514 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2515 }
2516 }
2517
2518 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2519
2520 ixgbe_vlan_rx_add_vid(netdev, 0);
2521
2522 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2523 ixgbe_irq_enable(adapter);
2524 }
2525
2526 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2527 {
2528 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2529
2530 if (adapter->vlgrp) {
2531 u16 vid;
2532 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2533 if (!vlan_group_get_device(adapter->vlgrp, vid))
2534 continue;
2535 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2536 }
2537 }
2538 }
2539
2540 /**
2541 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2542 * @netdev: network interface device structure
2543 *
2544 * The set_rx_method entry point is called whenever the unicast/multicast
2545 * address list or the network interface flags are updated. This routine is
2546 * responsible for configuring the hardware for proper unicast, multicast and
2547 * promiscuous mode.
2548 **/
2549 void ixgbe_set_rx_mode(struct net_device *netdev)
2550 {
2551 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2552 struct ixgbe_hw *hw = &adapter->hw;
2553 u32 fctrl, vlnctrl;
2554
2555 /* Check for Promiscuous and All Multicast modes */
2556
2557 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2558 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2559
2560 if (netdev->flags & IFF_PROMISC) {
2561 hw->addr_ctrl.user_set_promisc = 1;
2562 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2563 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2564 } else {
2565 if (netdev->flags & IFF_ALLMULTI) {
2566 fctrl |= IXGBE_FCTRL_MPE;
2567 fctrl &= ~IXGBE_FCTRL_UPE;
2568 } else {
2569 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2570 }
2571 vlnctrl |= IXGBE_VLNCTRL_VFE;
2572 hw->addr_ctrl.user_set_promisc = 0;
2573 }
2574
2575 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2576 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2577
2578 /* reprogram secondary unicast list */
2579 hw->mac.ops.update_uc_addr_list(hw, netdev);
2580
2581 /* reprogram multicast list */
2582 hw->mac.ops.update_mc_addr_list(hw, netdev);
2583
2584 if (adapter->num_vfs)
2585 ixgbe_restore_vf_multicasts(adapter);
2586 }
2587
2588 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2589 {
2590 int q_idx;
2591 struct ixgbe_q_vector *q_vector;
2592 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2593
2594 /* legacy and MSI only use one vector */
2595 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2596 q_vectors = 1;
2597
2598 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2599 struct napi_struct *napi;
2600 q_vector = adapter->q_vector[q_idx];
2601 napi = &q_vector->napi;
2602 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2603 if (!q_vector->rxr_count || !q_vector->txr_count) {
2604 if (q_vector->txr_count == 1)
2605 napi->poll = &ixgbe_clean_txonly;
2606 else if (q_vector->rxr_count == 1)
2607 napi->poll = &ixgbe_clean_rxonly;
2608 }
2609 }
2610
2611 napi_enable(napi);
2612 }
2613 }
2614
2615 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2616 {
2617 int q_idx;
2618 struct ixgbe_q_vector *q_vector;
2619 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2620
2621 /* legacy and MSI only use one vector */
2622 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2623 q_vectors = 1;
2624
2625 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2626 q_vector = adapter->q_vector[q_idx];
2627 napi_disable(&q_vector->napi);
2628 }
2629 }
2630
2631 #ifdef CONFIG_IXGBE_DCB
2632 /*
2633 * ixgbe_configure_dcb - Configure DCB hardware
2634 * @adapter: ixgbe adapter struct
2635 *
2636 * This is called by the driver on open to configure the DCB hardware.
2637 * This is also called by the gennetlink interface when reconfiguring
2638 * the DCB state.
2639 */
2640 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2641 {
2642 struct ixgbe_hw *hw = &adapter->hw;
2643 u32 txdctl, vlnctrl;
2644 int i, j;
2645
2646 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2647 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2648 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2649
2650 /* reconfigure the hardware */
2651 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2652
2653 for (i = 0; i < adapter->num_tx_queues; i++) {
2654 j = adapter->tx_ring[i]->reg_idx;
2655 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2656 /* PThresh workaround for Tx hang with DFP enabled. */
2657 txdctl |= 32;
2658 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2659 }
2660 /* Enable VLAN tag insert/strip */
2661 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2662 if (hw->mac.type == ixgbe_mac_82598EB) {
2663 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2664 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2665 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2666 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2667 vlnctrl |= IXGBE_VLNCTRL_VFE;
2668 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2669 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2670 for (i = 0; i < adapter->num_rx_queues; i++) {
2671 j = adapter->rx_ring[i]->reg_idx;
2672 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2673 vlnctrl |= IXGBE_RXDCTL_VME;
2674 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2675 }
2676 }
2677 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2678 }
2679
2680 #endif
2681 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2682 {
2683 struct net_device *netdev = adapter->netdev;
2684 struct ixgbe_hw *hw = &adapter->hw;
2685 int i;
2686
2687 ixgbe_set_rx_mode(netdev);
2688
2689 ixgbe_restore_vlan(adapter);
2690 #ifdef CONFIG_IXGBE_DCB
2691 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2692 if (hw->mac.type == ixgbe_mac_82598EB)
2693 netif_set_gso_max_size(netdev, 32768);
2694 else
2695 netif_set_gso_max_size(netdev, 65536);
2696 ixgbe_configure_dcb(adapter);
2697 } else {
2698 netif_set_gso_max_size(netdev, 65536);
2699 }
2700 #else
2701 netif_set_gso_max_size(netdev, 65536);
2702 #endif
2703
2704 #ifdef IXGBE_FCOE
2705 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2706 ixgbe_configure_fcoe(adapter);
2707
2708 #endif /* IXGBE_FCOE */
2709 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2710 for (i = 0; i < adapter->num_tx_queues; i++)
2711 adapter->tx_ring[i]->atr_sample_rate =
2712 adapter->atr_sample_rate;
2713 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2714 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2715 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2716 }
2717
2718 ixgbe_configure_tx(adapter);
2719 ixgbe_configure_rx(adapter);
2720 for (i = 0; i < adapter->num_rx_queues; i++)
2721 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
2722 (adapter->rx_ring[i]->count - 1));
2723 }
2724
2725 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2726 {
2727 switch (hw->phy.type) {
2728 case ixgbe_phy_sfp_avago:
2729 case ixgbe_phy_sfp_ftl:
2730 case ixgbe_phy_sfp_intel:
2731 case ixgbe_phy_sfp_unknown:
2732 case ixgbe_phy_tw_tyco:
2733 case ixgbe_phy_tw_unknown:
2734 return true;
2735 default:
2736 return false;
2737 }
2738 }
2739
2740 /**
2741 * ixgbe_sfp_link_config - set up SFP+ link
2742 * @adapter: pointer to private adapter struct
2743 **/
2744 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2745 {
2746 struct ixgbe_hw *hw = &adapter->hw;
2747
2748 if (hw->phy.multispeed_fiber) {
2749 /*
2750 * In multispeed fiber setups, the device may not have
2751 * had a physical connection when the driver loaded.
2752 * If that's the case, the initial link configuration
2753 * couldn't get the MAC into 10G or 1G mode, so we'll
2754 * never have a link status change interrupt fire.
2755 * We need to try and force an autonegotiation
2756 * session, then bring up link.
2757 */
2758 hw->mac.ops.setup_sfp(hw);
2759 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2760 schedule_work(&adapter->multispeed_fiber_task);
2761 } else {
2762 /*
2763 * Direct Attach Cu and non-multispeed fiber modules
2764 * still need to be configured properly prior to
2765 * attempting link.
2766 */
2767 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2768 schedule_work(&adapter->sfp_config_module_task);
2769 }
2770 }
2771
2772 /**
2773 * ixgbe_non_sfp_link_config - set up non-SFP+ link
2774 * @hw: pointer to private hardware struct
2775 *
2776 * Returns 0 on success, negative on failure
2777 **/
2778 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2779 {
2780 u32 autoneg;
2781 bool negotiation, link_up = false;
2782 u32 ret = IXGBE_ERR_LINK_SETUP;
2783
2784 if (hw->mac.ops.check_link)
2785 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2786
2787 if (ret)
2788 goto link_cfg_out;
2789
2790 if (hw->mac.ops.get_link_capabilities)
2791 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2792 if (ret)
2793 goto link_cfg_out;
2794
2795 if (hw->mac.ops.setup_link)
2796 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2797 link_cfg_out:
2798 return ret;
2799 }
2800
2801 #define IXGBE_MAX_RX_DESC_POLL 10
2802 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2803 int rxr)
2804 {
2805 int j = adapter->rx_ring[rxr]->reg_idx;
2806 int k;
2807
2808 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2809 if (IXGBE_READ_REG(&adapter->hw,
2810 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2811 break;
2812 else
2813 msleep(1);
2814 }
2815 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2816 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2817 "not set within the polling period\n", rxr);
2818 }
2819 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
2820 (adapter->rx_ring[rxr]->count - 1));
2821 }
2822
2823 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2824 {
2825 struct net_device *netdev = adapter->netdev;
2826 struct ixgbe_hw *hw = &adapter->hw;
2827 int i, j = 0;
2828 int num_rx_rings = adapter->num_rx_queues;
2829 int err;
2830 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2831 u32 txdctl, rxdctl, mhadd;
2832 u32 dmatxctl;
2833 u32 gpie;
2834 u32 ctrl_ext;
2835
2836 ixgbe_get_hw_control(adapter);
2837
2838 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2839 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2840 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2841 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2842 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2843 } else {
2844 /* MSI only */
2845 gpie = 0;
2846 }
2847 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2848 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
2849 gpie |= IXGBE_GPIE_VTMODE_64;
2850 }
2851 /* XXX: to interrupt immediately for EICS writes, enable this */
2852 /* gpie |= IXGBE_GPIE_EIMEN; */
2853 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2854 }
2855
2856 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2857 /*
2858 * use EIAM to auto-mask when MSI-X interrupt is asserted
2859 * this saves a register write for every interrupt
2860 */
2861 switch (hw->mac.type) {
2862 case ixgbe_mac_82598EB:
2863 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2864 break;
2865 default:
2866 case ixgbe_mac_82599EB:
2867 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2868 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2869 break;
2870 }
2871 } else {
2872 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2873 * specifically only auto mask tx and rx interrupts */
2874 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2875 }
2876
2877 /* Enable fan failure interrupt if media type is copper */
2878 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2879 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2880 gpie |= IXGBE_SDP1_GPIEN;
2881 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2882 }
2883
2884 if (hw->mac.type == ixgbe_mac_82599EB) {
2885 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2886 gpie |= IXGBE_SDP1_GPIEN;
2887 gpie |= IXGBE_SDP2_GPIEN;
2888 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2889 }
2890
2891 #ifdef IXGBE_FCOE
2892 /* adjust max frame to be able to do baby jumbo for FCoE */
2893 if ((netdev->features & NETIF_F_FCOE_MTU) &&
2894 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2895 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2896
2897 #endif /* IXGBE_FCOE */
2898 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2899 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2900 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2901 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2902
2903 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2904 }
2905
2906 for (i = 0; i < adapter->num_tx_queues; i++) {
2907 j = adapter->tx_ring[i]->reg_idx;
2908 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2909 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2910 txdctl |= (8 << 16);
2911 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2912 }
2913
2914 if (hw->mac.type == ixgbe_mac_82599EB) {
2915 /* DMATXCTL.EN must be set after all Tx queue config is done */
2916 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2917 dmatxctl |= IXGBE_DMATXCTL_TE;
2918 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2919 }
2920 for (i = 0; i < adapter->num_tx_queues; i++) {
2921 j = adapter->tx_ring[i]->reg_idx;
2922 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2923 txdctl |= IXGBE_TXDCTL_ENABLE;
2924 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2925 if (hw->mac.type == ixgbe_mac_82599EB) {
2926 int wait_loop = 10;
2927 /* poll for Tx Enable ready */
2928 do {
2929 msleep(1);
2930 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2931 } while (--wait_loop &&
2932 !(txdctl & IXGBE_TXDCTL_ENABLE));
2933 if (!wait_loop)
2934 DPRINTK(DRV, ERR, "Could not enable "
2935 "Tx Queue %d\n", j);
2936 }
2937 }
2938
2939 for (i = 0; i < num_rx_rings; i++) {
2940 j = adapter->rx_ring[i]->reg_idx;
2941 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2942 /* enable PTHRESH=32 descriptors (half the internal cache)
2943 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2944 * this also removes a pesky rx_no_buffer_count increment */
2945 rxdctl |= 0x0020;
2946 rxdctl |= IXGBE_RXDCTL_ENABLE;
2947 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2948 if (hw->mac.type == ixgbe_mac_82599EB)
2949 ixgbe_rx_desc_queue_enable(adapter, i);
2950 }
2951 /* enable all receives */
2952 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2953 if (hw->mac.type == ixgbe_mac_82598EB)
2954 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2955 else
2956 rxdctl |= IXGBE_RXCTRL_RXEN;
2957 hw->mac.ops.enable_rx_dma(hw, rxdctl);
2958
2959 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2960 ixgbe_configure_msix(adapter);
2961 else
2962 ixgbe_configure_msi_and_legacy(adapter);
2963
2964 clear_bit(__IXGBE_DOWN, &adapter->state);
2965 ixgbe_napi_enable_all(adapter);
2966
2967 /* clear any pending interrupts, may auto mask */
2968 IXGBE_READ_REG(hw, IXGBE_EICR);
2969
2970 ixgbe_irq_enable(adapter);
2971
2972 /*
2973 * If this adapter has a fan, check to see if we had a failure
2974 * before we enabled the interrupt.
2975 */
2976 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2977 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2978 if (esdp & IXGBE_ESDP_SDP1)
2979 DPRINTK(DRV, CRIT,
2980 "Fan has stopped, replace the adapter\n");
2981 }
2982
2983 /*
2984 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2985 * arrived before interrupts were enabled but after probe. Such
2986 * devices wouldn't have their type identified yet. We need to
2987 * kick off the SFP+ module setup first, then try to bring up link.
2988 * If we're not hot-pluggable SFP+, we just need to configure link
2989 * and bring it up.
2990 */
2991 if (hw->phy.type == ixgbe_phy_unknown) {
2992 err = hw->phy.ops.identify(hw);
2993 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2994 /*
2995 * Take the device down and schedule the sfp tasklet
2996 * which will unregister_netdev and log it.
2997 */
2998 ixgbe_down(adapter);
2999 schedule_work(&adapter->sfp_config_module_task);
3000 return err;
3001 }
3002 }
3003
3004 if (ixgbe_is_sfp(hw)) {
3005 ixgbe_sfp_link_config(adapter);
3006 } else {
3007 err = ixgbe_non_sfp_link_config(hw);
3008 if (err)
3009 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3010 }
3011
3012 for (i = 0; i < adapter->num_tx_queues; i++)
3013 set_bit(__IXGBE_FDIR_INIT_DONE,
3014 &(adapter->tx_ring[i]->reinit_state));
3015
3016 /* enable transmits */
3017 netif_tx_start_all_queues(netdev);
3018
3019 /* bring the link up in the watchdog, this could race with our first
3020 * link up interrupt but shouldn't be a problem */
3021 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3022 adapter->link_check_timeout = jiffies;
3023 mod_timer(&adapter->watchdog_timer, jiffies);
3024
3025 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3026 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3027 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3028 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3029
3030 return 0;
3031 }
3032
3033 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3034 {
3035 WARN_ON(in_interrupt());
3036 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3037 msleep(1);
3038 ixgbe_down(adapter);
3039 /*
3040 * If SR-IOV enabled then wait a bit before bringing the adapter
3041 * back up to give the VFs time to respond to the reset. The
3042 * two second wait is based upon the watchdog timer cycle in
3043 * the VF driver.
3044 */
3045 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3046 msleep(2000);
3047 ixgbe_up(adapter);
3048 clear_bit(__IXGBE_RESETTING, &adapter->state);
3049 }
3050
3051 int ixgbe_up(struct ixgbe_adapter *adapter)
3052 {
3053 /* hardware has been reset, we need to reload some things */
3054 ixgbe_configure(adapter);
3055
3056 return ixgbe_up_complete(adapter);
3057 }
3058
3059 void ixgbe_reset(struct ixgbe_adapter *adapter)
3060 {
3061 struct ixgbe_hw *hw = &adapter->hw;
3062 int err;
3063
3064 err = hw->mac.ops.init_hw(hw);
3065 switch (err) {
3066 case 0:
3067 case IXGBE_ERR_SFP_NOT_PRESENT:
3068 break;
3069 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3070 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3071 break;
3072 case IXGBE_ERR_EEPROM_VERSION:
3073 /* We are running on a pre-production device, log a warning */
3074 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3075 "adapter/LOM. Please be aware there may be issues "
3076 "associated with your hardware. If you are "
3077 "experiencing problems please contact your Intel or "
3078 "hardware representative who provided you with this "
3079 "hardware.\n");
3080 break;
3081 default:
3082 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3083 }
3084
3085 /* reprogram the RAR[0] in case user changed it. */
3086 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3087 IXGBE_RAH_AV);
3088 }
3089
3090 /**
3091 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3092 * @adapter: board private structure
3093 * @rx_ring: ring to free buffers from
3094 **/
3095 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3096 struct ixgbe_ring *rx_ring)
3097 {
3098 struct pci_dev *pdev = adapter->pdev;
3099 unsigned long size;
3100 unsigned int i;
3101
3102 /* Free all the Rx ring sk_buffs */
3103
3104 for (i = 0; i < rx_ring->count; i++) {
3105 struct ixgbe_rx_buffer *rx_buffer_info;
3106
3107 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3108 if (rx_buffer_info->dma) {
3109 pci_unmap_single(pdev, rx_buffer_info->dma,
3110 rx_ring->rx_buf_len,
3111 PCI_DMA_FROMDEVICE);
3112 rx_buffer_info->dma = 0;
3113 }
3114 if (rx_buffer_info->skb) {
3115 struct sk_buff *skb = rx_buffer_info->skb;
3116 rx_buffer_info->skb = NULL;
3117 do {
3118 struct sk_buff *this = skb;
3119 if (IXGBE_RSC_CB(this)->dma) {
3120 pci_unmap_single(pdev, IXGBE_RSC_CB(this)->dma,
3121 rx_ring->rx_buf_len,
3122 PCI_DMA_FROMDEVICE);
3123 IXGBE_RSC_CB(this)->dma = 0;
3124 }
3125 skb = skb->prev;
3126 dev_kfree_skb(this);
3127 } while (skb);
3128 }
3129 if (!rx_buffer_info->page)
3130 continue;
3131 if (rx_buffer_info->page_dma) {
3132 pci_unmap_page(pdev, rx_buffer_info->page_dma,
3133 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3134 rx_buffer_info->page_dma = 0;
3135 }
3136 put_page(rx_buffer_info->page);
3137 rx_buffer_info->page = NULL;
3138 rx_buffer_info->page_offset = 0;
3139 }
3140
3141 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3142 memset(rx_ring->rx_buffer_info, 0, size);
3143
3144 /* Zero out the descriptor ring */
3145 memset(rx_ring->desc, 0, rx_ring->size);
3146
3147 rx_ring->next_to_clean = 0;
3148 rx_ring->next_to_use = 0;
3149
3150 if (rx_ring->head)
3151 writel(0, adapter->hw.hw_addr + rx_ring->head);
3152 if (rx_ring->tail)
3153 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3154 }
3155
3156 /**
3157 * ixgbe_clean_tx_ring - Free Tx Buffers
3158 * @adapter: board private structure
3159 * @tx_ring: ring to be cleaned
3160 **/
3161 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3162 struct ixgbe_ring *tx_ring)
3163 {
3164 struct ixgbe_tx_buffer *tx_buffer_info;
3165 unsigned long size;
3166 unsigned int i;
3167
3168 /* Free all the Tx ring sk_buffs */
3169
3170 for (i = 0; i < tx_ring->count; i++) {
3171 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3172 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3173 }
3174
3175 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3176 memset(tx_ring->tx_buffer_info, 0, size);
3177
3178 /* Zero out the descriptor ring */
3179 memset(tx_ring->desc, 0, tx_ring->size);
3180
3181 tx_ring->next_to_use = 0;
3182 tx_ring->next_to_clean = 0;
3183
3184 if (tx_ring->head)
3185 writel(0, adapter->hw.hw_addr + tx_ring->head);
3186 if (tx_ring->tail)
3187 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3188 }
3189
3190 /**
3191 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3192 * @adapter: board private structure
3193 **/
3194 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3195 {
3196 int i;
3197
3198 for (i = 0; i < adapter->num_rx_queues; i++)
3199 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3200 }
3201
3202 /**
3203 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3204 * @adapter: board private structure
3205 **/
3206 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3207 {
3208 int i;
3209
3210 for (i = 0; i < adapter->num_tx_queues; i++)
3211 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3212 }
3213
3214 void ixgbe_down(struct ixgbe_adapter *adapter)
3215 {
3216 struct net_device *netdev = adapter->netdev;
3217 struct ixgbe_hw *hw = &adapter->hw;
3218 u32 rxctrl;
3219 u32 txdctl;
3220 int i, j;
3221
3222 /* signal that we are down to the interrupt handler */
3223 set_bit(__IXGBE_DOWN, &adapter->state);
3224
3225 /* disable receive for all VFs and wait one second */
3226 if (adapter->num_vfs) {
3227 /* ping all the active vfs to let them know we are going down */
3228 ixgbe_ping_all_vfs(adapter);
3229
3230 /* Disable all VFTE/VFRE TX/RX */
3231 ixgbe_disable_tx_rx(adapter);
3232
3233 /* Mark all the VFs as inactive */
3234 for (i = 0 ; i < adapter->num_vfs; i++)
3235 adapter->vfinfo[i].clear_to_send = 0;
3236 }
3237
3238 /* disable receives */
3239 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3240 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3241
3242 netif_tx_disable(netdev);
3243
3244 IXGBE_WRITE_FLUSH(hw);
3245 msleep(10);
3246
3247 netif_tx_stop_all_queues(netdev);
3248
3249 ixgbe_irq_disable(adapter);
3250
3251 ixgbe_napi_disable_all(adapter);
3252
3253 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3254 del_timer_sync(&adapter->sfp_timer);
3255 del_timer_sync(&adapter->watchdog_timer);
3256 cancel_work_sync(&adapter->watchdog_task);
3257
3258 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3259 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3260 cancel_work_sync(&adapter->fdir_reinit_task);
3261
3262 /* disable transmits in the hardware now that interrupts are off */
3263 for (i = 0; i < adapter->num_tx_queues; i++) {
3264 j = adapter->tx_ring[i]->reg_idx;
3265 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3266 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3267 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3268 }
3269 /* Disable the Tx DMA engine on 82599 */
3270 if (hw->mac.type == ixgbe_mac_82599EB)
3271 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3272 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3273 ~IXGBE_DMATXCTL_TE));
3274
3275 netif_carrier_off(netdev);
3276
3277 /* clear n-tuple filters that are cached */
3278 ethtool_ntuple_flush(netdev);
3279
3280 if (!pci_channel_offline(adapter->pdev))
3281 ixgbe_reset(adapter);
3282 ixgbe_clean_all_tx_rings(adapter);
3283 ixgbe_clean_all_rx_rings(adapter);
3284
3285 #ifdef CONFIG_IXGBE_DCA
3286 /* since we reset the hardware DCA settings were cleared */
3287 ixgbe_setup_dca(adapter);
3288 #endif
3289 }
3290
3291 /**
3292 * ixgbe_poll - NAPI Rx polling callback
3293 * @napi: structure for representing this polling device
3294 * @budget: how many packets driver is allowed to clean
3295 *
3296 * This function is used for legacy and MSI, NAPI mode
3297 **/
3298 static int ixgbe_poll(struct napi_struct *napi, int budget)
3299 {
3300 struct ixgbe_q_vector *q_vector =
3301 container_of(napi, struct ixgbe_q_vector, napi);
3302 struct ixgbe_adapter *adapter = q_vector->adapter;
3303 int tx_clean_complete, work_done = 0;
3304
3305 #ifdef CONFIG_IXGBE_DCA
3306 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3307 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3308 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3309 }
3310 #endif
3311
3312 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3313 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3314
3315 if (!tx_clean_complete)
3316 work_done = budget;
3317
3318 /* If budget not fully consumed, exit the polling mode */
3319 if (work_done < budget) {
3320 napi_complete(napi);
3321 if (adapter->rx_itr_setting & 1)
3322 ixgbe_set_itr(adapter);
3323 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3324 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3325 }
3326 return work_done;
3327 }
3328
3329 /**
3330 * ixgbe_tx_timeout - Respond to a Tx Hang
3331 * @netdev: network interface device structure
3332 **/
3333 static void ixgbe_tx_timeout(struct net_device *netdev)
3334 {
3335 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3336
3337 /* Do the reset outside of interrupt context */
3338 schedule_work(&adapter->reset_task);
3339 }
3340
3341 static void ixgbe_reset_task(struct work_struct *work)
3342 {
3343 struct ixgbe_adapter *adapter;
3344 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3345
3346 /* If we're already down or resetting, just bail */
3347 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3348 test_bit(__IXGBE_RESETTING, &adapter->state))
3349 return;
3350
3351 adapter->tx_timeout_count++;
3352
3353 ixgbe_reinit_locked(adapter);
3354 }
3355
3356 #ifdef CONFIG_IXGBE_DCB
3357 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3358 {
3359 bool ret = false;
3360 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3361
3362 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3363 return ret;
3364
3365 f->mask = 0x7 << 3;
3366 adapter->num_rx_queues = f->indices;
3367 adapter->num_tx_queues = f->indices;
3368 ret = true;
3369
3370 return ret;
3371 }
3372 #endif
3373
3374 /**
3375 * ixgbe_set_rss_queues: Allocate queues for RSS
3376 * @adapter: board private structure to initialize
3377 *
3378 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3379 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3380 *
3381 **/
3382 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3383 {
3384 bool ret = false;
3385 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3386
3387 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3388 f->mask = 0xF;
3389 adapter->num_rx_queues = f->indices;
3390 adapter->num_tx_queues = f->indices;
3391 ret = true;
3392 } else {
3393 ret = false;
3394 }
3395
3396 return ret;
3397 }
3398
3399 /**
3400 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3401 * @adapter: board private structure to initialize
3402 *
3403 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3404 * to the original CPU that initiated the Tx session. This runs in addition
3405 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3406 * Rx load across CPUs using RSS.
3407 *
3408 **/
3409 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3410 {
3411 bool ret = false;
3412 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3413
3414 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3415 f_fdir->mask = 0;
3416
3417 /* Flow Director must have RSS enabled */
3418 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3419 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3420 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3421 adapter->num_tx_queues = f_fdir->indices;
3422 adapter->num_rx_queues = f_fdir->indices;
3423 ret = true;
3424 } else {
3425 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3426 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3427 }
3428 return ret;
3429 }
3430
3431 #ifdef IXGBE_FCOE
3432 /**
3433 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3434 * @adapter: board private structure to initialize
3435 *
3436 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3437 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3438 * rx queues out of the max number of rx queues, instead, it is used as the
3439 * index of the first rx queue used by FCoE.
3440 *
3441 **/
3442 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3443 {
3444 bool ret = false;
3445 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3446
3447 f->indices = min((int)num_online_cpus(), f->indices);
3448 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3449 adapter->num_rx_queues = 1;
3450 adapter->num_tx_queues = 1;
3451 #ifdef CONFIG_IXGBE_DCB
3452 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3453 DPRINTK(PROBE, INFO, "FCoE enabled with DCB\n");
3454 ixgbe_set_dcb_queues(adapter);
3455 }
3456 #endif
3457 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3458 DPRINTK(PROBE, INFO, "FCoE enabled with RSS\n");
3459 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3460 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3461 ixgbe_set_fdir_queues(adapter);
3462 else
3463 ixgbe_set_rss_queues(adapter);
3464 }
3465 /* adding FCoE rx rings to the end */
3466 f->mask = adapter->num_rx_queues;
3467 adapter->num_rx_queues += f->indices;
3468 adapter->num_tx_queues += f->indices;
3469
3470 ret = true;
3471 }
3472
3473 return ret;
3474 }
3475
3476 #endif /* IXGBE_FCOE */
3477 /**
3478 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3479 * @adapter: board private structure to initialize
3480 *
3481 * IOV doesn't actually use anything, so just NAK the
3482 * request for now and let the other queue routines
3483 * figure out what to do.
3484 */
3485 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3486 {
3487 return false;
3488 }
3489
3490 /*
3491 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3492 * @adapter: board private structure to initialize
3493 *
3494 * This is the top level queue allocation routine. The order here is very
3495 * important, starting with the "most" number of features turned on at once,
3496 * and ending with the smallest set of features. This way large combinations
3497 * can be allocated if they're turned on, and smaller combinations are the
3498 * fallthrough conditions.
3499 *
3500 **/
3501 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3502 {
3503 /* Start with base case */
3504 adapter->num_rx_queues = 1;
3505 adapter->num_tx_queues = 1;
3506 adapter->num_rx_pools = adapter->num_rx_queues;
3507 adapter->num_rx_queues_per_pool = 1;
3508
3509 if (ixgbe_set_sriov_queues(adapter))
3510 return;
3511
3512 #ifdef IXGBE_FCOE
3513 if (ixgbe_set_fcoe_queues(adapter))
3514 goto done;
3515
3516 #endif /* IXGBE_FCOE */
3517 #ifdef CONFIG_IXGBE_DCB
3518 if (ixgbe_set_dcb_queues(adapter))
3519 goto done;
3520
3521 #endif
3522 if (ixgbe_set_fdir_queues(adapter))
3523 goto done;
3524
3525 if (ixgbe_set_rss_queues(adapter))
3526 goto done;
3527
3528 /* fallback to base case */
3529 adapter->num_rx_queues = 1;
3530 adapter->num_tx_queues = 1;
3531
3532 done:
3533 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3534 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3535 }
3536
3537 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3538 int vectors)
3539 {
3540 int err, vector_threshold;
3541
3542 /* We'll want at least 3 (vector_threshold):
3543 * 1) TxQ[0] Cleanup
3544 * 2) RxQ[0] Cleanup
3545 * 3) Other (Link Status Change, etc.)
3546 * 4) TCP Timer (optional)
3547 */
3548 vector_threshold = MIN_MSIX_COUNT;
3549
3550 /* The more we get, the more we will assign to Tx/Rx Cleanup
3551 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3552 * Right now, we simply care about how many we'll get; we'll
3553 * set them up later while requesting irq's.
3554 */
3555 while (vectors >= vector_threshold) {
3556 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3557 vectors);
3558 if (!err) /* Success in acquiring all requested vectors. */
3559 break;
3560 else if (err < 0)
3561 vectors = 0; /* Nasty failure, quit now */
3562 else /* err == number of vectors we should try again with */
3563 vectors = err;
3564 }
3565
3566 if (vectors < vector_threshold) {
3567 /* Can't allocate enough MSI-X interrupts? Oh well.
3568 * This just means we'll go with either a single MSI
3569 * vector or fall back to legacy interrupts.
3570 */
3571 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3572 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3573 kfree(adapter->msix_entries);
3574 adapter->msix_entries = NULL;
3575 } else {
3576 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3577 /*
3578 * Adjust for only the vectors we'll use, which is minimum
3579 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3580 * vectors we were allocated.
3581 */
3582 adapter->num_msix_vectors = min(vectors,
3583 adapter->max_msix_q_vectors + NON_Q_VECTORS);
3584 }
3585 }
3586
3587 /**
3588 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3589 * @adapter: board private structure to initialize
3590 *
3591 * Cache the descriptor ring offsets for RSS to the assigned rings.
3592 *
3593 **/
3594 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3595 {
3596 int i;
3597 bool ret = false;
3598
3599 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3600 for (i = 0; i < adapter->num_rx_queues; i++)
3601 adapter->rx_ring[i]->reg_idx = i;
3602 for (i = 0; i < adapter->num_tx_queues; i++)
3603 adapter->tx_ring[i]->reg_idx = i;
3604 ret = true;
3605 } else {
3606 ret = false;
3607 }
3608
3609 return ret;
3610 }
3611
3612 #ifdef CONFIG_IXGBE_DCB
3613 /**
3614 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3615 * @adapter: board private structure to initialize
3616 *
3617 * Cache the descriptor ring offsets for DCB to the assigned rings.
3618 *
3619 **/
3620 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3621 {
3622 int i;
3623 bool ret = false;
3624 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3625
3626 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3627 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3628 /* the number of queues is assumed to be symmetric */
3629 for (i = 0; i < dcb_i; i++) {
3630 adapter->rx_ring[i]->reg_idx = i << 3;
3631 adapter->tx_ring[i]->reg_idx = i << 2;
3632 }
3633 ret = true;
3634 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3635 if (dcb_i == 8) {
3636 /*
3637 * Tx TC0 starts at: descriptor queue 0
3638 * Tx TC1 starts at: descriptor queue 32
3639 * Tx TC2 starts at: descriptor queue 64
3640 * Tx TC3 starts at: descriptor queue 80
3641 * Tx TC4 starts at: descriptor queue 96
3642 * Tx TC5 starts at: descriptor queue 104
3643 * Tx TC6 starts at: descriptor queue 112
3644 * Tx TC7 starts at: descriptor queue 120
3645 *
3646 * Rx TC0-TC7 are offset by 16 queues each
3647 */
3648 for (i = 0; i < 3; i++) {
3649 adapter->tx_ring[i]->reg_idx = i << 5;
3650 adapter->rx_ring[i]->reg_idx = i << 4;
3651 }
3652 for ( ; i < 5; i++) {
3653 adapter->tx_ring[i]->reg_idx =
3654 ((i + 2) << 4);
3655 adapter->rx_ring[i]->reg_idx = i << 4;
3656 }
3657 for ( ; i < dcb_i; i++) {
3658 adapter->tx_ring[i]->reg_idx =
3659 ((i + 8) << 3);
3660 adapter->rx_ring[i]->reg_idx = i << 4;
3661 }
3662
3663 ret = true;
3664 } else if (dcb_i == 4) {
3665 /*
3666 * Tx TC0 starts at: descriptor queue 0
3667 * Tx TC1 starts at: descriptor queue 64
3668 * Tx TC2 starts at: descriptor queue 96
3669 * Tx TC3 starts at: descriptor queue 112
3670 *
3671 * Rx TC0-TC3 are offset by 32 queues each
3672 */
3673 adapter->tx_ring[0]->reg_idx = 0;
3674 adapter->tx_ring[1]->reg_idx = 64;
3675 adapter->tx_ring[2]->reg_idx = 96;
3676 adapter->tx_ring[3]->reg_idx = 112;
3677 for (i = 0 ; i < dcb_i; i++)
3678 adapter->rx_ring[i]->reg_idx = i << 5;
3679
3680 ret = true;
3681 } else {
3682 ret = false;
3683 }
3684 } else {
3685 ret = false;
3686 }
3687 } else {
3688 ret = false;
3689 }
3690
3691 return ret;
3692 }
3693 #endif
3694
3695 /**
3696 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3697 * @adapter: board private structure to initialize
3698 *
3699 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3700 *
3701 **/
3702 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3703 {
3704 int i;
3705 bool ret = false;
3706
3707 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3708 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3709 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3710 for (i = 0; i < adapter->num_rx_queues; i++)
3711 adapter->rx_ring[i]->reg_idx = i;
3712 for (i = 0; i < adapter->num_tx_queues; i++)
3713 adapter->tx_ring[i]->reg_idx = i;
3714 ret = true;
3715 }
3716
3717 return ret;
3718 }
3719
3720 #ifdef IXGBE_FCOE
3721 /**
3722 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3723 * @adapter: board private structure to initialize
3724 *
3725 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3726 *
3727 */
3728 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3729 {
3730 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3731 bool ret = false;
3732 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3733
3734 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3735 #ifdef CONFIG_IXGBE_DCB
3736 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3737 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3738
3739 ixgbe_cache_ring_dcb(adapter);
3740 /* find out queues in TC for FCoE */
3741 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
3742 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
3743 /*
3744 * In 82599, the number of Tx queues for each traffic
3745 * class for both 8-TC and 4-TC modes are:
3746 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3747 * 8 TCs: 32 32 16 16 8 8 8 8
3748 * 4 TCs: 64 64 32 32
3749 * We have max 8 queues for FCoE, where 8 the is
3750 * FCoE redirection table size. If TC for FCoE is
3751 * less than or equal to TC3, we have enough queues
3752 * to add max of 8 queues for FCoE, so we start FCoE
3753 * tx descriptor from the next one, i.e., reg_idx + 1.
3754 * If TC for FCoE is above TC3, implying 8 TC mode,
3755 * and we need 8 for FCoE, we have to take all queues
3756 * in that traffic class for FCoE.
3757 */
3758 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3759 fcoe_tx_i--;
3760 }
3761 #endif /* CONFIG_IXGBE_DCB */
3762 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3763 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3764 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3765 ixgbe_cache_ring_fdir(adapter);
3766 else
3767 ixgbe_cache_ring_rss(adapter);
3768
3769 fcoe_rx_i = f->mask;
3770 fcoe_tx_i = f->mask;
3771 }
3772 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3773 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
3774 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
3775 }
3776 ret = true;
3777 }
3778 return ret;
3779 }
3780
3781 #endif /* IXGBE_FCOE */
3782 /**
3783 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3784 * @adapter: board private structure to initialize
3785 *
3786 * SR-IOV doesn't use any descriptor rings but changes the default if
3787 * no other mapping is used.
3788 *
3789 */
3790 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
3791 {
3792 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
3793 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
3794 if (adapter->num_vfs)
3795 return true;
3796 else
3797 return false;
3798 }
3799
3800 /**
3801 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3802 * @adapter: board private structure to initialize
3803 *
3804 * Once we know the feature-set enabled for the device, we'll cache
3805 * the register offset the descriptor ring is assigned to.
3806 *
3807 * Note, the order the various feature calls is important. It must start with
3808 * the "most" features enabled at the same time, then trickle down to the
3809 * least amount of features turned on at once.
3810 **/
3811 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3812 {
3813 /* start with default case */
3814 adapter->rx_ring[0]->reg_idx = 0;
3815 adapter->tx_ring[0]->reg_idx = 0;
3816
3817 if (ixgbe_cache_ring_sriov(adapter))
3818 return;
3819
3820 #ifdef IXGBE_FCOE
3821 if (ixgbe_cache_ring_fcoe(adapter))
3822 return;
3823
3824 #endif /* IXGBE_FCOE */
3825 #ifdef CONFIG_IXGBE_DCB
3826 if (ixgbe_cache_ring_dcb(adapter))
3827 return;
3828
3829 #endif
3830 if (ixgbe_cache_ring_fdir(adapter))
3831 return;
3832
3833 if (ixgbe_cache_ring_rss(adapter))
3834 return;
3835 }
3836
3837 /**
3838 * ixgbe_alloc_queues - Allocate memory for all rings
3839 * @adapter: board private structure to initialize
3840 *
3841 * We allocate one ring per queue at run-time since we don't know the
3842 * number of queues at compile-time. The polling_netdev array is
3843 * intended for Multiqueue, but should work fine with a single queue.
3844 **/
3845 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3846 {
3847 int i;
3848 int orig_node = adapter->node;
3849
3850 for (i = 0; i < adapter->num_tx_queues; i++) {
3851 struct ixgbe_ring *ring = adapter->tx_ring[i];
3852 if (orig_node == -1) {
3853 int cur_node = next_online_node(adapter->node);
3854 if (cur_node == MAX_NUMNODES)
3855 cur_node = first_online_node;
3856 adapter->node = cur_node;
3857 }
3858 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3859 adapter->node);
3860 if (!ring)
3861 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3862 if (!ring)
3863 goto err_tx_ring_allocation;
3864 ring->count = adapter->tx_ring_count;
3865 ring->queue_index = i;
3866 ring->numa_node = adapter->node;
3867
3868 adapter->tx_ring[i] = ring;
3869 }
3870
3871 /* Restore the adapter's original node */
3872 adapter->node = orig_node;
3873
3874 for (i = 0; i < adapter->num_rx_queues; i++) {
3875 struct ixgbe_ring *ring = adapter->rx_ring[i];
3876 if (orig_node == -1) {
3877 int cur_node = next_online_node(adapter->node);
3878 if (cur_node == MAX_NUMNODES)
3879 cur_node = first_online_node;
3880 adapter->node = cur_node;
3881 }
3882 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3883 adapter->node);
3884 if (!ring)
3885 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3886 if (!ring)
3887 goto err_rx_ring_allocation;
3888 ring->count = adapter->rx_ring_count;
3889 ring->queue_index = i;
3890 ring->numa_node = adapter->node;
3891
3892 adapter->rx_ring[i] = ring;
3893 }
3894
3895 /* Restore the adapter's original node */
3896 adapter->node = orig_node;
3897
3898 ixgbe_cache_ring_register(adapter);
3899
3900 return 0;
3901
3902 err_rx_ring_allocation:
3903 for (i = 0; i < adapter->num_tx_queues; i++)
3904 kfree(adapter->tx_ring[i]);
3905 err_tx_ring_allocation:
3906 return -ENOMEM;
3907 }
3908
3909 /**
3910 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3911 * @adapter: board private structure to initialize
3912 *
3913 * Attempt to configure the interrupts using the best available
3914 * capabilities of the hardware and the kernel.
3915 **/
3916 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3917 {
3918 struct ixgbe_hw *hw = &adapter->hw;
3919 int err = 0;
3920 int vector, v_budget;
3921
3922 /*
3923 * It's easy to be greedy for MSI-X vectors, but it really
3924 * doesn't do us much good if we have a lot more vectors
3925 * than CPU's. So let's be conservative and only ask for
3926 * (roughly) the same number of vectors as there are CPU's.
3927 */
3928 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3929 (int)num_online_cpus()) + NON_Q_VECTORS;
3930
3931 /*
3932 * At the same time, hardware can only support a maximum of
3933 * hw.mac->max_msix_vectors vectors. With features
3934 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3935 * descriptor queues supported by our device. Thus, we cap it off in
3936 * those rare cases where the cpu count also exceeds our vector limit.
3937 */
3938 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3939
3940 /* A failure in MSI-X entry allocation isn't fatal, but it does
3941 * mean we disable MSI-X capabilities of the adapter. */
3942 adapter->msix_entries = kcalloc(v_budget,
3943 sizeof(struct msix_entry), GFP_KERNEL);
3944 if (adapter->msix_entries) {
3945 for (vector = 0; vector < v_budget; vector++)
3946 adapter->msix_entries[vector].entry = vector;
3947
3948 ixgbe_acquire_msix_vectors(adapter, v_budget);
3949
3950 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3951 goto out;
3952 }
3953
3954 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3955 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3956 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3957 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3958 adapter->atr_sample_rate = 0;
3959 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3960 ixgbe_disable_sriov(adapter);
3961
3962 ixgbe_set_num_queues(adapter);
3963
3964 err = pci_enable_msi(adapter->pdev);
3965 if (!err) {
3966 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3967 } else {
3968 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3969 "falling back to legacy. Error: %d\n", err);
3970 /* reset err */
3971 err = 0;
3972 }
3973
3974 out:
3975 return err;
3976 }
3977
3978 /**
3979 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3980 * @adapter: board private structure to initialize
3981 *
3982 * We allocate one q_vector per queue interrupt. If allocation fails we
3983 * return -ENOMEM.
3984 **/
3985 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3986 {
3987 int q_idx, num_q_vectors;
3988 struct ixgbe_q_vector *q_vector;
3989 int napi_vectors;
3990 int (*poll)(struct napi_struct *, int);
3991
3992 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3993 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3994 napi_vectors = adapter->num_rx_queues;
3995 poll = &ixgbe_clean_rxtx_many;
3996 } else {
3997 num_q_vectors = 1;
3998 napi_vectors = 1;
3999 poll = &ixgbe_poll;
4000 }
4001
4002 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4003 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4004 GFP_KERNEL, adapter->node);
4005 if (!q_vector)
4006 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4007 GFP_KERNEL);
4008 if (!q_vector)
4009 goto err_out;
4010 q_vector->adapter = adapter;
4011 if (q_vector->txr_count && !q_vector->rxr_count)
4012 q_vector->eitr = adapter->tx_eitr_param;
4013 else
4014 q_vector->eitr = adapter->rx_eitr_param;
4015 q_vector->v_idx = q_idx;
4016 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4017 adapter->q_vector[q_idx] = q_vector;
4018 }
4019
4020 return 0;
4021
4022 err_out:
4023 while (q_idx) {
4024 q_idx--;
4025 q_vector = adapter->q_vector[q_idx];
4026 netif_napi_del(&q_vector->napi);
4027 kfree(q_vector);
4028 adapter->q_vector[q_idx] = NULL;
4029 }
4030 return -ENOMEM;
4031 }
4032
4033 /**
4034 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4035 * @adapter: board private structure to initialize
4036 *
4037 * This function frees the memory allocated to the q_vectors. In addition if
4038 * NAPI is enabled it will delete any references to the NAPI struct prior
4039 * to freeing the q_vector.
4040 **/
4041 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4042 {
4043 int q_idx, num_q_vectors;
4044
4045 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4046 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4047 else
4048 num_q_vectors = 1;
4049
4050 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4051 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4052 adapter->q_vector[q_idx] = NULL;
4053 netif_napi_del(&q_vector->napi);
4054 kfree(q_vector);
4055 }
4056 }
4057
4058 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4059 {
4060 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4061 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4062 pci_disable_msix(adapter->pdev);
4063 kfree(adapter->msix_entries);
4064 adapter->msix_entries = NULL;
4065 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4066 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4067 pci_disable_msi(adapter->pdev);
4068 }
4069 return;
4070 }
4071
4072 /**
4073 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4074 * @adapter: board private structure to initialize
4075 *
4076 * We determine which interrupt scheme to use based on...
4077 * - Kernel support (MSI, MSI-X)
4078 * - which can be user-defined (via MODULE_PARAM)
4079 * - Hardware queue count (num_*_queues)
4080 * - defined by miscellaneous hardware support/features (RSS, etc.)
4081 **/
4082 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4083 {
4084 int err;
4085
4086 /* Number of supported queues */
4087 ixgbe_set_num_queues(adapter);
4088
4089 err = ixgbe_set_interrupt_capability(adapter);
4090 if (err) {
4091 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4092 goto err_set_interrupt;
4093 }
4094
4095 err = ixgbe_alloc_q_vectors(adapter);
4096 if (err) {
4097 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4098 "vectors\n");
4099 goto err_alloc_q_vectors;
4100 }
4101
4102 err = ixgbe_alloc_queues(adapter);
4103 if (err) {
4104 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4105 goto err_alloc_queues;
4106 }
4107
4108 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
4109 "Tx Queue count = %u\n",
4110 (adapter->num_rx_queues > 1) ? "Enabled" :
4111 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
4112
4113 set_bit(__IXGBE_DOWN, &adapter->state);
4114
4115 return 0;
4116
4117 err_alloc_queues:
4118 ixgbe_free_q_vectors(adapter);
4119 err_alloc_q_vectors:
4120 ixgbe_reset_interrupt_capability(adapter);
4121 err_set_interrupt:
4122 return err;
4123 }
4124
4125 /**
4126 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4127 * @adapter: board private structure to clear interrupt scheme on
4128 *
4129 * We go through and clear interrupt specific resources and reset the structure
4130 * to pre-load conditions
4131 **/
4132 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4133 {
4134 int i;
4135
4136 for (i = 0; i < adapter->num_tx_queues; i++) {
4137 kfree(adapter->tx_ring[i]);
4138 adapter->tx_ring[i] = NULL;
4139 }
4140 for (i = 0; i < adapter->num_rx_queues; i++) {
4141 kfree(adapter->rx_ring[i]);
4142 adapter->rx_ring[i] = NULL;
4143 }
4144
4145 ixgbe_free_q_vectors(adapter);
4146 ixgbe_reset_interrupt_capability(adapter);
4147 }
4148
4149 /**
4150 * ixgbe_sfp_timer - worker thread to find a missing module
4151 * @data: pointer to our adapter struct
4152 **/
4153 static void ixgbe_sfp_timer(unsigned long data)
4154 {
4155 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4156
4157 /*
4158 * Do the sfp_timer outside of interrupt context due to the
4159 * delays that sfp+ detection requires
4160 */
4161 schedule_work(&adapter->sfp_task);
4162 }
4163
4164 /**
4165 * ixgbe_sfp_task - worker thread to find a missing module
4166 * @work: pointer to work_struct containing our data
4167 **/
4168 static void ixgbe_sfp_task(struct work_struct *work)
4169 {
4170 struct ixgbe_adapter *adapter = container_of(work,
4171 struct ixgbe_adapter,
4172 sfp_task);
4173 struct ixgbe_hw *hw = &adapter->hw;
4174
4175 if ((hw->phy.type == ixgbe_phy_nl) &&
4176 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4177 s32 ret = hw->phy.ops.identify_sfp(hw);
4178 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4179 goto reschedule;
4180 ret = hw->phy.ops.reset(hw);
4181 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4182 dev_err(&adapter->pdev->dev, "failed to initialize "
4183 "because an unsupported SFP+ module type "
4184 "was detected.\n"
4185 "Reload the driver after installing a "
4186 "supported module.\n");
4187 unregister_netdev(adapter->netdev);
4188 } else {
4189 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4190 hw->phy.sfp_type);
4191 }
4192 /* don't need this routine any more */
4193 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4194 }
4195 return;
4196 reschedule:
4197 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4198 mod_timer(&adapter->sfp_timer,
4199 round_jiffies(jiffies + (2 * HZ)));
4200 }
4201
4202 /**
4203 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4204 * @adapter: board private structure to initialize
4205 *
4206 * ixgbe_sw_init initializes the Adapter private data structure.
4207 * Fields are initialized based on PCI device information and
4208 * OS network device settings (MTU size).
4209 **/
4210 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4211 {
4212 struct ixgbe_hw *hw = &adapter->hw;
4213 struct pci_dev *pdev = adapter->pdev;
4214 struct net_device *dev = adapter->netdev;
4215 unsigned int rss;
4216 #ifdef CONFIG_IXGBE_DCB
4217 int j;
4218 struct tc_configuration *tc;
4219 #endif
4220
4221 /* PCI config space info */
4222
4223 hw->vendor_id = pdev->vendor;
4224 hw->device_id = pdev->device;
4225 hw->revision_id = pdev->revision;
4226 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4227 hw->subsystem_device_id = pdev->subsystem_device;
4228
4229 /* Set capability flags */
4230 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4231 adapter->ring_feature[RING_F_RSS].indices = rss;
4232 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4233 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4234 if (hw->mac.type == ixgbe_mac_82598EB) {
4235 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4236 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4237 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4238 } else if (hw->mac.type == ixgbe_mac_82599EB) {
4239 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4240 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4241 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4242 if (dev->features & NETIF_F_NTUPLE) {
4243 /* Flow Director perfect filter enabled */
4244 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4245 adapter->atr_sample_rate = 0;
4246 spin_lock_init(&adapter->fdir_perfect_lock);
4247 } else {
4248 /* Flow Director hash filters enabled */
4249 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4250 adapter->atr_sample_rate = 20;
4251 }
4252 adapter->ring_feature[RING_F_FDIR].indices =
4253 IXGBE_MAX_FDIR_INDICES;
4254 adapter->fdir_pballoc = 0;
4255 #ifdef IXGBE_FCOE
4256 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4257 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4258 adapter->ring_feature[RING_F_FCOE].indices = 0;
4259 #ifdef CONFIG_IXGBE_DCB
4260 /* Default traffic class to use for FCoE */
4261 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4262 #endif
4263 #endif /* IXGBE_FCOE */
4264 }
4265
4266 #ifdef CONFIG_IXGBE_DCB
4267 /* Configure DCB traffic classes */
4268 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4269 tc = &adapter->dcb_cfg.tc_config[j];
4270 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4271 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4272 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4273 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4274 tc->dcb_pfc = pfc_disabled;
4275 }
4276 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4277 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4278 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4279 adapter->dcb_cfg.pfc_mode_enable = false;
4280 adapter->dcb_cfg.round_robin_enable = false;
4281 adapter->dcb_set_bitmap = 0x00;
4282 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4283 adapter->ring_feature[RING_F_DCB].indices);
4284
4285 #endif
4286
4287 /* default flow control settings */
4288 hw->fc.requested_mode = ixgbe_fc_full;
4289 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4290 #ifdef CONFIG_DCB
4291 adapter->last_lfc_mode = hw->fc.current_mode;
4292 #endif
4293 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4294 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4295 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4296 hw->fc.send_xon = true;
4297 hw->fc.disable_fc_autoneg = false;
4298
4299 /* enable itr by default in dynamic mode */
4300 adapter->rx_itr_setting = 1;
4301 adapter->rx_eitr_param = 20000;
4302 adapter->tx_itr_setting = 1;
4303 adapter->tx_eitr_param = 10000;
4304
4305 /* set defaults for eitr in MegaBytes */
4306 adapter->eitr_low = 10;
4307 adapter->eitr_high = 20;
4308
4309 /* set default ring sizes */
4310 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4311 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4312
4313 /* initialize eeprom parameters */
4314 if (ixgbe_init_eeprom_params_generic(hw)) {
4315 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4316 return -EIO;
4317 }
4318
4319 /* enable rx csum by default */
4320 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4321
4322 /* get assigned NUMA node */
4323 adapter->node = dev_to_node(&pdev->dev);
4324
4325 set_bit(__IXGBE_DOWN, &adapter->state);
4326
4327 return 0;
4328 }
4329
4330 /**
4331 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4332 * @adapter: board private structure
4333 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4334 *
4335 * Return 0 on success, negative on failure
4336 **/
4337 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4338 struct ixgbe_ring *tx_ring)
4339 {
4340 struct pci_dev *pdev = adapter->pdev;
4341 int size;
4342
4343 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4344 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4345 if (!tx_ring->tx_buffer_info)
4346 tx_ring->tx_buffer_info = vmalloc(size);
4347 if (!tx_ring->tx_buffer_info)
4348 goto err;
4349 memset(tx_ring->tx_buffer_info, 0, size);
4350
4351 /* round up to nearest 4K */
4352 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4353 tx_ring->size = ALIGN(tx_ring->size, 4096);
4354
4355 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4356 &tx_ring->dma);
4357 if (!tx_ring->desc)
4358 goto err;
4359
4360 tx_ring->next_to_use = 0;
4361 tx_ring->next_to_clean = 0;
4362 tx_ring->work_limit = tx_ring->count;
4363 return 0;
4364
4365 err:
4366 vfree(tx_ring->tx_buffer_info);
4367 tx_ring->tx_buffer_info = NULL;
4368 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4369 "descriptor ring\n");
4370 return -ENOMEM;
4371 }
4372
4373 /**
4374 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4375 * @adapter: board private structure
4376 *
4377 * If this function returns with an error, then it's possible one or
4378 * more of the rings is populated (while the rest are not). It is the
4379 * callers duty to clean those orphaned rings.
4380 *
4381 * Return 0 on success, negative on failure
4382 **/
4383 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4384 {
4385 int i, err = 0;
4386
4387 for (i = 0; i < adapter->num_tx_queues; i++) {
4388 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4389 if (!err)
4390 continue;
4391 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4392 break;
4393 }
4394
4395 return err;
4396 }
4397
4398 /**
4399 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4400 * @adapter: board private structure
4401 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4402 *
4403 * Returns 0 on success, negative on failure
4404 **/
4405 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4406 struct ixgbe_ring *rx_ring)
4407 {
4408 struct pci_dev *pdev = adapter->pdev;
4409 int size;
4410
4411 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4412 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4413 if (!rx_ring->rx_buffer_info)
4414 rx_ring->rx_buffer_info = vmalloc(size);
4415 if (!rx_ring->rx_buffer_info) {
4416 DPRINTK(PROBE, ERR,
4417 "vmalloc allocation failed for the rx desc ring\n");
4418 goto alloc_failed;
4419 }
4420 memset(rx_ring->rx_buffer_info, 0, size);
4421
4422 /* Round up to nearest 4K */
4423 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4424 rx_ring->size = ALIGN(rx_ring->size, 4096);
4425
4426 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4427
4428 if (!rx_ring->desc) {
4429 DPRINTK(PROBE, ERR,
4430 "Memory allocation failed for the rx desc ring\n");
4431 vfree(rx_ring->rx_buffer_info);
4432 goto alloc_failed;
4433 }
4434
4435 rx_ring->next_to_clean = 0;
4436 rx_ring->next_to_use = 0;
4437
4438 return 0;
4439
4440 alloc_failed:
4441 return -ENOMEM;
4442 }
4443
4444 /**
4445 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4446 * @adapter: board private structure
4447 *
4448 * If this function returns with an error, then it's possible one or
4449 * more of the rings is populated (while the rest are not). It is the
4450 * callers duty to clean those orphaned rings.
4451 *
4452 * Return 0 on success, negative on failure
4453 **/
4454
4455 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4456 {
4457 int i, err = 0;
4458
4459 for (i = 0; i < adapter->num_rx_queues; i++) {
4460 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
4461 if (!err)
4462 continue;
4463 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4464 break;
4465 }
4466
4467 return err;
4468 }
4469
4470 /**
4471 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4472 * @adapter: board private structure
4473 * @tx_ring: Tx descriptor ring for a specific queue
4474 *
4475 * Free all transmit software resources
4476 **/
4477 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4478 struct ixgbe_ring *tx_ring)
4479 {
4480 struct pci_dev *pdev = adapter->pdev;
4481
4482 ixgbe_clean_tx_ring(adapter, tx_ring);
4483
4484 vfree(tx_ring->tx_buffer_info);
4485 tx_ring->tx_buffer_info = NULL;
4486
4487 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4488
4489 tx_ring->desc = NULL;
4490 }
4491
4492 /**
4493 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4494 * @adapter: board private structure
4495 *
4496 * Free all transmit software resources
4497 **/
4498 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4499 {
4500 int i;
4501
4502 for (i = 0; i < adapter->num_tx_queues; i++)
4503 if (adapter->tx_ring[i]->desc)
4504 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
4505 }
4506
4507 /**
4508 * ixgbe_free_rx_resources - Free Rx Resources
4509 * @adapter: board private structure
4510 * @rx_ring: ring to clean the resources from
4511 *
4512 * Free all receive software resources
4513 **/
4514 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4515 struct ixgbe_ring *rx_ring)
4516 {
4517 struct pci_dev *pdev = adapter->pdev;
4518
4519 ixgbe_clean_rx_ring(adapter, rx_ring);
4520
4521 vfree(rx_ring->rx_buffer_info);
4522 rx_ring->rx_buffer_info = NULL;
4523
4524 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4525
4526 rx_ring->desc = NULL;
4527 }
4528
4529 /**
4530 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4531 * @adapter: board private structure
4532 *
4533 * Free all receive software resources
4534 **/
4535 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4536 {
4537 int i;
4538
4539 for (i = 0; i < adapter->num_rx_queues; i++)
4540 if (adapter->rx_ring[i]->desc)
4541 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
4542 }
4543
4544 /**
4545 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4546 * @netdev: network interface device structure
4547 * @new_mtu: new value for maximum frame size
4548 *
4549 * Returns 0 on success, negative on failure
4550 **/
4551 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4552 {
4553 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4554 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4555
4556 /* MTU < 68 is an error and causes problems on some kernels */
4557 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4558 return -EINVAL;
4559
4560 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4561 netdev->mtu, new_mtu);
4562 /* must set new MTU before calling down or up */
4563 netdev->mtu = new_mtu;
4564
4565 if (netif_running(netdev))
4566 ixgbe_reinit_locked(adapter);
4567
4568 return 0;
4569 }
4570
4571 /**
4572 * ixgbe_open - Called when a network interface is made active
4573 * @netdev: network interface device structure
4574 *
4575 * Returns 0 on success, negative value on failure
4576 *
4577 * The open entry point is called when a network interface is made
4578 * active by the system (IFF_UP). At this point all resources needed
4579 * for transmit and receive operations are allocated, the interrupt
4580 * handler is registered with the OS, the watchdog timer is started,
4581 * and the stack is notified that the interface is ready.
4582 **/
4583 static int ixgbe_open(struct net_device *netdev)
4584 {
4585 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4586 int err;
4587
4588 /* disallow open during test */
4589 if (test_bit(__IXGBE_TESTING, &adapter->state))
4590 return -EBUSY;
4591
4592 netif_carrier_off(netdev);
4593
4594 /* allocate transmit descriptors */
4595 err = ixgbe_setup_all_tx_resources(adapter);
4596 if (err)
4597 goto err_setup_tx;
4598
4599 /* allocate receive descriptors */
4600 err = ixgbe_setup_all_rx_resources(adapter);
4601 if (err)
4602 goto err_setup_rx;
4603
4604 ixgbe_configure(adapter);
4605
4606 err = ixgbe_request_irq(adapter);
4607 if (err)
4608 goto err_req_irq;
4609
4610 err = ixgbe_up_complete(adapter);
4611 if (err)
4612 goto err_up;
4613
4614 netif_tx_start_all_queues(netdev);
4615
4616 return 0;
4617
4618 err_up:
4619 ixgbe_release_hw_control(adapter);
4620 ixgbe_free_irq(adapter);
4621 err_req_irq:
4622 err_setup_rx:
4623 ixgbe_free_all_rx_resources(adapter);
4624 err_setup_tx:
4625 ixgbe_free_all_tx_resources(adapter);
4626 ixgbe_reset(adapter);
4627
4628 return err;
4629 }
4630
4631 /**
4632 * ixgbe_close - Disables a network interface
4633 * @netdev: network interface device structure
4634 *
4635 * Returns 0, this is not allowed to fail
4636 *
4637 * The close entry point is called when an interface is de-activated
4638 * by the OS. The hardware is still under the drivers control, but
4639 * needs to be disabled. A global MAC reset is issued to stop the
4640 * hardware, and all transmit and receive resources are freed.
4641 **/
4642 static int ixgbe_close(struct net_device *netdev)
4643 {
4644 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4645
4646 ixgbe_down(adapter);
4647 ixgbe_free_irq(adapter);
4648
4649 ixgbe_free_all_tx_resources(adapter);
4650 ixgbe_free_all_rx_resources(adapter);
4651
4652 ixgbe_release_hw_control(adapter);
4653
4654 return 0;
4655 }
4656
4657 #ifdef CONFIG_PM
4658 static int ixgbe_resume(struct pci_dev *pdev)
4659 {
4660 struct net_device *netdev = pci_get_drvdata(pdev);
4661 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4662 u32 err;
4663
4664 pci_set_power_state(pdev, PCI_D0);
4665 pci_restore_state(pdev);
4666 /*
4667 * pci_restore_state clears dev->state_saved so call
4668 * pci_save_state to restore it.
4669 */
4670 pci_save_state(pdev);
4671
4672 err = pci_enable_device_mem(pdev);
4673 if (err) {
4674 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4675 "suspend\n");
4676 return err;
4677 }
4678 pci_set_master(pdev);
4679
4680 pci_wake_from_d3(pdev, false);
4681
4682 err = ixgbe_init_interrupt_scheme(adapter);
4683 if (err) {
4684 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4685 "device\n");
4686 return err;
4687 }
4688
4689 ixgbe_reset(adapter);
4690
4691 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4692
4693 if (netif_running(netdev)) {
4694 err = ixgbe_open(adapter->netdev);
4695 if (err)
4696 return err;
4697 }
4698
4699 netif_device_attach(netdev);
4700
4701 return 0;
4702 }
4703 #endif /* CONFIG_PM */
4704
4705 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4706 {
4707 struct net_device *netdev = pci_get_drvdata(pdev);
4708 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4709 struct ixgbe_hw *hw = &adapter->hw;
4710 u32 ctrl, fctrl;
4711 u32 wufc = adapter->wol;
4712 #ifdef CONFIG_PM
4713 int retval = 0;
4714 #endif
4715
4716 netif_device_detach(netdev);
4717
4718 if (netif_running(netdev)) {
4719 ixgbe_down(adapter);
4720 ixgbe_free_irq(adapter);
4721 ixgbe_free_all_tx_resources(adapter);
4722 ixgbe_free_all_rx_resources(adapter);
4723 }
4724 ixgbe_clear_interrupt_scheme(adapter);
4725
4726 #ifdef CONFIG_PM
4727 retval = pci_save_state(pdev);
4728 if (retval)
4729 return retval;
4730
4731 #endif
4732 if (wufc) {
4733 ixgbe_set_rx_mode(netdev);
4734
4735 /* turn on all-multi mode if wake on multicast is enabled */
4736 if (wufc & IXGBE_WUFC_MC) {
4737 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4738 fctrl |= IXGBE_FCTRL_MPE;
4739 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4740 }
4741
4742 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4743 ctrl |= IXGBE_CTRL_GIO_DIS;
4744 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4745
4746 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4747 } else {
4748 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4749 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4750 }
4751
4752 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4753 pci_wake_from_d3(pdev, true);
4754 else
4755 pci_wake_from_d3(pdev, false);
4756
4757 *enable_wake = !!wufc;
4758
4759 ixgbe_release_hw_control(adapter);
4760
4761 pci_disable_device(pdev);
4762
4763 return 0;
4764 }
4765
4766 #ifdef CONFIG_PM
4767 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4768 {
4769 int retval;
4770 bool wake;
4771
4772 retval = __ixgbe_shutdown(pdev, &wake);
4773 if (retval)
4774 return retval;
4775
4776 if (wake) {
4777 pci_prepare_to_sleep(pdev);
4778 } else {
4779 pci_wake_from_d3(pdev, false);
4780 pci_set_power_state(pdev, PCI_D3hot);
4781 }
4782
4783 return 0;
4784 }
4785 #endif /* CONFIG_PM */
4786
4787 static void ixgbe_shutdown(struct pci_dev *pdev)
4788 {
4789 bool wake;
4790
4791 __ixgbe_shutdown(pdev, &wake);
4792
4793 if (system_state == SYSTEM_POWER_OFF) {
4794 pci_wake_from_d3(pdev, wake);
4795 pci_set_power_state(pdev, PCI_D3hot);
4796 }
4797 }
4798
4799 /**
4800 * ixgbe_update_stats - Update the board statistics counters.
4801 * @adapter: board private structure
4802 **/
4803 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4804 {
4805 struct net_device *netdev = adapter->netdev;
4806 struct ixgbe_hw *hw = &adapter->hw;
4807 u64 total_mpc = 0;
4808 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4809 u64 non_eop_descs = 0, restart_queue = 0;
4810
4811 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
4812 u64 rsc_count = 0;
4813 u64 rsc_flush = 0;
4814 for (i = 0; i < 16; i++)
4815 adapter->hw_rx_no_dma_resources +=
4816 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4817 for (i = 0; i < adapter->num_rx_queues; i++) {
4818 rsc_count += adapter->rx_ring[i]->rsc_count;
4819 rsc_flush += adapter->rx_ring[i]->rsc_flush;
4820 }
4821 adapter->rsc_total_count = rsc_count;
4822 adapter->rsc_total_flush = rsc_flush;
4823 }
4824
4825 /* gather some stats to the adapter struct that are per queue */
4826 for (i = 0; i < adapter->num_tx_queues; i++)
4827 restart_queue += adapter->tx_ring[i]->restart_queue;
4828 adapter->restart_queue = restart_queue;
4829
4830 for (i = 0; i < adapter->num_rx_queues; i++)
4831 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
4832 adapter->non_eop_descs = non_eop_descs;
4833
4834 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4835 for (i = 0; i < 8; i++) {
4836 /* for packet buffers not used, the register should read 0 */
4837 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4838 missed_rx += mpc;
4839 adapter->stats.mpc[i] += mpc;
4840 total_mpc += adapter->stats.mpc[i];
4841 if (hw->mac.type == ixgbe_mac_82598EB)
4842 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4843 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4844 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4845 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4846 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4847 if (hw->mac.type == ixgbe_mac_82599EB) {
4848 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4849 IXGBE_PXONRXCNT(i));
4850 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4851 IXGBE_PXOFFRXCNT(i));
4852 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4853 } else {
4854 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4855 IXGBE_PXONRXC(i));
4856 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4857 IXGBE_PXOFFRXC(i));
4858 }
4859 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4860 IXGBE_PXONTXC(i));
4861 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4862 IXGBE_PXOFFTXC(i));
4863 }
4864 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4865 /* work around hardware counting issue */
4866 adapter->stats.gprc -= missed_rx;
4867
4868 /* 82598 hardware only has a 32 bit counter in the high register */
4869 if (hw->mac.type == ixgbe_mac_82599EB) {
4870 u64 tmp;
4871 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4872 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4873 adapter->stats.gorc += (tmp << 32);
4874 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4875 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4876 adapter->stats.gotc += (tmp << 32);
4877 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4878 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4879 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4880 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4881 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4882 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4883 #ifdef IXGBE_FCOE
4884 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4885 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4886 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4887 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4888 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4889 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4890 #endif /* IXGBE_FCOE */
4891 } else {
4892 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4893 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4894 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4895 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4896 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4897 }
4898 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4899 adapter->stats.bprc += bprc;
4900 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4901 if (hw->mac.type == ixgbe_mac_82598EB)
4902 adapter->stats.mprc -= bprc;
4903 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4904 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4905 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4906 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4907 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4908 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4909 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4910 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4911 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4912 adapter->stats.lxontxc += lxon;
4913 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4914 adapter->stats.lxofftxc += lxoff;
4915 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4916 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4917 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4918 /*
4919 * 82598 errata - tx of flow control packets is included in tx counters
4920 */
4921 xon_off_tot = lxon + lxoff;
4922 adapter->stats.gptc -= xon_off_tot;
4923 adapter->stats.mptc -= xon_off_tot;
4924 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4925 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4926 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4927 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4928 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4929 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4930 adapter->stats.ptc64 -= xon_off_tot;
4931 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4932 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4933 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4934 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4935 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4936 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4937
4938 /* Fill out the OS statistics structure */
4939 netdev->stats.multicast = adapter->stats.mprc;
4940
4941 /* Rx Errors */
4942 netdev->stats.rx_errors = adapter->stats.crcerrs +
4943 adapter->stats.rlec;
4944 netdev->stats.rx_dropped = 0;
4945 netdev->stats.rx_length_errors = adapter->stats.rlec;
4946 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4947 netdev->stats.rx_missed_errors = total_mpc;
4948 }
4949
4950 /**
4951 * ixgbe_watchdog - Timer Call-back
4952 * @data: pointer to adapter cast into an unsigned long
4953 **/
4954 static void ixgbe_watchdog(unsigned long data)
4955 {
4956 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4957 struct ixgbe_hw *hw = &adapter->hw;
4958 u64 eics = 0;
4959 int i;
4960
4961 /*
4962 * Do the watchdog outside of interrupt context due to the lovely
4963 * delays that some of the newer hardware requires
4964 */
4965
4966 if (test_bit(__IXGBE_DOWN, &adapter->state))
4967 goto watchdog_short_circuit;
4968
4969 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4970 /*
4971 * for legacy and MSI interrupts don't set any bits
4972 * that are enabled for EIAM, because this operation
4973 * would set *both* EIMS and EICS for any bit in EIAM
4974 */
4975 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4976 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4977 goto watchdog_reschedule;
4978 }
4979
4980 /* get one bit for every active tx/rx interrupt vector */
4981 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4982 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4983 if (qv->rxr_count || qv->txr_count)
4984 eics |= ((u64)1 << i);
4985 }
4986
4987 /* Cause software interrupt to ensure rx rings are cleaned */
4988 ixgbe_irq_rearm_queues(adapter, eics);
4989
4990 watchdog_reschedule:
4991 /* Reset the timer */
4992 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4993
4994 watchdog_short_circuit:
4995 schedule_work(&adapter->watchdog_task);
4996 }
4997
4998 /**
4999 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5000 * @work: pointer to work_struct containing our data
5001 **/
5002 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5003 {
5004 struct ixgbe_adapter *adapter = container_of(work,
5005 struct ixgbe_adapter,
5006 multispeed_fiber_task);
5007 struct ixgbe_hw *hw = &adapter->hw;
5008 u32 autoneg;
5009 bool negotiation;
5010
5011 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5012 autoneg = hw->phy.autoneg_advertised;
5013 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5014 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5015 hw->mac.autotry_restart = false;
5016 if (hw->mac.ops.setup_link)
5017 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5018 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5019 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5020 }
5021
5022 /**
5023 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5024 * @work: pointer to work_struct containing our data
5025 **/
5026 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5027 {
5028 struct ixgbe_adapter *adapter = container_of(work,
5029 struct ixgbe_adapter,
5030 sfp_config_module_task);
5031 struct ixgbe_hw *hw = &adapter->hw;
5032 u32 err;
5033
5034 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5035
5036 /* Time for electrical oscillations to settle down */
5037 msleep(100);
5038 err = hw->phy.ops.identify_sfp(hw);
5039
5040 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5041 dev_err(&adapter->pdev->dev, "failed to initialize because "
5042 "an unsupported SFP+ module type was detected.\n"
5043 "Reload the driver after installing a supported "
5044 "module.\n");
5045 unregister_netdev(adapter->netdev);
5046 return;
5047 }
5048 hw->mac.ops.setup_sfp(hw);
5049
5050 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5051 /* This will also work for DA Twinax connections */
5052 schedule_work(&adapter->multispeed_fiber_task);
5053 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5054 }
5055
5056 /**
5057 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5058 * @work: pointer to work_struct containing our data
5059 **/
5060 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5061 {
5062 struct ixgbe_adapter *adapter = container_of(work,
5063 struct ixgbe_adapter,
5064 fdir_reinit_task);
5065 struct ixgbe_hw *hw = &adapter->hw;
5066 int i;
5067
5068 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5069 for (i = 0; i < adapter->num_tx_queues; i++)
5070 set_bit(__IXGBE_FDIR_INIT_DONE,
5071 &(adapter->tx_ring[i]->reinit_state));
5072 } else {
5073 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
5074 "ignored adding FDIR ATR filters\n");
5075 }
5076 /* Done FDIR Re-initialization, enable transmits */
5077 netif_tx_start_all_queues(adapter->netdev);
5078 }
5079
5080 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5081
5082 /**
5083 * ixgbe_watchdog_task - worker thread to bring link up
5084 * @work: pointer to work_struct containing our data
5085 **/
5086 static void ixgbe_watchdog_task(struct work_struct *work)
5087 {
5088 struct ixgbe_adapter *adapter = container_of(work,
5089 struct ixgbe_adapter,
5090 watchdog_task);
5091 struct net_device *netdev = adapter->netdev;
5092 struct ixgbe_hw *hw = &adapter->hw;
5093 u32 link_speed;
5094 bool link_up;
5095 int i;
5096 struct ixgbe_ring *tx_ring;
5097 int some_tx_pending = 0;
5098
5099 mutex_lock(&ixgbe_watchdog_lock);
5100
5101 link_up = adapter->link_up;
5102 link_speed = adapter->link_speed;
5103
5104 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5105 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5106 if (link_up) {
5107 #ifdef CONFIG_DCB
5108 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5109 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5110 hw->mac.ops.fc_enable(hw, i);
5111 } else {
5112 hw->mac.ops.fc_enable(hw, 0);
5113 }
5114 #else
5115 hw->mac.ops.fc_enable(hw, 0);
5116 #endif
5117 }
5118
5119 if (link_up ||
5120 time_after(jiffies, (adapter->link_check_timeout +
5121 IXGBE_TRY_LINK_TIMEOUT))) {
5122 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5123 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5124 }
5125 adapter->link_up = link_up;
5126 adapter->link_speed = link_speed;
5127 }
5128
5129 if (link_up) {
5130 if (!netif_carrier_ok(netdev)) {
5131 bool flow_rx, flow_tx;
5132
5133 if (hw->mac.type == ixgbe_mac_82599EB) {
5134 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5135 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5136 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5137 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5138 } else {
5139 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5140 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5141 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5142 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5143 }
5144
5145 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5146 "Flow Control: %s\n",
5147 netdev->name,
5148 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5149 "10 Gbps" :
5150 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5151 "1 Gbps" : "unknown speed")),
5152 ((flow_rx && flow_tx) ? "RX/TX" :
5153 (flow_rx ? "RX" :
5154 (flow_tx ? "TX" : "None"))));
5155
5156 netif_carrier_on(netdev);
5157 } else {
5158 /* Force detection of hung controller */
5159 adapter->detect_tx_hung = true;
5160 }
5161 } else {
5162 adapter->link_up = false;
5163 adapter->link_speed = 0;
5164 if (netif_carrier_ok(netdev)) {
5165 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5166 netdev->name);
5167 netif_carrier_off(netdev);
5168 }
5169 }
5170
5171 if (!netif_carrier_ok(netdev)) {
5172 for (i = 0; i < adapter->num_tx_queues; i++) {
5173 tx_ring = adapter->tx_ring[i];
5174 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5175 some_tx_pending = 1;
5176 break;
5177 }
5178 }
5179
5180 if (some_tx_pending) {
5181 /* We've lost link, so the controller stops DMA,
5182 * but we've got queued Tx work that's never going
5183 * to get done, so reset controller to flush Tx.
5184 * (Do the reset outside of interrupt context).
5185 */
5186 schedule_work(&adapter->reset_task);
5187 }
5188 }
5189
5190 ixgbe_update_stats(adapter);
5191 mutex_unlock(&ixgbe_watchdog_lock);
5192 }
5193
5194 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5195 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5196 u32 tx_flags, u8 *hdr_len)
5197 {
5198 struct ixgbe_adv_tx_context_desc *context_desc;
5199 unsigned int i;
5200 int err;
5201 struct ixgbe_tx_buffer *tx_buffer_info;
5202 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5203 u32 mss_l4len_idx, l4len;
5204
5205 if (skb_is_gso(skb)) {
5206 if (skb_header_cloned(skb)) {
5207 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5208 if (err)
5209 return err;
5210 }
5211 l4len = tcp_hdrlen(skb);
5212 *hdr_len += l4len;
5213
5214 if (skb->protocol == htons(ETH_P_IP)) {
5215 struct iphdr *iph = ip_hdr(skb);
5216 iph->tot_len = 0;
5217 iph->check = 0;
5218 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5219 iph->daddr, 0,
5220 IPPROTO_TCP,
5221 0);
5222 } else if (skb_is_gso_v6(skb)) {
5223 ipv6_hdr(skb)->payload_len = 0;
5224 tcp_hdr(skb)->check =
5225 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5226 &ipv6_hdr(skb)->daddr,
5227 0, IPPROTO_TCP, 0);
5228 }
5229
5230 i = tx_ring->next_to_use;
5231
5232 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5233 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5234
5235 /* VLAN MACLEN IPLEN */
5236 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5237 vlan_macip_lens |=
5238 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5239 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5240 IXGBE_ADVTXD_MACLEN_SHIFT);
5241 *hdr_len += skb_network_offset(skb);
5242 vlan_macip_lens |=
5243 (skb_transport_header(skb) - skb_network_header(skb));
5244 *hdr_len +=
5245 (skb_transport_header(skb) - skb_network_header(skb));
5246 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5247 context_desc->seqnum_seed = 0;
5248
5249 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5250 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5251 IXGBE_ADVTXD_DTYP_CTXT);
5252
5253 if (skb->protocol == htons(ETH_P_IP))
5254 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5255 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5256 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5257
5258 /* MSS L4LEN IDX */
5259 mss_l4len_idx =
5260 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5261 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5262 /* use index 1 for TSO */
5263 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5264 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5265
5266 tx_buffer_info->time_stamp = jiffies;
5267 tx_buffer_info->next_to_watch = i;
5268
5269 i++;
5270 if (i == tx_ring->count)
5271 i = 0;
5272 tx_ring->next_to_use = i;
5273
5274 return true;
5275 }
5276 return false;
5277 }
5278
5279 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5280 struct ixgbe_ring *tx_ring,
5281 struct sk_buff *skb, u32 tx_flags)
5282 {
5283 struct ixgbe_adv_tx_context_desc *context_desc;
5284 unsigned int i;
5285 struct ixgbe_tx_buffer *tx_buffer_info;
5286 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5287
5288 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5289 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5290 i = tx_ring->next_to_use;
5291 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5292 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5293
5294 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5295 vlan_macip_lens |=
5296 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5297 vlan_macip_lens |= (skb_network_offset(skb) <<
5298 IXGBE_ADVTXD_MACLEN_SHIFT);
5299 if (skb->ip_summed == CHECKSUM_PARTIAL)
5300 vlan_macip_lens |= (skb_transport_header(skb) -
5301 skb_network_header(skb));
5302
5303 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5304 context_desc->seqnum_seed = 0;
5305
5306 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5307 IXGBE_ADVTXD_DTYP_CTXT);
5308
5309 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5310 __be16 protocol;
5311
5312 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5313 const struct vlan_ethhdr *vhdr =
5314 (const struct vlan_ethhdr *)skb->data;
5315
5316 protocol = vhdr->h_vlan_encapsulated_proto;
5317 } else {
5318 protocol = skb->protocol;
5319 }
5320
5321 switch (protocol) {
5322 case cpu_to_be16(ETH_P_IP):
5323 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5324 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5325 type_tucmd_mlhl |=
5326 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5327 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5328 type_tucmd_mlhl |=
5329 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5330 break;
5331 case cpu_to_be16(ETH_P_IPV6):
5332 /* XXX what about other V6 headers?? */
5333 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5334 type_tucmd_mlhl |=
5335 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5336 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5337 type_tucmd_mlhl |=
5338 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5339 break;
5340 default:
5341 if (unlikely(net_ratelimit())) {
5342 DPRINTK(PROBE, WARNING,
5343 "partial checksum but proto=%x!\n",
5344 skb->protocol);
5345 }
5346 break;
5347 }
5348 }
5349
5350 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5351 /* use index zero for tx checksum offload */
5352 context_desc->mss_l4len_idx = 0;
5353
5354 tx_buffer_info->time_stamp = jiffies;
5355 tx_buffer_info->next_to_watch = i;
5356
5357 i++;
5358 if (i == tx_ring->count)
5359 i = 0;
5360 tx_ring->next_to_use = i;
5361
5362 return true;
5363 }
5364
5365 return false;
5366 }
5367
5368 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5369 struct ixgbe_ring *tx_ring,
5370 struct sk_buff *skb, u32 tx_flags,
5371 unsigned int first)
5372 {
5373 struct pci_dev *pdev = adapter->pdev;
5374 struct ixgbe_tx_buffer *tx_buffer_info;
5375 unsigned int len;
5376 unsigned int total = skb->len;
5377 unsigned int offset = 0, size, count = 0, i;
5378 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5379 unsigned int f;
5380
5381 i = tx_ring->next_to_use;
5382
5383 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5384 /* excluding fcoe_crc_eof for FCoE */
5385 total -= sizeof(struct fcoe_crc_eof);
5386
5387 len = min(skb_headlen(skb), total);
5388 while (len) {
5389 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5390 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5391
5392 tx_buffer_info->length = size;
5393 tx_buffer_info->mapped_as_page = false;
5394 tx_buffer_info->dma = pci_map_single(pdev,
5395 skb->data + offset,
5396 size, PCI_DMA_TODEVICE);
5397 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5398 goto dma_error;
5399 tx_buffer_info->time_stamp = jiffies;
5400 tx_buffer_info->next_to_watch = i;
5401
5402 len -= size;
5403 total -= size;
5404 offset += size;
5405 count++;
5406
5407 if (len) {
5408 i++;
5409 if (i == tx_ring->count)
5410 i = 0;
5411 }
5412 }
5413
5414 for (f = 0; f < nr_frags; f++) {
5415 struct skb_frag_struct *frag;
5416
5417 frag = &skb_shinfo(skb)->frags[f];
5418 len = min((unsigned int)frag->size, total);
5419 offset = frag->page_offset;
5420
5421 while (len) {
5422 i++;
5423 if (i == tx_ring->count)
5424 i = 0;
5425
5426 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5427 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5428
5429 tx_buffer_info->length = size;
5430 tx_buffer_info->dma = pci_map_page(adapter->pdev,
5431 frag->page,
5432 offset, size,
5433 PCI_DMA_TODEVICE);
5434 tx_buffer_info->mapped_as_page = true;
5435 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5436 goto dma_error;
5437 tx_buffer_info->time_stamp = jiffies;
5438 tx_buffer_info->next_to_watch = i;
5439
5440 len -= size;
5441 total -= size;
5442 offset += size;
5443 count++;
5444 }
5445 if (total == 0)
5446 break;
5447 }
5448
5449 tx_ring->tx_buffer_info[i].skb = skb;
5450 tx_ring->tx_buffer_info[first].next_to_watch = i;
5451
5452 return count;
5453
5454 dma_error:
5455 dev_err(&pdev->dev, "TX DMA map failed\n");
5456
5457 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5458 tx_buffer_info->dma = 0;
5459 tx_buffer_info->time_stamp = 0;
5460 tx_buffer_info->next_to_watch = 0;
5461 if (count)
5462 count--;
5463
5464 /* clear timestamp and dma mappings for remaining portion of packet */
5465 while (count--) {
5466 if (i==0)
5467 i += tx_ring->count;
5468 i--;
5469 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5470 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5471 }
5472
5473 return 0;
5474 }
5475
5476 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5477 struct ixgbe_ring *tx_ring,
5478 int tx_flags, int count, u32 paylen, u8 hdr_len)
5479 {
5480 union ixgbe_adv_tx_desc *tx_desc = NULL;
5481 struct ixgbe_tx_buffer *tx_buffer_info;
5482 u32 olinfo_status = 0, cmd_type_len = 0;
5483 unsigned int i;
5484 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5485
5486 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5487
5488 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5489
5490 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5491 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5492
5493 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5494 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5495
5496 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5497 IXGBE_ADVTXD_POPTS_SHIFT;
5498
5499 /* use index 1 context for tso */
5500 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5501 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5502 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5503 IXGBE_ADVTXD_POPTS_SHIFT;
5504
5505 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5506 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5507 IXGBE_ADVTXD_POPTS_SHIFT;
5508
5509 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5510 olinfo_status |= IXGBE_ADVTXD_CC;
5511 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5512 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5513 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5514 }
5515
5516 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5517
5518 i = tx_ring->next_to_use;
5519 while (count--) {
5520 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5521 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5522 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5523 tx_desc->read.cmd_type_len =
5524 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5525 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5526 i++;
5527 if (i == tx_ring->count)
5528 i = 0;
5529 }
5530
5531 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5532
5533 /*
5534 * Force memory writes to complete before letting h/w
5535 * know there are new descriptors to fetch. (Only
5536 * applicable for weak-ordered memory model archs,
5537 * such as IA-64).
5538 */
5539 wmb();
5540
5541 tx_ring->next_to_use = i;
5542 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5543 }
5544
5545 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5546 int queue, u32 tx_flags)
5547 {
5548 /* Right now, we support IPv4 only */
5549 struct ixgbe_atr_input atr_input;
5550 struct tcphdr *th;
5551 struct iphdr *iph = ip_hdr(skb);
5552 struct ethhdr *eth = (struct ethhdr *)skb->data;
5553 u16 vlan_id, src_port, dst_port, flex_bytes;
5554 u32 src_ipv4_addr, dst_ipv4_addr;
5555 u8 l4type = 0;
5556
5557 /* check if we're UDP or TCP */
5558 if (iph->protocol == IPPROTO_TCP) {
5559 th = tcp_hdr(skb);
5560 src_port = th->source;
5561 dst_port = th->dest;
5562 l4type |= IXGBE_ATR_L4TYPE_TCP;
5563 /* l4type IPv4 type is 0, no need to assign */
5564 } else {
5565 /* Unsupported L4 header, just bail here */
5566 return;
5567 }
5568
5569 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5570
5571 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5572 IXGBE_TX_FLAGS_VLAN_SHIFT;
5573 src_ipv4_addr = iph->saddr;
5574 dst_ipv4_addr = iph->daddr;
5575 flex_bytes = eth->h_proto;
5576
5577 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5578 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5579 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5580 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5581 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5582 /* src and dst are inverted, think how the receiver sees them */
5583 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5584 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5585
5586 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5587 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5588 }
5589
5590 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5591 struct ixgbe_ring *tx_ring, int size)
5592 {
5593 netif_stop_subqueue(netdev, tx_ring->queue_index);
5594 /* Herbert's original patch had:
5595 * smp_mb__after_netif_stop_queue();
5596 * but since that doesn't exist yet, just open code it. */
5597 smp_mb();
5598
5599 /* We need to check again in a case another CPU has just
5600 * made room available. */
5601 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5602 return -EBUSY;
5603
5604 /* A reprieve! - use start_queue because it doesn't call schedule */
5605 netif_start_subqueue(netdev, tx_ring->queue_index);
5606 ++tx_ring->restart_queue;
5607 return 0;
5608 }
5609
5610 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5611 struct ixgbe_ring *tx_ring, int size)
5612 {
5613 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5614 return 0;
5615 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5616 }
5617
5618 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5619 {
5620 struct ixgbe_adapter *adapter = netdev_priv(dev);
5621 int txq = smp_processor_id();
5622
5623 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5624 while (unlikely(txq >= dev->real_num_tx_queues))
5625 txq -= dev->real_num_tx_queues;
5626 return txq;
5627 }
5628
5629 #ifdef IXGBE_FCOE
5630 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5631 ((skb->protocol == htons(ETH_P_FCOE)) ||
5632 (skb->protocol == htons(ETH_P_FIP)))) {
5633 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5634 txq += adapter->ring_feature[RING_F_FCOE].mask;
5635 return txq;
5636 }
5637 #endif
5638 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5639 if (skb->priority == TC_PRIO_CONTROL)
5640 txq = adapter->ring_feature[RING_F_DCB].indices-1;
5641 else
5642 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
5643 >> 13;
5644 return txq;
5645 }
5646
5647 return skb_tx_hash(dev, skb);
5648 }
5649
5650 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5651 struct net_device *netdev)
5652 {
5653 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5654 struct ixgbe_ring *tx_ring;
5655 struct netdev_queue *txq;
5656 unsigned int first;
5657 unsigned int tx_flags = 0;
5658 u8 hdr_len = 0;
5659 int tso;
5660 int count = 0;
5661 unsigned int f;
5662
5663 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5664 tx_flags |= vlan_tx_tag_get(skb);
5665 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5666 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5667 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5668 }
5669 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5670 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5671 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5672 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5673 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5674 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5675 }
5676
5677 tx_ring = adapter->tx_ring[skb->queue_mapping];
5678
5679 #ifdef IXGBE_FCOE
5680 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
5681 #ifdef CONFIG_IXGBE_DCB
5682 /* for FCoE with DCB, we force the priority to what
5683 * was specified by the switch */
5684 if ((skb->protocol == htons(ETH_P_FCOE)) ||
5685 (skb->protocol == htons(ETH_P_FIP))) {
5686 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5687 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5688 tx_flags |= ((adapter->fcoe.up << 13)
5689 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5690 }
5691 #endif
5692 /* flag for FCoE offloads */
5693 if (skb->protocol == htons(ETH_P_FCOE))
5694 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5695 }
5696 #endif
5697
5698 /* four things can cause us to need a context descriptor */
5699 if (skb_is_gso(skb) ||
5700 (skb->ip_summed == CHECKSUM_PARTIAL) ||
5701 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5702 (tx_flags & IXGBE_TX_FLAGS_FCOE))
5703 count++;
5704
5705 count += TXD_USE_COUNT(skb_headlen(skb));
5706 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5707 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5708
5709 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5710 adapter->tx_busy++;
5711 return NETDEV_TX_BUSY;
5712 }
5713
5714 first = tx_ring->next_to_use;
5715 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5716 #ifdef IXGBE_FCOE
5717 /* setup tx offload for FCoE */
5718 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5719 if (tso < 0) {
5720 dev_kfree_skb_any(skb);
5721 return NETDEV_TX_OK;
5722 }
5723 if (tso)
5724 tx_flags |= IXGBE_TX_FLAGS_FSO;
5725 #endif /* IXGBE_FCOE */
5726 } else {
5727 if (skb->protocol == htons(ETH_P_IP))
5728 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5729 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5730 if (tso < 0) {
5731 dev_kfree_skb_any(skb);
5732 return NETDEV_TX_OK;
5733 }
5734
5735 if (tso)
5736 tx_flags |= IXGBE_TX_FLAGS_TSO;
5737 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5738 (skb->ip_summed == CHECKSUM_PARTIAL))
5739 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5740 }
5741
5742 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5743 if (count) {
5744 /* add the ATR filter if ATR is on */
5745 if (tx_ring->atr_sample_rate) {
5746 ++tx_ring->atr_count;
5747 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5748 test_bit(__IXGBE_FDIR_INIT_DONE,
5749 &tx_ring->reinit_state)) {
5750 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5751 tx_flags);
5752 tx_ring->atr_count = 0;
5753 }
5754 }
5755 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
5756 txq->tx_bytes += skb->len;
5757 txq->tx_packets++;
5758 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5759 hdr_len);
5760 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5761
5762 } else {
5763 dev_kfree_skb_any(skb);
5764 tx_ring->tx_buffer_info[first].time_stamp = 0;
5765 tx_ring->next_to_use = first;
5766 }
5767
5768 return NETDEV_TX_OK;
5769 }
5770
5771 /**
5772 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5773 * @netdev: network interface device structure
5774 * @p: pointer to an address structure
5775 *
5776 * Returns 0 on success, negative on failure
5777 **/
5778 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5779 {
5780 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5781 struct ixgbe_hw *hw = &adapter->hw;
5782 struct sockaddr *addr = p;
5783
5784 if (!is_valid_ether_addr(addr->sa_data))
5785 return -EADDRNOTAVAIL;
5786
5787 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5788 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5789
5790 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
5791 IXGBE_RAH_AV);
5792
5793 return 0;
5794 }
5795
5796 static int
5797 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5798 {
5799 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5800 struct ixgbe_hw *hw = &adapter->hw;
5801 u16 value;
5802 int rc;
5803
5804 if (prtad != hw->phy.mdio.prtad)
5805 return -EINVAL;
5806 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5807 if (!rc)
5808 rc = value;
5809 return rc;
5810 }
5811
5812 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5813 u16 addr, u16 value)
5814 {
5815 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5816 struct ixgbe_hw *hw = &adapter->hw;
5817
5818 if (prtad != hw->phy.mdio.prtad)
5819 return -EINVAL;
5820 return hw->phy.ops.write_reg(hw, addr, devad, value);
5821 }
5822
5823 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5824 {
5825 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5826
5827 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5828 }
5829
5830 /**
5831 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5832 * netdev->dev_addrs
5833 * @netdev: network interface device structure
5834 *
5835 * Returns non-zero on failure
5836 **/
5837 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5838 {
5839 int err = 0;
5840 struct ixgbe_adapter *adapter = netdev_priv(dev);
5841 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5842
5843 if (is_valid_ether_addr(mac->san_addr)) {
5844 rtnl_lock();
5845 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5846 rtnl_unlock();
5847 }
5848 return err;
5849 }
5850
5851 /**
5852 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5853 * netdev->dev_addrs
5854 * @netdev: network interface device structure
5855 *
5856 * Returns non-zero on failure
5857 **/
5858 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5859 {
5860 int err = 0;
5861 struct ixgbe_adapter *adapter = netdev_priv(dev);
5862 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5863
5864 if (is_valid_ether_addr(mac->san_addr)) {
5865 rtnl_lock();
5866 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5867 rtnl_unlock();
5868 }
5869 return err;
5870 }
5871
5872 #ifdef CONFIG_NET_POLL_CONTROLLER
5873 /*
5874 * Polling 'interrupt' - used by things like netconsole to send skbs
5875 * without having to re-enable interrupts. It's not called while
5876 * the interrupt routine is executing.
5877 */
5878 static void ixgbe_netpoll(struct net_device *netdev)
5879 {
5880 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5881 int i;
5882
5883 /* if interface is down do nothing */
5884 if (test_bit(__IXGBE_DOWN, &adapter->state))
5885 return;
5886
5887 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5888 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5889 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5890 for (i = 0; i < num_q_vectors; i++) {
5891 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5892 ixgbe_msix_clean_many(0, q_vector);
5893 }
5894 } else {
5895 ixgbe_intr(adapter->pdev->irq, netdev);
5896 }
5897 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5898 }
5899 #endif
5900
5901 static const struct net_device_ops ixgbe_netdev_ops = {
5902 .ndo_open = ixgbe_open,
5903 .ndo_stop = ixgbe_close,
5904 .ndo_start_xmit = ixgbe_xmit_frame,
5905 .ndo_select_queue = ixgbe_select_queue,
5906 .ndo_set_rx_mode = ixgbe_set_rx_mode,
5907 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5908 .ndo_validate_addr = eth_validate_addr,
5909 .ndo_set_mac_address = ixgbe_set_mac,
5910 .ndo_change_mtu = ixgbe_change_mtu,
5911 .ndo_tx_timeout = ixgbe_tx_timeout,
5912 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5913 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5914 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
5915 .ndo_do_ioctl = ixgbe_ioctl,
5916 #ifdef CONFIG_NET_POLL_CONTROLLER
5917 .ndo_poll_controller = ixgbe_netpoll,
5918 #endif
5919 #ifdef IXGBE_FCOE
5920 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5921 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5922 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5923 .ndo_fcoe_disable = ixgbe_fcoe_disable,
5924 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
5925 #endif /* IXGBE_FCOE */
5926 };
5927
5928 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
5929 const struct ixgbe_info *ii)
5930 {
5931 #ifdef CONFIG_PCI_IOV
5932 struct ixgbe_hw *hw = &adapter->hw;
5933 int err;
5934
5935 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
5936 return;
5937
5938 /* The 82599 supports up to 64 VFs per physical function
5939 * but this implementation limits allocation to 63 so that
5940 * basic networking resources are still available to the
5941 * physical function
5942 */
5943 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
5944 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
5945 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
5946 if (err) {
5947 DPRINTK(PROBE, ERR,
5948 "Failed to enable PCI sriov: %d\n", err);
5949 goto err_novfs;
5950 }
5951 /* If call to enable VFs succeeded then allocate memory
5952 * for per VF control structures.
5953 */
5954 adapter->vfinfo =
5955 kcalloc(adapter->num_vfs,
5956 sizeof(struct vf_data_storage), GFP_KERNEL);
5957 if (adapter->vfinfo) {
5958 /* Now that we're sure SR-IOV is enabled
5959 * and memory allocated set up the mailbox parameters
5960 */
5961 ixgbe_init_mbx_params_pf(hw);
5962 memcpy(&hw->mbx.ops, ii->mbx_ops,
5963 sizeof(hw->mbx.ops));
5964
5965 /* Disable RSC when in SR-IOV mode */
5966 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
5967 IXGBE_FLAG2_RSC_ENABLED);
5968 return;
5969 }
5970
5971 /* Oh oh */
5972 DPRINTK(PROBE, ERR,
5973 "Unable to allocate memory for VF "
5974 "Data Storage - SRIOV disabled\n");
5975 pci_disable_sriov(adapter->pdev);
5976
5977 err_novfs:
5978 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
5979 adapter->num_vfs = 0;
5980 #endif /* CONFIG_PCI_IOV */
5981 }
5982
5983 /**
5984 * ixgbe_probe - Device Initialization Routine
5985 * @pdev: PCI device information struct
5986 * @ent: entry in ixgbe_pci_tbl
5987 *
5988 * Returns 0 on success, negative on failure
5989 *
5990 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5991 * The OS initialization, configuring of the adapter private structure,
5992 * and a hardware reset occur.
5993 **/
5994 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5995 const struct pci_device_id *ent)
5996 {
5997 struct net_device *netdev;
5998 struct ixgbe_adapter *adapter = NULL;
5999 struct ixgbe_hw *hw;
6000 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6001 static int cards_found;
6002 int i, err, pci_using_dac;
6003 unsigned int indices = num_possible_cpus();
6004 #ifdef IXGBE_FCOE
6005 u16 device_caps;
6006 #endif
6007 u32 part_num, eec;
6008
6009 err = pci_enable_device_mem(pdev);
6010 if (err)
6011 return err;
6012
6013 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
6014 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
6015 pci_using_dac = 1;
6016 } else {
6017 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6018 if (err) {
6019 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6020 if (err) {
6021 dev_err(&pdev->dev, "No usable DMA "
6022 "configuration, aborting\n");
6023 goto err_dma;
6024 }
6025 }
6026 pci_using_dac = 0;
6027 }
6028
6029 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6030 IORESOURCE_MEM), ixgbe_driver_name);
6031 if (err) {
6032 dev_err(&pdev->dev,
6033 "pci_request_selected_regions failed 0x%x\n", err);
6034 goto err_pci_reg;
6035 }
6036
6037 pci_enable_pcie_error_reporting(pdev);
6038
6039 pci_set_master(pdev);
6040 pci_save_state(pdev);
6041
6042 if (ii->mac == ixgbe_mac_82598EB)
6043 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6044 else
6045 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6046
6047 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6048 #ifdef IXGBE_FCOE
6049 indices += min_t(unsigned int, num_possible_cpus(),
6050 IXGBE_MAX_FCOE_INDICES);
6051 #endif
6052 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6053 if (!netdev) {
6054 err = -ENOMEM;
6055 goto err_alloc_etherdev;
6056 }
6057
6058 SET_NETDEV_DEV(netdev, &pdev->dev);
6059
6060 pci_set_drvdata(pdev, netdev);
6061 adapter = netdev_priv(netdev);
6062
6063 adapter->netdev = netdev;
6064 adapter->pdev = pdev;
6065 hw = &adapter->hw;
6066 hw->back = adapter;
6067 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6068
6069 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6070 pci_resource_len(pdev, 0));
6071 if (!hw->hw_addr) {
6072 err = -EIO;
6073 goto err_ioremap;
6074 }
6075
6076 for (i = 1; i <= 5; i++) {
6077 if (pci_resource_len(pdev, i) == 0)
6078 continue;
6079 }
6080
6081 netdev->netdev_ops = &ixgbe_netdev_ops;
6082 ixgbe_set_ethtool_ops(netdev);
6083 netdev->watchdog_timeo = 5 * HZ;
6084 strcpy(netdev->name, pci_name(pdev));
6085
6086 adapter->bd_number = cards_found;
6087
6088 /* Setup hw api */
6089 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6090 hw->mac.type = ii->mac;
6091
6092 /* EEPROM */
6093 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6094 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6095 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6096 if (!(eec & (1 << 8)))
6097 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6098
6099 /* PHY */
6100 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6101 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6102 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6103 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6104 hw->phy.mdio.mmds = 0;
6105 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6106 hw->phy.mdio.dev = netdev;
6107 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6108 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6109
6110 /* set up this timer and work struct before calling get_invariants
6111 * which might start the timer
6112 */
6113 init_timer(&adapter->sfp_timer);
6114 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6115 adapter->sfp_timer.data = (unsigned long) adapter;
6116
6117 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6118
6119 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6120 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6121
6122 /* a new SFP+ module arrival, called from GPI SDP2 context */
6123 INIT_WORK(&adapter->sfp_config_module_task,
6124 ixgbe_sfp_config_module_task);
6125
6126 ii->get_invariants(hw);
6127
6128 /* setup the private structure */
6129 err = ixgbe_sw_init(adapter);
6130 if (err)
6131 goto err_sw_init;
6132
6133 /* Make it possible the adapter to be woken up via WOL */
6134 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6135 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6136
6137 /*
6138 * If there is a fan on this device and it has failed log the
6139 * failure.
6140 */
6141 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6142 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6143 if (esdp & IXGBE_ESDP_SDP1)
6144 DPRINTK(PROBE, CRIT,
6145 "Fan has stopped, replace the adapter\n");
6146 }
6147
6148 /* reset_hw fills in the perm_addr as well */
6149 err = hw->mac.ops.reset_hw(hw);
6150 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6151 hw->mac.type == ixgbe_mac_82598EB) {
6152 /*
6153 * Start a kernel thread to watch for a module to arrive.
6154 * Only do this for 82598, since 82599 will generate
6155 * interrupts on module arrival.
6156 */
6157 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6158 mod_timer(&adapter->sfp_timer,
6159 round_jiffies(jiffies + (2 * HZ)));
6160 err = 0;
6161 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6162 dev_err(&adapter->pdev->dev, "failed to initialize because "
6163 "an unsupported SFP+ module type was detected.\n"
6164 "Reload the driver after installing a supported "
6165 "module.\n");
6166 goto err_sw_init;
6167 } else if (err) {
6168 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
6169 goto err_sw_init;
6170 }
6171
6172 ixgbe_probe_vf(adapter, ii);
6173
6174 netdev->features = NETIF_F_SG |
6175 NETIF_F_IP_CSUM |
6176 NETIF_F_HW_VLAN_TX |
6177 NETIF_F_HW_VLAN_RX |
6178 NETIF_F_HW_VLAN_FILTER;
6179
6180 netdev->features |= NETIF_F_IPV6_CSUM;
6181 netdev->features |= NETIF_F_TSO;
6182 netdev->features |= NETIF_F_TSO6;
6183 netdev->features |= NETIF_F_GRO;
6184
6185 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6186 netdev->features |= NETIF_F_SCTP_CSUM;
6187
6188 netdev->vlan_features |= NETIF_F_TSO;
6189 netdev->vlan_features |= NETIF_F_TSO6;
6190 netdev->vlan_features |= NETIF_F_IP_CSUM;
6191 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6192 netdev->vlan_features |= NETIF_F_SG;
6193
6194 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6195 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6196 IXGBE_FLAG_DCB_ENABLED);
6197 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6198 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6199
6200 #ifdef CONFIG_IXGBE_DCB
6201 netdev->dcbnl_ops = &dcbnl_ops;
6202 #endif
6203
6204 #ifdef IXGBE_FCOE
6205 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6206 if (hw->mac.ops.get_device_caps) {
6207 hw->mac.ops.get_device_caps(hw, &device_caps);
6208 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6209 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6210 }
6211 }
6212 #endif /* IXGBE_FCOE */
6213 if (pci_using_dac)
6214 netdev->features |= NETIF_F_HIGHDMA;
6215
6216 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6217 netdev->features |= NETIF_F_LRO;
6218
6219 /* make sure the EEPROM is good */
6220 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6221 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
6222 err = -EIO;
6223 goto err_eeprom;
6224 }
6225
6226 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6227 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6228
6229 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6230 dev_err(&pdev->dev, "invalid MAC address\n");
6231 err = -EIO;
6232 goto err_eeprom;
6233 }
6234
6235 init_timer(&adapter->watchdog_timer);
6236 adapter->watchdog_timer.function = &ixgbe_watchdog;
6237 adapter->watchdog_timer.data = (unsigned long)adapter;
6238
6239 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6240 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6241
6242 err = ixgbe_init_interrupt_scheme(adapter);
6243 if (err)
6244 goto err_sw_init;
6245
6246 switch (pdev->device) {
6247 case IXGBE_DEV_ID_82599_KX4:
6248 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6249 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6250 break;
6251 default:
6252 adapter->wol = 0;
6253 break;
6254 }
6255 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6256
6257 /* pick up the PCI bus settings for reporting later */
6258 hw->mac.ops.get_bus_info(hw);
6259
6260 /* print bus type/speed/width info */
6261 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
6262 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6263 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6264 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6265 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6266 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
6267 "Unknown"),
6268 netdev->dev_addr);
6269 ixgbe_read_pba_num_generic(hw, &part_num);
6270 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6271 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6272 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6273 (part_num >> 8), (part_num & 0xff));
6274 else
6275 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6276 hw->mac.type, hw->phy.type,
6277 (part_num >> 8), (part_num & 0xff));
6278
6279 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6280 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
6281 "this card is not sufficient for optimal "
6282 "performance.\n");
6283 dev_warn(&pdev->dev, "For optimal performance a x8 "
6284 "PCI-Express slot is required.\n");
6285 }
6286
6287 /* save off EEPROM version number */
6288 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6289
6290 /* reset the hardware with the new settings */
6291 err = hw->mac.ops.start_hw(hw);
6292
6293 if (err == IXGBE_ERR_EEPROM_VERSION) {
6294 /* We are running on a pre-production device, log a warning */
6295 dev_warn(&pdev->dev, "This device is a pre-production "
6296 "adapter/LOM. Please be aware there may be issues "
6297 "associated with your hardware. If you are "
6298 "experiencing problems please contact your Intel or "
6299 "hardware representative who provided you with this "
6300 "hardware.\n");
6301 }
6302 strcpy(netdev->name, "eth%d");
6303 err = register_netdev(netdev);
6304 if (err)
6305 goto err_register;
6306
6307 /* carrier off reporting is important to ethtool even BEFORE open */
6308 netif_carrier_off(netdev);
6309
6310 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6311 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6312 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6313
6314 #ifdef CONFIG_IXGBE_DCA
6315 if (dca_add_requester(&pdev->dev) == 0) {
6316 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6317 ixgbe_setup_dca(adapter);
6318 }
6319 #endif
6320 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6321 DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n",
6322 adapter->num_vfs);
6323 for (i = 0; i < adapter->num_vfs; i++)
6324 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6325 }
6326
6327 /* add san mac addr to netdev */
6328 ixgbe_add_sanmac_netdev(netdev);
6329
6330 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
6331 cards_found++;
6332 return 0;
6333
6334 err_register:
6335 ixgbe_release_hw_control(adapter);
6336 ixgbe_clear_interrupt_scheme(adapter);
6337 err_sw_init:
6338 err_eeprom:
6339 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6340 ixgbe_disable_sriov(adapter);
6341 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6342 del_timer_sync(&adapter->sfp_timer);
6343 cancel_work_sync(&adapter->sfp_task);
6344 cancel_work_sync(&adapter->multispeed_fiber_task);
6345 cancel_work_sync(&adapter->sfp_config_module_task);
6346 iounmap(hw->hw_addr);
6347 err_ioremap:
6348 free_netdev(netdev);
6349 err_alloc_etherdev:
6350 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6351 IORESOURCE_MEM));
6352 err_pci_reg:
6353 err_dma:
6354 pci_disable_device(pdev);
6355 return err;
6356 }
6357
6358 /**
6359 * ixgbe_remove - Device Removal Routine
6360 * @pdev: PCI device information struct
6361 *
6362 * ixgbe_remove is called by the PCI subsystem to alert the driver
6363 * that it should release a PCI device. The could be caused by a
6364 * Hot-Plug event, or because the driver is going to be removed from
6365 * memory.
6366 **/
6367 static void __devexit ixgbe_remove(struct pci_dev *pdev)
6368 {
6369 struct net_device *netdev = pci_get_drvdata(pdev);
6370 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6371
6372 set_bit(__IXGBE_DOWN, &adapter->state);
6373 /* clear the module not found bit to make sure the worker won't
6374 * reschedule
6375 */
6376 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6377 del_timer_sync(&adapter->watchdog_timer);
6378
6379 del_timer_sync(&adapter->sfp_timer);
6380 cancel_work_sync(&adapter->watchdog_task);
6381 cancel_work_sync(&adapter->sfp_task);
6382 if (adapter->hw.phy.multispeed_fiber) {
6383 struct ixgbe_hw *hw = &adapter->hw;
6384 /*
6385 * Restart clause 37 autoneg, disable and re-enable
6386 * the tx laser, to clear & alert the link partner
6387 * that it needs to restart autotry
6388 */
6389 hw->mac.autotry_restart = true;
6390 hw->mac.ops.flap_tx_laser(hw);
6391 }
6392 cancel_work_sync(&adapter->multispeed_fiber_task);
6393 cancel_work_sync(&adapter->sfp_config_module_task);
6394 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6395 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6396 cancel_work_sync(&adapter->fdir_reinit_task);
6397 flush_scheduled_work();
6398
6399 #ifdef CONFIG_IXGBE_DCA
6400 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6401 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6402 dca_remove_requester(&pdev->dev);
6403 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6404 }
6405
6406 #endif
6407 #ifdef IXGBE_FCOE
6408 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6409 ixgbe_cleanup_fcoe(adapter);
6410
6411 #endif /* IXGBE_FCOE */
6412
6413 /* remove the added san mac */
6414 ixgbe_del_sanmac_netdev(netdev);
6415
6416 if (netdev->reg_state == NETREG_REGISTERED)
6417 unregister_netdev(netdev);
6418
6419 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6420 ixgbe_disable_sriov(adapter);
6421
6422 ixgbe_clear_interrupt_scheme(adapter);
6423
6424 ixgbe_release_hw_control(adapter);
6425
6426 iounmap(adapter->hw.hw_addr);
6427 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6428 IORESOURCE_MEM));
6429
6430 DPRINTK(PROBE, INFO, "complete\n");
6431
6432 free_netdev(netdev);
6433
6434 pci_disable_pcie_error_reporting(pdev);
6435
6436 pci_disable_device(pdev);
6437 }
6438
6439 /**
6440 * ixgbe_io_error_detected - called when PCI error is detected
6441 * @pdev: Pointer to PCI device
6442 * @state: The current pci connection state
6443 *
6444 * This function is called after a PCI bus error affecting
6445 * this device has been detected.
6446 */
6447 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
6448 pci_channel_state_t state)
6449 {
6450 struct net_device *netdev = pci_get_drvdata(pdev);
6451 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6452
6453 netif_device_detach(netdev);
6454
6455 if (state == pci_channel_io_perm_failure)
6456 return PCI_ERS_RESULT_DISCONNECT;
6457
6458 if (netif_running(netdev))
6459 ixgbe_down(adapter);
6460 pci_disable_device(pdev);
6461
6462 /* Request a slot reset. */
6463 return PCI_ERS_RESULT_NEED_RESET;
6464 }
6465
6466 /**
6467 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6468 * @pdev: Pointer to PCI device
6469 *
6470 * Restart the card from scratch, as if from a cold-boot.
6471 */
6472 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6473 {
6474 struct net_device *netdev = pci_get_drvdata(pdev);
6475 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6476 pci_ers_result_t result;
6477 int err;
6478
6479 if (pci_enable_device_mem(pdev)) {
6480 DPRINTK(PROBE, ERR,
6481 "Cannot re-enable PCI device after reset.\n");
6482 result = PCI_ERS_RESULT_DISCONNECT;
6483 } else {
6484 pci_set_master(pdev);
6485 pci_restore_state(pdev);
6486 pci_save_state(pdev);
6487
6488 pci_wake_from_d3(pdev, false);
6489
6490 ixgbe_reset(adapter);
6491 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6492 result = PCI_ERS_RESULT_RECOVERED;
6493 }
6494
6495 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6496 if (err) {
6497 dev_err(&pdev->dev,
6498 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6499 /* non-fatal, continue */
6500 }
6501
6502 return result;
6503 }
6504
6505 /**
6506 * ixgbe_io_resume - called when traffic can start flowing again.
6507 * @pdev: Pointer to PCI device
6508 *
6509 * This callback is called when the error recovery driver tells us that
6510 * its OK to resume normal operation.
6511 */
6512 static void ixgbe_io_resume(struct pci_dev *pdev)
6513 {
6514 struct net_device *netdev = pci_get_drvdata(pdev);
6515 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6516
6517 if (netif_running(netdev)) {
6518 if (ixgbe_up(adapter)) {
6519 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6520 return;
6521 }
6522 }
6523
6524 netif_device_attach(netdev);
6525 }
6526
6527 static struct pci_error_handlers ixgbe_err_handler = {
6528 .error_detected = ixgbe_io_error_detected,
6529 .slot_reset = ixgbe_io_slot_reset,
6530 .resume = ixgbe_io_resume,
6531 };
6532
6533 static struct pci_driver ixgbe_driver = {
6534 .name = ixgbe_driver_name,
6535 .id_table = ixgbe_pci_tbl,
6536 .probe = ixgbe_probe,
6537 .remove = __devexit_p(ixgbe_remove),
6538 #ifdef CONFIG_PM
6539 .suspend = ixgbe_suspend,
6540 .resume = ixgbe_resume,
6541 #endif
6542 .shutdown = ixgbe_shutdown,
6543 .err_handler = &ixgbe_err_handler
6544 };
6545
6546 /**
6547 * ixgbe_init_module - Driver Registration Routine
6548 *
6549 * ixgbe_init_module is the first routine called when the driver is
6550 * loaded. All it does is register with the PCI subsystem.
6551 **/
6552 static int __init ixgbe_init_module(void)
6553 {
6554 int ret;
6555 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6556 ixgbe_driver_string, ixgbe_driver_version);
6557
6558 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6559
6560 #ifdef CONFIG_IXGBE_DCA
6561 dca_register_notify(&dca_notifier);
6562 #endif
6563
6564 ret = pci_register_driver(&ixgbe_driver);
6565 return ret;
6566 }
6567
6568 module_init(ixgbe_init_module);
6569
6570 /**
6571 * ixgbe_exit_module - Driver Exit Cleanup Routine
6572 *
6573 * ixgbe_exit_module is called just before the driver is removed
6574 * from memory.
6575 **/
6576 static void __exit ixgbe_exit_module(void)
6577 {
6578 #ifdef CONFIG_IXGBE_DCA
6579 dca_unregister_notify(&dca_notifier);
6580 #endif
6581 pci_unregister_driver(&ixgbe_driver);
6582 }
6583
6584 #ifdef CONFIG_IXGBE_DCA
6585 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6586 void *p)
6587 {
6588 int ret_val;
6589
6590 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6591 __ixgbe_notify_dca);
6592
6593 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6594 }
6595
6596 #endif /* CONFIG_IXGBE_DCA */
6597 #ifdef DEBUG
6598 /**
6599 * ixgbe_get_hw_dev_name - return device name string
6600 * used by hardware layer to print debugging information
6601 **/
6602 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6603 {
6604 struct ixgbe_adapter *adapter = hw->back;
6605 return adapter->netdev->name;
6606 }
6607
6608 #endif
6609 module_exit(ixgbe_exit_module);
6610
6611 /* ixgbe_main.c */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree