drivers/staging/et131x/et1310_phy.c

   1 /*
   2  * Agere Systems Inc.
   3  * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
   4  *
   5  * Copyright * 2005 Agere Systems Inc.
   6  * All rights reserved.
   7  *   http://www.agere.com
   8  *
   9  *------------------------------------------------------------------------------
  10  *
  11  * et1310_phy.c - Routines for configuring and accessing the PHY
  12  *
  13  *------------------------------------------------------------------------------
  14  *
  15  * SOFTWARE LICENSE
  16  *
  17  * This software is provided subject to the following terms and conditions,
  18  * which you should read carefully before using the software.  Using this
  19  * software indicates your acceptance of these terms and conditions.  If you do
  20  * not agree with these terms and conditions, do not use the software.
  21  *
  22  * Copyright * 2005 Agere Systems Inc.
  23  * All rights reserved.
  24  *
  25  * Redistribution and use in source or binary forms, with or without
  26  * modifications, are permitted provided that the following conditions are met:
  27  *
  28  * . Redistributions of source code must retain the above copyright notice, this
  29  *    list of conditions and the following Disclaimer as comments in the code as
  30  *    well as in the documentation and/or other materials provided with the
  31  *    distribution.
  32  *
  33  * . Redistributions in binary form must reproduce the above copyright notice,
  34  *    this list of conditions and the following Disclaimer in the documentation
  35  *    and/or other materials provided with the distribution.
  36  *
  37  * . Neither the name of Agere Systems Inc. nor the names of the contributors
  38  *    may be used to endorse or promote products derived from this software
  39  *    without specific prior written permission.
  40  *
  41  * Disclaimer
  42  *
  43  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  44  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
  45  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
  46  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
  47  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
  48  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  49  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  50  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  51  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
  52  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  53  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  54  * DAMAGE.
  55  *
  56  */
  57
  58 #include "et131x_version.h"
  59 #include "et131x_defs.h"
  60
  61 #include <linux/pci.h>
  62 #include <linux/init.h>
  63 #include <linux/module.h>
  64 #include <linux/types.h>
  65 #include <linux/kernel.h>
  66
  67 #include <linux/sched.h>
  68 #include <linux/ptrace.h>
  69 #include <linux/ctype.h>
  70 #include <linux/string.h>
  71 #include <linux/timer.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/in.h>
  74 #include <linux/delay.h>
  75 #include <linux/io.h>
  76 #include <linux/bitops.h>
  77 #include <asm/system.h>
  78
  79 #include <linux/netdevice.h>
  80 #include <linux/etherdevice.h>
  81 #include <linux/skbuff.h>
  82 #include <linux/if_arp.h>
  83 #include <linux/ioport.h>
  84 #include <linux/random.h>
  85
  86 #include "et1310_phy.h"
  87
  88 #include "et131x_adapter.h"
  89
  90 #include "et1310_address_map.h"
  91 #include "et1310_tx.h"
  92 #include "et1310_rx.h"
  93
  94 #include "et131x.h"
  95
  96 /**
  97  * et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
  98  * @adapter: pointer to our private adapter structure
  99  * @xcvr_addr: the address of the transceiver
 100  * @xcvr_reg: the register to read
 101  * @value: pointer to a 16-bit value in which the value will be stored
 102  *
 103  * Returns 0 on success, errno on failure (as defined in errno.h)
 104  */
 105 int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 xcvr_addr,
 106               u8 xcvr_reg, u16 *value)
 107 {
 108         struct mac_regs __iomem *mac = &adapter->regs->mac;
 109         int status = 0;
 110         u32 delay;
 111         u32 mii_addr;
 112         u32 mii_cmd;
 113         u32 mii_indicator;
 114
 115         /* Save a local copy of the registers we are dealing with so we can
 116          * set them back
 117          */
 118         mii_addr = readl(&mac->mii_mgmt_addr);
 119         mii_cmd = readl(&mac->mii_mgmt_cmd);
 120
 121         /* Stop the current operation */
 122         writel(0, &mac->mii_mgmt_cmd);
 123
 124         /* Set up the register we need to read from on the correct PHY */
 125         writel(MII_ADDR(xcvr_addr, xcvr_reg), &mac->mii_mgmt_addr);
 126
 127         /* Kick the read cycle off */
 128         delay = 0;
 129
 130         writel(0x1, &mac->mii_mgmt_cmd);
 131
 132         do {
 133                 udelay(50);
 134                 delay++;
 135                 mii_indicator = readl(&mac->mii_mgmt_indicator);
 136         } while ((mii_indicator & MGMT_WAIT) && delay < 50);
 137
 138         /* If we hit the max delay, we could not read the register */
 139         if (delay == 50) {
 140                 dev_warn(&adapter->pdev->dev,
 141                             "xcvrReg 0x%08x could not be read\n", xcvr_reg);
 142                 dev_warn(&adapter->pdev->dev, "status is  0x%08x\n",
 143                             mii_indicator);
 144
 145                 status = -EIO;
 146         }
 147
 148         /* If we hit here we were able to read the register and we need to
 149          * return the value to the caller */
 150         *value = readl(&mac->mii_mgmt_stat) & 0xFFFF;
 151
 152         /* Stop the read operation */
 153         writel(0, &mac->mii_mgmt_cmd);
 154
 155         /* set the registers we touched back to the state at which we entered
 156          * this function
 157          */
 158         writel(mii_addr, &mac->mii_mgmt_addr);
 159         writel(mii_cmd, &mac->mii_mgmt_cmd);
 160
 161         return status;
 162 }
 163
 164 /**
 165  * et131x_mii_write - Write to a PHY register through the MII interface of the MAC
 166  * @adapter: pointer to our private adapter structure
 167  * @xcvr_reg: the register to read
 168  * @value: 16-bit value to write
 169  *
 170  * FIXME: one caller in netdev still
 171  *
 172  * Return 0 on success, errno on failure (as defined in errno.h)
 173  */
 174 int et131x_mii_write(struct et131x_adapter *adapter, u8 xcvr_reg, u16 value)
 175 {
 176         struct mac_regs __iomem *mac = &adapter->regs->mac;
 177         int status = 0;
 178         u8 xcvr_addr = adapter->stats.xcvr_addr;
 179         u32 delay;
 180         u32 mii_addr;
 181         u32 mii_cmd;
 182         u32 mii_indicator;
 183
 184         /* Save a local copy of the registers we are dealing with so we can
 185          * set them back
 186          */
 187         mii_addr = readl(&mac->mii_mgmt_addr);
 188         mii_cmd = readl(&mac->mii_mgmt_cmd);
 189
 190         /* Stop the current operation */
 191         writel(0, &mac->mii_mgmt_cmd);
 192
 193         /* Set up the register we need to write to on the correct PHY */
 194         writel(MII_ADDR(xcvr_addr, xcvr_reg), &mac->mii_mgmt_addr);
 195
 196         /* Add the value to write to the registers to the mac */
 197         writel(value, &mac->mii_mgmt_ctrl);
 198         delay = 0;
 199
 200         do {
 201                 udelay(50);
 202                 delay++;
 203                 mii_indicator = readl(&mac->mii_mgmt_indicator);
 204         } while ((mii_indicator & MGMT_BUSY) && delay < 100);
 205
 206         /* If we hit the max delay, we could not write the register */
 207         if (delay == 100) {
 208                 u16 tmp;
 209
 210                 dev_warn(&adapter->pdev->dev,
 211                     "xcvrReg 0x%08x could not be written", xcvr_reg);
 212                 dev_warn(&adapter->pdev->dev, "status is  0x%08x\n",
 213                             mii_indicator);
 214                 dev_warn(&adapter->pdev->dev, "command is  0x%08x\n",
 215                             readl(&mac->mii_mgmt_cmd));
 216
 217                 et131x_mii_read(adapter, xcvr_reg, &tmp);
 218
 219                 status = -EIO;
 220         }
 221         /* Stop the write operation */
 222         writel(0, &mac->mii_mgmt_cmd);
 223
 224         /*
 225          * set the registers we touched back to the state at which we entered
 226          * this function
 227          */
 228         writel(mii_addr, &mac->mii_mgmt_addr);
 229         writel(mii_cmd, &mac->mii_mgmt_cmd);
 230
 231         return status;
 232 }
 233
 234 /**
 235  * et131x_xcvr_find - Find the PHY ID
 236  * @adapter: pointer to our private adapter structure
 237  *
 238  * Returns 0 on success, errno on failure (as defined in errno.h)
 239  */
 240 int et131x_xcvr_find(struct et131x_adapter *adapter)
 241 {
 242         u8 xcvr_addr;
 243         u16 idr1;
 244         u16 idr2;
 245
 246         /* We need to get xcvr id and address we just get the first one */
 247         for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) {
 248                 /* Read the ID from the PHY */
 249                 et131x_phy_mii_read(adapter, xcvr_addr,
 250                              (u8) offsetof(struct mi_regs, idr1),
 251                              &idr1);
 252                 et131x_phy_mii_read(adapter, xcvr_addr,
 253                              (u8) offsetof(struct mi_regs, idr2),
 254                              &idr2);
 255
 256                 if (idr1 != 0 && idr1 != 0xffff) {
 257                         adapter->stats.xcvr_addr = xcvr_addr;
 258                         return 0;
 259                 }
 260         }
 261         return -ENODEV;
 262 }
 263
 264 void et1310_phy_reset(struct et131x_adapter *adapter)
 265 {
 266         et131x_mii_write(adapter, PHY_CONTROL, 0x8000);
 267 }
 268
 269 /**
 270  *      et1310_phy_power_down   -       PHY power control
 271  *      @adapter: device to control
 272  *      @down: true for off/false for back on
 273  *
 274  *      one hundred, ten, one thousand megs
 275  *      How would you like to have your LAN accessed
 276  *      Can't you see that this code processed
 277  *      Phy power, phy power..
 278  */
 279 void et1310_phy_power_down(struct et131x_adapter *adapter, bool down)
 280 {
 281         u16 data;
 282
 283         et131x_mii_read(adapter, PHY_CONTROL, &data);
 284         data &= ~0x0800;        /* Power UP */
 285         if (down) /* Power DOWN */
 286                 data |= 0x0800;
 287         et131x_mii_write(adapter, PHY_CONTROL, data);
 288 }
 289
 290 /**
 291  *      et1310_phy_auto_neg     -       autonegotiate control
 292  *      @adapter: device to control
 293  *      @enabe: autoneg on/off
 294  *
 295  *      Set up the autonegotiation state according to whether we will be
 296  *      negotiating the state or forcing a speed.
 297  */
 298 static void et1310_phy_auto_neg(struct et131x_adapter *adapter, bool enable)
 299 {
 300         u16 data;
 301
 302         et131x_mii_read(adapter, PHY_CONTROL, &data);
 303         data &= ~0x1000;        /* Autonegotiation OFF */
 304         if (enable)
 305                 data |= 0x1000;         /* Autonegotiation ON */
 306         et131x_mii_write(adapter, PHY_CONTROL, data);
 307 }
 308
 309 /**
 310  *      et1310_phy_duplex_mode  -       duplex control
 311  *      @adapter: device to control
 312  *      @duplex: duplex on/off
 313  *
 314  *      Set up the duplex state on the PHY
 315  */
 316 static void et1310_phy_duplex_mode(struct et131x_adapter *adapter, u16 duplex)
 317 {
 318         u16 data;
 319
 320         et131x_mii_read(adapter, PHY_CONTROL, &data);
 321         data &= ~0x100;         /* Set Half Duplex */
 322         if (duplex == TRUEPHY_DUPLEX_FULL)
 323                 data |= 0x100;  /* Set Full Duplex */
 324         et131x_mii_write(adapter, PHY_CONTROL, data);
 325 }
 326
 327 /**
 328  *      et1310_phy_speed_select -       speed control
 329  *      @adapter: device to control
 330  *      @duplex: duplex on/off
 331  *
 332  *      Set the speed of our PHY.
 333  */
 334 static void et1310_phy_speed_select(struct et131x_adapter *adapter, u16 speed)
 335 {
 336         u16 data;
 337         static const u16 bits[3] = {0x0000, 0x2000, 0x0040};
 338
 339         /* Read the PHY control register */
 340         et131x_mii_read(adapter, PHY_CONTROL, &data);
 341         /* Clear all Speed settings (Bits 6, 13) */
 342         data &= ~0x2040;
 343         /* Write back the new speed */
 344         et131x_mii_write(adapter, PHY_CONTROL, data | bits[speed]);
 345 }
 346
 347 /**
 348  *      et1310_phy_link_status  -       read link state
 349  *      @adapter: device to read
 350  *      @link_status: reported link state
 351  *      @autoneg: reported autonegotiation state (complete/incomplete/disabled)
 352  *      @linkspeed: returnedlink speed in use
 353  *      @duplex_mode: reported half/full duplex state
 354  *      @mdi_mdix: not yet working
 355  *      @masterslave: report whether we are master or slave
 356  *      @polarity: link polarity
 357  *
 358  *      I can read your lan like a magazine
 359  *      I see if your up
 360  *      I know your link speed
 361  *      I see all the setting that you'd rather keep
 362  */
 363 static void et1310_phy_link_status(struct et131x_adapter *adapter,
 364                           u8 *link_status,
 365                           u32 *autoneg,
 366                           u32 *linkspeed,
 367                           u32 *duplex_mode,
 368                           u32 *mdi_mdix,
 369                           u32 *masterslave, u32 *polarity)
 370 {
 371         u16 mistatus = 0;
 372         u16 is1000BaseT = 0;
 373         u16 vmi_phystatus = 0;
 374         u16 control = 0;
 375
 376         et131x_mii_read(adapter, PHY_STATUS, &mistatus);
 377         et131x_mii_read(adapter, PHY_1000_STATUS, &is1000BaseT);
 378         et131x_mii_read(adapter, PHY_PHY_STATUS, &vmi_phystatus);
 379         et131x_mii_read(adapter, PHY_CONTROL, &control);
 380
 381         *link_status = (vmi_phystatus & 0x0040) ? 1 : 0;
 382         *autoneg = (control & 0x1000) ? ((vmi_phystatus & 0x0020) ?
 383                                             TRUEPHY_ANEG_COMPLETE :
 384                                             TRUEPHY_ANEG_NOT_COMPLETE) :
 385                     TRUEPHY_ANEG_DISABLED;
 386         *linkspeed = (vmi_phystatus & 0x0300) >> 8;
 387         *duplex_mode = (vmi_phystatus & 0x0080) >> 7;
 388         /* NOTE: Need to complete this */
 389         *mdi_mdix = 0;
 390
 391         *masterslave = (is1000BaseT & 0x4000) ?
 392                         TRUEPHY_CFG_MASTER : TRUEPHY_CFG_SLAVE;
 393         *polarity = (vmi_phystatus & 0x0400) ?
 394                         TRUEPHY_POLARITY_INVERTED : TRUEPHY_POLARITY_NORMAL;
 395 }
 396
 397 static void et1310_phy_and_or_reg(struct et131x_adapter *adapter,
 398                                   u16 regnum, u16 and_mask, u16 or_mask)
 399 {
 400         u16 reg;
 401
 402         et131x_mii_read(adapter, regnum, &reg);
 403         reg &= and_mask;
 404         reg |= or_mask;
 405         et131x_mii_write(adapter, regnum, reg);
 406 }
 407
 408 /* Still used from _mac for BIT_READ */
 409 void et1310_phy_access_mii_bit(struct et131x_adapter *adapter, u16 action,
 410                                u16 regnum, u16 bitnum, u8 *value)
 411 {
 412         u16 reg;
 413         u16 mask = 0x0001 << bitnum;
 414
 415         /* Read the requested register */
 416         et131x_mii_read(adapter, regnum, &reg);
 417
 418         switch (action) {
 419         case TRUEPHY_BIT_READ:
 420                 *value = (reg & mask) >> bitnum;
 421                 break;
 422
 423         case TRUEPHY_BIT_SET:
 424                 et131x_mii_write(adapter, regnum, reg | mask);
 425                 break;
 426
 427         case TRUEPHY_BIT_CLEAR:
 428                 et131x_mii_write(adapter, regnum, reg & ~mask);
 429                 break;
 430
 431         default:
 432                 break;
 433         }
 434 }
 435
 436 void et1310_phy_advertise_1000BaseT(struct et131x_adapter *adapter,
 437                                   u16 duplex)
 438 {
 439         u16 data;
 440
 441         /* Read the PHY 1000 Base-T Control Register */
 442         et131x_mii_read(adapter, PHY_1000_CONTROL, &data);
 443
 444         /* Clear Bits 8,9 */
 445         data &= ~0x0300;
 446
 447         switch (duplex) {
 448         case TRUEPHY_ADV_DUPLEX_NONE:
 449                 /* Duplex already cleared, do nothing */
 450                 break;
 451
 452         case TRUEPHY_ADV_DUPLEX_FULL:
 453                 /* Set Bit 9 */
 454                 data |= 0x0200;
 455                 break;
 456
 457         case TRUEPHY_ADV_DUPLEX_HALF:
 458                 /* Set Bit 8 */
 459                 data |= 0x0100;
 460                 break;
 461
 462         case TRUEPHY_ADV_DUPLEX_BOTH:
 463         default:
 464                 data |= 0x0300;
 465                 break;
 466         }
 467
 468         /* Write back advertisement */
 469         et131x_mii_write(adapter, PHY_1000_CONTROL, data);
 470 }
 471
 472 static void et1310_phy_advertise_100BaseT(struct et131x_adapter *adapter,
 473                                           u16 duplex)
 474 {
 475         u16 data;
 476
 477         /* Read the Autonegotiation Register (10/100) */
 478         et131x_mii_read(adapter, PHY_AUTO_ADVERTISEMENT, &data);
 479
 480         /* Clear bits 7,8 */
 481         data &= ~0x0180;
 482
 483         switch (duplex) {
 484         case TRUEPHY_ADV_DUPLEX_NONE:
 485                 /* Duplex already cleared, do nothing */
 486                 break;
 487
 488         case TRUEPHY_ADV_DUPLEX_FULL:
 489                 /* Set Bit 8 */
 490                 data |= 0x0100;
 491                 break;
 492
 493         case TRUEPHY_ADV_DUPLEX_HALF:
 494                 /* Set Bit 7 */
 495                 data |= 0x0080;
 496                 break;
 497
 498         case TRUEPHY_ADV_DUPLEX_BOTH:
 499         default:
 500                 /* Set Bits 7,8 */
 501                 data |= 0x0180;
 502                 break;
 503         }
 504
 505         /* Write back advertisement */
 506         et131x_mii_write(adapter, PHY_AUTO_ADVERTISEMENT, data);
 507 }
 508
 509 static void et1310_phy_advertise_10BaseT(struct et131x_adapter *adapter,
 510                                 u16 duplex)
 511 {
 512         u16 data;
 513
 514         /* Read the Autonegotiation Register (10/100) */
 515         et131x_mii_read(adapter, PHY_AUTO_ADVERTISEMENT, &data);
 516
 517         /* Clear bits 5,6 */
 518         data &= ~0x0060;
 519
 520         switch (duplex) {
 521         case TRUEPHY_ADV_DUPLEX_NONE:
 522                 /* Duplex already cleared, do nothing */
 523                 break;
 524
 525         case TRUEPHY_ADV_DUPLEX_FULL:
 526                 /* Set Bit 6 */
 527                 data |= 0x0040;
 528                 break;
 529
 530         case TRUEPHY_ADV_DUPLEX_HALF:
 531                 /* Set Bit 5 */
 532                 data |= 0x0020;
 533                 break;
 534
 535         case TRUEPHY_ADV_DUPLEX_BOTH:
 536         default:
 537                 /* Set Bits 5,6 */
 538                 data |= 0x0060;
 539                 break;
 540         }
 541
 542         /* Write back advertisement */
 543         et131x_mii_write(adapter, PHY_AUTO_ADVERTISEMENT, data);
 544 }
 545
 546 /**
 547  * et131x_xcvr_init - Init the phy if we are setting it into force mode
 548  * @adapter: pointer to our private adapter structure
 549  *
 550  */
 551 static void et131x_xcvr_init(struct et131x_adapter *adapter)
 552 {
 553         u16 imr;
 554         u16 isr;
 555         u16 lcr2;
 556
 557         /* Zero out the adapter structure variable representing BMSR */
 558         adapter->bmsr = 0;
 559
 560         et131x_mii_read(adapter, (u8) offsetof(struct mi_regs, isr), &isr);
 561         et131x_mii_read(adapter, (u8) offsetof(struct mi_regs, imr), &imr);
 562
 563         /* Set the link status interrupt only.  Bad behavior when link status
 564          * and auto neg are set, we run into a nested interrupt problem
 565          */
 566         imr |= 0x0105;
 567
 568         et131x_mii_write(adapter, (u8) offsetof(struct mi_regs, imr), imr);
 569
 570         /* Set the LED behavior such that LED 1 indicates speed (off =
 571          * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
 572          * link and activity (on for link, blink off for activity).
 573          *
 574          * NOTE: Some customizations have been added here for specific
 575          * vendors; The LED behavior is now determined by vendor data in the
 576          * EEPROM. However, the above description is the default.
 577          */
 578         if ((adapter->eeprom_data[1] & 0x4) == 0) {
 579                 et131x_mii_read(adapter, (u8) offsetof(struct mi_regs, lcr2),
 580                        &lcr2);
 581
 582                 lcr2 &= 0x00FF;
 583                 lcr2 |= 0xA000; /* led link */
 584
 585                 if ((adapter->eeprom_data[1] & 0x8) == 0)
 586                         lcr2 |= 0x0300;
 587                 else
 588                         lcr2 |= 0x0400;
 589
 590                 et131x_mii_write(adapter, (u8) offsetof(struct mi_regs, lcr2),
 591                         lcr2);
 592         }
 593
 594         /* Determine if we need to go into a force mode and set it */
 595         if (adapter->ai_force_speed == 0 && adapter->ai_force_duplex == 0) {
 596                 if (adapter->wanted_flow == FLOW_TXONLY ||
 597                     adapter->wanted_flow == FLOW_BOTH)
 598                         et1310_phy_access_mii_bit(adapter,
 599                                               TRUEPHY_BIT_SET, 4, 11, NULL);
 600                 else
 601                         et1310_phy_access_mii_bit(adapter,
 602                                               TRUEPHY_BIT_CLEAR, 4, 11, NULL);
 603
 604                 if (adapter->wanted_flow == FLOW_BOTH)
 605                         et1310_phy_access_mii_bit(adapter,
 606                                               TRUEPHY_BIT_SET, 4, 10, NULL);
 607                 else
 608                         et1310_phy_access_mii_bit(adapter,
 609                                               TRUEPHY_BIT_CLEAR, 4, 10, NULL);
 610
 611                 /* Set the phy to autonegotiation */
 612                 et1310_phy_auto_neg(adapter, true);
 613
 614                 /* NOTE - Do we need this? */
 615                 et1310_phy_access_mii_bit(adapter, TRUEPHY_BIT_SET, 0, 9, NULL);
 616                 return;
 617         }
 618
 619         et1310_phy_auto_neg(adapter, false);
 620
 621         /* Set to the correct force mode. */
 622         if (adapter->ai_force_duplex != 1) {
 623                 if (adapter->wanted_flow == FLOW_TXONLY ||
 624                     adapter->wanted_flow == FLOW_BOTH)
 625                         et1310_phy_access_mii_bit(adapter,
 626                                       TRUEPHY_BIT_SET, 4, 11, NULL);
 627                 else
 628                         et1310_phy_access_mii_bit(adapter,
 629                                               TRUEPHY_BIT_CLEAR, 4, 11, NULL);
 630
 631                 if (adapter->wanted_flow == FLOW_BOTH)
 632                         et1310_phy_access_mii_bit(adapter,
 633                                               TRUEPHY_BIT_SET, 4, 10, NULL);
 634                 else
 635                         et1310_phy_access_mii_bit(adapter,
 636                                               TRUEPHY_BIT_CLEAR, 4, 10, NULL);
 637         } else {
 638                 et1310_phy_access_mii_bit(adapter, TRUEPHY_BIT_CLEAR,
 639                                           4, 10, NULL);
 640                 et1310_phy_access_mii_bit(adapter, TRUEPHY_BIT_CLEAR,
 641                                           4, 11, NULL);
 642         }
 643         et1310_phy_power_down(adapter, 1);
 644         switch (adapter->ai_force_speed) {
 645         case 10:
 646                 /* First we need to turn off all other advertisement */
 647                 et1310_phy_advertise_1000BaseT(adapter, TRUEPHY_ADV_DUPLEX_NONE);
 648                 et1310_phy_advertise_100BaseT(adapter, TRUEPHY_ADV_DUPLEX_NONE);
 649                 if (adapter->ai_force_duplex == 1) {
 650                         /* Set our advertise values accordingly */
 651                         et1310_phy_advertise_10BaseT(adapter,
 652                                                 TRUEPHY_ADV_DUPLEX_HALF);
 653                 } else if (adapter->ai_force_duplex == 2) {
 654                         /* Set our advertise values accordingly */
 655                         et1310_phy_advertise_10BaseT(adapter,
 656                                                 TRUEPHY_ADV_DUPLEX_FULL);
 657                 } else {
 658                         /* Disable autoneg */
 659                         et1310_phy_auto_neg(adapter, false);
 660                         /* Disable rest of the advertisements */
 661                         et1310_phy_advertise_10BaseT(adapter,
 662                                         TRUEPHY_ADV_DUPLEX_NONE);
 663                         /* Force 10 Mbps */
 664                         et1310_phy_speed_select(adapter, TRUEPHY_SPEED_10MBPS);
 665                         /* Force Full duplex */
 666                         et1310_phy_duplex_mode(adapter, TRUEPHY_DUPLEX_FULL);
 667                 }
 668                 break;
 669         case 100:
 670                 /* first we need to turn off all other advertisement */
 671                 et1310_phy_advertise_1000BaseT(adapter, TRUEPHY_ADV_DUPLEX_NONE);
 672                 et1310_phy_advertise_10BaseT(adapter, TRUEPHY_ADV_DUPLEX_NONE);
 673                 if (adapter->ai_force_duplex == 1) {
 674                         /* Set our advertise values accordingly */
 675                         et1310_phy_advertise_100BaseT(adapter,
 676                                                 TRUEPHY_ADV_DUPLEX_HALF);
 677                         /* Set speed */
 678                         et1310_phy_speed_select(adapter, TRUEPHY_SPEED_100MBPS);
 679                 } else if (adapter->ai_force_duplex == 2) {
 680                         /* Set our advertise values accordingly */
 681                         et1310_phy_advertise_100BaseT(adapter,
 682                                                 TRUEPHY_ADV_DUPLEX_FULL);
 683                 } else {
 684                         /* Disable autoneg */
 685                         et1310_phy_auto_neg(adapter, false);
 686                         /* Disable other advertisement */
 687                         et1310_phy_advertise_100BaseT(adapter,
 688                                                 TRUEPHY_ADV_DUPLEX_NONE);
 689                         /* Force 100 Mbps */
 690                         et1310_phy_speed_select(adapter, TRUEPHY_SPEED_100MBPS);
 691                         /* Force Full duplex */
 692                         et1310_phy_duplex_mode(adapter, TRUEPHY_DUPLEX_FULL);
 693                 }
 694                 break;
 695         case 1000:
 696                 /* first we need to turn off all other advertisement */
 697                 et1310_phy_advertise_100BaseT(adapter, TRUEPHY_ADV_DUPLEX_NONE);
 698                 et1310_phy_advertise_10BaseT(adapter, TRUEPHY_ADV_DUPLEX_NONE);
 699                 /* set our advertise values accordingly */
 700                 et1310_phy_advertise_1000BaseT(adapter, TRUEPHY_ADV_DUPLEX_FULL);
 701                 break;
 702         }
 703         et1310_phy_power_down(adapter, 0);
 704 }
 705
 706 /**
 707  * et131x_setphy_normal - Set PHY for normal operation.
 708  * @adapter: pointer to our private adapter structure
 709  *
 710  * Used by Power Management to force the PHY into 10 Base T half-duplex mode,
 711  * when going to D3 in WOL mode. Also used during initialization to set the
 712  * PHY for normal operation.
 713  */
 714 void et131x_setphy_normal(struct et131x_adapter *adapter)
 715 {
 716         /* Make sure the PHY is powered up */
 717         et1310_phy_power_down(adapter, 0);
 718         et131x_xcvr_init(adapter);
 719 }
 720
 721 void et131x_mii_check(struct et131x_adapter *adapter,
 722                       u16 bmsr, u16 bmsr_ints)
 723 {
 724         u8 link_status;
 725         u32 autoneg_status;
 726         u32 speed;
 727         u32 duplex;
 728         u32 mdi_mdix;
 729         u32 masterslave;
 730         u32 polarity;
 731
 732         if (bmsr_ints & MI_BMSR_LINK_STATUS) {
 733                 if (bmsr & MI_BMSR_LINK_STATUS) {
 734                         adapter->boot_coma = 20;
 735                         netif_carrier_on(adapter->netdev);
 736                 } else {
 737                         dev_warn(&adapter->pdev->dev,
 738                             "Link down - cable problem ?\n");
 739
 740                         if (adapter->linkspeed == TRUEPHY_SPEED_10MBPS) {
 741                                 /* NOTE - Is there a way to query this without
 742                                  * TruePHY?
 743                                  * && TRU_QueryCoreType(adapter->hTruePhy, 0) ==
 744                                  * EMI_TRUEPHY_A13O) {
 745                                  */
 746                                 u16 register18;
 747
 748                                 et131x_mii_read(adapter, 0x12, &register18);
 749                                 et131x_mii_write(adapter, 0x12, register18 | 0x4);
 750                                 et131x_mii_write(adapter, 0x10,
 751                                                  register18 | 0x8402);
 752                                 et131x_mii_write(adapter, 0x11, register18 | 511);
 753                                 et131x_mii_write(adapter, 0x12, register18);
 754                         }
 755
 756                         netif_carrier_off(adapter->netdev);
 757
 758                         adapter->linkspeed = 0;
 759                         adapter->duplex_mode = 0;
 760
 761                         /* Free the packets being actively sent & stopped */
 762                         et131x_free_busy_send_packets(adapter);
 763
 764                         /* Re-initialize the send structures */
 765                         et131x_init_send(adapter);
 766
 767                         /* Reset the RFD list and re-start RU */
 768                         et131x_reset_recv(adapter);
 769
 770                         /*
 771                          * Bring the device back to the state it was during
 772                          * init prior to autonegotiation being complete. This
 773                          * way, when we get the auto-neg complete interrupt,
 774                          * we can complete init by calling config_mac_regs2.
 775                          */
 776                         et131x_soft_reset(adapter);
 777
 778                         /* Setup ET1310 as per the documentation */
 779                         et131x_adapter_setup(adapter);
 780
 781                         /* Setup the PHY into coma mode until the cable is
 782                          * plugged back in
 783                          */
 784                         if (adapter->registry_phy_coma == 1)
 785                                 et1310_enable_phy_coma(adapter);
 786                 }
 787         }
 788
 789         if ((bmsr_ints & MI_BMSR_AUTO_NEG_COMPLETE) ||
 790            (adapter->ai_force_duplex == 3 && (bmsr_ints & MI_BMSR_LINK_STATUS))) {
 791                 if ((bmsr & MI_BMSR_AUTO_NEG_COMPLETE) ||
 792                     adapter->ai_force_duplex == 3) {
 793                         et1310_phy_link_status(adapter,
 794                                              &link_status, &autoneg_status,
 795                                              &speed, &duplex, &mdi_mdix,
 796                                              &masterslave, &polarity);
 797
 798                         adapter->linkspeed = speed;
 799                         adapter->duplex_mode = duplex;
 800
 801                         adapter->boot_coma = 20;
 802
 803                         if (adapter->linkspeed == TRUEPHY_SPEED_10MBPS) {
 804                                 /*
 805                                  * NOTE - Is there a way to query this without
 806                                  * TruePHY?
 807                                  * && TRU_QueryCoreType(adapter->hTruePhy, 0)==
 808                                  * EMI_TRUEPHY_A13O) {
 809                                  */
 810                                 u16 register18;
 811
 812                                 et131x_mii_read(adapter, 0x12, &register18);
 813                                 et131x_mii_write(adapter, 0x12, register18 | 0x4);
 814                                 et131x_mii_write(adapter, 0x10,
 815                                                  register18 | 0x8402);
 816                                 et131x_mii_write(adapter, 0x11, register18 | 511);
 817                                 et131x_mii_write(adapter, 0x12, register18);
 818                         }
 819
 820                         et1310_config_flow_control(adapter);
 821
 822                         if (adapter->linkspeed == TRUEPHY_SPEED_1000MBPS &&
 823                                         adapter->registry_jumbo_packet > 2048)
 824                                 et1310_phy_and_or_reg(adapter, 0x16, 0xcfff,
 825                                                                    0x2000);
 826
 827                         et131x_set_rx_dma_timer(adapter);
 828                         et1310_config_mac_regs2(adapter);
 829                 }
 830         }
 831 }
 832
 833 /*
 834  * The routines which follow provide low-level access to the PHY, and are used
 835  * primarily by the routines above (although there are a few places elsewhere
 836  * in the driver where this level of access is required).
 837  */
 838 static const u16 config_phy[25][2] = {
 839         /* Reg   Value          Register */
 840         /* Addr                         */
 841         {0x880B, 0x0926},       /* AfeIfCreg4B1000Msbs */
 842         {0x880C, 0x0926},       /* AfeIfCreg4B100Msbs */
 843         {0x880D, 0x0926},       /* AfeIfCreg4B10Msbs */
 844
 845         {0x880E, 0xB4D3},       /* AfeIfCreg4B1000Lsbs */
 846         {0x880F, 0xB4D3},       /* AfeIfCreg4B100Lsbs */
 847         {0x8810, 0xB4D3},       /* AfeIfCreg4B10Lsbs */
 848
 849         {0x8805, 0xB03E},       /* AfeIfCreg3B1000Msbs */
 850         {0x8806, 0xB03E},       /* AfeIfCreg3B100Msbs */
 851         {0x8807, 0xFF00},       /* AfeIfCreg3B10Msbs */
 852
 853         {0x8808, 0xE090},       /* AfeIfCreg3B1000Lsbs */
 854         {0x8809, 0xE110},       /* AfeIfCreg3B100Lsbs */
 855         {0x880A, 0x0000},       /* AfeIfCreg3B10Lsbs */
 856
 857         {0x300D, 1},            /* DisableNorm */
 858
 859         {0x280C, 0x0180},       /* LinkHoldEnd */
 860
 861         {0x1C21, 0x0002},       /* AlphaM */
 862
 863         {0x3821, 6},            /* FfeLkgTx0 */
 864         {0x381D, 1},            /* FfeLkg1g4 */
 865         {0x381E, 1},            /* FfeLkg1g5 */
 866         {0x381F, 1},            /* FfeLkg1g6 */
 867         {0x3820, 1},            /* FfeLkg1g7 */
 868
 869         {0x8402, 0x01F0},       /* Btinact */
 870         {0x800E, 20},           /* LftrainTime */
 871         {0x800F, 24},           /* DvguardTime */
 872         {0x8010, 46},           /* IdlguardTime */
 873
 874         {0, 0}
 875 };
 876
 877 /* condensed version of the phy initialization routine */
 878 void et1310_phy_init(struct et131x_adapter *adapter)
 879 {
 880         u16 data, index;
 881
 882         /* get the identity (again ?) */
 883         et131x_mii_read(adapter, PHY_ID_1, &data);
 884         et131x_mii_read(adapter, PHY_ID_2, &data);
 885
 886         /* what does this do/achieve ? */
 887         /* should read 0002 */
 888         et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, &data);
 889         et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, 0x0006);
 890
 891         /* read modem register 0402, should I do something with the return
 892            data ? */
 893         et131x_mii_write(adapter, PHY_INDEX_REG, 0x0402);
 894         et131x_mii_read(adapter, PHY_DATA_REG, &data);
 895
 896         /* what does this do/achieve ? */
 897         et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, 0x0002);
 898
 899         /* get the identity (again ?) */
 900         et131x_mii_read(adapter, PHY_ID_1, &data);
 901         et131x_mii_read(adapter, PHY_ID_2, &data);
 902
 903         /* what does this achieve ? */
 904         /* should read 0002 */
 905         et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, &data);
 906         et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, 0x0006);
 907
 908         /* read modem register 0402, should I do something with
 909            the return data? */
 910         et131x_mii_write(adapter, PHY_INDEX_REG, 0x0402);
 911         et131x_mii_read(adapter, PHY_DATA_REG, &data);
 912
 913         et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, 0x0002);
 914
 915         /* what does this achieve (should return 0x1040) */
 916         et131x_mii_read(adapter, PHY_CONTROL, &data);
 917         /* should read 0002 */
 918         et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, &data);
 919         et131x_mii_write(adapter, PHY_CONTROL, 0x1840);
 920
 921         et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, 0x0007);
 922
 923         /* here the writing of the array starts.... */
 924         index = 0;
 925         while (config_phy[index][0] != 0x0000) {
 926                 /* write value */
 927                 et131x_mii_write(adapter, PHY_INDEX_REG, config_phy[index][0]);
 928                 et131x_mii_write(adapter, PHY_DATA_REG, config_phy[index][1]);
 929
 930                 /* read it back */
 931                 et131x_mii_write(adapter, PHY_INDEX_REG, config_phy[index][0]);
 932                 et131x_mii_read(adapter, PHY_DATA_REG, &data);
 933
 934                 /* do a check on the value read back ? */
 935                 index++;
 936         }
 937         /* here the writing of the array ends... */
 938
 939         et131x_mii_read(adapter, PHY_CONTROL, &data);           /* 0x1840 */
 940         /* should read 0007 */
 941         et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, &data);
 942         et131x_mii_write(adapter, PHY_CONTROL, 0x1040);
 943         et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, 0x0002);
 944 }
 945