2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/radeon_drm.h>
32 #include <linux/vgaarb.h>
33 #include "radeon_reg.h"
35 #include "radeon_asic.h"
39 * Clear GPU surface registers.
41 void radeon_surface_init(struct radeon_device
*rdev
)
43 /* FIXME: check this out */
44 if (rdev
->family
< CHIP_R600
) {
47 for (i
= 0; i
< 8; i
++) {
48 WREG32(RADEON_SURFACE0_INFO
+
49 i
* (RADEON_SURFACE1_INFO
- RADEON_SURFACE0_INFO
),
53 WREG32(RADEON_SURFACE_CNTL
, 0);
58 * GPU scratch registers helpers function.
60 void radeon_scratch_init(struct radeon_device
*rdev
)
64 /* FIXME: check this out */
65 if (rdev
->family
< CHIP_R300
) {
66 rdev
->scratch
.num_reg
= 5;
68 rdev
->scratch
.num_reg
= 7;
70 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
71 rdev
->scratch
.free
[i
] = true;
72 rdev
->scratch
.reg
[i
] = RADEON_SCRATCH_REG0
+ (i
* 4);
76 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
)
80 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
81 if (rdev
->scratch
.free
[i
]) {
82 rdev
->scratch
.free
[i
] = false;
83 *reg
= rdev
->scratch
.reg
[i
];
90 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
)
94 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
95 if (rdev
->scratch
.reg
[i
] == reg
) {
96 rdev
->scratch
.free
[i
] = true;
103 * MC common functions
105 int radeon_mc_setup(struct radeon_device
*rdev
)
109 /* Some chips have an "issue" with the memory controller, the
110 * location must be aligned to the size. We just align it down,
111 * too bad if we walk over the top of system memory, we don't
112 * use DMA without a remapped anyway.
113 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
115 /* FGLRX seems to setup like this, VRAM a 0, then GART.
118 * Note: from R6xx the address space is 40bits but here we only
119 * use 32bits (still have to see a card which would exhaust 4G
122 if (rdev
->mc
.vram_location
!= 0xFFFFFFFFUL
) {
123 /* vram location was already setup try to put gtt after
125 tmp
= rdev
->mc
.vram_location
+ rdev
->mc
.mc_vram_size
;
126 tmp
= (tmp
+ rdev
->mc
.gtt_size
- 1) & ~(rdev
->mc
.gtt_size
- 1);
127 if ((0xFFFFFFFFUL
- tmp
) >= rdev
->mc
.gtt_size
) {
128 rdev
->mc
.gtt_location
= tmp
;
130 if (rdev
->mc
.gtt_size
>= rdev
->mc
.vram_location
) {
131 printk(KERN_ERR
"[drm] GTT too big to fit "
132 "before or after vram location.\n");
135 rdev
->mc
.gtt_location
= 0;
137 } else if (rdev
->mc
.gtt_location
!= 0xFFFFFFFFUL
) {
138 /* gtt location was already setup try to put vram before
140 if (rdev
->mc
.mc_vram_size
< rdev
->mc
.gtt_location
) {
141 rdev
->mc
.vram_location
= 0;
143 tmp
= rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
;
144 tmp
+= (rdev
->mc
.mc_vram_size
- 1);
145 tmp
&= ~(rdev
->mc
.mc_vram_size
- 1);
146 if ((0xFFFFFFFFUL
- tmp
) >= rdev
->mc
.mc_vram_size
) {
147 rdev
->mc
.vram_location
= tmp
;
149 printk(KERN_ERR
"[drm] vram too big to fit "
150 "before or after GTT location.\n");
155 rdev
->mc
.vram_location
= 0;
156 tmp
= rdev
->mc
.mc_vram_size
;
157 tmp
= (tmp
+ rdev
->mc
.gtt_size
- 1) & ~(rdev
->mc
.gtt_size
- 1);
158 rdev
->mc
.gtt_location
= tmp
;
160 rdev
->mc
.vram_start
= rdev
->mc
.vram_location
;
161 rdev
->mc
.vram_end
= rdev
->mc
.vram_location
+ rdev
->mc
.mc_vram_size
- 1;
162 rdev
->mc
.gtt_start
= rdev
->mc
.gtt_location
;
163 rdev
->mc
.gtt_end
= rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
- 1;
164 DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev
->mc
.mc_vram_size
>> 20));
165 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
166 (unsigned)rdev
->mc
.vram_location
,
167 (unsigned)(rdev
->mc
.vram_location
+ rdev
->mc
.mc_vram_size
- 1));
168 DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev
->mc
.gtt_size
>> 20));
169 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
170 (unsigned)rdev
->mc
.gtt_location
,
171 (unsigned)(rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
- 1));
177 * GPU helpers function.
179 bool radeon_card_posted(struct radeon_device
*rdev
)
183 /* first check CRTCs */
184 if (ASIC_IS_AVIVO(rdev
)) {
185 reg
= RREG32(AVIVO_D1CRTC_CONTROL
) |
186 RREG32(AVIVO_D2CRTC_CONTROL
);
187 if (reg
& AVIVO_CRTC_EN
) {
191 reg
= RREG32(RADEON_CRTC_GEN_CNTL
) |
192 RREG32(RADEON_CRTC2_GEN_CNTL
);
193 if (reg
& RADEON_CRTC_EN
) {
198 /* then check MEM_SIZE, in case the crtcs are off */
199 if (rdev
->family
>= CHIP_R600
)
200 reg
= RREG32(R600_CONFIG_MEMSIZE
);
202 reg
= RREG32(RADEON_CONFIG_MEMSIZE
);
211 bool radeon_boot_test_post_card(struct radeon_device
*rdev
)
213 if (radeon_card_posted(rdev
))
217 DRM_INFO("GPU not posted. posting now...\n");
218 if (rdev
->is_atom_bios
)
219 atom_asic_init(rdev
->mode_info
.atom_context
);
221 radeon_combios_asic_init(rdev
->ddev
);
224 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
229 int radeon_dummy_page_init(struct radeon_device
*rdev
)
231 rdev
->dummy_page
.page
= alloc_page(GFP_DMA32
| GFP_KERNEL
| __GFP_ZERO
);
232 if (rdev
->dummy_page
.page
== NULL
)
234 rdev
->dummy_page
.addr
= pci_map_page(rdev
->pdev
, rdev
->dummy_page
.page
,
235 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
236 if (!rdev
->dummy_page
.addr
) {
237 __free_page(rdev
->dummy_page
.page
);
238 rdev
->dummy_page
.page
= NULL
;
244 void radeon_dummy_page_fini(struct radeon_device
*rdev
)
246 if (rdev
->dummy_page
.page
== NULL
)
248 pci_unmap_page(rdev
->pdev
, rdev
->dummy_page
.addr
,
249 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
250 __free_page(rdev
->dummy_page
.page
);
251 rdev
->dummy_page
.page
= NULL
;
256 * Registers accessors functions.
258 uint32_t radeon_invalid_rreg(struct radeon_device
*rdev
, uint32_t reg
)
260 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg
);
265 void radeon_invalid_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
267 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
272 void radeon_register_accessor_init(struct radeon_device
*rdev
)
274 rdev
->mc_rreg
= &radeon_invalid_rreg
;
275 rdev
->mc_wreg
= &radeon_invalid_wreg
;
276 rdev
->pll_rreg
= &radeon_invalid_rreg
;
277 rdev
->pll_wreg
= &radeon_invalid_wreg
;
278 rdev
->pciep_rreg
= &radeon_invalid_rreg
;
279 rdev
->pciep_wreg
= &radeon_invalid_wreg
;
281 /* Don't change order as we are overridding accessor. */
282 if (rdev
->family
< CHIP_RV515
) {
283 rdev
->pcie_reg_mask
= 0xff;
285 rdev
->pcie_reg_mask
= 0x7ff;
287 /* FIXME: not sure here */
288 if (rdev
->family
<= CHIP_R580
) {
289 rdev
->pll_rreg
= &r100_pll_rreg
;
290 rdev
->pll_wreg
= &r100_pll_wreg
;
292 if (rdev
->family
>= CHIP_R420
) {
293 rdev
->mc_rreg
= &r420_mc_rreg
;
294 rdev
->mc_wreg
= &r420_mc_wreg
;
296 if (rdev
->family
>= CHIP_RV515
) {
297 rdev
->mc_rreg
= &rv515_mc_rreg
;
298 rdev
->mc_wreg
= &rv515_mc_wreg
;
300 if (rdev
->family
== CHIP_RS400
|| rdev
->family
== CHIP_RS480
) {
301 rdev
->mc_rreg
= &rs400_mc_rreg
;
302 rdev
->mc_wreg
= &rs400_mc_wreg
;
304 if (rdev
->family
== CHIP_RS690
|| rdev
->family
== CHIP_RS740
) {
305 rdev
->mc_rreg
= &rs690_mc_rreg
;
306 rdev
->mc_wreg
= &rs690_mc_wreg
;
308 if (rdev
->family
== CHIP_RS600
) {
309 rdev
->mc_rreg
= &rs600_mc_rreg
;
310 rdev
->mc_wreg
= &rs600_mc_wreg
;
312 if (rdev
->family
>= CHIP_R600
) {
313 rdev
->pciep_rreg
= &r600_pciep_rreg
;
314 rdev
->pciep_wreg
= &r600_pciep_wreg
;
322 int radeon_asic_init(struct radeon_device
*rdev
)
324 radeon_register_accessor_init(rdev
);
325 switch (rdev
->family
) {
335 rdev
->asic
= &r100_asic
;
341 rdev
->asic
= &r300_asic
;
342 if (rdev
->flags
& RADEON_IS_PCIE
) {
343 rdev
->asic
->gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
;
344 rdev
->asic
->gart_set_page
= &rv370_pcie_gart_set_page
;
350 rdev
->asic
= &r420_asic
;
354 rdev
->asic
= &rs400_asic
;
357 rdev
->asic
= &rs600_asic
;
361 rdev
->asic
= &rs690_asic
;
364 rdev
->asic
= &rv515_asic
;
371 rdev
->asic
= &r520_asic
;
381 rdev
->asic
= &r600_asic
;
387 rdev
->asic
= &rv770_asic
;
390 /* FIXME: not supported yet */
398 * Wrapper around modesetting bits.
400 int radeon_clocks_init(struct radeon_device
*rdev
)
404 r
= radeon_static_clocks_init(rdev
->ddev
);
408 DRM_INFO("Clocks initialized !\n");
412 void radeon_clocks_fini(struct radeon_device
*rdev
)
416 /* ATOM accessor methods */
417 static uint32_t cail_pll_read(struct card_info
*info
, uint32_t reg
)
419 struct radeon_device
*rdev
= info
->dev
->dev_private
;
422 r
= rdev
->pll_rreg(rdev
, reg
);
426 static void cail_pll_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
428 struct radeon_device
*rdev
= info
->dev
->dev_private
;
430 rdev
->pll_wreg(rdev
, reg
, val
);
433 static uint32_t cail_mc_read(struct card_info
*info
, uint32_t reg
)
435 struct radeon_device
*rdev
= info
->dev
->dev_private
;
438 r
= rdev
->mc_rreg(rdev
, reg
);
442 static void cail_mc_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
444 struct radeon_device
*rdev
= info
->dev
->dev_private
;
446 rdev
->mc_wreg(rdev
, reg
, val
);
449 static void cail_reg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
451 struct radeon_device
*rdev
= info
->dev
->dev_private
;
456 static uint32_t cail_reg_read(struct card_info
*info
, uint32_t reg
)
458 struct radeon_device
*rdev
= info
->dev
->dev_private
;
465 int radeon_atombios_init(struct radeon_device
*rdev
)
467 struct card_info
*atom_card_info
=
468 kzalloc(sizeof(struct card_info
), GFP_KERNEL
);
473 rdev
->mode_info
.atom_card_info
= atom_card_info
;
474 atom_card_info
->dev
= rdev
->ddev
;
475 atom_card_info
->reg_read
= cail_reg_read
;
476 atom_card_info
->reg_write
= cail_reg_write
;
477 atom_card_info
->mc_read
= cail_mc_read
;
478 atom_card_info
->mc_write
= cail_mc_write
;
479 atom_card_info
->pll_read
= cail_pll_read
;
480 atom_card_info
->pll_write
= cail_pll_write
;
482 rdev
->mode_info
.atom_context
= atom_parse(atom_card_info
, rdev
->bios
);
483 radeon_atom_initialize_bios_scratch_regs(rdev
->ddev
);
484 atom_allocate_fb_scratch(rdev
->mode_info
.atom_context
);
488 void radeon_atombios_fini(struct radeon_device
*rdev
)
490 if (rdev
->mode_info
.atom_context
) {
491 kfree(rdev
->mode_info
.atom_context
->scratch
);
492 kfree(rdev
->mode_info
.atom_context
);
494 kfree(rdev
->mode_info
.atom_card_info
);
497 int radeon_combios_init(struct radeon_device
*rdev
)
499 radeon_combios_initialize_bios_scratch_regs(rdev
->ddev
);
503 void radeon_combios_fini(struct radeon_device
*rdev
)
507 /* if we get transitioned to only one device, tak VGA back */
508 static unsigned int radeon_vga_set_decode(void *cookie
, bool state
)
510 struct radeon_device
*rdev
= cookie
;
511 radeon_vga_set_state(rdev
, state
);
513 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
514 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
516 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
519 void radeon_agp_disable(struct radeon_device
*rdev
)
521 rdev
->flags
&= ~RADEON_IS_AGP
;
522 if (rdev
->family
>= CHIP_R600
) {
523 DRM_INFO("Forcing AGP to PCIE mode\n");
524 rdev
->flags
|= RADEON_IS_PCIE
;
525 } else if (rdev
->family
>= CHIP_RV515
||
526 rdev
->family
== CHIP_RV380
||
527 rdev
->family
== CHIP_RV410
||
528 rdev
->family
== CHIP_R423
) {
529 DRM_INFO("Forcing AGP to PCIE mode\n");
530 rdev
->flags
|= RADEON_IS_PCIE
;
531 rdev
->asic
->gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
;
532 rdev
->asic
->gart_set_page
= &rv370_pcie_gart_set_page
;
534 DRM_INFO("Forcing AGP to PCI mode\n");
535 rdev
->flags
|= RADEON_IS_PCI
;
536 rdev
->asic
->gart_tlb_flush
= &r100_pci_gart_tlb_flush
;
537 rdev
->asic
->gart_set_page
= &r100_pci_gart_set_page
;
544 int radeon_device_init(struct radeon_device
*rdev
,
545 struct drm_device
*ddev
,
546 struct pci_dev
*pdev
,
552 DRM_INFO("radeon: Initializing kernel modesetting.\n");
553 rdev
->shutdown
= false;
554 rdev
->dev
= &pdev
->dev
;
558 rdev
->family
= flags
& RADEON_FAMILY_MASK
;
559 rdev
->is_atom_bios
= false;
560 rdev
->usec_timeout
= RADEON_MAX_USEC_TIMEOUT
;
561 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
562 rdev
->gpu_lockup
= false;
563 rdev
->accel_working
= false;
564 /* mutex initialization are all done here so we
565 * can recall function without having locking issues */
566 mutex_init(&rdev
->cs_mutex
);
567 mutex_init(&rdev
->ib_pool
.mutex
);
568 mutex_init(&rdev
->cp
.mutex
);
569 if (rdev
->family
>= CHIP_R600
)
570 spin_lock_init(&rdev
->ih
.lock
);
571 mutex_init(&rdev
->gem
.mutex
);
572 rwlock_init(&rdev
->fence_drv
.lock
);
573 INIT_LIST_HEAD(&rdev
->gem
.objects
);
575 /* setup workqueue */
576 rdev
->wq
= create_workqueue("radeon");
577 if (rdev
->wq
== NULL
)
580 /* Set asic functions */
581 r
= radeon_asic_init(rdev
);
586 if (rdev
->flags
& RADEON_IS_AGP
&& radeon_agpmode
== -1) {
587 radeon_agp_disable(rdev
);
590 /* set DMA mask + need_dma32 flags.
591 * PCIE - can handle 40-bits.
592 * IGP - can handle 40-bits (in theory)
593 * AGP - generally dma32 is safest
596 rdev
->need_dma32
= false;
597 if (rdev
->flags
& RADEON_IS_AGP
)
598 rdev
->need_dma32
= true;
599 if (rdev
->flags
& RADEON_IS_PCI
)
600 rdev
->need_dma32
= true;
602 dma_bits
= rdev
->need_dma32
? 32 : 40;
603 r
= pci_set_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
605 printk(KERN_WARNING
"radeon: No suitable DMA available.\n");
608 /* Registers mapping */
609 /* TODO: block userspace mapping of io register */
610 rdev
->rmmio_base
= drm_get_resource_start(rdev
->ddev
, 2);
611 rdev
->rmmio_size
= drm_get_resource_len(rdev
->ddev
, 2);
612 rdev
->rmmio
= ioremap(rdev
->rmmio_base
, rdev
->rmmio_size
);
613 if (rdev
->rmmio
== NULL
) {
616 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev
->rmmio_base
);
617 DRM_INFO("register mmio size: %u\n", (unsigned)rdev
->rmmio_size
);
619 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
620 /* this will fail for cards that aren't VGA class devices, just
622 vga_client_register(rdev
->pdev
, rdev
, NULL
, radeon_vga_set_decode
);
624 r
= radeon_init(rdev
);
628 if (rdev
->flags
& RADEON_IS_AGP
&& !rdev
->accel_working
) {
629 /* Acceleration not working on AGP card try again
630 * with fallback to PCI or PCIE GART
632 radeon_gpu_reset(rdev
);
634 radeon_agp_disable(rdev
);
635 r
= radeon_init(rdev
);
639 if (radeon_testing
) {
640 radeon_test_moves(rdev
);
642 if (radeon_benchmarking
) {
643 radeon_benchmark(rdev
);
648 void radeon_device_fini(struct radeon_device
*rdev
)
650 DRM_INFO("radeon: finishing device.\n");
651 rdev
->shutdown
= true;
653 destroy_workqueue(rdev
->wq
);
654 vga_client_register(rdev
->pdev
, NULL
, NULL
, NULL
);
655 iounmap(rdev
->rmmio
);
663 int radeon_suspend_kms(struct drm_device
*dev
, pm_message_t state
)
665 struct radeon_device
*rdev
= dev
->dev_private
;
666 struct drm_crtc
*crtc
;
669 if (dev
== NULL
|| rdev
== NULL
) {
672 if (state
.event
== PM_EVENT_PRETHAW
) {
675 /* unpin the front buffers */
676 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
677 struct radeon_framebuffer
*rfb
= to_radeon_framebuffer(crtc
->fb
);
678 struct radeon_bo
*robj
;
680 if (rfb
== NULL
|| rfb
->obj
== NULL
) {
683 robj
= rfb
->obj
->driver_private
;
684 if (robj
!= rdev
->fbdev_rbo
) {
685 r
= radeon_bo_reserve(robj
, false);
686 if (unlikely(r
== 0)) {
687 radeon_bo_unpin(robj
);
688 radeon_bo_unreserve(robj
);
692 /* evict vram memory */
693 radeon_bo_evict_vram(rdev
);
694 /* wait for gpu to finish processing current batch */
695 radeon_fence_wait_last(rdev
);
697 radeon_save_bios_scratch_regs(rdev
);
699 radeon_suspend(rdev
);
700 radeon_hpd_fini(rdev
);
701 /* evict remaining vram memory */
702 radeon_bo_evict_vram(rdev
);
704 pci_save_state(dev
->pdev
);
705 if (state
.event
== PM_EVENT_SUSPEND
) {
706 /* Shut down the device */
707 pci_disable_device(dev
->pdev
);
708 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
710 acquire_console_sem();
711 fb_set_suspend(rdev
->fbdev_info
, 1);
712 release_console_sem();
716 int radeon_resume_kms(struct drm_device
*dev
)
718 struct radeon_device
*rdev
= dev
->dev_private
;
720 acquire_console_sem();
721 pci_set_power_state(dev
->pdev
, PCI_D0
);
722 pci_restore_state(dev
->pdev
);
723 if (pci_enable_device(dev
->pdev
)) {
724 release_console_sem();
727 pci_set_master(dev
->pdev
);
728 /* resume AGP if in use */
729 radeon_agp_resume(rdev
);
731 radeon_restore_bios_scratch_regs(rdev
);
732 fb_set_suspend(rdev
->fbdev_info
, 0);
733 release_console_sem();
735 /* reset hpd state */
736 radeon_hpd_init(rdev
);
737 /* blat the mode back in */
738 drm_helper_resume_force_mode(dev
);
746 struct radeon_debugfs
{
747 struct drm_info_list
*files
;
750 static struct radeon_debugfs _radeon_debugfs
[RADEON_DEBUGFS_MAX_NUM_FILES
];
751 static unsigned _radeon_debugfs_count
= 0;
753 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
754 struct drm_info_list
*files
,
759 for (i
= 0; i
< _radeon_debugfs_count
; i
++) {
760 if (_radeon_debugfs
[i
].files
== files
) {
761 /* Already registered */
765 if ((_radeon_debugfs_count
+ nfiles
) > RADEON_DEBUGFS_MAX_NUM_FILES
) {
766 DRM_ERROR("Reached maximum number of debugfs files.\n");
767 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
770 _radeon_debugfs
[_radeon_debugfs_count
].files
= files
;
771 _radeon_debugfs
[_radeon_debugfs_count
].num_files
= nfiles
;
772 _radeon_debugfs_count
++;
773 #if defined(CONFIG_DEBUG_FS)
774 drm_debugfs_create_files(files
, nfiles
,
775 rdev
->ddev
->control
->debugfs_root
,
776 rdev
->ddev
->control
);
777 drm_debugfs_create_files(files
, nfiles
,
778 rdev
->ddev
->primary
->debugfs_root
,
779 rdev
->ddev
->primary
);
784 #if defined(CONFIG_DEBUG_FS)
785 int radeon_debugfs_init(struct drm_minor
*minor
)
790 void radeon_debugfs_cleanup(struct drm_minor
*minor
)
794 for (i
= 0; i
< _radeon_debugfs_count
; i
++) {
795 drm_debugfs_remove_files(_radeon_debugfs
[i
].files
,
796 _radeon_debugfs
[i
].num_files
, minor
);