arch/arm/mach-at91/board-dt.c

   1 /*
   2  *  Setup code for AT91SAM Evaluation Kits with Device Tree support
   3  *
   4  *  Covers: * AT91SAM9G45-EKES  board
   5  *          * AT91SAM9M10-EKES  board
   6  *          * AT91SAM9M10G45-EK board
   7  *
   8  *  Copyright (C) 2011 Atmel,
   9  *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  10  *
  11  * Licensed under GPLv2 or later.
  12  */
  13
  14 #include <linux/types.h>
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/gpio.h>
  18 #include <linux/irqdomain.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_platform.h>
  21
  22 #include <mach/hardware.h>
  23 #include <mach/board.h>
  24 #include <mach/system_rev.h>
  25 #include <mach/at91sam9_smc.h>
  26
  27 #include <asm/setup.h>
  28 #include <asm/irq.h>
  29 #include <asm/mach/arch.h>
  30 #include <asm/mach/map.h>
  31 #include <asm/mach/irq.h>
  32
  33 #include "sam9_smc.h"
  34 #include "generic.h"
  35
  36
  37 static void __init ek_init_early(void)
  38 {
  39         /* Initialize processor: 12.000 MHz crystal */
  40         at91_initialize(12000000);
  41
  42         /* DGBU on ttyS0. (Rx & Tx only) */
  43         at91_register_uart(0, 0, 0);
  44
  45         /* set serial console to ttyS0 (ie, DBGU) */
  46         at91_set_serial_console(0);
  47 }
  48
  49 /* det_pin is not connected */
  50 static struct atmel_nand_data __initdata ek_nand_data = {
  51         .ale            = 21,
  52         .cle            = 22,
  53         .rdy_pin        = AT91_PIN_PC8,
  54         .enable_pin     = AT91_PIN_PC14,
  55 };
  56
  57 static struct sam9_smc_config __initdata ek_nand_smc_config = {
  58         .ncs_read_setup         = 0,
  59         .nrd_setup              = 2,
  60         .ncs_write_setup        = 0,
  61         .nwe_setup              = 2,
  62
  63         .ncs_read_pulse         = 4,
  64         .nrd_pulse              = 4,
  65         .ncs_write_pulse        = 4,
  66         .nwe_pulse              = 4,
  67
  68         .read_cycle             = 7,
  69         .write_cycle            = 7,
  70
  71         .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
  72         .tdf_cycles             = 3,
  73 };
  74
  75 static void __init ek_add_device_nand(void)
  76 {
  77         ek_nand_data.bus_width_16 = board_have_nand_16bit();
  78         /* setup bus-width (8 or 16) */
  79         if (ek_nand_data.bus_width_16)
  80                 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
  81         else
  82                 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
  83
  84         /* configure chip-select 3 (NAND) */
  85         sam9_smc_configure(3, &ek_nand_smc_config);
  86
  87         at91_add_device_nand(&ek_nand_data);
  88 }
  89
  90 static const struct of_device_id aic_of_match[] __initconst = {
  91         { .compatible = "atmel,at91rm9200-aic", },
  92         {},
  93 };
  94
  95 static void __init at91_dt_init_irq(void)
  96 {
  97         irq_domain_generate_simple(aic_of_match, 0xfffff000, 0);
  98         at91_init_irq_default();
  99 }
 100
 101 static void __init at91_dt_device_init(void)
 102 {
 103         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 104
 105         /* NAND */
 106         ek_add_device_nand();
 107 }
 108
 109 static const char *at91_dt_board_compat[] __initdata = {
 110         "atmel,at91sam9m10g45ek",
 111         NULL
 112 };
 113
 114 DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
 115         /* Maintainer: Atmel */
 116         .timer          = &at91sam926x_timer,
 117         .map_io         = at91_map_io,
 118         .init_early     = ek_init_early,
 119         .init_irq       = at91_dt_init_irq,
 120         .init_machine   = at91_dt_device_init,
 121         .dt_compat      = at91_dt_board_compat,
 122 MACHINE_END