arch/powerpc/platforms/8xx/mpc885ads_setup.c

   1 /*
   2  * Platform setup for the Freescale mpc885ads board
   3  *
   4  * Vitaly Bordug <vbordug@ru.mvista.com>
   5  *
   6  * Copyright 2005 MontaVista Software Inc.
   7  *
   8  * Heavily modified by Scott Wood <scottwood@freescale.com>
   9  * Copyright 2007 Freescale Semiconductor, Inc.
  10  *
  11  * This file is licensed under the terms of the GNU General Public License
  12  * version 2. This program is licensed "as is" without any warranty of any
  13  * kind, whether express or implied.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/param.h>
  19 #include <linux/string.h>
  20 #include <linux/ioport.h>
  21 #include <linux/device.h>
  22 #include <linux/delay.h>
  23
  24 #include <linux/fs_enet_pd.h>
  25 #include <linux/fs_uart_pd.h>
  26 #include <linux/fsl_devices.h>
  27 #include <linux/mii.h>
  28 #include <linux/of_platform.h>
  29
  30 #include <asm/delay.h>
  31 #include <asm/io.h>
  32 #include <asm/machdep.h>
  33 #include <asm/page.h>
  34 #include <asm/processor.h>
  35 #include <asm/system.h>
  36 #include <asm/time.h>
  37 #include <asm/mpc8xx.h>
  38 #include <asm/8xx_immap.h>
  39 #include <asm/commproc.h>
  40 #include <asm/fs_pd.h>
  41 #include <asm/udbg.h>
  42
  43 #include "mpc8xx.h"
  44
  45 static u32 __iomem *bcsr, *bcsr5;
  46
  47 #ifdef CONFIG_PCMCIA_M8XX
  48 static void pcmcia_hw_setup(int slot, int enable)
  49 {
  50         if (enable)
  51                 clrbits32(&bcsr[1], BCSR1_PCCEN);
  52         else
  53                 setbits32(&bcsr[1], BCSR1_PCCEN);
  54 }
  55
  56 static int pcmcia_set_voltage(int slot, int vcc, int vpp)
  57 {
  58         u32 reg = 0;
  59
  60         switch (vcc) {
  61         case 0:
  62                 break;
  63         case 33:
  64                 reg |= BCSR1_PCCVCC0;
  65                 break;
  66         case 50:
  67                 reg |= BCSR1_PCCVCC1;
  68                 break;
  69         default:
  70                 return 1;
  71         }
  72
  73         switch (vpp) {
  74         case 0:
  75                 break;
  76         case 33:
  77         case 50:
  78                 if (vcc == vpp)
  79                         reg |= BCSR1_PCCVPP1;
  80                 else
  81                         return 1;
  82                 break;
  83         case 120:
  84                 if ((vcc == 33) || (vcc == 50))
  85                         reg |= BCSR1_PCCVPP0;
  86                 else
  87                         return 1;
  88         default:
  89                 return 1;
  90         }
  91
  92         /* first, turn off all power */
  93         clrbits32(&bcsr[1], 0x00610000);
  94
  95         /* enable new powersettings */
  96         setbits32(&bcsr[1], reg);
  97
  98         return 0;
  99 }
 100 #endif
 101
 102 struct cpm_pin {
 103         int port, pin, flags;
 104 };
 105
 106 static struct cpm_pin mpc885ads_pins[] = {
 107         /* SMC1 */
 108         {CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
 109         {CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
 110
 111         /* SMC2 */
 112 #ifndef CONFIG_MPC8xx_SECOND_ETH_FEC2
 113         {CPM_PORTE, 21, CPM_PIN_INPUT}, /* RX */
 114         {CPM_PORTE, 20, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
 115 #endif
 116
 117         /* SCC3 */
 118         {CPM_PORTA, 9, CPM_PIN_INPUT}, /* RX */
 119         {CPM_PORTA, 8, CPM_PIN_INPUT}, /* TX */
 120         {CPM_PORTC, 4, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* RENA */
 121         {CPM_PORTC, 5, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* CLSN */
 122         {CPM_PORTE, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TENA */
 123         {CPM_PORTE, 17, CPM_PIN_INPUT}, /* CLK5 */
 124         {CPM_PORTE, 16, CPM_PIN_INPUT}, /* CLK6 */
 125
 126         /* MII1 */
 127         {CPM_PORTA, 0, CPM_PIN_INPUT},
 128         {CPM_PORTA, 1, CPM_PIN_INPUT},
 129         {CPM_PORTA, 2, CPM_PIN_INPUT},
 130         {CPM_PORTA, 3, CPM_PIN_INPUT},
 131         {CPM_PORTA, 4, CPM_PIN_OUTPUT},
 132         {CPM_PORTA, 10, CPM_PIN_OUTPUT},
 133         {CPM_PORTA, 11, CPM_PIN_OUTPUT},
 134         {CPM_PORTB, 19, CPM_PIN_INPUT},
 135         {CPM_PORTB, 31, CPM_PIN_INPUT},
 136         {CPM_PORTC, 12, CPM_PIN_INPUT},
 137         {CPM_PORTC, 13, CPM_PIN_INPUT},
 138         {CPM_PORTE, 30, CPM_PIN_OUTPUT},
 139         {CPM_PORTE, 31, CPM_PIN_OUTPUT},
 140
 141         /* MII2 */
 142 #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
 143         {CPM_PORTE, 14, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 144         {CPM_PORTE, 15, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 145         {CPM_PORTE, 16, CPM_PIN_OUTPUT},
 146         {CPM_PORTE, 17, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 147         {CPM_PORTE, 18, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 148         {CPM_PORTE, 19, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 149         {CPM_PORTE, 20, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 150         {CPM_PORTE, 21, CPM_PIN_OUTPUT},
 151         {CPM_PORTE, 22, CPM_PIN_OUTPUT},
 152         {CPM_PORTE, 23, CPM_PIN_OUTPUT},
 153         {CPM_PORTE, 24, CPM_PIN_OUTPUT},
 154         {CPM_PORTE, 25, CPM_PIN_OUTPUT},
 155         {CPM_PORTE, 26, CPM_PIN_OUTPUT},
 156         {CPM_PORTE, 27, CPM_PIN_OUTPUT},
 157         {CPM_PORTE, 28, CPM_PIN_OUTPUT},
 158         {CPM_PORTE, 29, CPM_PIN_OUTPUT},
 159 #endif
 160 };
 161
 162 static void __init init_ioports(void)
 163 {
 164         int i;
 165
 166         for (i = 0; i < ARRAY_SIZE(mpc885ads_pins); i++) {
 167                 struct cpm_pin *pin = &mpc885ads_pins[i];
 168                 cpm1_set_pin(pin->port, pin->pin, pin->flags);
 169         }
 170
 171         cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
 172         cpm1_clk_setup(CPM_CLK_SMC2, CPM_BRG2, CPM_CLK_RTX);
 173         cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK5, CPM_CLK_TX);
 174         cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK6, CPM_CLK_RX);
 175
 176         /* Set FEC1 and FEC2 to MII mode */
 177         clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
 178 }
 179
 180 static void __init mpc885ads_setup_arch(void)
 181 {
 182         struct device_node *np;
 183
 184         cpm_reset();
 185         init_ioports();
 186
 187         np = of_find_compatible_node(NULL, NULL, "fsl,mpc885ads-bcsr");
 188         if (!np) {
 189                 printk(KERN_CRIT "Could not find fsl,mpc885ads-bcsr node\n");
 190                 return;
 191         }
 192
 193         bcsr = of_iomap(np, 0);
 194         bcsr5 = of_iomap(np, 1);
 195         of_node_put(np);
 196
 197         if (!bcsr || !bcsr5) {
 198                 printk(KERN_CRIT "Could not remap BCSR\n");
 199                 return;
 200         }
 201
 202         clrbits32(&bcsr[1], BCSR1_RS232EN_1);
 203 #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
 204         setbits32(&bcsr[1], BCSR1_RS232EN_2);
 205 #else
 206         clrbits32(&bcsr[1], BCSR1_RS232EN_2);
 207 #endif
 208
 209         clrbits32(bcsr5, BCSR5_MII1_EN);
 210         setbits32(bcsr5, BCSR5_MII1_RST);
 211         udelay(1000);
 212         clrbits32(bcsr5, BCSR5_MII1_RST);
 213
 214 #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
 215         clrbits32(bcsr5, BCSR5_MII2_EN);
 216         setbits32(bcsr5, BCSR5_MII2_RST);
 217         udelay(1000);
 218         clrbits32(bcsr5, BCSR5_MII2_RST);
 219 #else
 220         setbits32(bcsr5, BCSR5_MII2_EN);
 221 #endif
 222
 223 #ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
 224         clrbits32(&bcsr[4], BCSR4_ETH10_RST);
 225         udelay(1000);
 226         setbits32(&bcsr[4], BCSR4_ETH10_RST);
 227
 228         setbits32(&bcsr[1], BCSR1_ETHEN);
 229
 230         np = of_find_node_by_path("/soc@ff000000/cpm@9c0/serial@a80");
 231 #else
 232         np = of_find_node_by_path("/soc@ff000000/cpm@9c0/ethernet@a40");
 233 #endif
 234
 235         /* The SCC3 enet registers overlap the SMC1 registers, so
 236          * one of the two must be removed from the device tree.
 237          */
 238
 239         if (np) {
 240                 of_detach_node(np);
 241                 of_node_put(np);
 242         }
 243
 244 #ifdef CONFIG_PCMCIA_M8XX
 245         /* Set up board specific hook-ups.*/
 246         m8xx_pcmcia_ops.hw_ctrl = pcmcia_hw_setup;
 247         m8xx_pcmcia_ops.voltage_set = pcmcia_set_voltage;
 248 #endif
 249 }
 250
 251 static int __init mpc885ads_probe(void)
 252 {
 253         unsigned long root = of_get_flat_dt_root();
 254         return of_flat_dt_is_compatible(root, "fsl,mpc885ads");
 255 }
 256
 257 static struct of_device_id __initdata of_bus_ids[] = {
 258         { .name = "soc", },
 259         { .name = "cpm", },
 260         { .name = "localbus", },
 261         {},
 262 };
 263
 264 static int __init declare_of_platform_devices(void)
 265 {
 266         /* Publish the QE devices */
 267         of_platform_bus_probe(NULL, of_bus_ids, NULL);
 268
 269         return 0;
 270 }
 271 machine_device_initcall(mpc885_ads, declare_of_platform_devices);
 272
 273 define_machine(mpc885_ads) {
 274         .name                   = "Freescale MPC885 ADS",
 275         .probe                  = mpc885ads_probe,
 276         .setup_arch             = mpc885ads_setup_arch,
 277         .init_IRQ               = mpc8xx_pics_init,
 278         .get_irq                = mpc8xx_get_irq,
 279         .restart                = mpc8xx_restart,
 280         .calibrate_decr         = mpc8xx_calibrate_decr,
 281         .set_rtc_time           = mpc8xx_set_rtc_time,
 282         .get_rtc_time           = mpc8xx_get_rtc_time,
 283         .progress               = udbg_progress,
 284 };