drivers/usb/dwc3/gadget.h

   1 /**
   2  * gadget.h - DesignWare USB3 DRD Gadget Header
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #ifndef __DRIVERS_USB_DWC3_GADGET_H
  40 #define __DRIVERS_USB_DWC3_GADGET_H
  41
  42 #include <linux/list.h>
  43 #include <linux/usb/gadget.h>
  44 #include "io.h"
  45
  46 struct dwc3;
  47 #define to_dwc3_ep(ep)          (container_of(ep, struct dwc3_ep, endpoint))
  48 #define gadget_to_dwc(g)        (container_of(g, struct dwc3, gadget))
  49
  50 /**
  51  * struct dwc3_gadget_ep_depcfg_param1 - DEPCMDPAR0 for DEPCFG command
  52  * @interrupt_number: self-explanatory
  53  * @reserved7_5: set to zero
  54  * @xfer_complete_enable: event generated when transfer completed
  55  * @xfer_in_progress_enable: event generated when transfer in progress
  56  * @xfer_not_ready_enable: event generated when transfer not read
  57  * @fifo_error_enable: generates events when FIFO Underrun (IN eps)
  58  *      or FIFO Overrun (OUT) eps
  59  * @reserved_12: set to zero
  60  * @stream_event_enable: event generated on stream
  61  * @reserved14_15: set to zero
  62  * @binterval_m1: bInterval minus 1
  63  * @stream_capable: this EP is capable of handling streams
  64  * @ep_number: self-explanatory
  65  * @bulk_based: Set to ‘1’ if this isochronous endpoint represents a bulk
  66  *      data stream that ignores the relationship of bus time to the
  67  *      intervals programmed in TRBs.
  68  * @fifo_based: Set to ‘1’ if this isochronous endpoint represents a
  69  *      FIFO-based data stream where TRBs have fixed values and are never
  70  *      written back by the core.
  71  */
  72 struct dwc3_gadget_ep_depcfg_param1 {
  73         u32     interrupt_number:5;
  74         u32     reserved7_5:3;          /* set to zero */
  75         u32     xfer_complete_enable:1;
  76         u32     xfer_in_progress_enable:1;
  77         u32     xfer_not_ready_enable:1;
  78         u32     fifo_error_enable:1;    /* IN-underrun, OUT-overrun */
  79         u32     reserved12:1;           /* set to zero */
  80         u32     stream_event_enable:1;
  81         u32     reserved14_15:2;
  82         u32     binterval_m1:8;         /* bInterval minus 1 */
  83         u32     stream_capable:1;
  84         u32     ep_number:5;
  85         u32     bulk_based:1;
  86         u32     fifo_based:1;
  87 } __packed;
  88
  89 /**
  90  * struct dwc3_gadget_ep_depcfg_param0 - Parameter 0 for DEPCFG
  91  * @reserved0: set to zero
  92  * @ep_type: Endpoint Type (control, bulk, iso, interrupt)
  93  * @max_packet_size: max packet size in bytes
  94  * @reserved16_14: set to zero
  95  * @fifo_number: self-explanatory
  96  * @burst_size: burst size minus 1
  97  * @data_sequence_number: Must be 0 when an endpoint is initially configured
  98  *      May be non-zero when an endpoint is configured after a power transition
  99  *      that requires a save/restore.
 100  * @ignore_sequence_number: Set to ‘1’ to avoid resetting the sequence
 101  *      number. This setting is used by software to modify the DEPEVTEN
 102  *      event enable bits without modifying other endpoint settings.
 103  */
 104 struct dwc3_gadget_ep_depcfg_param0 {
 105         u32     reserved0:1;
 106         u32     ep_type:2;
 107         u32     max_packet_size:11;
 108         u32     reserved16_14:3;
 109         u32     fifo_number:5;
 110         u32     burst_size:4;
 111         u32     data_sequence_number:5;
 112         u32     ignore_sequence_number:1;
 113 } __packed;
 114
 115 /**
 116  * struct dwc3_gadget_ep_depxfercfg_param0 - Parameter 0 of DEPXFERCFG
 117  * @number_xfer_resources: Defines the number of Transfer Resources allocated
 118  *      to this endpoint.  This field must be set to 1.
 119  * @reserved16_31: set to zero;
 120  */
 121 struct dwc3_gadget_ep_depxfercfg_param0 {
 122         u32             number_xfer_resources:16;
 123         u32             reserved16_31:16;
 124 } __packed;
 125
 126 /**
 127  * struct dwc3_gadget_ep_depstrtxfer_param1 - Parameter 1 of DEPSTRTXFER
 128  * @transfer_desc_addr_low: Indicates the lower 32 bits of the external
 129  *      memory's start address for the transfer descriptor. Because TRBs
 130  *      must be aligned to a 16-byte boundary, the lower 4 bits of this
 131  *      address must be 0.
 132  */
 133 struct dwc3_gadget_ep_depstrtxfer_param1 {
 134         u32             transfer_desc_addr_low;
 135 } __packed;
 136
 137 /**
 138  * struct dwc3_gadget_ep_depstrtxfer_param1 - Parameter 1 of DEPSTRTXFER
 139  * @transfer_desc_addr_high: Indicates the higher 32 bits of the external
 140  *      memory’s start address for the transfer descriptor.
 141  */
 142 struct dwc3_gadget_ep_depstrtxfer_param0 {
 143         u32             transfer_desc_addr_high;
 144 } __packed;
 145
 146 struct dwc3_gadget_ep_cmd_params {
 147         union {
 148                 u32     raw;
 149         } param2;
 150
 151         union {
 152                 u32     raw;
 153                 struct dwc3_gadget_ep_depcfg_param1 depcfg;
 154                 struct dwc3_gadget_ep_depstrtxfer_param1 depstrtxfer;
 155         } param1;
 156
 157         union {
 158                 u32     raw;
 159                 struct dwc3_gadget_ep_depcfg_param0 depcfg;
 160                 struct dwc3_gadget_ep_depxfercfg_param0 depxfercfg;
 161                 struct dwc3_gadget_ep_depstrtxfer_param0 depstrtxfer;
 162         } param0;
 163 } __packed;
 164
 165 /* -------------------------------------------------------------------------- */
 166
 167 struct dwc3_request {
 168         struct usb_request      request;
 169         struct list_head        list;
 170         struct dwc3_ep          *dep;
 171
 172         u8                      epnum;
 173         struct dwc3_trb_hw      *trb;
 174         dma_addr_t              trb_dma;
 175
 176         unsigned                direction:1;
 177         unsigned                mapped:1;
 178         unsigned                queued:1;
 179 };
 180 #define to_dwc3_request(r)      (container_of(r, struct dwc3_request, request))
 181
 182 static inline struct dwc3_request *next_request(struct list_head *list)
 183 {
 184         if (list_empty(list))
 185                 return NULL;
 186
 187         return list_first_entry(list, struct dwc3_request, list);
 188 }
 189
 190 static inline void dwc3_gadget_move_request_queued(struct dwc3_request *req)
 191 {
 192         struct dwc3_ep          *dep = req->dep;
 193
 194         req->queued = true;
 195         list_move_tail(&req->list, &dep->req_queued);
 196 }
 197
 198 #if defined(CONFIG_USB_GADGET_DWC3) || defined(CONFIG_USB_GADGET_DWC3_MODULE)
 199 int dwc3_gadget_init(struct dwc3 *dwc);
 200 void dwc3_gadget_exit(struct dwc3 *dwc);
 201 #else
 202 static inline int dwc3_gadget_init(struct dwc3 *dwc) { return 0; }
 203 static inline void dwc3_gadget_exit(struct dwc3 *dwc) { }
 204 static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 205                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 206 {
 207         return 0;
 208 }
 209 #endif
 210
 211 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 212                 int status);
 213
 214 void dwc3_ep0_interrupt(struct dwc3 *dwc, const struct dwc3_event_depevt *event);
 215 void dwc3_ep0_out_start(struct dwc3 *dwc);
 216 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 217                 gfp_t gfp_flags);
 218 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value);
 219 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 220                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
 221 void dwc3_map_buffer_to_dma(struct dwc3_request *req);
 222 void dwc3_unmap_buffer_from_dma(struct dwc3_request *req);
 223
 224 /**
 225  * dwc3_gadget_ep_get_transfer_index - Gets transfer index from HW
 226  * @dwc: DesignWare USB3 Pointer
 227  * @number: DWC endpoint number
 228  *
 229  * Caller should take care of locking
 230  */
 231 static inline u32 dwc3_gadget_ep_get_transfer_index(struct dwc3 *dwc, u8 number)
 232 {
 233         u32                     res_id;
 234
 235         res_id = dwc3_readl(dwc->regs, DWC3_DEPCMD(number));
 236
 237         return DWC3_DEPCMD_GET_RSC_IDX(res_id);
 238 }
 239
 240 /**
 241  * dwc3_gadget_event_string - returns event name
 242  * @event: the event code
 243  */
 244 static inline const char *dwc3_gadget_event_string(u8 event)
 245 {
 246         switch (event) {
 247         case DWC3_DEVICE_EVENT_DISCONNECT:
 248                 return "Disconnect";
 249         case DWC3_DEVICE_EVENT_RESET:
 250                 return "Reset";
 251         case DWC3_DEVICE_EVENT_CONNECT_DONE:
 252                 return "Connection Done";
 253         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
 254                 return "Link Status Change";
 255         case DWC3_DEVICE_EVENT_WAKEUP:
 256                 return "WakeUp";
 257         case DWC3_DEVICE_EVENT_EOPF:
 258                 return "End-Of-Frame";
 259         case DWC3_DEVICE_EVENT_SOF:
 260                 return "Start-Of-Frame";
 261         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
 262                 return "Erratic Error";
 263         case DWC3_DEVICE_EVENT_CMD_CMPL:
 264                 return "Command Complete";
 265         case DWC3_DEVICE_EVENT_OVERFLOW:
 266                 return "Overflow";
 267         }
 268
 269         return "UNKNOWN";
 270 }
 271
 272 /**
 273  * dwc3_ep_event_string - returns event name
 274  * @event: then event code
 275  */
 276 static inline const char *dwc3_ep_event_string(u8 event)
 277 {
 278         switch (event) {
 279         case DWC3_DEPEVT_XFERCOMPLETE:
 280                 return "Transfer Complete";
 281         case DWC3_DEPEVT_XFERINPROGRESS:
 282                 return "Transfer In-Progress";
 283         case DWC3_DEPEVT_XFERNOTREADY:
 284                 return "Transfer Not Ready";
 285         case DWC3_DEPEVT_RXTXFIFOEVT:
 286                 return "FIFO";
 287         case DWC3_DEPEVT_STREAMEVT:
 288                 return "Stream";
 289         case DWC3_DEPEVT_EPCMDCMPLT:
 290                 return "Endpoint Command Complete";
 291         }
 292
 293         return "UNKNOWN";
 294 }
 295
 296 #endif /* __DRIVERS_USB_DWC3_GADGET_H */