2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/kernel.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/interrupt.h>
46 #include <linux/list.h>
47 #include <linux/dma-mapping.h>
49 #include <linux/usb/ch9.h>
50 #include <linux/usb/gadget.h>
56 static void dwc3_ep0_inspect_setup(struct dwc3
*dwc
,
57 const struct dwc3_event_depevt
*event
);
59 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state
)
68 case EP0_STATUS_PHASE
:
69 return "Status Phase";
75 static int dwc3_ep0_start_trans(struct dwc3
*dwc
, u8 epnum
, dma_addr_t buf_dma
,
78 struct dwc3_gadget_ep_cmd_params params
;
79 struct dwc3_trb_hw
*trb_hw
;
85 dep
= dwc
->eps
[epnum
];
86 if (dep
->flags
& DWC3_EP_BUSY
) {
87 dev_vdbg(dwc
->dev
, "%s: still busy\n", dep
->name
);
91 trb_hw
= dwc
->ep0_trb
;
92 memset(&trb
, 0, sizeof(trb
));
103 dwc3_trb_to_hw(&trb
, trb_hw
);
105 memset(¶ms
, 0, sizeof(params
));
106 params
.param0
.depstrtxfer
.transfer_desc_addr_high
=
107 upper_32_bits(dwc
->ep0_trb_addr
);
108 params
.param1
.depstrtxfer
.transfer_desc_addr_low
=
109 lower_32_bits(dwc
->ep0_trb_addr
);
111 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
112 DWC3_DEPCMD_STARTTRANSFER
, ¶ms
);
114 dev_dbg(dwc
->dev
, "failed to send STARTTRANSFER command\n");
118 dep
->flags
|= DWC3_EP_BUSY
;
119 dep
->res_trans_idx
= dwc3_gadget_ep_get_transfer_index(dwc
,
122 dwc
->ep0_next_event
= DWC3_EP0_COMPLETE
;
127 static int __dwc3_gadget_ep0_queue(struct dwc3_ep
*dep
,
128 struct dwc3_request
*req
)
132 req
->request
.actual
= 0;
133 req
->request
.status
= -EINPROGRESS
;
134 req
->epnum
= dep
->number
;
136 list_add_tail(&req
->list
, &dep
->request_list
);
139 * Gadget driver might not be quick enough to queue a request
140 * before we get a Transfer Not Ready event on this endpoint.
142 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
143 * flag is set, it's telling us that as soon as Gadget queues the
144 * required request, we should kick the transfer here because the
145 * IRQ we were waiting for is long gone.
147 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
148 struct dwc3
*dwc
= dep
->dwc
;
152 direction
= !!(dep
->flags
& DWC3_EP0_DIR_IN
);
154 if (dwc
->ep0state
== EP0_STATUS_PHASE
) {
155 type
= dwc
->three_stage_setup
156 ? DWC3_TRBCTL_CONTROL_STATUS3
157 : DWC3_TRBCTL_CONTROL_STATUS2
;
158 } else if (dwc
->ep0state
== EP0_DATA_PHASE
) {
159 type
= DWC3_TRBCTL_CONTROL_DATA
;
161 /* should never happen */
166 ret
= dwc3_ep0_start_trans(dwc
, direction
,
167 req
->request
.dma
, req
->request
.length
, type
);
168 dep
->flags
&= ~(DWC3_EP_PENDING_REQUEST
|
175 int dwc3_gadget_ep0_queue(struct usb_ep
*ep
, struct usb_request
*request
,
178 struct dwc3_request
*req
= to_dwc3_request(request
);
179 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
180 struct dwc3
*dwc
= dep
->dwc
;
186 spin_lock_irqsave(&dwc
->lock
, flags
);
188 dev_dbg(dwc
->dev
, "trying to queue request %p to disabled %s\n",
194 /* we share one TRB for ep0/1 */
195 if (!list_empty(&dwc
->eps
[0]->request_list
) ||
196 !list_empty(&dwc
->eps
[1]->request_list
) ||
197 dwc
->ep0_status_pending
) {
202 dev_vdbg(dwc
->dev
, "queueing request %p to %s length %d, state '%s'\n",
203 request
, dep
->name
, request
->length
,
204 dwc3_ep0_state_string(dwc
->ep0state
));
206 ret
= __dwc3_gadget_ep0_queue(dep
, req
);
209 spin_unlock_irqrestore(&dwc
->lock
, flags
);
214 static void dwc3_ep0_stall_and_restart(struct dwc3
*dwc
)
216 struct dwc3_ep
*dep
= dwc
->eps
[0];
218 /* stall is always issued on EP0 */
219 __dwc3_gadget_ep_set_halt(dwc
->eps
[0], 1);
220 dwc
->eps
[0]->flags
= DWC3_EP_ENABLED
;
222 if (!list_empty(&dep
->request_list
)) {
223 struct dwc3_request
*req
;
225 req
= next_request(&dep
->request_list
);
226 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
229 dwc
->ep0state
= EP0_SETUP_PHASE
;
230 dwc3_ep0_out_start(dwc
);
233 void dwc3_ep0_out_start(struct dwc3
*dwc
)
237 ret
= dwc3_ep0_start_trans(dwc
, 0, dwc
->ctrl_req_addr
, 8,
238 DWC3_TRBCTL_CONTROL_SETUP
);
242 static struct dwc3_ep
*dwc3_wIndex_to_dep(struct dwc3
*dwc
, __le16 wIndex_le
)
245 u32 windex
= le16_to_cpu(wIndex_le
);
248 epnum
= (windex
& USB_ENDPOINT_NUMBER_MASK
) << 1;
249 if ((windex
& USB_ENDPOINT_DIR_MASK
) == USB_DIR_IN
)
252 dep
= dwc
->eps
[epnum
];
253 if (dep
->flags
& DWC3_EP_ENABLED
)
259 static void dwc3_ep0_send_status_response(struct dwc3
*dwc
)
261 dwc3_ep0_start_trans(dwc
, 1, dwc
->setup_buf_addr
,
262 dwc
->ep0_usb_req
.length
,
263 DWC3_TRBCTL_CONTROL_DATA
);
269 static int dwc3_ep0_handle_status(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
274 __le16
*response_pkt
;
276 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
278 case USB_RECIP_DEVICE
:
280 * We are self-powered. U1/U2/LTM will be set later
281 * once we handle this states. RemoteWakeup is 0 on SS
283 usb_status
|= dwc
->is_selfpowered
<< USB_DEVICE_SELF_POWERED
;
286 case USB_RECIP_INTERFACE
:
288 * Function Remote Wake Capable D0
289 * Function Remote Wakeup D1
293 case USB_RECIP_ENDPOINT
:
294 dep
= dwc3_wIndex_to_dep(dwc
, ctrl
->wIndex
);
298 if (dep
->flags
& DWC3_EP_STALL
)
299 usb_status
= 1 << USB_ENDPOINT_HALT
;
305 response_pkt
= (__le16
*) dwc
->setup_buf
;
306 *response_pkt
= cpu_to_le16(usb_status
);
307 dwc
->ep0_usb_req
.length
= sizeof(*response_pkt
);
308 dwc
->ep0_status_pending
= 1;
313 static int dwc3_ep0_handle_feature(struct dwc3
*dwc
,
314 struct usb_ctrlrequest
*ctrl
, int set
)
324 wValue
= le16_to_cpu(ctrl
->wValue
);
325 wIndex
= le16_to_cpu(ctrl
->wIndex
);
326 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
328 case USB_RECIP_DEVICE
:
331 * 9.4.1 says only only for SS, in AddressState only for
332 * default control pipe
335 case USB_DEVICE_U1_ENABLE
:
336 case USB_DEVICE_U2_ENABLE
:
337 case USB_DEVICE_LTM_ENABLE
:
338 if (dwc
->dev_state
!= DWC3_CONFIGURED_STATE
)
340 if (dwc
->speed
!= DWC3_DSTS_SUPERSPEED
)
344 /* XXX add U[12] & LTM */
346 case USB_DEVICE_REMOTE_WAKEUP
:
348 case USB_DEVICE_U1_ENABLE
:
350 case USB_DEVICE_U2_ENABLE
:
352 case USB_DEVICE_LTM_ENABLE
:
355 case USB_DEVICE_TEST_MODE
:
356 if ((wIndex
& 0xff) != 0)
362 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
363 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
376 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
383 case USB_RECIP_INTERFACE
:
385 case USB_INTRF_FUNC_SUSPEND
:
386 if (wIndex
& USB_INTRF_FUNC_SUSPEND_LP
)
387 /* XXX enable Low power suspend */
389 if (wIndex
& USB_INTRF_FUNC_SUSPEND_RW
)
390 /* XXX enable remote wakeup */
398 case USB_RECIP_ENDPOINT
:
400 case USB_ENDPOINT_HALT
:
402 dep
= dwc3_wIndex_to_dep(dwc
, ctrl
->wIndex
);
405 ret
= __dwc3_gadget_ep_set_halt(dep
, set
);
421 static int dwc3_ep0_set_address(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
426 addr
= le16_to_cpu(ctrl
->wValue
);
430 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
431 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
432 reg
|= DWC3_DCFG_DEVADDR(addr
);
433 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
436 dwc
->dev_state
= DWC3_ADDRESS_STATE
;
438 dwc
->dev_state
= DWC3_DEFAULT_STATE
;
443 static int dwc3_ep0_delegate_req(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
447 spin_unlock(&dwc
->lock
);
448 ret
= dwc
->gadget_driver
->setup(&dwc
->gadget
, ctrl
);
449 spin_lock(&dwc
->lock
);
453 static int dwc3_ep0_set_config(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
458 cfg
= le16_to_cpu(ctrl
->wValue
);
460 switch (dwc
->dev_state
) {
461 case DWC3_DEFAULT_STATE
:
465 case DWC3_ADDRESS_STATE
:
466 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
467 /* if the cfg matches and the cfg is non zero */
469 dwc
->dev_state
= DWC3_CONFIGURED_STATE
;
472 case DWC3_CONFIGURED_STATE
:
473 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
475 dwc
->dev_state
= DWC3_ADDRESS_STATE
;
481 static int dwc3_ep0_std_request(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
485 switch (ctrl
->bRequest
) {
486 case USB_REQ_GET_STATUS
:
487 dev_vdbg(dwc
->dev
, "USB_REQ_GET_STATUS\n");
488 ret
= dwc3_ep0_handle_status(dwc
, ctrl
);
490 case USB_REQ_CLEAR_FEATURE
:
491 dev_vdbg(dwc
->dev
, "USB_REQ_CLEAR_FEATURE\n");
492 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 0);
494 case USB_REQ_SET_FEATURE
:
495 dev_vdbg(dwc
->dev
, "USB_REQ_SET_FEATURE\n");
496 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 1);
498 case USB_REQ_SET_ADDRESS
:
499 dev_vdbg(dwc
->dev
, "USB_REQ_SET_ADDRESS\n");
500 ret
= dwc3_ep0_set_address(dwc
, ctrl
);
502 case USB_REQ_SET_CONFIGURATION
:
503 dev_vdbg(dwc
->dev
, "USB_REQ_SET_CONFIGURATION\n");
504 ret
= dwc3_ep0_set_config(dwc
, ctrl
);
507 dev_vdbg(dwc
->dev
, "Forwarding to gadget driver\n");
508 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
515 static void dwc3_ep0_inspect_setup(struct dwc3
*dwc
,
516 const struct dwc3_event_depevt
*event
)
518 struct usb_ctrlrequest
*ctrl
= dwc
->ctrl_req
;
522 if (!dwc
->gadget_driver
)
525 len
= le16_to_cpu(ctrl
->wLength
);
527 dwc
->three_stage_setup
= false;
528 dwc
->ep0_expect_in
= false;
529 dwc
->ep0_next_event
= DWC3_EP0_NRDY_STATUS
;
531 dwc
->three_stage_setup
= true;
532 dwc
->ep0_expect_in
= !!(ctrl
->bRequestType
& USB_DIR_IN
);
533 dwc
->ep0_next_event
= DWC3_EP0_NRDY_DATA
;
536 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
)
537 ret
= dwc3_ep0_std_request(dwc
, ctrl
);
539 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
545 dwc3_ep0_stall_and_restart(dwc
);
548 static void dwc3_ep0_complete_data(struct dwc3
*dwc
,
549 const struct dwc3_event_depevt
*event
)
551 struct dwc3_request
*r
= NULL
;
552 struct usb_request
*ur
;
558 epnum
= event
->endpoint_number
;
559 dep
= dwc
->eps
[epnum
];
561 dwc
->ep0_next_event
= DWC3_EP0_NRDY_STATUS
;
563 if (!dwc
->ep0_status_pending
) {
564 r
= next_request(&dwc
->eps
[0]->request_list
);
567 ur
= &dwc
->ep0_usb_req
;
568 dwc
->ep0_status_pending
= 0;
571 dwc3_trb_to_nat(dwc
->ep0_trb
, &trb
);
573 if (dwc
->ep0_bounced
) {
574 struct dwc3_ep
*ep0
= dwc
->eps
[0];
576 transferred
= min_t(u32
, ur
->length
,
577 ep0
->endpoint
.maxpacket
- trb
.length
);
578 memcpy(ur
->buf
, dwc
->ep0_bounce
, transferred
);
579 dwc
->ep0_bounced
= false;
581 transferred
= ur
->length
- trb
.length
;
582 ur
->actual
+= transferred
;
585 if ((epnum
& 1) && ur
->actual
< ur
->length
) {
586 /* for some reason we did not get everything out */
588 dwc3_ep0_stall_and_restart(dwc
);
591 * handle the case where we have to send a zero packet. This
592 * seems to be case when req.length > maxpacket. Could it be?
595 dwc3_gadget_giveback(dep
, r
, 0);
599 static void dwc3_ep0_complete_req(struct dwc3
*dwc
,
600 const struct dwc3_event_depevt
*event
)
602 struct dwc3_request
*r
;
607 if (!list_empty(&dep
->request_list
)) {
608 r
= next_request(&dep
->request_list
);
610 dwc3_gadget_giveback(dep
, r
, 0);
613 dwc
->ep0state
= EP0_SETUP_PHASE
;
614 dwc3_ep0_out_start(dwc
);
617 static void dwc3_ep0_xfer_complete(struct dwc3
*dwc
,
618 const struct dwc3_event_depevt
*event
)
620 struct dwc3_ep
*dep
= dwc
->eps
[event
->endpoint_number
];
622 dep
->flags
&= ~DWC3_EP_BUSY
;
624 switch (dwc
->ep0state
) {
625 case EP0_SETUP_PHASE
:
626 dev_vdbg(dwc
->dev
, "Inspecting Setup Bytes\n");
627 dwc3_ep0_inspect_setup(dwc
, event
);
631 dev_vdbg(dwc
->dev
, "Data Phase\n");
632 dwc3_ep0_complete_data(dwc
, event
);
635 case EP0_STATUS_PHASE
:
636 dev_vdbg(dwc
->dev
, "Status Phase\n");
637 dwc3_ep0_complete_req(dwc
, event
);
640 WARN(true, "UNKNOWN ep0state %d\n", dwc
->ep0state
);
644 static void dwc3_ep0_do_control_setup(struct dwc3
*dwc
,
645 const struct dwc3_event_depevt
*event
)
647 dwc
->ep0state
= EP0_SETUP_PHASE
;
648 dwc3_ep0_out_start(dwc
);
651 static void dwc3_ep0_do_control_data(struct dwc3
*dwc
,
652 const struct dwc3_event_depevt
*event
)
655 struct dwc3_request
*req
;
659 dwc
->ep0state
= EP0_DATA_PHASE
;
661 if (dwc
->ep0_status_pending
) {
662 dwc3_ep0_send_status_response(dwc
);
666 if (list_empty(&dep
->request_list
)) {
667 dev_vdbg(dwc
->dev
, "pending request for EP0 Data phase\n");
668 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
670 if (event
->endpoint_number
)
671 dep
->flags
|= DWC3_EP0_DIR_IN
;
675 req
= next_request(&dep
->request_list
);
676 req
->direction
= !!event
->endpoint_number
;
678 dwc
->ep0state
= EP0_DATA_PHASE
;
679 if (req
->request
.length
== 0) {
680 ret
= dwc3_ep0_start_trans(dwc
, event
->endpoint_number
,
681 dwc
->ctrl_req_addr
, 0,
682 DWC3_TRBCTL_CONTROL_DATA
);
683 } else if ((req
->request
.length
% dep
->endpoint
.maxpacket
)
684 && (event
->endpoint_number
== 0)) {
685 dwc3_map_buffer_to_dma(req
);
687 WARN_ON(req
->request
.length
> dep
->endpoint
.maxpacket
);
689 dwc
->ep0_bounced
= true;
692 * REVISIT in case request length is bigger than EP0
693 * wMaxPacketSize, we will need two chained TRBs to handle
696 ret
= dwc3_ep0_start_trans(dwc
, event
->endpoint_number
,
697 dwc
->ep0_bounce_addr
, dep
->endpoint
.maxpacket
,
698 DWC3_TRBCTL_CONTROL_DATA
);
700 dwc3_map_buffer_to_dma(req
);
702 ret
= dwc3_ep0_start_trans(dwc
, event
->endpoint_number
,
703 req
->request
.dma
, req
->request
.length
,
704 DWC3_TRBCTL_CONTROL_DATA
);
710 static void dwc3_ep0_do_control_status(struct dwc3
*dwc
,
711 const struct dwc3_event_depevt
*event
)
716 dwc
->ep0state
= EP0_STATUS_PHASE
;
718 type
= dwc
->three_stage_setup
? DWC3_TRBCTL_CONTROL_STATUS3
719 : DWC3_TRBCTL_CONTROL_STATUS2
;
721 ret
= dwc3_ep0_start_trans(dwc
, event
->endpoint_number
,
722 dwc
->ctrl_req_addr
, 0, type
);
727 static void dwc3_ep0_xfernotready(struct dwc3
*dwc
,
728 const struct dwc3_event_depevt
*event
)
730 switch (event
->status
) {
731 case DEPEVT_STATUS_CONTROL_SETUP
:
732 dev_vdbg(dwc
->dev
, "Control Setup\n");
733 dwc3_ep0_do_control_setup(dwc
, event
);
736 case DEPEVT_STATUS_CONTROL_DATA
:
737 dev_vdbg(dwc
->dev
, "Control Data\n");
739 if (dwc
->ep0_next_event
!= DWC3_EP0_NRDY_DATA
) {
740 dev_vdbg(dwc
->dev
, "Expected %d got %d\n",
744 dwc3_ep0_stall_and_restart(dwc
);
749 * One of the possible error cases is when Host _does_
750 * request for Data Phase, but it does so on the wrong
753 * Here, we already know ep0_next_event is DATA (see above),
754 * so we only need to check for direction.
756 if (dwc
->ep0_expect_in
!= event
->endpoint_number
) {
757 dev_vdbg(dwc
->dev
, "Wrong direction for Data phase\n");
758 dwc3_ep0_stall_and_restart(dwc
);
762 dwc3_ep0_do_control_data(dwc
, event
);
765 case DEPEVT_STATUS_CONTROL_STATUS
:
766 dev_vdbg(dwc
->dev
, "Control Status\n");
768 if (dwc
->ep0_next_event
!= DWC3_EP0_NRDY_STATUS
) {
769 dev_vdbg(dwc
->dev
, "Expected %d got %d\n",
771 DWC3_EP0_NRDY_STATUS
);
773 dwc3_ep0_stall_and_restart(dwc
);
776 dwc3_ep0_do_control_status(dwc
, event
);
780 void dwc3_ep0_interrupt(struct dwc3
*dwc
,
781 const const struct dwc3_event_depevt
*event
)
783 u8 epnum
= event
->endpoint_number
;
785 dev_dbg(dwc
->dev
, "%s while ep%d%s in state '%s'\n",
786 dwc3_ep_event_string(event
->endpoint_event
),
787 epnum
>> 1, (epnum
& 1) ? "in" : "out",
788 dwc3_ep0_state_string(dwc
->ep0state
));
790 switch (event
->endpoint_event
) {
791 case DWC3_DEPEVT_XFERCOMPLETE
:
792 dwc3_ep0_xfer_complete(dwc
, event
);
795 case DWC3_DEPEVT_XFERNOTREADY
:
796 dwc3_ep0_xfernotready(dwc
, event
);
799 case DWC3_DEPEVT_XFERINPROGRESS
:
800 case DWC3_DEPEVT_RXTXFIFOEVT
:
801 case DWC3_DEPEVT_STREAMEVT
:
802 case DWC3_DEPEVT_EPCMDCMPLT
: