arch/ia64/kernel/irq_ia64.c

   1 /*
   2  * linux/arch/ia64/kernel/irq_ia64.c
   3  *
   4  * Copyright (C) 1998-2001 Hewlett-Packard Co
   5  *      Stephane Eranian <eranian@hpl.hp.com>
   6  *      David Mosberger-Tang <davidm@hpl.hp.com>
   7  *
   8  *  6/10/99: Updated to bring in sync with x86 version to facilitate
   9  *           support for SMP and different interrupt controllers.
  10  *
  11  * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
  12  *                      PCI to vector allocation routine.
  13  * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
  14  *                                              Added CPU Hotplug handling for IPF.
  15  */
  16
  17 #include <linux/module.h>
  18
  19 #include <linux/jiffies.h>
  20 #include <linux/errno.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/ioport.h>
  24 #include <linux/kernel_stat.h>
  25 #include <linux/slab.h>
  26 #include <linux/ptrace.h>
  27 #include <linux/random.h>       /* for rand_initialize_irq() */
  28 #include <linux/signal.h>
  29 #include <linux/smp.h>
  30 #include <linux/threads.h>
  31 #include <linux/bitops.h>
  32 #include <linux/irq.h>
  33
  34 #include <asm/delay.h>
  35 #include <asm/intrinsics.h>
  36 #include <asm/io.h>
  37 #include <asm/hw_irq.h>
  38 #include <asm/machvec.h>
  39 #include <asm/pgtable.h>
  40 #include <asm/system.h>
  41 #include <asm/tlbflush.h>
  42
  43 #ifdef CONFIG_PERFMON
  44 # include <asm/perfmon.h>
  45 #endif
  46
  47 #define IRQ_DEBUG       0
  48
  49 #define IRQ_VECTOR_UNASSIGNED   (0)
  50
  51 #define IRQ_UNUSED              (0)
  52 #define IRQ_USED                (1)
  53 #define IRQ_RSVD                (2)
  54
  55 /* These can be overridden in platform_irq_init */
  56 int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
  57 int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;
  58
  59 /* default base addr of IPI table */
  60 void __iomem *ipi_base_addr = ((void __iomem *)
  61                                (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));
  62
  63 static cpumask_t vector_allocation_domain(int cpu);
  64
  65 /*
  66  * Legacy IRQ to IA-64 vector translation table.
  67  */
  68 __u8 isa_irq_to_vector_map[16] = {
  69         /* 8259 IRQ translation, first 16 entries */
  70         0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
  71         0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
  72 };
  73 EXPORT_SYMBOL(isa_irq_to_vector_map);
  74
  75 DEFINE_SPINLOCK(vector_lock);
  76
  77 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
  78         [0 ... NR_IRQS - 1] = {
  79                 .vector = IRQ_VECTOR_UNASSIGNED,
  80                 .domain = CPU_MASK_NONE
  81         }
  82 };
  83
  84 DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
  85         [0 ... IA64_NUM_VECTORS - 1] = IA64_SPURIOUS_INT_VECTOR
  86 };
  87
  88 static cpumask_t vector_table[IA64_MAX_DEVICE_VECTORS] = {
  89         [0 ... IA64_MAX_DEVICE_VECTORS - 1] = CPU_MASK_NONE
  90 };
  91
  92 static int irq_status[NR_IRQS] = {
  93         [0 ... NR_IRQS -1] = IRQ_UNUSED
  94 };
  95
  96 int check_irq_used(int irq)
  97 {
  98         if (irq_status[irq] == IRQ_USED)
  99                 return 1;
 100
 101         return -1;
 102 }
 103
 104 static void reserve_irq(unsigned int irq)
 105 {
 106         unsigned long flags;
 107
 108         spin_lock_irqsave(&vector_lock, flags);
 109         irq_status[irq] = IRQ_RSVD;
 110         spin_unlock_irqrestore(&vector_lock, flags);
 111 }
 112
 113 static inline int find_unassigned_irq(void)
 114 {
 115         int irq;
 116
 117         for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
 118                 if (irq_status[irq] == IRQ_UNUSED)
 119                         return irq;
 120         return -ENOSPC;
 121 }
 122
 123 static inline int find_unassigned_vector(cpumask_t domain)
 124 {
 125         cpumask_t mask;
 126         int pos;
 127
 128         cpus_and(mask, domain, cpu_online_map);
 129         if (cpus_empty(mask))
 130                 return -EINVAL;
 131
 132         for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
 133                 cpus_and(mask, domain, vector_table[pos]);
 134                 if (!cpus_empty(mask))
 135                         continue;
 136                 return IA64_FIRST_DEVICE_VECTOR + pos;
 137         }
 138         return -ENOSPC;
 139 }
 140
 141 static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
 142 {
 143         cpumask_t mask;
 144         int cpu, pos;
 145         struct irq_cfg *cfg = &irq_cfg[irq];
 146
 147         cpus_and(mask, domain, cpu_online_map);
 148         if (cpus_empty(mask))
 149                 return -EINVAL;
 150         if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
 151                 return 0;
 152         if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
 153                 return -EBUSY;
 154         for_each_cpu_mask(cpu, mask)
 155                 per_cpu(vector_irq, cpu)[vector] = irq;
 156         cfg->vector = vector;
 157         cfg->domain = domain;
 158         irq_status[irq] = IRQ_USED;
 159         pos = vector - IA64_FIRST_DEVICE_VECTOR;
 160         cpus_or(vector_table[pos], vector_table[pos], domain);
 161         return 0;
 162 }
 163
 164 int bind_irq_vector(int irq, int vector, cpumask_t domain)
 165 {
 166         unsigned long flags;
 167         int ret;
 168
 169         spin_lock_irqsave(&vector_lock, flags);
 170         ret = __bind_irq_vector(irq, vector, domain);
 171         spin_unlock_irqrestore(&vector_lock, flags);
 172         return ret;
 173 }
 174
 175 static void clear_irq_vector(int irq)
 176 {
 177         unsigned long flags;
 178         int vector, cpu, pos;
 179         cpumask_t mask;
 180         cpumask_t domain;
 181         struct irq_cfg *cfg = &irq_cfg[irq];
 182
 183         spin_lock_irqsave(&vector_lock, flags);
 184         BUG_ON((unsigned)irq >= NR_IRQS);
 185         BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
 186         vector = cfg->vector;
 187         domain = cfg->domain;
 188         cpus_and(mask, cfg->domain, cpu_online_map);
 189         for_each_cpu_mask(cpu, mask)
 190                 per_cpu(vector_irq, cpu)[vector] = IA64_SPURIOUS_INT_VECTOR;
 191         cfg->vector = IRQ_VECTOR_UNASSIGNED;
 192         cfg->domain = CPU_MASK_NONE;
 193         irq_status[irq] = IRQ_UNUSED;
 194         pos = vector - IA64_FIRST_DEVICE_VECTOR;
 195         cpus_andnot(vector_table[pos], vector_table[pos], domain);
 196         spin_unlock_irqrestore(&vector_lock, flags);
 197 }
 198
 199 int
 200 assign_irq_vector (int irq)
 201 {
 202         unsigned long flags;
 203         int vector, cpu;
 204         cpumask_t domain;
 205
 206         vector = -ENOSPC;
 207
 208         spin_lock_irqsave(&vector_lock, flags);
 209         if (irq < 0) {
 210                 goto out;
 211         }
 212         for_each_online_cpu(cpu) {
 213                 domain = vector_allocation_domain(cpu);
 214                 vector = find_unassigned_vector(domain);
 215                 if (vector >= 0)
 216                         break;
 217         }
 218         if (vector < 0)
 219                 goto out;
 220         BUG_ON(__bind_irq_vector(irq, vector, domain));
 221  out:
 222         spin_unlock_irqrestore(&vector_lock, flags);
 223         return vector;
 224 }
 225
 226 void
 227 free_irq_vector (int vector)
 228 {
 229         if (vector < IA64_FIRST_DEVICE_VECTOR ||
 230             vector > IA64_LAST_DEVICE_VECTOR)
 231                 return;
 232         clear_irq_vector(vector);
 233 }
 234
 235 int
 236 reserve_irq_vector (int vector)
 237 {
 238         if (vector < IA64_FIRST_DEVICE_VECTOR ||
 239             vector > IA64_LAST_DEVICE_VECTOR)
 240                 return -EINVAL;
 241         return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
 242 }
 243
 244 /*
 245  * Initialize vector_irq on a new cpu. This function must be called
 246  * with vector_lock held.
 247  */
 248 void __setup_vector_irq(int cpu)
 249 {
 250         int irq, vector;
 251
 252         /* Clear vector_irq */
 253         for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
 254                 per_cpu(vector_irq, cpu)[vector] = IA64_SPURIOUS_INT_VECTOR;
 255         /* Mark the inuse vectors */
 256         for (irq = 0; irq < NR_IRQS; ++irq) {
 257                 if (!cpu_isset(cpu, irq_cfg[irq].domain))
 258                         continue;
 259                 vector = irq_to_vector(irq);
 260                 per_cpu(vector_irq, cpu)[vector] = irq;
 261         }
 262 }
 263
 264 static cpumask_t vector_allocation_domain(int cpu)
 265 {
 266         return CPU_MASK_ALL;
 267 }
 268
 269
 270 void destroy_and_reserve_irq(unsigned int irq)
 271 {
 272         dynamic_irq_cleanup(irq);
 273
 274         clear_irq_vector(irq);
 275         reserve_irq(irq);
 276 }
 277
 278 /*
 279  * Dynamic irq allocate and deallocation for MSI
 280  */
 281 int create_irq(void)
 282 {
 283         unsigned long flags;
 284         int irq, vector, cpu;
 285         cpumask_t domain;
 286
 287         irq = vector = -ENOSPC;
 288         spin_lock_irqsave(&vector_lock, flags);
 289         for_each_online_cpu(cpu) {
 290                 domain = vector_allocation_domain(cpu);
 291                 vector = find_unassigned_vector(domain);
 292                 if (vector >= 0)
 293                         break;
 294         }
 295         if (vector < 0)
 296                 goto out;
 297         irq = find_unassigned_irq();
 298         if (irq < 0)
 299                 goto out;
 300         BUG_ON(__bind_irq_vector(irq, vector, domain));
 301  out:
 302         spin_unlock_irqrestore(&vector_lock, flags);
 303         if (irq >= 0)
 304                 dynamic_irq_init(irq);
 305         return irq;
 306 }
 307
 308 void destroy_irq(unsigned int irq)
 309 {
 310         dynamic_irq_cleanup(irq);
 311         clear_irq_vector(irq);
 312 }
 313
 314 #ifdef CONFIG_SMP
 315 #       define IS_RESCHEDULE(vec)       (vec == IA64_IPI_RESCHEDULE)
 316 #       define IS_LOCAL_TLB_FLUSH(vec)  (vec == IA64_IPI_LOCAL_TLB_FLUSH)
 317 #else
 318 #       define IS_RESCHEDULE(vec)       (0)
 319 #       define IS_LOCAL_TLB_FLUSH(vec)  (0)
 320 #endif
 321 /*
 322  * That's where the IVT branches when we get an external
 323  * interrupt. This branches to the correct hardware IRQ handler via
 324  * function ptr.
 325  */
 326 void
 327 ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
 328 {
 329         struct pt_regs *old_regs = set_irq_regs(regs);
 330         unsigned long saved_tpr;
 331
 332 #if IRQ_DEBUG
 333         {
 334                 unsigned long bsp, sp;
 335
 336                 /*
 337                  * Note: if the interrupt happened while executing in
 338                  * the context switch routine (ia64_switch_to), we may
 339                  * get a spurious stack overflow here.  This is
 340                  * because the register and the memory stack are not
 341                  * switched atomically.
 342                  */
 343                 bsp = ia64_getreg(_IA64_REG_AR_BSP);
 344                 sp = ia64_getreg(_IA64_REG_SP);
 345
 346                 if ((sp - bsp) < 1024) {
 347                         static unsigned char count;
 348                         static long last_time;
 349
 350                         if (jiffies - last_time > 5*HZ)
 351                                 count = 0;
 352                         if (++count < 5) {
 353                                 last_time = jiffies;
 354                                 printk("ia64_handle_irq: DANGER: less than "
 355                                        "1KB of free stack space!!\n"
 356                                        "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
 357                         }
 358                 }
 359         }
 360 #endif /* IRQ_DEBUG */
 361
 362         /*
 363          * Always set TPR to limit maximum interrupt nesting depth to
 364          * 16 (without this, it would be ~240, which could easily lead
 365          * to kernel stack overflows).
 366          */
 367         irq_enter();
 368         saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
 369         ia64_srlz_d();
 370         while (vector != IA64_SPURIOUS_INT_VECTOR) {
 371                 if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
 372                         smp_local_flush_tlb();
 373                         kstat_this_cpu.irqs[vector]++;
 374                 } else if (unlikely(IS_RESCHEDULE(vector)))
 375                         kstat_this_cpu.irqs[vector]++;
 376                 else {
 377                         ia64_setreg(_IA64_REG_CR_TPR, vector);
 378                         ia64_srlz_d();
 379
 380                         generic_handle_irq(local_vector_to_irq(vector));
 381
 382                         /*
 383                          * Disable interrupts and send EOI:
 384                          */
 385                         local_irq_disable();
 386                         ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
 387                 }
 388                 ia64_eoi();
 389                 vector = ia64_get_ivr();
 390         }
 391         /*
 392          * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
 393          * handler needs to be able to wait for further keyboard interrupts, which can't
 394          * come through until ia64_eoi() has been done.
 395          */
 396         irq_exit();
 397         set_irq_regs(old_regs);
 398 }
 399
 400 #ifdef CONFIG_HOTPLUG_CPU
 401 /*
 402  * This function emulates a interrupt processing when a cpu is about to be
 403  * brought down.
 404  */
 405 void ia64_process_pending_intr(void)
 406 {
 407         ia64_vector vector;
 408         unsigned long saved_tpr;
 409         extern unsigned int vectors_in_migration[NR_IRQS];
 410
 411         vector = ia64_get_ivr();
 412
 413          irq_enter();
 414          saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
 415          ia64_srlz_d();
 416
 417          /*
 418           * Perform normal interrupt style processing
 419           */
 420         while (vector != IA64_SPURIOUS_INT_VECTOR) {
 421                 if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
 422                         smp_local_flush_tlb();
 423                         kstat_this_cpu.irqs[vector]++;
 424                 } else if (unlikely(IS_RESCHEDULE(vector)))
 425                         kstat_this_cpu.irqs[vector]++;
 426                 else {
 427                         struct pt_regs *old_regs = set_irq_regs(NULL);
 428
 429                         ia64_setreg(_IA64_REG_CR_TPR, vector);
 430                         ia64_srlz_d();
 431
 432                         /*
 433                          * Now try calling normal ia64_handle_irq as it would have got called
 434                          * from a real intr handler. Try passing null for pt_regs, hopefully
 435                          * it will work. I hope it works!.
 436                          * Probably could shared code.
 437                          */
 438                         vectors_in_migration[local_vector_to_irq(vector)]=0;
 439                         generic_handle_irq(local_vector_to_irq(vector));
 440                         set_irq_regs(old_regs);
 441
 442                         /*
 443                          * Disable interrupts and send EOI
 444                          */
 445                         local_irq_disable();
 446                         ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
 447                 }
 448                 ia64_eoi();
 449                 vector = ia64_get_ivr();
 450         }
 451         irq_exit();
 452 }
 453 #endif
 454
 455
 456 #ifdef CONFIG_SMP
 457
 458 static irqreturn_t dummy_handler (int irq, void *dev_id)
 459 {
 460         BUG();
 461 }
 462 extern irqreturn_t handle_IPI (int irq, void *dev_id);
 463
 464 static struct irqaction ipi_irqaction = {
 465         .handler =      handle_IPI,
 466         .flags =        IRQF_DISABLED,
 467         .name =         "IPI"
 468 };
 469
 470 static struct irqaction resched_irqaction = {
 471         .handler =      dummy_handler,
 472         .flags =        IRQF_DISABLED,
 473         .name =         "resched"
 474 };
 475
 476 static struct irqaction tlb_irqaction = {
 477         .handler =      dummy_handler,
 478         .flags =        IRQF_DISABLED,
 479         .name =         "tlb_flush"
 480 };
 481
 482 #endif
 483
 484 void
 485 register_percpu_irq (ia64_vector vec, struct irqaction *action)
 486 {
 487         irq_desc_t *desc;
 488         unsigned int irq;
 489
 490         irq = vec;
 491         BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
 492         desc = irq_desc + irq;
 493         desc->status |= IRQ_PER_CPU;
 494         desc->chip = &irq_type_ia64_lsapic;
 495         if (action)
 496                 setup_irq(irq, action);
 497 }
 498
 499 void __init
 500 init_IRQ (void)
 501 {
 502         register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
 503 #ifdef CONFIG_SMP
 504         register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
 505         register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
 506         register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
 507 #endif
 508 #ifdef CONFIG_PERFMON
 509         pfm_init_percpu();
 510 #endif
 511         platform_irq_init();
 512 }
 513
 514 void
 515 ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
 516 {
 517         void __iomem *ipi_addr;
 518         unsigned long ipi_data;
 519         unsigned long phys_cpu_id;
 520
 521 #ifdef CONFIG_SMP
 522         phys_cpu_id = cpu_physical_id(cpu);
 523 #else
 524         phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
 525 #endif
 526
 527         /*
 528          * cpu number is in 8bit ID and 8bit EID
 529          */
 530
 531         ipi_data = (delivery_mode << 8) | (vector & 0xff);
 532         ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));
 533
 534         writeq(ipi_data, ipi_addr);
 535 }