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dm table: share target argument parsing functions
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / forcedeth.c
blobe64cd9ceac3f082e2f88844be5262c411860100a
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
7 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * Known bugs:
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
41 */
42
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45 #define FORCEDETH_VERSION "0.64"
46 #define DRV_NAME "forcedeth"
47
48 #include <linux/module.h>
49 #include <linux/types.h>
50 #include <linux/pci.h>
51 #include <linux/interrupt.h>
52 #include <linux/netdevice.h>
53 #include <linux/etherdevice.h>
54 #include <linux/delay.h>
55 #include <linux/sched.h>
56 #include <linux/spinlock.h>
57 #include <linux/ethtool.h>
58 #include <linux/timer.h>
59 #include <linux/skbuff.h>
60 #include <linux/mii.h>
61 #include <linux/random.h>
62 #include <linux/init.h>
63 #include <linux/if_vlan.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/slab.h>
66 #include <linux/uaccess.h>
67 #include <linux/prefetch.h>
68 #include <linux/io.h>
69
70 #include <asm/irq.h>
71 #include <asm/system.h>
72
73 #define TX_WORK_PER_LOOP 64
74 #define RX_WORK_PER_LOOP 64
75
76 /*
77 * Hardware access:
78 */
79
80 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
81 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
82 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
83 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
84 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
85 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
86 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
87 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
88 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
89 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
90 #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
91 #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
92 #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
93 #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
94 #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
95 #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
96 #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
97 #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
98 #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
99 #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
100 #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
101 #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
102 #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
103 #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
104 #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
105 #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
106 #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
107
108 enum {
109 NvRegIrqStatus = 0x000,
110 #define NVREG_IRQSTAT_MIIEVENT 0x040
111 #define NVREG_IRQSTAT_MASK 0x83ff
112 NvRegIrqMask = 0x004,
113 #define NVREG_IRQ_RX_ERROR 0x0001
114 #define NVREG_IRQ_RX 0x0002
115 #define NVREG_IRQ_RX_NOBUF 0x0004
116 #define NVREG_IRQ_TX_ERR 0x0008
117 #define NVREG_IRQ_TX_OK 0x0010
118 #define NVREG_IRQ_TIMER 0x0020
119 #define NVREG_IRQ_LINK 0x0040
120 #define NVREG_IRQ_RX_FORCED 0x0080
121 #define NVREG_IRQ_TX_FORCED 0x0100
122 #define NVREG_IRQ_RECOVER_ERROR 0x8200
123 #define NVREG_IRQMASK_THROUGHPUT 0x00df
124 #define NVREG_IRQMASK_CPU 0x0060
125 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
126 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
127 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
128
129 NvRegUnknownSetupReg6 = 0x008,
130 #define NVREG_UNKSETUP6_VAL 3
131
132 /*
133 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
134 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
135 */
136 NvRegPollingInterval = 0x00c,
137 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
138 #define NVREG_POLL_DEFAULT_CPU 13
139 NvRegMSIMap0 = 0x020,
140 NvRegMSIMap1 = 0x024,
141 NvRegMSIIrqMask = 0x030,
142 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
143 NvRegMisc1 = 0x080,
144 #define NVREG_MISC1_PAUSE_TX 0x01
145 #define NVREG_MISC1_HD 0x02
146 #define NVREG_MISC1_FORCE 0x3b0f3c
147
148 NvRegMacReset = 0x34,
149 #define NVREG_MAC_RESET_ASSERT 0x0F3
150 NvRegTransmitterControl = 0x084,
151 #define NVREG_XMITCTL_START 0x01
152 #define NVREG_XMITCTL_MGMT_ST 0x40000000
153 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
154 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
155 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
156 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
157 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
158 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
159 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
160 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
161 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
162 #define NVREG_XMITCTL_DATA_START 0x00100000
163 #define NVREG_XMITCTL_DATA_READY 0x00010000
164 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
165 NvRegTransmitterStatus = 0x088,
166 #define NVREG_XMITSTAT_BUSY 0x01
167
168 NvRegPacketFilterFlags = 0x8c,
169 #define NVREG_PFF_PAUSE_RX 0x08
170 #define NVREG_PFF_ALWAYS 0x7F0000
171 #define NVREG_PFF_PROMISC 0x80
172 #define NVREG_PFF_MYADDR 0x20
173 #define NVREG_PFF_LOOPBACK 0x10
174
175 NvRegOffloadConfig = 0x90,
176 #define NVREG_OFFLOAD_HOMEPHY 0x601
177 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
178 NvRegReceiverControl = 0x094,
179 #define NVREG_RCVCTL_START 0x01
180 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
181 NvRegReceiverStatus = 0x98,
182 #define NVREG_RCVSTAT_BUSY 0x01
183
184 NvRegSlotTime = 0x9c,
185 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
186 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
187 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
188 #define NVREG_SLOTTIME_HALF 0x0000ff00
189 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
190 #define NVREG_SLOTTIME_MASK 0x000000ff
191
192 NvRegTxDeferral = 0xA0,
193 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
194 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
195 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
196 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
197 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
198 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
199 NvRegRxDeferral = 0xA4,
200 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
201 NvRegMacAddrA = 0xA8,
202 NvRegMacAddrB = 0xAC,
203 NvRegMulticastAddrA = 0xB0,
204 #define NVREG_MCASTADDRA_FORCE 0x01
205 NvRegMulticastAddrB = 0xB4,
206 NvRegMulticastMaskA = 0xB8,
207 #define NVREG_MCASTMASKA_NONE 0xffffffff
208 NvRegMulticastMaskB = 0xBC,
209 #define NVREG_MCASTMASKB_NONE 0xffff
210
211 NvRegPhyInterface = 0xC0,
212 #define PHY_RGMII 0x10000000
213 NvRegBackOffControl = 0xC4,
214 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
215 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
216 #define NVREG_BKOFFCTRL_SELECT 24
217 #define NVREG_BKOFFCTRL_GEAR 12
218
219 NvRegTxRingPhysAddr = 0x100,
220 NvRegRxRingPhysAddr = 0x104,
221 NvRegRingSizes = 0x108,
222 #define NVREG_RINGSZ_TXSHIFT 0
223 #define NVREG_RINGSZ_RXSHIFT 16
224 NvRegTransmitPoll = 0x10c,
225 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
226 NvRegLinkSpeed = 0x110,
227 #define NVREG_LINKSPEED_FORCE 0x10000
228 #define NVREG_LINKSPEED_10 1000
229 #define NVREG_LINKSPEED_100 100
230 #define NVREG_LINKSPEED_1000 50
231 #define NVREG_LINKSPEED_MASK (0xFFF)
232 NvRegUnknownSetupReg5 = 0x130,
233 #define NVREG_UNKSETUP5_BIT31 (1<<31)
234 NvRegTxWatermark = 0x13c,
235 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
236 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
237 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
238 NvRegTxRxControl = 0x144,
239 #define NVREG_TXRXCTL_KICK 0x0001
240 #define NVREG_TXRXCTL_BIT1 0x0002
241 #define NVREG_TXRXCTL_BIT2 0x0004
242 #define NVREG_TXRXCTL_IDLE 0x0008
243 #define NVREG_TXRXCTL_RESET 0x0010
244 #define NVREG_TXRXCTL_RXCHECK 0x0400
245 #define NVREG_TXRXCTL_DESC_1 0
246 #define NVREG_TXRXCTL_DESC_2 0x002100
247 #define NVREG_TXRXCTL_DESC_3 0xc02200
248 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
249 #define NVREG_TXRXCTL_VLANINS 0x00080
250 NvRegTxRingPhysAddrHigh = 0x148,
251 NvRegRxRingPhysAddrHigh = 0x14C,
252 NvRegTxPauseFrame = 0x170,
253 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
254 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
255 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
256 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
257 NvRegTxPauseFrameLimit = 0x174,
258 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
259 NvRegMIIStatus = 0x180,
260 #define NVREG_MIISTAT_ERROR 0x0001
261 #define NVREG_MIISTAT_LINKCHANGE 0x0008
262 #define NVREG_MIISTAT_MASK_RW 0x0007
263 #define NVREG_MIISTAT_MASK_ALL 0x000f
264 NvRegMIIMask = 0x184,
265 #define NVREG_MII_LINKCHANGE 0x0008
266
267 NvRegAdapterControl = 0x188,
268 #define NVREG_ADAPTCTL_START 0x02
269 #define NVREG_ADAPTCTL_LINKUP 0x04
270 #define NVREG_ADAPTCTL_PHYVALID 0x40000
271 #define NVREG_ADAPTCTL_RUNNING 0x100000
272 #define NVREG_ADAPTCTL_PHYSHIFT 24
273 NvRegMIISpeed = 0x18c,
274 #define NVREG_MIISPEED_BIT8 (1<<8)
275 #define NVREG_MIIDELAY 5
276 NvRegMIIControl = 0x190,
277 #define NVREG_MIICTL_INUSE 0x08000
278 #define NVREG_MIICTL_WRITE 0x00400
279 #define NVREG_MIICTL_ADDRSHIFT 5
280 NvRegMIIData = 0x194,
281 NvRegTxUnicast = 0x1a0,
282 NvRegTxMulticast = 0x1a4,
283 NvRegTxBroadcast = 0x1a8,
284 NvRegWakeUpFlags = 0x200,
285 #define NVREG_WAKEUPFLAGS_VAL 0x7770
286 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
287 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
288 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
289 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
290 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
291 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
292 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
293 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
294 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
295 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
296
297 NvRegMgmtUnitGetVersion = 0x204,
298 #define NVREG_MGMTUNITGETVERSION 0x01
299 NvRegMgmtUnitVersion = 0x208,
300 #define NVREG_MGMTUNITVERSION 0x08
301 NvRegPowerCap = 0x268,
302 #define NVREG_POWERCAP_D3SUPP (1<<30)
303 #define NVREG_POWERCAP_D2SUPP (1<<26)
304 #define NVREG_POWERCAP_D1SUPP (1<<25)
305 NvRegPowerState = 0x26c,
306 #define NVREG_POWERSTATE_POWEREDUP 0x8000
307 #define NVREG_POWERSTATE_VALID 0x0100
308 #define NVREG_POWERSTATE_MASK 0x0003
309 #define NVREG_POWERSTATE_D0 0x0000
310 #define NVREG_POWERSTATE_D1 0x0001
311 #define NVREG_POWERSTATE_D2 0x0002
312 #define NVREG_POWERSTATE_D3 0x0003
313 NvRegMgmtUnitControl = 0x278,
314 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
315 NvRegTxCnt = 0x280,
316 NvRegTxZeroReXmt = 0x284,
317 NvRegTxOneReXmt = 0x288,
318 NvRegTxManyReXmt = 0x28c,
319 NvRegTxLateCol = 0x290,
320 NvRegTxUnderflow = 0x294,
321 NvRegTxLossCarrier = 0x298,
322 NvRegTxExcessDef = 0x29c,
323 NvRegTxRetryErr = 0x2a0,
324 NvRegRxFrameErr = 0x2a4,
325 NvRegRxExtraByte = 0x2a8,
326 NvRegRxLateCol = 0x2ac,
327 NvRegRxRunt = 0x2b0,
328 NvRegRxFrameTooLong = 0x2b4,
329 NvRegRxOverflow = 0x2b8,
330 NvRegRxFCSErr = 0x2bc,
331 NvRegRxFrameAlignErr = 0x2c0,
332 NvRegRxLenErr = 0x2c4,
333 NvRegRxUnicast = 0x2c8,
334 NvRegRxMulticast = 0x2cc,
335 NvRegRxBroadcast = 0x2d0,
336 NvRegTxDef = 0x2d4,
337 NvRegTxFrame = 0x2d8,
338 NvRegRxCnt = 0x2dc,
339 NvRegTxPause = 0x2e0,
340 NvRegRxPause = 0x2e4,
341 NvRegRxDropFrame = 0x2e8,
342 NvRegVlanControl = 0x300,
343 #define NVREG_VLANCONTROL_ENABLE 0x2000
344 NvRegMSIXMap0 = 0x3e0,
345 NvRegMSIXMap1 = 0x3e4,
346 NvRegMSIXIrqStatus = 0x3f0,
347
348 NvRegPowerState2 = 0x600,
349 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
350 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
351 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
352 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
353 };
354
355 /* Big endian: should work, but is untested */
356 struct ring_desc {
357 __le32 buf;
358 __le32 flaglen;
359 };
360
361 struct ring_desc_ex {
362 __le32 bufhigh;
363 __le32 buflow;
364 __le32 txvlan;
365 __le32 flaglen;
366 };
367
368 union ring_type {
369 struct ring_desc *orig;
370 struct ring_desc_ex *ex;
371 };
372
373 #define FLAG_MASK_V1 0xffff0000
374 #define FLAG_MASK_V2 0xffffc000
375 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
376 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
377
378 #define NV_TX_LASTPACKET (1<<16)
379 #define NV_TX_RETRYERROR (1<<19)
380 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
381 #define NV_TX_FORCED_INTERRUPT (1<<24)
382 #define NV_TX_DEFERRED (1<<26)
383 #define NV_TX_CARRIERLOST (1<<27)
384 #define NV_TX_LATECOLLISION (1<<28)
385 #define NV_TX_UNDERFLOW (1<<29)
386 #define NV_TX_ERROR (1<<30)
387 #define NV_TX_VALID (1<<31)
388
389 #define NV_TX2_LASTPACKET (1<<29)
390 #define NV_TX2_RETRYERROR (1<<18)
391 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
392 #define NV_TX2_FORCED_INTERRUPT (1<<30)
393 #define NV_TX2_DEFERRED (1<<25)
394 #define NV_TX2_CARRIERLOST (1<<26)
395 #define NV_TX2_LATECOLLISION (1<<27)
396 #define NV_TX2_UNDERFLOW (1<<28)
397 /* error and valid are the same for both */
398 #define NV_TX2_ERROR (1<<30)
399 #define NV_TX2_VALID (1<<31)
400 #define NV_TX2_TSO (1<<28)
401 #define NV_TX2_TSO_SHIFT 14
402 #define NV_TX2_TSO_MAX_SHIFT 14
403 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
404 #define NV_TX2_CHECKSUM_L3 (1<<27)
405 #define NV_TX2_CHECKSUM_L4 (1<<26)
406
407 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
408
409 #define NV_RX_DESCRIPTORVALID (1<<16)
410 #define NV_RX_MISSEDFRAME (1<<17)
411 #define NV_RX_SUBSTRACT1 (1<<18)
412 #define NV_RX_ERROR1 (1<<23)
413 #define NV_RX_ERROR2 (1<<24)
414 #define NV_RX_ERROR3 (1<<25)
415 #define NV_RX_ERROR4 (1<<26)
416 #define NV_RX_CRCERR (1<<27)
417 #define NV_RX_OVERFLOW (1<<28)
418 #define NV_RX_FRAMINGERR (1<<29)
419 #define NV_RX_ERROR (1<<30)
420 #define NV_RX_AVAIL (1<<31)
421 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
422
423 #define NV_RX2_CHECKSUMMASK (0x1C000000)
424 #define NV_RX2_CHECKSUM_IP (0x10000000)
425 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
426 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
427 #define NV_RX2_DESCRIPTORVALID (1<<29)
428 #define NV_RX2_SUBSTRACT1 (1<<25)
429 #define NV_RX2_ERROR1 (1<<18)
430 #define NV_RX2_ERROR2 (1<<19)
431 #define NV_RX2_ERROR3 (1<<20)
432 #define NV_RX2_ERROR4 (1<<21)
433 #define NV_RX2_CRCERR (1<<22)
434 #define NV_RX2_OVERFLOW (1<<23)
435 #define NV_RX2_FRAMINGERR (1<<24)
436 /* error and avail are the same for both */
437 #define NV_RX2_ERROR (1<<30)
438 #define NV_RX2_AVAIL (1<<31)
439 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
440
441 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
442 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
443
444 /* Miscellaneous hardware related defines: */
445 #define NV_PCI_REGSZ_VER1 0x270
446 #define NV_PCI_REGSZ_VER2 0x2d4
447 #define NV_PCI_REGSZ_VER3 0x604
448 #define NV_PCI_REGSZ_MAX 0x604
449
450 /* various timeout delays: all in usec */
451 #define NV_TXRX_RESET_DELAY 4
452 #define NV_TXSTOP_DELAY1 10
453 #define NV_TXSTOP_DELAY1MAX 500000
454 #define NV_TXSTOP_DELAY2 100
455 #define NV_RXSTOP_DELAY1 10
456 #define NV_RXSTOP_DELAY1MAX 500000
457 #define NV_RXSTOP_DELAY2 100
458 #define NV_SETUP5_DELAY 5
459 #define NV_SETUP5_DELAYMAX 50000
460 #define NV_POWERUP_DELAY 5
461 #define NV_POWERUP_DELAYMAX 5000
462 #define NV_MIIBUSY_DELAY 50
463 #define NV_MIIPHY_DELAY 10
464 #define NV_MIIPHY_DELAYMAX 10000
465 #define NV_MAC_RESET_DELAY 64
466
467 #define NV_WAKEUPPATTERNS 5
468 #define NV_WAKEUPMASKENTRIES 4
469
470 /* General driver defaults */
471 #define NV_WATCHDOG_TIMEO (5*HZ)
472
473 #define RX_RING_DEFAULT 512
474 #define TX_RING_DEFAULT 256
475 #define RX_RING_MIN 128
476 #define TX_RING_MIN 64
477 #define RING_MAX_DESC_VER_1 1024
478 #define RING_MAX_DESC_VER_2_3 16384
479
480 /* rx/tx mac addr + type + vlan + align + slack*/
481 #define NV_RX_HEADERS (64)
482 /* even more slack. */
483 #define NV_RX_ALLOC_PAD (64)
484
485 /* maximum mtu size */
486 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
487 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
488
489 #define OOM_REFILL (1+HZ/20)
490 #define POLL_WAIT (1+HZ/100)
491 #define LINK_TIMEOUT (3*HZ)
492 #define STATS_INTERVAL (10*HZ)
493
494 /*
495 * desc_ver values:
496 * The nic supports three different descriptor types:
497 * - DESC_VER_1: Original
498 * - DESC_VER_2: support for jumbo frames.
499 * - DESC_VER_3: 64-bit format.
500 */
501 #define DESC_VER_1 1
502 #define DESC_VER_2 2
503 #define DESC_VER_3 3
504
505 /* PHY defines */
506 #define PHY_OUI_MARVELL 0x5043
507 #define PHY_OUI_CICADA 0x03f1
508 #define PHY_OUI_VITESSE 0x01c1
509 #define PHY_OUI_REALTEK 0x0732
510 #define PHY_OUI_REALTEK2 0x0020
511 #define PHYID1_OUI_MASK 0x03ff
512 #define PHYID1_OUI_SHFT 6
513 #define PHYID2_OUI_MASK 0xfc00
514 #define PHYID2_OUI_SHFT 10
515 #define PHYID2_MODEL_MASK 0x03f0
516 #define PHY_MODEL_REALTEK_8211 0x0110
517 #define PHY_REV_MASK 0x0001
518 #define PHY_REV_REALTEK_8211B 0x0000
519 #define PHY_REV_REALTEK_8211C 0x0001
520 #define PHY_MODEL_REALTEK_8201 0x0200
521 #define PHY_MODEL_MARVELL_E3016 0x0220
522 #define PHY_MARVELL_E3016_INITMASK 0x0300
523 #define PHY_CICADA_INIT1 0x0f000
524 #define PHY_CICADA_INIT2 0x0e00
525 #define PHY_CICADA_INIT3 0x01000
526 #define PHY_CICADA_INIT4 0x0200
527 #define PHY_CICADA_INIT5 0x0004
528 #define PHY_CICADA_INIT6 0x02000
529 #define PHY_VITESSE_INIT_REG1 0x1f
530 #define PHY_VITESSE_INIT_REG2 0x10
531 #define PHY_VITESSE_INIT_REG3 0x11
532 #define PHY_VITESSE_INIT_REG4 0x12
533 #define PHY_VITESSE_INIT_MSK1 0xc
534 #define PHY_VITESSE_INIT_MSK2 0x0180
535 #define PHY_VITESSE_INIT1 0x52b5
536 #define PHY_VITESSE_INIT2 0xaf8a
537 #define PHY_VITESSE_INIT3 0x8
538 #define PHY_VITESSE_INIT4 0x8f8a
539 #define PHY_VITESSE_INIT5 0xaf86
540 #define PHY_VITESSE_INIT6 0x8f86
541 #define PHY_VITESSE_INIT7 0xaf82
542 #define PHY_VITESSE_INIT8 0x0100
543 #define PHY_VITESSE_INIT9 0x8f82
544 #define PHY_VITESSE_INIT10 0x0
545 #define PHY_REALTEK_INIT_REG1 0x1f
546 #define PHY_REALTEK_INIT_REG2 0x19
547 #define PHY_REALTEK_INIT_REG3 0x13
548 #define PHY_REALTEK_INIT_REG4 0x14
549 #define PHY_REALTEK_INIT_REG5 0x18
550 #define PHY_REALTEK_INIT_REG6 0x11
551 #define PHY_REALTEK_INIT_REG7 0x01
552 #define PHY_REALTEK_INIT1 0x0000
553 #define PHY_REALTEK_INIT2 0x8e00
554 #define PHY_REALTEK_INIT3 0x0001
555 #define PHY_REALTEK_INIT4 0xad17
556 #define PHY_REALTEK_INIT5 0xfb54
557 #define PHY_REALTEK_INIT6 0xf5c7
558 #define PHY_REALTEK_INIT7 0x1000
559 #define PHY_REALTEK_INIT8 0x0003
560 #define PHY_REALTEK_INIT9 0x0008
561 #define PHY_REALTEK_INIT10 0x0005
562 #define PHY_REALTEK_INIT11 0x0200
563 #define PHY_REALTEK_INIT_MSK1 0x0003
564
565 #define PHY_GIGABIT 0x0100
566
567 #define PHY_TIMEOUT 0x1
568 #define PHY_ERROR 0x2
569
570 #define PHY_100 0x1
571 #define PHY_1000 0x2
572 #define PHY_HALF 0x100
573
574 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
575 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
576 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
577 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
578 #define NV_PAUSEFRAME_RX_REQ 0x0010
579 #define NV_PAUSEFRAME_TX_REQ 0x0020
580 #define NV_PAUSEFRAME_AUTONEG 0x0040
581
582 /* MSI/MSI-X defines */
583 #define NV_MSI_X_MAX_VECTORS 8
584 #define NV_MSI_X_VECTORS_MASK 0x000f
585 #define NV_MSI_CAPABLE 0x0010
586 #define NV_MSI_X_CAPABLE 0x0020
587 #define NV_MSI_ENABLED 0x0040
588 #define NV_MSI_X_ENABLED 0x0080
589
590 #define NV_MSI_X_VECTOR_ALL 0x0
591 #define NV_MSI_X_VECTOR_RX 0x0
592 #define NV_MSI_X_VECTOR_TX 0x1
593 #define NV_MSI_X_VECTOR_OTHER 0x2
594
595 #define NV_MSI_PRIV_OFFSET 0x68
596 #define NV_MSI_PRIV_VALUE 0xffffffff
597
598 #define NV_RESTART_TX 0x1
599 #define NV_RESTART_RX 0x2
600
601 #define NV_TX_LIMIT_COUNT 16
602
603 #define NV_DYNAMIC_THRESHOLD 4
604 #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
605
606 /* statistics */
607 struct nv_ethtool_str {
608 char name[ETH_GSTRING_LEN];
609 };
610
611 static const struct nv_ethtool_str nv_estats_str[] = {
612 { "tx_bytes" },
613 { "tx_zero_rexmt" },
614 { "tx_one_rexmt" },
615 { "tx_many_rexmt" },
616 { "tx_late_collision" },
617 { "tx_fifo_errors" },
618 { "tx_carrier_errors" },
619 { "tx_excess_deferral" },
620 { "tx_retry_error" },
621 { "rx_frame_error" },
622 { "rx_extra_byte" },
623 { "rx_late_collision" },
624 { "rx_runt" },
625 { "rx_frame_too_long" },
626 { "rx_over_errors" },
627 { "rx_crc_errors" },
628 { "rx_frame_align_error" },
629 { "rx_length_error" },
630 { "rx_unicast" },
631 { "rx_multicast" },
632 { "rx_broadcast" },
633 { "rx_packets" },
634 { "rx_errors_total" },
635 { "tx_errors_total" },
636
637 /* version 2 stats */
638 { "tx_deferral" },
639 { "tx_packets" },
640 { "rx_bytes" },
641 { "tx_pause" },
642 { "rx_pause" },
643 { "rx_drop_frame" },
644
645 /* version 3 stats */
646 { "tx_unicast" },
647 { "tx_multicast" },
648 { "tx_broadcast" }
649 };
650
651 struct nv_ethtool_stats {
652 u64 tx_bytes;
653 u64 tx_zero_rexmt;
654 u64 tx_one_rexmt;
655 u64 tx_many_rexmt;
656 u64 tx_late_collision;
657 u64 tx_fifo_errors;
658 u64 tx_carrier_errors;
659 u64 tx_excess_deferral;
660 u64 tx_retry_error;
661 u64 rx_frame_error;
662 u64 rx_extra_byte;
663 u64 rx_late_collision;
664 u64 rx_runt;
665 u64 rx_frame_too_long;
666 u64 rx_over_errors;
667 u64 rx_crc_errors;
668 u64 rx_frame_align_error;
669 u64 rx_length_error;
670 u64 rx_unicast;
671 u64 rx_multicast;
672 u64 rx_broadcast;
673 u64 rx_packets;
674 u64 rx_errors_total;
675 u64 tx_errors_total;
676
677 /* version 2 stats */
678 u64 tx_deferral;
679 u64 tx_packets;
680 u64 rx_bytes;
681 u64 tx_pause;
682 u64 rx_pause;
683 u64 rx_drop_frame;
684
685 /* version 3 stats */
686 u64 tx_unicast;
687 u64 tx_multicast;
688 u64 tx_broadcast;
689 };
690
691 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
692 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
693 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
694
695 /* diagnostics */
696 #define NV_TEST_COUNT_BASE 3
697 #define NV_TEST_COUNT_EXTENDED 4
698
699 static const struct nv_ethtool_str nv_etests_str[] = {
700 { "link (online/offline)" },
701 { "register (offline) " },
702 { "interrupt (offline) " },
703 { "loopback (offline) " }
704 };
705
706 struct register_test {
707 __u32 reg;
708 __u32 mask;
709 };
710
711 static const struct register_test nv_registers_test[] = {
712 { NvRegUnknownSetupReg6, 0x01 },
713 { NvRegMisc1, 0x03c },
714 { NvRegOffloadConfig, 0x03ff },
715 { NvRegMulticastAddrA, 0xffffffff },
716 { NvRegTxWatermark, 0x0ff },
717 { NvRegWakeUpFlags, 0x07777 },
718 { 0, 0 }
719 };
720
721 struct nv_skb_map {
722 struct sk_buff *skb;
723 dma_addr_t dma;
724 unsigned int dma_len:31;
725 unsigned int dma_single:1;
726 struct ring_desc_ex *first_tx_desc;
727 struct nv_skb_map *next_tx_ctx;
728 };
729
730 /*
731 * SMP locking:
732 * All hardware access under netdev_priv(dev)->lock, except the performance
733 * critical parts:
734 * - rx is (pseudo-) lockless: it relies on the single-threading provided
735 * by the arch code for interrupts.
736 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
737 * needs netdev_priv(dev)->lock :-(
738 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
739 */
740
741 /* in dev: base, irq */
742 struct fe_priv {
743 spinlock_t lock;
744
745 struct net_device *dev;
746 struct napi_struct napi;
747
748 /* General data:
749 * Locking: spin_lock(&np->lock); */
750 struct nv_ethtool_stats estats;
751 int in_shutdown;
752 u32 linkspeed;
753 int duplex;
754 int autoneg;
755 int fixed_mode;
756 int phyaddr;
757 int wolenabled;
758 unsigned int phy_oui;
759 unsigned int phy_model;
760 unsigned int phy_rev;
761 u16 gigabit;
762 int intr_test;
763 int recover_error;
764 int quiet_count;
765
766 /* General data: RO fields */
767 dma_addr_t ring_addr;
768 struct pci_dev *pci_dev;
769 u32 orig_mac[2];
770 u32 events;
771 u32 irqmask;
772 u32 desc_ver;
773 u32 txrxctl_bits;
774 u32 vlanctl_bits;
775 u32 driver_data;
776 u32 device_id;
777 u32 register_size;
778 u32 mac_in_use;
779 int mgmt_version;
780 int mgmt_sema;
781
782 void __iomem *base;
783
784 /* rx specific fields.
785 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
786 */
787 union ring_type get_rx, put_rx, first_rx, last_rx;
788 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
789 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
790 struct nv_skb_map *rx_skb;
791
792 union ring_type rx_ring;
793 unsigned int rx_buf_sz;
794 unsigned int pkt_limit;
795 struct timer_list oom_kick;
796 struct timer_list nic_poll;
797 struct timer_list stats_poll;
798 u32 nic_poll_irq;
799 int rx_ring_size;
800
801 /* media detection workaround.
802 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
803 */
804 int need_linktimer;
805 unsigned long link_timeout;
806 /*
807 * tx specific fields.
808 */
809 union ring_type get_tx, put_tx, first_tx, last_tx;
810 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
811 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
812 struct nv_skb_map *tx_skb;
813
814 union ring_type tx_ring;
815 u32 tx_flags;
816 int tx_ring_size;
817 int tx_limit;
818 u32 tx_pkts_in_progress;
819 struct nv_skb_map *tx_change_owner;
820 struct nv_skb_map *tx_end_flip;
821 int tx_stop;
822
823 /* msi/msi-x fields */
824 u32 msi_flags;
825 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
826
827 /* flow control */
828 u32 pause_flags;
829
830 /* power saved state */
831 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
832
833 /* for different msi-x irq type */
834 char name_rx[IFNAMSIZ + 3]; /* -rx */
835 char name_tx[IFNAMSIZ + 3]; /* -tx */
836 char name_other[IFNAMSIZ + 6]; /* -other */
837 };
838
839 /*
840 * Maximum number of loops until we assume that a bit in the irq mask
841 * is stuck. Overridable with module param.
842 */
843 static int max_interrupt_work = 4;
844
845 /*
846 * Optimization can be either throuput mode or cpu mode
847 *
848 * Throughput Mode: Every tx and rx packet will generate an interrupt.
849 * CPU Mode: Interrupts are controlled by a timer.
850 */
851 enum {
852 NV_OPTIMIZATION_MODE_THROUGHPUT,
853 NV_OPTIMIZATION_MODE_CPU,
854 NV_OPTIMIZATION_MODE_DYNAMIC
855 };
856 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
857
858 /*
859 * Poll interval for timer irq
860 *
861 * This interval determines how frequent an interrupt is generated.
862 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
863 * Min = 0, and Max = 65535
864 */
865 static int poll_interval = -1;
866
867 /*
868 * MSI interrupts
869 */
870 enum {
871 NV_MSI_INT_DISABLED,
872 NV_MSI_INT_ENABLED
873 };
874 static int msi = NV_MSI_INT_ENABLED;
875
876 /*
877 * MSIX interrupts
878 */
879 enum {
880 NV_MSIX_INT_DISABLED,
881 NV_MSIX_INT_ENABLED
882 };
883 static int msix = NV_MSIX_INT_ENABLED;
884
885 /*
886 * DMA 64bit
887 */
888 enum {
889 NV_DMA_64BIT_DISABLED,
890 NV_DMA_64BIT_ENABLED
891 };
892 static int dma_64bit = NV_DMA_64BIT_ENABLED;
893
894 /*
895 * Crossover Detection
896 * Realtek 8201 phy + some OEM boards do not work properly.
897 */
898 enum {
899 NV_CROSSOVER_DETECTION_DISABLED,
900 NV_CROSSOVER_DETECTION_ENABLED
901 };
902 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
903
904 /*
905 * Power down phy when interface is down (persists through reboot;
906 * older Linux and other OSes may not power it up again)
907 */
908 static int phy_power_down;
909
910 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
911 {
912 return netdev_priv(dev);
913 }
914
915 static inline u8 __iomem *get_hwbase(struct net_device *dev)
916 {
917 return ((struct fe_priv *)netdev_priv(dev))->base;
918 }
919
920 static inline void pci_push(u8 __iomem *base)
921 {
922 /* force out pending posted writes */
923 readl(base);
924 }
925
926 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
927 {
928 return le32_to_cpu(prd->flaglen)
929 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
930 }
931
932 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
933 {
934 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
935 }
936
937 static bool nv_optimized(struct fe_priv *np)
938 {
939 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
940 return false;
941 return true;
942 }
943
944 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
945 int delay, int delaymax)
946 {
947 u8 __iomem *base = get_hwbase(dev);
948
949 pci_push(base);
950 do {
951 udelay(delay);
952 delaymax -= delay;
953 if (delaymax < 0)
954 return 1;
955 } while ((readl(base + offset) & mask) != target);
956 return 0;
957 }
958
959 #define NV_SETUP_RX_RING 0x01
960 #define NV_SETUP_TX_RING 0x02
961
962 static inline u32 dma_low(dma_addr_t addr)
963 {
964 return addr;
965 }
966
967 static inline u32 dma_high(dma_addr_t addr)
968 {
969 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
970 }
971
972 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
973 {
974 struct fe_priv *np = get_nvpriv(dev);
975 u8 __iomem *base = get_hwbase(dev);
976
977 if (!nv_optimized(np)) {
978 if (rxtx_flags & NV_SETUP_RX_RING)
979 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
980 if (rxtx_flags & NV_SETUP_TX_RING)
981 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
982 } else {
983 if (rxtx_flags & NV_SETUP_RX_RING) {
984 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
985 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
986 }
987 if (rxtx_flags & NV_SETUP_TX_RING) {
988 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
989 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
990 }
991 }
992 }
993
994 static void free_rings(struct net_device *dev)
995 {
996 struct fe_priv *np = get_nvpriv(dev);
997
998 if (!nv_optimized(np)) {
999 if (np->rx_ring.orig)
1000 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1001 np->rx_ring.orig, np->ring_addr);
1002 } else {
1003 if (np->rx_ring.ex)
1004 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1005 np->rx_ring.ex, np->ring_addr);
1006 }
1007 kfree(np->rx_skb);
1008 kfree(np->tx_skb);
1009 }
1010
1011 static int using_multi_irqs(struct net_device *dev)
1012 {
1013 struct fe_priv *np = get_nvpriv(dev);
1014
1015 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1016 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1017 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1018 return 0;
1019 else
1020 return 1;
1021 }
1022
1023 static void nv_txrx_gate(struct net_device *dev, bool gate)
1024 {
1025 struct fe_priv *np = get_nvpriv(dev);
1026 u8 __iomem *base = get_hwbase(dev);
1027 u32 powerstate;
1028
1029 if (!np->mac_in_use &&
1030 (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1031 powerstate = readl(base + NvRegPowerState2);
1032 if (gate)
1033 powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1034 else
1035 powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1036 writel(powerstate, base + NvRegPowerState2);
1037 }
1038 }
1039
1040 static void nv_enable_irq(struct net_device *dev)
1041 {
1042 struct fe_priv *np = get_nvpriv(dev);
1043
1044 if (!using_multi_irqs(dev)) {
1045 if (np->msi_flags & NV_MSI_X_ENABLED)
1046 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1047 else
1048 enable_irq(np->pci_dev->irq);
1049 } else {
1050 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1051 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1052 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1053 }
1054 }
1055
1056 static void nv_disable_irq(struct net_device *dev)
1057 {
1058 struct fe_priv *np = get_nvpriv(dev);
1059
1060 if (!using_multi_irqs(dev)) {
1061 if (np->msi_flags & NV_MSI_X_ENABLED)
1062 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1063 else
1064 disable_irq(np->pci_dev->irq);
1065 } else {
1066 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1067 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1068 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1069 }
1070 }
1071
1072 /* In MSIX mode, a write to irqmask behaves as XOR */
1073 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1074 {
1075 u8 __iomem *base = get_hwbase(dev);
1076
1077 writel(mask, base + NvRegIrqMask);
1078 }
1079
1080 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1081 {
1082 struct fe_priv *np = get_nvpriv(dev);
1083 u8 __iomem *base = get_hwbase(dev);
1084
1085 if (np->msi_flags & NV_MSI_X_ENABLED) {
1086 writel(mask, base + NvRegIrqMask);
1087 } else {
1088 if (np->msi_flags & NV_MSI_ENABLED)
1089 writel(0, base + NvRegMSIIrqMask);
1090 writel(0, base + NvRegIrqMask);
1091 }
1092 }
1093
1094 static void nv_napi_enable(struct net_device *dev)
1095 {
1096 struct fe_priv *np = get_nvpriv(dev);
1097
1098 napi_enable(&np->napi);
1099 }
1100
1101 static void nv_napi_disable(struct net_device *dev)
1102 {
1103 struct fe_priv *np = get_nvpriv(dev);
1104
1105 napi_disable(&np->napi);
1106 }
1107
1108 #define MII_READ (-1)
1109 /* mii_rw: read/write a register on the PHY.
1110 *
1111 * Caller must guarantee serialization
1112 */
1113 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1114 {
1115 u8 __iomem *base = get_hwbase(dev);
1116 u32 reg;
1117 int retval;
1118
1119 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1120
1121 reg = readl(base + NvRegMIIControl);
1122 if (reg & NVREG_MIICTL_INUSE) {
1123 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1124 udelay(NV_MIIBUSY_DELAY);
1125 }
1126
1127 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1128 if (value != MII_READ) {
1129 writel(value, base + NvRegMIIData);
1130 reg |= NVREG_MIICTL_WRITE;
1131 }
1132 writel(reg, base + NvRegMIIControl);
1133
1134 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1135 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1136 retval = -1;
1137 } else if (value != MII_READ) {
1138 /* it was a write operation - fewer failures are detectable */
1139 retval = 0;
1140 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1141 retval = -1;
1142 } else {
1143 retval = readl(base + NvRegMIIData);
1144 }
1145
1146 return retval;
1147 }
1148
1149 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1150 {
1151 struct fe_priv *np = netdev_priv(dev);
1152 u32 miicontrol;
1153 unsigned int tries = 0;
1154
1155 miicontrol = BMCR_RESET | bmcr_setup;
1156 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1157 return -1;
1158
1159 /* wait for 500ms */
1160 msleep(500);
1161
1162 /* must wait till reset is deasserted */
1163 while (miicontrol & BMCR_RESET) {
1164 usleep_range(10000, 20000);
1165 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1166 /* FIXME: 100 tries seem excessive */
1167 if (tries++ > 100)
1168 return -1;
1169 }
1170 return 0;
1171 }
1172
1173 static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1174 {
1175 static const struct {
1176 int reg;
1177 int init;
1178 } ri[] = {
1179 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1180 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1181 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1182 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1183 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1184 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1185 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1186 };
1187 int i;
1188
1189 for (i = 0; i < ARRAY_SIZE(ri); i++) {
1190 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1191 return PHY_ERROR;
1192 }
1193
1194 return 0;
1195 }
1196
1197 static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1198 {
1199 u32 reg;
1200 u8 __iomem *base = get_hwbase(dev);
1201 u32 powerstate = readl(base + NvRegPowerState2);
1202
1203 /* need to perform hw phy reset */
1204 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1205 writel(powerstate, base + NvRegPowerState2);
1206 msleep(25);
1207
1208 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1209 writel(powerstate, base + NvRegPowerState2);
1210 msleep(25);
1211
1212 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1213 reg |= PHY_REALTEK_INIT9;
1214 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1215 return PHY_ERROR;
1216 if (mii_rw(dev, np->phyaddr,
1217 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1218 return PHY_ERROR;
1219 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1220 if (!(reg & PHY_REALTEK_INIT11)) {
1221 reg |= PHY_REALTEK_INIT11;
1222 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1223 return PHY_ERROR;
1224 }
1225 if (mii_rw(dev, np->phyaddr,
1226 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1227 return PHY_ERROR;
1228
1229 return 0;
1230 }
1231
1232 static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1233 {
1234 u32 phy_reserved;
1235
1236 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1237 phy_reserved = mii_rw(dev, np->phyaddr,
1238 PHY_REALTEK_INIT_REG6, MII_READ);
1239 phy_reserved |= PHY_REALTEK_INIT7;
1240 if (mii_rw(dev, np->phyaddr,
1241 PHY_REALTEK_INIT_REG6, phy_reserved))
1242 return PHY_ERROR;
1243 }
1244
1245 return 0;
1246 }
1247
1248 static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1249 {
1250 u32 phy_reserved;
1251
1252 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1253 if (mii_rw(dev, np->phyaddr,
1254 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1255 return PHY_ERROR;
1256 phy_reserved = mii_rw(dev, np->phyaddr,
1257 PHY_REALTEK_INIT_REG2, MII_READ);
1258 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1259 phy_reserved |= PHY_REALTEK_INIT3;
1260 if (mii_rw(dev, np->phyaddr,
1261 PHY_REALTEK_INIT_REG2, phy_reserved))
1262 return PHY_ERROR;
1263 if (mii_rw(dev, np->phyaddr,
1264 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1265 return PHY_ERROR;
1266 }
1267
1268 return 0;
1269 }
1270
1271 static int init_cicada(struct net_device *dev, struct fe_priv *np,
1272 u32 phyinterface)
1273 {
1274 u32 phy_reserved;
1275
1276 if (phyinterface & PHY_RGMII) {
1277 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1278 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1279 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1280 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1281 return PHY_ERROR;
1282 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1283 phy_reserved |= PHY_CICADA_INIT5;
1284 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1285 return PHY_ERROR;
1286 }
1287 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1288 phy_reserved |= PHY_CICADA_INIT6;
1289 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1290 return PHY_ERROR;
1291
1292 return 0;
1293 }
1294
1295 static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1296 {
1297 u32 phy_reserved;
1298
1299 if (mii_rw(dev, np->phyaddr,
1300 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1301 return PHY_ERROR;
1302 if (mii_rw(dev, np->phyaddr,
1303 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1304 return PHY_ERROR;
1305 phy_reserved = mii_rw(dev, np->phyaddr,
1306 PHY_VITESSE_INIT_REG4, MII_READ);
1307 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1308 return PHY_ERROR;
1309 phy_reserved = mii_rw(dev, np->phyaddr,
1310 PHY_VITESSE_INIT_REG3, MII_READ);
1311 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1312 phy_reserved |= PHY_VITESSE_INIT3;
1313 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1314 return PHY_ERROR;
1315 if (mii_rw(dev, np->phyaddr,
1316 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1317 return PHY_ERROR;
1318 if (mii_rw(dev, np->phyaddr,
1319 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1320 return PHY_ERROR;
1321 phy_reserved = mii_rw(dev, np->phyaddr,
1322 PHY_VITESSE_INIT_REG4, MII_READ);
1323 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1324 phy_reserved |= PHY_VITESSE_INIT3;
1325 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1326 return PHY_ERROR;
1327 phy_reserved = mii_rw(dev, np->phyaddr,
1328 PHY_VITESSE_INIT_REG3, MII_READ);
1329 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1330 return PHY_ERROR;
1331 if (mii_rw(dev, np->phyaddr,
1332 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1333 return PHY_ERROR;
1334 if (mii_rw(dev, np->phyaddr,
1335 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1336 return PHY_ERROR;
1337 phy_reserved = mii_rw(dev, np->phyaddr,
1338 PHY_VITESSE_INIT_REG4, MII_READ);
1339 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1340 return PHY_ERROR;
1341 phy_reserved = mii_rw(dev, np->phyaddr,
1342 PHY_VITESSE_INIT_REG3, MII_READ);
1343 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1344 phy_reserved |= PHY_VITESSE_INIT8;
1345 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1346 return PHY_ERROR;
1347 if (mii_rw(dev, np->phyaddr,
1348 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1349 return PHY_ERROR;
1350 if (mii_rw(dev, np->phyaddr,
1351 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1352 return PHY_ERROR;
1353
1354 return 0;
1355 }
1356
1357 static int phy_init(struct net_device *dev)
1358 {
1359 struct fe_priv *np = get_nvpriv(dev);
1360 u8 __iomem *base = get_hwbase(dev);
1361 u32 phyinterface;
1362 u32 mii_status, mii_control, mii_control_1000, reg;
1363
1364 /* phy errata for E3016 phy */
1365 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1366 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1367 reg &= ~PHY_MARVELL_E3016_INITMASK;
1368 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1369 netdev_info(dev, "%s: phy write to errata reg failed\n",
1370 pci_name(np->pci_dev));
1371 return PHY_ERROR;
1372 }
1373 }
1374 if (np->phy_oui == PHY_OUI_REALTEK) {
1375 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1376 np->phy_rev == PHY_REV_REALTEK_8211B) {
1377 if (init_realtek_8211b(dev, np)) {
1378 netdev_info(dev, "%s: phy init failed\n",
1379 pci_name(np->pci_dev));
1380 return PHY_ERROR;
1381 }
1382 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1383 np->phy_rev == PHY_REV_REALTEK_8211C) {
1384 if (init_realtek_8211c(dev, np)) {
1385 netdev_info(dev, "%s: phy init failed\n",
1386 pci_name(np->pci_dev));
1387 return PHY_ERROR;
1388 }
1389 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1390 if (init_realtek_8201(dev, np)) {
1391 netdev_info(dev, "%s: phy init failed\n",
1392 pci_name(np->pci_dev));
1393 return PHY_ERROR;
1394 }
1395 }
1396 }
1397
1398 /* set advertise register */
1399 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1400 reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1401 ADVERTISE_100HALF | ADVERTISE_100FULL |
1402 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1403 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1404 netdev_info(dev, "%s: phy write to advertise failed\n",
1405 pci_name(np->pci_dev));
1406 return PHY_ERROR;
1407 }
1408
1409 /* get phy interface type */
1410 phyinterface = readl(base + NvRegPhyInterface);
1411
1412 /* see if gigabit phy */
1413 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1414 if (mii_status & PHY_GIGABIT) {
1415 np->gigabit = PHY_GIGABIT;
1416 mii_control_1000 = mii_rw(dev, np->phyaddr,
1417 MII_CTRL1000, MII_READ);
1418 mii_control_1000 &= ~ADVERTISE_1000HALF;
1419 if (phyinterface & PHY_RGMII)
1420 mii_control_1000 |= ADVERTISE_1000FULL;
1421 else
1422 mii_control_1000 &= ~ADVERTISE_1000FULL;
1423
1424 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1425 netdev_info(dev, "%s: phy init failed\n",
1426 pci_name(np->pci_dev));
1427 return PHY_ERROR;
1428 }
1429 } else
1430 np->gigabit = 0;
1431
1432 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1433 mii_control |= BMCR_ANENABLE;
1434
1435 if (np->phy_oui == PHY_OUI_REALTEK &&
1436 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1437 np->phy_rev == PHY_REV_REALTEK_8211C) {
1438 /* start autoneg since we already performed hw reset above */
1439 mii_control |= BMCR_ANRESTART;
1440 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1441 netdev_info(dev, "%s: phy init failed\n",
1442 pci_name(np->pci_dev));
1443 return PHY_ERROR;
1444 }
1445 } else {
1446 /* reset the phy
1447 * (certain phys need bmcr to be setup with reset)
1448 */
1449 if (phy_reset(dev, mii_control)) {
1450 netdev_info(dev, "%s: phy reset failed\n",
1451 pci_name(np->pci_dev));
1452 return PHY_ERROR;
1453 }
1454 }
1455
1456 /* phy vendor specific configuration */
1457 if ((np->phy_oui == PHY_OUI_CICADA)) {
1458 if (init_cicada(dev, np, phyinterface)) {
1459 netdev_info(dev, "%s: phy init failed\n",
1460 pci_name(np->pci_dev));
1461 return PHY_ERROR;
1462 }
1463 } else if (np->phy_oui == PHY_OUI_VITESSE) {
1464 if (init_vitesse(dev, np)) {
1465 netdev_info(dev, "%s: phy init failed\n",
1466 pci_name(np->pci_dev));
1467 return PHY_ERROR;
1468 }
1469 } else if (np->phy_oui == PHY_OUI_REALTEK) {
1470 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1471 np->phy_rev == PHY_REV_REALTEK_8211B) {
1472 /* reset could have cleared these out, set them back */
1473 if (init_realtek_8211b(dev, np)) {
1474 netdev_info(dev, "%s: phy init failed\n",
1475 pci_name(np->pci_dev));
1476 return PHY_ERROR;
1477 }
1478 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1479 if (init_realtek_8201(dev, np) ||
1480 init_realtek_8201_cross(dev, np)) {
1481 netdev_info(dev, "%s: phy init failed\n",
1482 pci_name(np->pci_dev));
1483 return PHY_ERROR;
1484 }
1485 }
1486 }
1487
1488 /* some phys clear out pause advertisement on reset, set it back */
1489 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1490
1491 /* restart auto negotiation, power down phy */
1492 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1493 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1494 if (phy_power_down)
1495 mii_control |= BMCR_PDOWN;
1496 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1497 return PHY_ERROR;
1498
1499 return 0;
1500 }
1501
1502 static void nv_start_rx(struct net_device *dev)
1503 {
1504 struct fe_priv *np = netdev_priv(dev);
1505 u8 __iomem *base = get_hwbase(dev);
1506 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1507
1508 /* Already running? Stop it. */
1509 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1510 rx_ctrl &= ~NVREG_RCVCTL_START;
1511 writel(rx_ctrl, base + NvRegReceiverControl);
1512 pci_push(base);
1513 }
1514 writel(np->linkspeed, base + NvRegLinkSpeed);
1515 pci_push(base);
1516 rx_ctrl |= NVREG_RCVCTL_START;
1517 if (np->mac_in_use)
1518 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1519 writel(rx_ctrl, base + NvRegReceiverControl);
1520 pci_push(base);
1521 }
1522
1523 static void nv_stop_rx(struct net_device *dev)
1524 {
1525 struct fe_priv *np = netdev_priv(dev);
1526 u8 __iomem *base = get_hwbase(dev);
1527 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1528
1529 if (!np->mac_in_use)
1530 rx_ctrl &= ~NVREG_RCVCTL_START;
1531 else
1532 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1533 writel(rx_ctrl, base + NvRegReceiverControl);
1534 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1535 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1536 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1537 __func__);
1538
1539 udelay(NV_RXSTOP_DELAY2);
1540 if (!np->mac_in_use)
1541 writel(0, base + NvRegLinkSpeed);
1542 }
1543
1544 static void nv_start_tx(struct net_device *dev)
1545 {
1546 struct fe_priv *np = netdev_priv(dev);
1547 u8 __iomem *base = get_hwbase(dev);
1548 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1549
1550 tx_ctrl |= NVREG_XMITCTL_START;
1551 if (np->mac_in_use)
1552 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1553 writel(tx_ctrl, base + NvRegTransmitterControl);
1554 pci_push(base);
1555 }
1556
1557 static void nv_stop_tx(struct net_device *dev)
1558 {
1559 struct fe_priv *np = netdev_priv(dev);
1560 u8 __iomem *base = get_hwbase(dev);
1561 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1562
1563 if (!np->mac_in_use)
1564 tx_ctrl &= ~NVREG_XMITCTL_START;
1565 else
1566 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1567 writel(tx_ctrl, base + NvRegTransmitterControl);
1568 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1569 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1570 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1571 __func__);
1572
1573 udelay(NV_TXSTOP_DELAY2);
1574 if (!np->mac_in_use)
1575 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1576 base + NvRegTransmitPoll);
1577 }
1578
1579 static void nv_start_rxtx(struct net_device *dev)
1580 {
1581 nv_start_rx(dev);
1582 nv_start_tx(dev);
1583 }
1584
1585 static void nv_stop_rxtx(struct net_device *dev)
1586 {
1587 nv_stop_rx(dev);
1588 nv_stop_tx(dev);
1589 }
1590
1591 static void nv_txrx_reset(struct net_device *dev)
1592 {
1593 struct fe_priv *np = netdev_priv(dev);
1594 u8 __iomem *base = get_hwbase(dev);
1595
1596 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1597 pci_push(base);
1598 udelay(NV_TXRX_RESET_DELAY);
1599 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1600 pci_push(base);
1601 }
1602
1603 static void nv_mac_reset(struct net_device *dev)
1604 {
1605 struct fe_priv *np = netdev_priv(dev);
1606 u8 __iomem *base = get_hwbase(dev);
1607 u32 temp1, temp2, temp3;
1608
1609 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1610 pci_push(base);
1611
1612 /* save registers since they will be cleared on reset */
1613 temp1 = readl(base + NvRegMacAddrA);
1614 temp2 = readl(base + NvRegMacAddrB);
1615 temp3 = readl(base + NvRegTransmitPoll);
1616
1617 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1618 pci_push(base);
1619 udelay(NV_MAC_RESET_DELAY);
1620 writel(0, base + NvRegMacReset);
1621 pci_push(base);
1622 udelay(NV_MAC_RESET_DELAY);
1623
1624 /* restore saved registers */
1625 writel(temp1, base + NvRegMacAddrA);
1626 writel(temp2, base + NvRegMacAddrB);
1627 writel(temp3, base + NvRegTransmitPoll);
1628
1629 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1630 pci_push(base);
1631 }
1632
1633 static void nv_get_hw_stats(struct net_device *dev)
1634 {
1635 struct fe_priv *np = netdev_priv(dev);
1636 u8 __iomem *base = get_hwbase(dev);
1637
1638 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1639 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1640 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1641 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1642 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1643 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1644 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1645 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1646 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1647 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1648 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1649 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1650 np->estats.rx_runt += readl(base + NvRegRxRunt);
1651 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1652 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1653 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1654 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1655 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1656 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1657 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1658 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1659 np->estats.rx_packets =
1660 np->estats.rx_unicast +
1661 np->estats.rx_multicast +
1662 np->estats.rx_broadcast;
1663 np->estats.rx_errors_total =
1664 np->estats.rx_crc_errors +
1665 np->estats.rx_over_errors +
1666 np->estats.rx_frame_error +
1667 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1668 np->estats.rx_late_collision +
1669 np->estats.rx_runt +
1670 np->estats.rx_frame_too_long;
1671 np->estats.tx_errors_total =
1672 np->estats.tx_late_collision +
1673 np->estats.tx_fifo_errors +
1674 np->estats.tx_carrier_errors +
1675 np->estats.tx_excess_deferral +
1676 np->estats.tx_retry_error;
1677
1678 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1679 np->estats.tx_deferral += readl(base + NvRegTxDef);
1680 np->estats.tx_packets += readl(base + NvRegTxFrame);
1681 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1682 np->estats.tx_pause += readl(base + NvRegTxPause);
1683 np->estats.rx_pause += readl(base + NvRegRxPause);
1684 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1685 }
1686
1687 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1688 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1689 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1690 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1691 }
1692 }
1693
1694 /*
1695 * nv_get_stats: dev->get_stats function
1696 * Get latest stats value from the nic.
1697 * Called with read_lock(&dev_base_lock) held for read -
1698 * only synchronized against unregister_netdevice.
1699 */
1700 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1701 {
1702 struct fe_priv *np = netdev_priv(dev);
1703
1704 /* If the nic supports hw counters then retrieve latest values */
1705 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1706 nv_get_hw_stats(dev);
1707
1708 /* copy to net_device stats */
1709 dev->stats.tx_bytes = np->estats.tx_bytes;
1710 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1711 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1712 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1713 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1714 dev->stats.rx_errors = np->estats.rx_errors_total;
1715 dev->stats.tx_errors = np->estats.tx_errors_total;
1716 }
1717
1718 return &dev->stats;
1719 }
1720
1721 /*
1722 * nv_alloc_rx: fill rx ring entries.
1723 * Return 1 if the allocations for the skbs failed and the
1724 * rx engine is without Available descriptors
1725 */
1726 static int nv_alloc_rx(struct net_device *dev)
1727 {
1728 struct fe_priv *np = netdev_priv(dev);
1729 struct ring_desc *less_rx;
1730
1731 less_rx = np->get_rx.orig;
1732 if (less_rx-- == np->first_rx.orig)
1733 less_rx = np->last_rx.orig;
1734
1735 while (np->put_rx.orig != less_rx) {
1736 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1737 if (skb) {
1738 np->put_rx_ctx->skb = skb;
1739 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1740 skb->data,
1741 skb_tailroom(skb),
1742 PCI_DMA_FROMDEVICE);
1743 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1744 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1745 wmb();
1746 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1747 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1748 np->put_rx.orig = np->first_rx.orig;
1749 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1750 np->put_rx_ctx = np->first_rx_ctx;
1751 } else
1752 return 1;
1753 }
1754 return 0;
1755 }
1756
1757 static int nv_alloc_rx_optimized(struct net_device *dev)
1758 {
1759 struct fe_priv *np = netdev_priv(dev);
1760 struct ring_desc_ex *less_rx;
1761
1762 less_rx = np->get_rx.ex;
1763 if (less_rx-- == np->first_rx.ex)
1764 less_rx = np->last_rx.ex;
1765
1766 while (np->put_rx.ex != less_rx) {
1767 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1768 if (skb) {
1769 np->put_rx_ctx->skb = skb;
1770 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1771 skb->data,
1772 skb_tailroom(skb),
1773 PCI_DMA_FROMDEVICE);
1774 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1775 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1776 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1777 wmb();
1778 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1779 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1780 np->put_rx.ex = np->first_rx.ex;
1781 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1782 np->put_rx_ctx = np->first_rx_ctx;
1783 } else
1784 return 1;
1785 }
1786 return 0;
1787 }
1788
1789 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1790 static void nv_do_rx_refill(unsigned long data)
1791 {
1792 struct net_device *dev = (struct net_device *) data;
1793 struct fe_priv *np = netdev_priv(dev);
1794
1795 /* Just reschedule NAPI rx processing */
1796 napi_schedule(&np->napi);
1797 }
1798
1799 static void nv_init_rx(struct net_device *dev)
1800 {
1801 struct fe_priv *np = netdev_priv(dev);
1802 int i;
1803
1804 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1805
1806 if (!nv_optimized(np))
1807 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1808 else
1809 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1810 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1811 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1812
1813 for (i = 0; i < np->rx_ring_size; i++) {
1814 if (!nv_optimized(np)) {
1815 np->rx_ring.orig[i].flaglen = 0;
1816 np->rx_ring.orig[i].buf = 0;
1817 } else {
1818 np->rx_ring.ex[i].flaglen = 0;
1819 np->rx_ring.ex[i].txvlan = 0;
1820 np->rx_ring.ex[i].bufhigh = 0;
1821 np->rx_ring.ex[i].buflow = 0;
1822 }
1823 np->rx_skb[i].skb = NULL;
1824 np->rx_skb[i].dma = 0;
1825 }
1826 }
1827
1828 static void nv_init_tx(struct net_device *dev)
1829 {
1830 struct fe_priv *np = netdev_priv(dev);
1831 int i;
1832
1833 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1834
1835 if (!nv_optimized(np))
1836 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1837 else
1838 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1839 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1840 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1841 np->tx_pkts_in_progress = 0;
1842 np->tx_change_owner = NULL;
1843 np->tx_end_flip = NULL;
1844 np->tx_stop = 0;
1845
1846 for (i = 0; i < np->tx_ring_size; i++) {
1847 if (!nv_optimized(np)) {
1848 np->tx_ring.orig[i].flaglen = 0;
1849 np->tx_ring.orig[i].buf = 0;
1850 } else {
1851 np->tx_ring.ex[i].flaglen = 0;
1852 np->tx_ring.ex[i].txvlan = 0;
1853 np->tx_ring.ex[i].bufhigh = 0;
1854 np->tx_ring.ex[i].buflow = 0;
1855 }
1856 np->tx_skb[i].skb = NULL;
1857 np->tx_skb[i].dma = 0;
1858 np->tx_skb[i].dma_len = 0;
1859 np->tx_skb[i].dma_single = 0;
1860 np->tx_skb[i].first_tx_desc = NULL;
1861 np->tx_skb[i].next_tx_ctx = NULL;
1862 }
1863 }
1864
1865 static int nv_init_ring(struct net_device *dev)
1866 {
1867 struct fe_priv *np = netdev_priv(dev);
1868
1869 nv_init_tx(dev);
1870 nv_init_rx(dev);
1871
1872 if (!nv_optimized(np))
1873 return nv_alloc_rx(dev);
1874 else
1875 return nv_alloc_rx_optimized(dev);
1876 }
1877
1878 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1879 {
1880 if (tx_skb->dma) {
1881 if (tx_skb->dma_single)
1882 pci_unmap_single(np->pci_dev, tx_skb->dma,
1883 tx_skb->dma_len,
1884 PCI_DMA_TODEVICE);
1885 else
1886 pci_unmap_page(np->pci_dev, tx_skb->dma,
1887 tx_skb->dma_len,
1888 PCI_DMA_TODEVICE);
1889 tx_skb->dma = 0;
1890 }
1891 }
1892
1893 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1894 {
1895 nv_unmap_txskb(np, tx_skb);
1896 if (tx_skb->skb) {
1897 dev_kfree_skb_any(tx_skb->skb);
1898 tx_skb->skb = NULL;
1899 return 1;
1900 }
1901 return 0;
1902 }
1903
1904 static void nv_drain_tx(struct net_device *dev)
1905 {
1906 struct fe_priv *np = netdev_priv(dev);
1907 unsigned int i;
1908
1909 for (i = 0; i < np->tx_ring_size; i++) {
1910 if (!nv_optimized(np)) {
1911 np->tx_ring.orig[i].flaglen = 0;
1912 np->tx_ring.orig[i].buf = 0;
1913 } else {
1914 np->tx_ring.ex[i].flaglen = 0;
1915 np->tx_ring.ex[i].txvlan = 0;
1916 np->tx_ring.ex[i].bufhigh = 0;
1917 np->tx_ring.ex[i].buflow = 0;
1918 }
1919 if (nv_release_txskb(np, &np->tx_skb[i]))
1920 dev->stats.tx_dropped++;
1921 np->tx_skb[i].dma = 0;
1922 np->tx_skb[i].dma_len = 0;
1923 np->tx_skb[i].dma_single = 0;
1924 np->tx_skb[i].first_tx_desc = NULL;
1925 np->tx_skb[i].next_tx_ctx = NULL;
1926 }
1927 np->tx_pkts_in_progress = 0;
1928 np->tx_change_owner = NULL;
1929 np->tx_end_flip = NULL;
1930 }
1931
1932 static void nv_drain_rx(struct net_device *dev)
1933 {
1934 struct fe_priv *np = netdev_priv(dev);
1935 int i;
1936
1937 for (i = 0; i < np->rx_ring_size; i++) {
1938 if (!nv_optimized(np)) {
1939 np->rx_ring.orig[i].flaglen = 0;
1940 np->rx_ring.orig[i].buf = 0;
1941 } else {
1942 np->rx_ring.ex[i].flaglen = 0;
1943 np->rx_ring.ex[i].txvlan = 0;
1944 np->rx_ring.ex[i].bufhigh = 0;
1945 np->rx_ring.ex[i].buflow = 0;
1946 }
1947 wmb();
1948 if (np->rx_skb[i].skb) {
1949 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1950 (skb_end_pointer(np->rx_skb[i].skb) -
1951 np->rx_skb[i].skb->data),
1952 PCI_DMA_FROMDEVICE);
1953 dev_kfree_skb(np->rx_skb[i].skb);
1954 np->rx_skb[i].skb = NULL;
1955 }
1956 }
1957 }
1958
1959 static void nv_drain_rxtx(struct net_device *dev)
1960 {
1961 nv_drain_tx(dev);
1962 nv_drain_rx(dev);
1963 }
1964
1965 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1966 {
1967 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1968 }
1969
1970 static void nv_legacybackoff_reseed(struct net_device *dev)
1971 {
1972 u8 __iomem *base = get_hwbase(dev);
1973 u32 reg;
1974 u32 low;
1975 int tx_status = 0;
1976
1977 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1978 get_random_bytes(&low, sizeof(low));
1979 reg |= low & NVREG_SLOTTIME_MASK;
1980
1981 /* Need to stop tx before change takes effect.
1982 * Caller has already gained np->lock.
1983 */
1984 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1985 if (tx_status)
1986 nv_stop_tx(dev);
1987 nv_stop_rx(dev);
1988 writel(reg, base + NvRegSlotTime);
1989 if (tx_status)
1990 nv_start_tx(dev);
1991 nv_start_rx(dev);
1992 }
1993
1994 /* Gear Backoff Seeds */
1995 #define BACKOFF_SEEDSET_ROWS 8
1996 #define BACKOFF_SEEDSET_LFSRS 15
1997
1998 /* Known Good seed sets */
1999 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2000 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2001 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2002 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2003 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2004 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2005 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2006 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2007 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2008
2009 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2010 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2011 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2012 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2013 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2014 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2015 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2016 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2017 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2018
2019 static void nv_gear_backoff_reseed(struct net_device *dev)
2020 {
2021 u8 __iomem *base = get_hwbase(dev);
2022 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2023 u32 temp, seedset, combinedSeed;
2024 int i;
2025
2026 /* Setup seed for free running LFSR */
2027 /* We are going to read the time stamp counter 3 times
2028 and swizzle bits around to increase randomness */
2029 get_random_bytes(&miniseed1, sizeof(miniseed1));
2030 miniseed1 &= 0x0fff;
2031 if (miniseed1 == 0)
2032 miniseed1 = 0xabc;
2033
2034 get_random_bytes(&miniseed2, sizeof(miniseed2));
2035 miniseed2 &= 0x0fff;
2036 if (miniseed2 == 0)
2037 miniseed2 = 0xabc;
2038 miniseed2_reversed =
2039 ((miniseed2 & 0xF00) >> 8) |
2040 (miniseed2 & 0x0F0) |
2041 ((miniseed2 & 0x00F) << 8);
2042
2043 get_random_bytes(&miniseed3, sizeof(miniseed3));
2044 miniseed3 &= 0x0fff;
2045 if (miniseed3 == 0)
2046 miniseed3 = 0xabc;
2047 miniseed3_reversed =
2048 ((miniseed3 & 0xF00) >> 8) |
2049 (miniseed3 & 0x0F0) |
2050 ((miniseed3 & 0x00F) << 8);
2051
2052 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2053 (miniseed2 ^ miniseed3_reversed);
2054
2055 /* Seeds can not be zero */
2056 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2057 combinedSeed |= 0x08;
2058 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2059 combinedSeed |= 0x8000;
2060
2061 /* No need to disable tx here */
2062 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2063 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2064 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2065 writel(temp, base + NvRegBackOffControl);
2066
2067 /* Setup seeds for all gear LFSRs. */
2068 get_random_bytes(&seedset, sizeof(seedset));
2069 seedset = seedset % BACKOFF_SEEDSET_ROWS;
2070 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2071 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2072 temp |= main_seedset[seedset][i-1] & 0x3ff;
2073 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2074 writel(temp, base + NvRegBackOffControl);
2075 }
2076 }
2077
2078 /*
2079 * nv_start_xmit: dev->hard_start_xmit function
2080 * Called with netif_tx_lock held.
2081 */
2082 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2083 {
2084 struct fe_priv *np = netdev_priv(dev);
2085 u32 tx_flags = 0;
2086 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2087 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2088 unsigned int i;
2089 u32 offset = 0;
2090 u32 bcnt;
2091 u32 size = skb_headlen(skb);
2092 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2093 u32 empty_slots;
2094 struct ring_desc *put_tx;
2095 struct ring_desc *start_tx;
2096 struct ring_desc *prev_tx;
2097 struct nv_skb_map *prev_tx_ctx;
2098 unsigned long flags;
2099
2100 /* add fragments to entries count */
2101 for (i = 0; i < fragments; i++) {
2102 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2103 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2104 }
2105
2106 spin_lock_irqsave(&np->lock, flags);
2107 empty_slots = nv_get_empty_tx_slots(np);
2108 if (unlikely(empty_slots <= entries)) {
2109 netif_stop_queue(dev);
2110 np->tx_stop = 1;
2111 spin_unlock_irqrestore(&np->lock, flags);
2112 return NETDEV_TX_BUSY;
2113 }
2114 spin_unlock_irqrestore(&np->lock, flags);
2115
2116 start_tx = put_tx = np->put_tx.orig;
2117
2118 /* setup the header buffer */
2119 do {
2120 prev_tx = put_tx;
2121 prev_tx_ctx = np->put_tx_ctx;
2122 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2123 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2124 PCI_DMA_TODEVICE);
2125 np->put_tx_ctx->dma_len = bcnt;
2126 np->put_tx_ctx->dma_single = 1;
2127 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2128 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2129
2130 tx_flags = np->tx_flags;
2131 offset += bcnt;
2132 size -= bcnt;
2133 if (unlikely(put_tx++ == np->last_tx.orig))
2134 put_tx = np->first_tx.orig;
2135 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2136 np->put_tx_ctx = np->first_tx_ctx;
2137 } while (size);
2138
2139 /* setup the fragments */
2140 for (i = 0; i < fragments; i++) {
2141 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2142 u32 size = frag->size;
2143 offset = 0;
2144
2145 do {
2146 prev_tx = put_tx;
2147 prev_tx_ctx = np->put_tx_ctx;
2148 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2149 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2150 PCI_DMA_TODEVICE);
2151 np->put_tx_ctx->dma_len = bcnt;
2152 np->put_tx_ctx->dma_single = 0;
2153 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2154 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2155
2156 offset += bcnt;
2157 size -= bcnt;
2158 if (unlikely(put_tx++ == np->last_tx.orig))
2159 put_tx = np->first_tx.orig;
2160 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2161 np->put_tx_ctx = np->first_tx_ctx;
2162 } while (size);
2163 }
2164
2165 /* set last fragment flag */
2166 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2167
2168 /* save skb in this slot's context area */
2169 prev_tx_ctx->skb = skb;
2170
2171 if (skb_is_gso(skb))
2172 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2173 else
2174 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2175 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2176
2177 spin_lock_irqsave(&np->lock, flags);
2178
2179 /* set tx flags */
2180 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2181 np->put_tx.orig = put_tx;
2182
2183 spin_unlock_irqrestore(&np->lock, flags);
2184
2185 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2186 return NETDEV_TX_OK;
2187 }
2188
2189 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2190 struct net_device *dev)
2191 {
2192 struct fe_priv *np = netdev_priv(dev);
2193 u32 tx_flags = 0;
2194 u32 tx_flags_extra;
2195 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2196 unsigned int i;
2197 u32 offset = 0;
2198 u32 bcnt;
2199 u32 size = skb_headlen(skb);
2200 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2201 u32 empty_slots;
2202 struct ring_desc_ex *put_tx;
2203 struct ring_desc_ex *start_tx;
2204 struct ring_desc_ex *prev_tx;
2205 struct nv_skb_map *prev_tx_ctx;
2206 struct nv_skb_map *start_tx_ctx;
2207 unsigned long flags;
2208
2209 /* add fragments to entries count */
2210 for (i = 0; i < fragments; i++) {
2211 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2212 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2213 }
2214
2215 spin_lock_irqsave(&np->lock, flags);
2216 empty_slots = nv_get_empty_tx_slots(np);
2217 if (unlikely(empty_slots <= entries)) {
2218 netif_stop_queue(dev);
2219 np->tx_stop = 1;
2220 spin_unlock_irqrestore(&np->lock, flags);
2221 return NETDEV_TX_BUSY;
2222 }
2223 spin_unlock_irqrestore(&np->lock, flags);
2224
2225 start_tx = put_tx = np->put_tx.ex;
2226 start_tx_ctx = np->put_tx_ctx;
2227
2228 /* setup the header buffer */
2229 do {
2230 prev_tx = put_tx;
2231 prev_tx_ctx = np->put_tx_ctx;
2232 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2233 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2234 PCI_DMA_TODEVICE);
2235 np->put_tx_ctx->dma_len = bcnt;
2236 np->put_tx_ctx->dma_single = 1;
2237 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2238 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2239 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2240
2241 tx_flags = NV_TX2_VALID;
2242 offset += bcnt;
2243 size -= bcnt;
2244 if (unlikely(put_tx++ == np->last_tx.ex))
2245 put_tx = np->first_tx.ex;
2246 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2247 np->put_tx_ctx = np->first_tx_ctx;
2248 } while (size);
2249
2250 /* setup the fragments */
2251 for (i = 0; i < fragments; i++) {
2252 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2253 u32 size = frag->size;
2254 offset = 0;
2255
2256 do {
2257 prev_tx = put_tx;
2258 prev_tx_ctx = np->put_tx_ctx;
2259 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2260 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2261 PCI_DMA_TODEVICE);
2262 np->put_tx_ctx->dma_len = bcnt;
2263 np->put_tx_ctx->dma_single = 0;
2264 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2265 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2266 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2267
2268 offset += bcnt;
2269 size -= bcnt;
2270 if (unlikely(put_tx++ == np->last_tx.ex))
2271 put_tx = np->first_tx.ex;
2272 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2273 np->put_tx_ctx = np->first_tx_ctx;
2274 } while (size);
2275 }
2276
2277 /* set last fragment flag */
2278 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2279
2280 /* save skb in this slot's context area */
2281 prev_tx_ctx->skb = skb;
2282
2283 if (skb_is_gso(skb))
2284 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2285 else
2286 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2287 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2288
2289 /* vlan tag */
2290 if (vlan_tx_tag_present(skb))
2291 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2292 vlan_tx_tag_get(skb));
2293 else
2294 start_tx->txvlan = 0;
2295
2296 spin_lock_irqsave(&np->lock, flags);
2297
2298 if (np->tx_limit) {
2299 /* Limit the number of outstanding tx. Setup all fragments, but
2300 * do not set the VALID bit on the first descriptor. Save a pointer
2301 * to that descriptor and also for next skb_map element.
2302 */
2303
2304 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2305 if (!np->tx_change_owner)
2306 np->tx_change_owner = start_tx_ctx;
2307
2308 /* remove VALID bit */
2309 tx_flags &= ~NV_TX2_VALID;
2310 start_tx_ctx->first_tx_desc = start_tx;
2311 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2312 np->tx_end_flip = np->put_tx_ctx;
2313 } else {
2314 np->tx_pkts_in_progress++;
2315 }
2316 }
2317
2318 /* set tx flags */
2319 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2320 np->put_tx.ex = put_tx;
2321
2322 spin_unlock_irqrestore(&np->lock, flags);
2323
2324 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2325 return NETDEV_TX_OK;
2326 }
2327
2328 static inline void nv_tx_flip_ownership(struct net_device *dev)
2329 {
2330 struct fe_priv *np = netdev_priv(dev);
2331
2332 np->tx_pkts_in_progress--;
2333 if (np->tx_change_owner) {
2334 np->tx_change_owner->first_tx_desc->flaglen |=
2335 cpu_to_le32(NV_TX2_VALID);
2336 np->tx_pkts_in_progress++;
2337
2338 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2339 if (np->tx_change_owner == np->tx_end_flip)
2340 np->tx_change_owner = NULL;
2341
2342 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2343 }
2344 }
2345
2346 /*
2347 * nv_tx_done: check for completed packets, release the skbs.
2348 *
2349 * Caller must own np->lock.
2350 */
2351 static int nv_tx_done(struct net_device *dev, int limit)
2352 {
2353 struct fe_priv *np = netdev_priv(dev);
2354 u32 flags;
2355 int tx_work = 0;
2356 struct ring_desc *orig_get_tx = np->get_tx.orig;
2357
2358 while ((np->get_tx.orig != np->put_tx.orig) &&
2359 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2360 (tx_work < limit)) {
2361
2362 nv_unmap_txskb(np, np->get_tx_ctx);
2363
2364 if (np->desc_ver == DESC_VER_1) {
2365 if (flags & NV_TX_LASTPACKET) {
2366 if (flags & NV_TX_ERROR) {
2367 if (flags & NV_TX_UNDERFLOW)
2368 dev->stats.tx_fifo_errors++;
2369 if (flags & NV_TX_CARRIERLOST)
2370 dev->stats.tx_carrier_errors++;
2371 if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2372 nv_legacybackoff_reseed(dev);
2373 dev->stats.tx_errors++;
2374 } else {
2375 dev->stats.tx_packets++;
2376 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2377 }
2378 dev_kfree_skb_any(np->get_tx_ctx->skb);
2379 np->get_tx_ctx->skb = NULL;
2380 tx_work++;
2381 }
2382 } else {
2383 if (flags & NV_TX2_LASTPACKET) {
2384 if (flags & NV_TX2_ERROR) {
2385 if (flags & NV_TX2_UNDERFLOW)
2386 dev->stats.tx_fifo_errors++;
2387 if (flags & NV_TX2_CARRIERLOST)
2388 dev->stats.tx_carrier_errors++;
2389 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2390 nv_legacybackoff_reseed(dev);
2391 dev->stats.tx_errors++;
2392 } else {
2393 dev->stats.tx_packets++;
2394 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2395 }
2396 dev_kfree_skb_any(np->get_tx_ctx->skb);
2397 np->get_tx_ctx->skb = NULL;
2398 tx_work++;
2399 }
2400 }
2401 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2402 np->get_tx.orig = np->first_tx.orig;
2403 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2404 np->get_tx_ctx = np->first_tx_ctx;
2405 }
2406 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2407 np->tx_stop = 0;
2408 netif_wake_queue(dev);
2409 }
2410 return tx_work;
2411 }
2412
2413 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2414 {
2415 struct fe_priv *np = netdev_priv(dev);
2416 u32 flags;
2417 int tx_work = 0;
2418 struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2419
2420 while ((np->get_tx.ex != np->put_tx.ex) &&
2421 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2422 (tx_work < limit)) {
2423
2424 nv_unmap_txskb(np, np->get_tx_ctx);
2425
2426 if (flags & NV_TX2_LASTPACKET) {
2427 if (!(flags & NV_TX2_ERROR))
2428 dev->stats.tx_packets++;
2429 else {
2430 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2431 if (np->driver_data & DEV_HAS_GEAR_MODE)
2432 nv_gear_backoff_reseed(dev);
2433 else
2434 nv_legacybackoff_reseed(dev);
2435 }
2436 }
2437
2438 dev_kfree_skb_any(np->get_tx_ctx->skb);
2439 np->get_tx_ctx->skb = NULL;
2440 tx_work++;
2441
2442 if (np->tx_limit)
2443 nv_tx_flip_ownership(dev);
2444 }
2445 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2446 np->get_tx.ex = np->first_tx.ex;
2447 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2448 np->get_tx_ctx = np->first_tx_ctx;
2449 }
2450 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2451 np->tx_stop = 0;
2452 netif_wake_queue(dev);
2453 }
2454 return tx_work;
2455 }
2456
2457 /*
2458 * nv_tx_timeout: dev->tx_timeout function
2459 * Called with netif_tx_lock held.
2460 */
2461 static void nv_tx_timeout(struct net_device *dev)
2462 {
2463 struct fe_priv *np = netdev_priv(dev);
2464 u8 __iomem *base = get_hwbase(dev);
2465 u32 status;
2466 union ring_type put_tx;
2467 int saved_tx_limit;
2468 int i;
2469
2470 if (np->msi_flags & NV_MSI_X_ENABLED)
2471 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2472 else
2473 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2474
2475 netdev_info(dev, "Got tx_timeout. irq: %08x\n", status);
2476
2477 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2478 netdev_info(dev, "Dumping tx registers\n");
2479 for (i = 0; i <= np->register_size; i += 32) {
2480 netdev_info(dev,
2481 "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2482 i,
2483 readl(base + i + 0), readl(base + i + 4),
2484 readl(base + i + 8), readl(base + i + 12),
2485 readl(base + i + 16), readl(base + i + 20),
2486 readl(base + i + 24), readl(base + i + 28));
2487 }
2488 netdev_info(dev, "Dumping tx ring\n");
2489 for (i = 0; i < np->tx_ring_size; i += 4) {
2490 if (!nv_optimized(np)) {
2491 netdev_info(dev,
2492 "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2493 i,
2494 le32_to_cpu(np->tx_ring.orig[i].buf),
2495 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2496 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2497 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2498 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2499 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2500 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2501 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2502 } else {
2503 netdev_info(dev,
2504 "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2505 i,
2506 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2507 le32_to_cpu(np->tx_ring.ex[i].buflow),
2508 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2509 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2510 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2511 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2512 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2513 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2514 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2515 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2516 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2517 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2518 }
2519 }
2520
2521 spin_lock_irq(&np->lock);
2522
2523 /* 1) stop tx engine */
2524 nv_stop_tx(dev);
2525
2526 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2527 saved_tx_limit = np->tx_limit;
2528 np->tx_limit = 0; /* prevent giving HW any limited pkts */
2529 np->tx_stop = 0; /* prevent waking tx queue */
2530 if (!nv_optimized(np))
2531 nv_tx_done(dev, np->tx_ring_size);
2532 else
2533 nv_tx_done_optimized(dev, np->tx_ring_size);
2534
2535 /* save current HW position */
2536 if (np->tx_change_owner)
2537 put_tx.ex = np->tx_change_owner->first_tx_desc;
2538 else
2539 put_tx = np->put_tx;
2540
2541 /* 3) clear all tx state */
2542 nv_drain_tx(dev);
2543 nv_init_tx(dev);
2544
2545 /* 4) restore state to current HW position */
2546 np->get_tx = np->put_tx = put_tx;
2547 np->tx_limit = saved_tx_limit;
2548
2549 /* 5) restart tx engine */
2550 nv_start_tx(dev);
2551 netif_wake_queue(dev);
2552 spin_unlock_irq(&np->lock);
2553 }
2554
2555 /*
2556 * Called when the nic notices a mismatch between the actual data len on the
2557 * wire and the len indicated in the 802 header
2558 */
2559 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2560 {
2561 int hdrlen; /* length of the 802 header */
2562 int protolen; /* length as stored in the proto field */
2563
2564 /* 1) calculate len according to header */
2565 if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2566 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2567 hdrlen = VLAN_HLEN;
2568 } else {
2569 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2570 hdrlen = ETH_HLEN;
2571 }
2572 if (protolen > ETH_DATA_LEN)
2573 return datalen; /* Value in proto field not a len, no checks possible */
2574
2575 protolen += hdrlen;
2576 /* consistency checks: */
2577 if (datalen > ETH_ZLEN) {
2578 if (datalen >= protolen) {
2579 /* more data on wire than in 802 header, trim of
2580 * additional data.
2581 */
2582 return protolen;
2583 } else {
2584 /* less data on wire than mentioned in header.
2585 * Discard the packet.
2586 */
2587 return -1;
2588 }
2589 } else {
2590 /* short packet. Accept only if 802 values are also short */
2591 if (protolen > ETH_ZLEN) {
2592 return -1;
2593 }
2594 return datalen;
2595 }
2596 }
2597
2598 static int nv_rx_process(struct net_device *dev, int limit)
2599 {
2600 struct fe_priv *np = netdev_priv(dev);
2601 u32 flags;
2602 int rx_work = 0;
2603 struct sk_buff *skb;
2604 int len;
2605
2606 while ((np->get_rx.orig != np->put_rx.orig) &&
2607 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2608 (rx_work < limit)) {
2609
2610 /*
2611 * the packet is for us - immediately tear down the pci mapping.
2612 * TODO: check if a prefetch of the first cacheline improves
2613 * the performance.
2614 */
2615 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2616 np->get_rx_ctx->dma_len,
2617 PCI_DMA_FROMDEVICE);
2618 skb = np->get_rx_ctx->skb;
2619 np->get_rx_ctx->skb = NULL;
2620
2621 /* look at what we actually got: */
2622 if (np->desc_ver == DESC_VER_1) {
2623 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2624 len = flags & LEN_MASK_V1;
2625 if (unlikely(flags & NV_RX_ERROR)) {
2626 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2627 len = nv_getlen(dev, skb->data, len);
2628 if (len < 0) {
2629 dev->stats.rx_errors++;
2630 dev_kfree_skb(skb);
2631 goto next_pkt;
2632 }
2633 }
2634 /* framing errors are soft errors */
2635 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2636 if (flags & NV_RX_SUBSTRACT1)
2637 len--;
2638 }
2639 /* the rest are hard errors */
2640 else {
2641 if (flags & NV_RX_MISSEDFRAME)
2642 dev->stats.rx_missed_errors++;
2643 if (flags & NV_RX_CRCERR)
2644 dev->stats.rx_crc_errors++;
2645 if (flags & NV_RX_OVERFLOW)
2646 dev->stats.rx_over_errors++;
2647 dev->stats.rx_errors++;
2648 dev_kfree_skb(skb);
2649 goto next_pkt;
2650 }
2651 }
2652 } else {
2653 dev_kfree_skb(skb);
2654 goto next_pkt;
2655 }
2656 } else {
2657 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2658 len = flags & LEN_MASK_V2;
2659 if (unlikely(flags & NV_RX2_ERROR)) {
2660 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2661 len = nv_getlen(dev, skb->data, len);
2662 if (len < 0) {
2663 dev->stats.rx_errors++;
2664 dev_kfree_skb(skb);
2665 goto next_pkt;
2666 }
2667 }
2668 /* framing errors are soft errors */
2669 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2670 if (flags & NV_RX2_SUBSTRACT1)
2671 len--;
2672 }
2673 /* the rest are hard errors */
2674 else {
2675 if (flags & NV_RX2_CRCERR)
2676 dev->stats.rx_crc_errors++;
2677 if (flags & NV_RX2_OVERFLOW)
2678 dev->stats.rx_over_errors++;
2679 dev->stats.rx_errors++;
2680 dev_kfree_skb(skb);
2681 goto next_pkt;
2682 }
2683 }
2684 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2685 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2686 skb->ip_summed = CHECKSUM_UNNECESSARY;
2687 } else {
2688 dev_kfree_skb(skb);
2689 goto next_pkt;
2690 }
2691 }
2692 /* got a valid packet - forward it to the network core */
2693 skb_put(skb, len);
2694 skb->protocol = eth_type_trans(skb, dev);
2695 napi_gro_receive(&np->napi, skb);
2696 dev->stats.rx_packets++;
2697 dev->stats.rx_bytes += len;
2698 next_pkt:
2699 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2700 np->get_rx.orig = np->first_rx.orig;
2701 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2702 np->get_rx_ctx = np->first_rx_ctx;
2703
2704 rx_work++;
2705 }
2706
2707 return rx_work;
2708 }
2709
2710 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2711 {
2712 struct fe_priv *np = netdev_priv(dev);
2713 u32 flags;
2714 u32 vlanflags = 0;
2715 int rx_work = 0;
2716 struct sk_buff *skb;
2717 int len;
2718
2719 while ((np->get_rx.ex != np->put_rx.ex) &&
2720 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2721 (rx_work < limit)) {
2722
2723 /*
2724 * the packet is for us - immediately tear down the pci mapping.
2725 * TODO: check if a prefetch of the first cacheline improves
2726 * the performance.
2727 */
2728 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2729 np->get_rx_ctx->dma_len,
2730 PCI_DMA_FROMDEVICE);
2731 skb = np->get_rx_ctx->skb;
2732 np->get_rx_ctx->skb = NULL;
2733
2734 /* look at what we actually got: */
2735 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2736 len = flags & LEN_MASK_V2;
2737 if (unlikely(flags & NV_RX2_ERROR)) {
2738 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2739 len = nv_getlen(dev, skb->data, len);
2740 if (len < 0) {
2741 dev_kfree_skb(skb);
2742 goto next_pkt;
2743 }
2744 }
2745 /* framing errors are soft errors */
2746 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2747 if (flags & NV_RX2_SUBSTRACT1)
2748 len--;
2749 }
2750 /* the rest are hard errors */
2751 else {
2752 dev_kfree_skb(skb);
2753 goto next_pkt;
2754 }
2755 }
2756
2757 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2758 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2759 skb->ip_summed = CHECKSUM_UNNECESSARY;
2760
2761 /* got a valid packet - forward it to the network core */
2762 skb_put(skb, len);
2763 skb->protocol = eth_type_trans(skb, dev);
2764 prefetch(skb->data);
2765
2766 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2767 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2768 u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK;
2769
2770 __vlan_hwaccel_put_tag(skb, vid);
2771 }
2772 napi_gro_receive(&np->napi, skb);
2773
2774 dev->stats.rx_packets++;
2775 dev->stats.rx_bytes += len;
2776 } else {
2777 dev_kfree_skb(skb);
2778 }
2779 next_pkt:
2780 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2781 np->get_rx.ex = np->first_rx.ex;
2782 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2783 np->get_rx_ctx = np->first_rx_ctx;
2784
2785 rx_work++;
2786 }
2787
2788 return rx_work;
2789 }
2790
2791 static void set_bufsize(struct net_device *dev)
2792 {
2793 struct fe_priv *np = netdev_priv(dev);
2794
2795 if (dev->mtu <= ETH_DATA_LEN)
2796 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2797 else
2798 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2799 }
2800
2801 /*
2802 * nv_change_mtu: dev->change_mtu function
2803 * Called with dev_base_lock held for read.
2804 */
2805 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2806 {
2807 struct fe_priv *np = netdev_priv(dev);
2808 int old_mtu;
2809
2810 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2811 return -EINVAL;
2812
2813 old_mtu = dev->mtu;
2814 dev->mtu = new_mtu;
2815
2816 /* return early if the buffer sizes will not change */
2817 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2818 return 0;
2819 if (old_mtu == new_mtu)
2820 return 0;
2821
2822 /* synchronized against open : rtnl_lock() held by caller */
2823 if (netif_running(dev)) {
2824 u8 __iomem *base = get_hwbase(dev);
2825 /*
2826 * It seems that the nic preloads valid ring entries into an
2827 * internal buffer. The procedure for flushing everything is
2828 * guessed, there is probably a simpler approach.
2829 * Changing the MTU is a rare event, it shouldn't matter.
2830 */
2831 nv_disable_irq(dev);
2832 nv_napi_disable(dev);
2833 netif_tx_lock_bh(dev);
2834 netif_addr_lock(dev);
2835 spin_lock(&np->lock);
2836 /* stop engines */
2837 nv_stop_rxtx(dev);
2838 nv_txrx_reset(dev);
2839 /* drain rx queue */
2840 nv_drain_rxtx(dev);
2841 /* reinit driver view of the rx queue */
2842 set_bufsize(dev);
2843 if (nv_init_ring(dev)) {
2844 if (!np->in_shutdown)
2845 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2846 }
2847 /* reinit nic view of the rx queue */
2848 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2849 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2850 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2851 base + NvRegRingSizes);
2852 pci_push(base);
2853 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2854 pci_push(base);
2855
2856 /* restart rx engine */
2857 nv_start_rxtx(dev);
2858 spin_unlock(&np->lock);
2859 netif_addr_unlock(dev);
2860 netif_tx_unlock_bh(dev);
2861 nv_napi_enable(dev);
2862 nv_enable_irq(dev);
2863 }
2864 return 0;
2865 }
2866
2867 static void nv_copy_mac_to_hw(struct net_device *dev)
2868 {
2869 u8 __iomem *base = get_hwbase(dev);
2870 u32 mac[2];
2871
2872 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2873 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2874 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2875
2876 writel(mac[0], base + NvRegMacAddrA);
2877 writel(mac[1], base + NvRegMacAddrB);
2878 }
2879
2880 /*
2881 * nv_set_mac_address: dev->set_mac_address function
2882 * Called with rtnl_lock() held.
2883 */
2884 static int nv_set_mac_address(struct net_device *dev, void *addr)
2885 {
2886 struct fe_priv *np = netdev_priv(dev);
2887 struct sockaddr *macaddr = (struct sockaddr *)addr;
2888
2889 if (!is_valid_ether_addr(macaddr->sa_data))
2890 return -EADDRNOTAVAIL;
2891
2892 /* synchronized against open : rtnl_lock() held by caller */
2893 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2894
2895 if (netif_running(dev)) {
2896 netif_tx_lock_bh(dev);
2897 netif_addr_lock(dev);
2898 spin_lock_irq(&np->lock);
2899
2900 /* stop rx engine */
2901 nv_stop_rx(dev);
2902
2903 /* set mac address */
2904 nv_copy_mac_to_hw(dev);
2905
2906 /* restart rx engine */
2907 nv_start_rx(dev);
2908 spin_unlock_irq(&np->lock);
2909 netif_addr_unlock(dev);
2910 netif_tx_unlock_bh(dev);
2911 } else {
2912 nv_copy_mac_to_hw(dev);
2913 }
2914 return 0;
2915 }
2916
2917 /*
2918 * nv_set_multicast: dev->set_multicast function
2919 * Called with netif_tx_lock held.
2920 */
2921 static void nv_set_multicast(struct net_device *dev)
2922 {
2923 struct fe_priv *np = netdev_priv(dev);
2924 u8 __iomem *base = get_hwbase(dev);
2925 u32 addr[2];
2926 u32 mask[2];
2927 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2928
2929 memset(addr, 0, sizeof(addr));
2930 memset(mask, 0, sizeof(mask));
2931
2932 if (dev->flags & IFF_PROMISC) {
2933 pff |= NVREG_PFF_PROMISC;
2934 } else {
2935 pff |= NVREG_PFF_MYADDR;
2936
2937 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
2938 u32 alwaysOff[2];
2939 u32 alwaysOn[2];
2940
2941 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2942 if (dev->flags & IFF_ALLMULTI) {
2943 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2944 } else {
2945 struct netdev_hw_addr *ha;
2946
2947 netdev_for_each_mc_addr(ha, dev) {
2948 unsigned char *addr = ha->addr;
2949 u32 a, b;
2950
2951 a = le32_to_cpu(*(__le32 *) addr);
2952 b = le16_to_cpu(*(__le16 *) (&addr[4]));
2953 alwaysOn[0] &= a;
2954 alwaysOff[0] &= ~a;
2955 alwaysOn[1] &= b;
2956 alwaysOff[1] &= ~b;
2957 }
2958 }
2959 addr[0] = alwaysOn[0];
2960 addr[1] = alwaysOn[1];
2961 mask[0] = alwaysOn[0] | alwaysOff[0];
2962 mask[1] = alwaysOn[1] | alwaysOff[1];
2963 } else {
2964 mask[0] = NVREG_MCASTMASKA_NONE;
2965 mask[1] = NVREG_MCASTMASKB_NONE;
2966 }
2967 }
2968 addr[0] |= NVREG_MCASTADDRA_FORCE;
2969 pff |= NVREG_PFF_ALWAYS;
2970 spin_lock_irq(&np->lock);
2971 nv_stop_rx(dev);
2972 writel(addr[0], base + NvRegMulticastAddrA);
2973 writel(addr[1], base + NvRegMulticastAddrB);
2974 writel(mask[0], base + NvRegMulticastMaskA);
2975 writel(mask[1], base + NvRegMulticastMaskB);
2976 writel(pff, base + NvRegPacketFilterFlags);
2977 nv_start_rx(dev);
2978 spin_unlock_irq(&np->lock);
2979 }
2980
2981 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2982 {
2983 struct fe_priv *np = netdev_priv(dev);
2984 u8 __iomem *base = get_hwbase(dev);
2985
2986 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2987
2988 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2989 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2990 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2991 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2992 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2993 } else {
2994 writel(pff, base + NvRegPacketFilterFlags);
2995 }
2996 }
2997 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2998 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2999 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3000 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3001 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3002 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3003 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3004 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3005 /* limit the number of tx pause frames to a default of 8 */
3006 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3007 }
3008 writel(pause_enable, base + NvRegTxPauseFrame);
3009 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3010 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3011 } else {
3012 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3013 writel(regmisc, base + NvRegMisc1);
3014 }
3015 }
3016 }
3017
3018 /**
3019 * nv_update_linkspeed: Setup the MAC according to the link partner
3020 * @dev: Network device to be configured
3021 *
3022 * The function queries the PHY and checks if there is a link partner.
3023 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3024 * set to 10 MBit HD.
3025 *
3026 * The function returns 0 if there is no link partner and 1 if there is
3027 * a good link partner.
3028 */
3029 static int nv_update_linkspeed(struct net_device *dev)
3030 {
3031 struct fe_priv *np = netdev_priv(dev);
3032 u8 __iomem *base = get_hwbase(dev);
3033 int adv = 0;
3034 int lpa = 0;
3035 int adv_lpa, adv_pause, lpa_pause;
3036 int newls = np->linkspeed;
3037 int newdup = np->duplex;
3038 int mii_status;
3039 int retval = 0;
3040 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3041 u32 txrxFlags = 0;
3042 u32 phy_exp;
3043
3044 /* BMSR_LSTATUS is latched, read it twice:
3045 * we want the current value.
3046 */
3047 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3048 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3049
3050 if (!(mii_status & BMSR_LSTATUS)) {
3051 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3052 newdup = 0;
3053 retval = 0;
3054 goto set_speed;
3055 }
3056
3057 if (np->autoneg == 0) {
3058 if (np->fixed_mode & LPA_100FULL) {
3059 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3060 newdup = 1;
3061 } else if (np->fixed_mode & LPA_100HALF) {
3062 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3063 newdup = 0;
3064 } else if (np->fixed_mode & LPA_10FULL) {
3065 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3066 newdup = 1;
3067 } else {
3068 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3069 newdup = 0;
3070 }
3071 retval = 1;
3072 goto set_speed;
3073 }
3074 /* check auto negotiation is complete */
3075 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3076 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3077 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3078 newdup = 0;
3079 retval = 0;
3080 goto set_speed;
3081 }
3082
3083 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3084 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3085
3086 retval = 1;
3087 if (np->gigabit == PHY_GIGABIT) {
3088 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3089 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3090
3091 if ((control_1000 & ADVERTISE_1000FULL) &&
3092 (status_1000 & LPA_1000FULL)) {
3093 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3094 newdup = 1;
3095 goto set_speed;
3096 }
3097 }
3098
3099 /* FIXME: handle parallel detection properly */
3100 adv_lpa = lpa & adv;
3101 if (adv_lpa & LPA_100FULL) {
3102 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3103 newdup = 1;
3104 } else if (adv_lpa & LPA_100HALF) {
3105 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3106 newdup = 0;
3107 } else if (adv_lpa & LPA_10FULL) {
3108 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3109 newdup = 1;
3110 } else if (adv_lpa & LPA_10HALF) {
3111 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3112 newdup = 0;
3113 } else {
3114 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3115 newdup = 0;
3116 }
3117
3118 set_speed:
3119 if (np->duplex == newdup && np->linkspeed == newls)
3120 return retval;
3121
3122 np->duplex = newdup;
3123 np->linkspeed = newls;
3124
3125 /* The transmitter and receiver must be restarted for safe update */
3126 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3127 txrxFlags |= NV_RESTART_TX;
3128 nv_stop_tx(dev);
3129 }
3130 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3131 txrxFlags |= NV_RESTART_RX;
3132 nv_stop_rx(dev);
3133 }
3134
3135 if (np->gigabit == PHY_GIGABIT) {
3136 phyreg = readl(base + NvRegSlotTime);
3137 phyreg &= ~(0x3FF00);
3138 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3139 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3140 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3141 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3142 phyreg |= NVREG_SLOTTIME_1000_FULL;
3143 writel(phyreg, base + NvRegSlotTime);
3144 }
3145
3146 phyreg = readl(base + NvRegPhyInterface);
3147 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3148 if (np->duplex == 0)
3149 phyreg |= PHY_HALF;
3150 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3151 phyreg |= PHY_100;
3152 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3153 phyreg |= PHY_1000;
3154 writel(phyreg, base + NvRegPhyInterface);
3155
3156 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3157 if (phyreg & PHY_RGMII) {
3158 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3159 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3160 } else {
3161 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3162 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3163 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3164 else
3165 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3166 } else {
3167 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3168 }
3169 }
3170 } else {
3171 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3172 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3173 else
3174 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3175 }
3176 writel(txreg, base + NvRegTxDeferral);
3177
3178 if (np->desc_ver == DESC_VER_1) {
3179 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3180 } else {
3181 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3182 txreg = NVREG_TX_WM_DESC2_3_1000;
3183 else
3184 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3185 }
3186 writel(txreg, base + NvRegTxWatermark);
3187
3188 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3189 base + NvRegMisc1);
3190 pci_push(base);
3191 writel(np->linkspeed, base + NvRegLinkSpeed);
3192 pci_push(base);
3193
3194 pause_flags = 0;
3195 /* setup pause frame */
3196 if (np->duplex != 0) {
3197 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3198 adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3199 lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3200
3201 switch (adv_pause) {
3202 case ADVERTISE_PAUSE_CAP:
3203 if (lpa_pause & LPA_PAUSE_CAP) {
3204 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3205 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3206 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3207 }
3208 break;
3209 case ADVERTISE_PAUSE_ASYM:
3210 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3211 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3212 break;
3213 case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3214 if (lpa_pause & LPA_PAUSE_CAP) {
3215 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3216 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3217 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3218 }
3219 if (lpa_pause == LPA_PAUSE_ASYM)
3220 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3221 break;
3222 }
3223 } else {
3224 pause_flags = np->pause_flags;
3225 }
3226 }
3227 nv_update_pause(dev, pause_flags);
3228
3229 if (txrxFlags & NV_RESTART_TX)
3230 nv_start_tx(dev);
3231 if (txrxFlags & NV_RESTART_RX)
3232 nv_start_rx(dev);
3233
3234 return retval;
3235 }
3236
3237 static void nv_linkchange(struct net_device *dev)
3238 {
3239 if (nv_update_linkspeed(dev)) {
3240 if (!netif_carrier_ok(dev)) {
3241 netif_carrier_on(dev);
3242 netdev_info(dev, "link up\n");
3243 nv_txrx_gate(dev, false);
3244 nv_start_rx(dev);
3245 }
3246 } else {
3247 if (netif_carrier_ok(dev)) {
3248 netif_carrier_off(dev);
3249 netdev_info(dev, "link down\n");
3250 nv_txrx_gate(dev, true);
3251 nv_stop_rx(dev);
3252 }
3253 }
3254 }
3255
3256 static void nv_link_irq(struct net_device *dev)
3257 {
3258 u8 __iomem *base = get_hwbase(dev);
3259 u32 miistat;
3260
3261 miistat = readl(base + NvRegMIIStatus);
3262 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3263
3264 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3265 nv_linkchange(dev);
3266 }
3267
3268 static void nv_msi_workaround(struct fe_priv *np)
3269 {
3270
3271 /* Need to toggle the msi irq mask within the ethernet device,
3272 * otherwise, future interrupts will not be detected.
3273 */
3274 if (np->msi_flags & NV_MSI_ENABLED) {
3275 u8 __iomem *base = np->base;
3276
3277 writel(0, base + NvRegMSIIrqMask);
3278 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3279 }
3280 }
3281
3282 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3283 {
3284 struct fe_priv *np = netdev_priv(dev);
3285
3286 if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3287 if (total_work > NV_DYNAMIC_THRESHOLD) {
3288 /* transition to poll based interrupts */
3289 np->quiet_count = 0;
3290 if (np->irqmask != NVREG_IRQMASK_CPU) {
3291 np->irqmask = NVREG_IRQMASK_CPU;
3292 return 1;
3293 }
3294 } else {
3295 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3296 np->quiet_count++;
3297 } else {
3298 /* reached a period of low activity, switch
3299 to per tx/rx packet interrupts */
3300 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3301 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3302 return 1;
3303 }
3304 }
3305 }
3306 }
3307 return 0;
3308 }
3309
3310 static irqreturn_t nv_nic_irq(int foo, void *data)
3311 {
3312 struct net_device *dev = (struct net_device *) data;
3313 struct fe_priv *np = netdev_priv(dev);
3314 u8 __iomem *base = get_hwbase(dev);
3315
3316 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3317 np->events = readl(base + NvRegIrqStatus);
3318 writel(np->events, base + NvRegIrqStatus);
3319 } else {
3320 np->events = readl(base + NvRegMSIXIrqStatus);
3321 writel(np->events, base + NvRegMSIXIrqStatus);
3322 }
3323 if (!(np->events & np->irqmask))
3324 return IRQ_NONE;
3325
3326 nv_msi_workaround(np);
3327
3328 if (napi_schedule_prep(&np->napi)) {
3329 /*
3330 * Disable further irq's (msix not enabled with napi)
3331 */
3332 writel(0, base + NvRegIrqMask);
3333 __napi_schedule(&np->napi);
3334 }
3335
3336 return IRQ_HANDLED;
3337 }
3338
3339 /**
3340 * All _optimized functions are used to help increase performance
3341 * (reduce CPU and increase throughput). They use descripter version 3,
3342 * compiler directives, and reduce memory accesses.
3343 */
3344 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3345 {
3346 struct net_device *dev = (struct net_device *) data;
3347 struct fe_priv *np = netdev_priv(dev);
3348 u8 __iomem *base = get_hwbase(dev);
3349
3350 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3351 np->events = readl(base + NvRegIrqStatus);
3352 writel(np->events, base + NvRegIrqStatus);
3353 } else {
3354 np->events = readl(base + NvRegMSIXIrqStatus);
3355 writel(np->events, base + NvRegMSIXIrqStatus);
3356 }
3357 if (!(np->events & np->irqmask))
3358 return IRQ_NONE;
3359
3360 nv_msi_workaround(np);
3361
3362 if (napi_schedule_prep(&np->napi)) {
3363 /*
3364 * Disable further irq's (msix not enabled with napi)
3365 */
3366 writel(0, base + NvRegIrqMask);
3367 __napi_schedule(&np->napi);
3368 }
3369
3370 return IRQ_HANDLED;
3371 }
3372
3373 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3374 {
3375 struct net_device *dev = (struct net_device *) data;
3376 struct fe_priv *np = netdev_priv(dev);
3377 u8 __iomem *base = get_hwbase(dev);
3378 u32 events;
3379 int i;
3380 unsigned long flags;
3381
3382 for (i = 0;; i++) {
3383 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3384 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3385 if (!(events & np->irqmask))
3386 break;
3387
3388 spin_lock_irqsave(&np->lock, flags);
3389 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3390 spin_unlock_irqrestore(&np->lock, flags);
3391
3392 if (unlikely(i > max_interrupt_work)) {
3393 spin_lock_irqsave(&np->lock, flags);
3394 /* disable interrupts on the nic */
3395 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3396 pci_push(base);
3397
3398 if (!np->in_shutdown) {
3399 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3400 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3401 }
3402 spin_unlock_irqrestore(&np->lock, flags);
3403 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3404 __func__, i);
3405 break;
3406 }
3407
3408 }
3409
3410 return IRQ_RETVAL(i);
3411 }
3412
3413 static int nv_napi_poll(struct napi_struct *napi, int budget)
3414 {
3415 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3416 struct net_device *dev = np->dev;
3417 u8 __iomem *base = get_hwbase(dev);
3418 unsigned long flags;
3419 int retcode;
3420 int rx_count, tx_work = 0, rx_work = 0;
3421
3422 do {
3423 if (!nv_optimized(np)) {
3424 spin_lock_irqsave(&np->lock, flags);
3425 tx_work += nv_tx_done(dev, np->tx_ring_size);
3426 spin_unlock_irqrestore(&np->lock, flags);
3427
3428 rx_count = nv_rx_process(dev, budget - rx_work);
3429 retcode = nv_alloc_rx(dev);
3430 } else {
3431 spin_lock_irqsave(&np->lock, flags);
3432 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3433 spin_unlock_irqrestore(&np->lock, flags);
3434
3435 rx_count = nv_rx_process_optimized(dev,
3436 budget - rx_work);
3437 retcode = nv_alloc_rx_optimized(dev);
3438 }
3439 } while (retcode == 0 &&
3440 rx_count > 0 && (rx_work += rx_count) < budget);
3441
3442 if (retcode) {
3443 spin_lock_irqsave(&np->lock, flags);
3444 if (!np->in_shutdown)
3445 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3446 spin_unlock_irqrestore(&np->lock, flags);
3447 }
3448
3449 nv_change_interrupt_mode(dev, tx_work + rx_work);
3450
3451 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3452 spin_lock_irqsave(&np->lock, flags);
3453 nv_link_irq(dev);
3454 spin_unlock_irqrestore(&np->lock, flags);
3455 }
3456 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3457 spin_lock_irqsave(&np->lock, flags);
3458 nv_linkchange(dev);
3459 spin_unlock_irqrestore(&np->lock, flags);
3460 np->link_timeout = jiffies + LINK_TIMEOUT;
3461 }
3462 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3463 spin_lock_irqsave(&np->lock, flags);
3464 if (!np->in_shutdown) {
3465 np->nic_poll_irq = np->irqmask;
3466 np->recover_error = 1;
3467 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3468 }
3469 spin_unlock_irqrestore(&np->lock, flags);
3470 napi_complete(napi);
3471 return rx_work;
3472 }
3473
3474 if (rx_work < budget) {
3475 /* re-enable interrupts
3476 (msix not enabled in napi) */
3477 napi_complete(napi);
3478
3479 writel(np->irqmask, base + NvRegIrqMask);
3480 }
3481 return rx_work;
3482 }
3483
3484 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3485 {
3486 struct net_device *dev = (struct net_device *) data;
3487 struct fe_priv *np = netdev_priv(dev);
3488 u8 __iomem *base = get_hwbase(dev);
3489 u32 events;
3490 int i;
3491 unsigned long flags;
3492
3493 for (i = 0;; i++) {
3494 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3495 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3496 if (!(events & np->irqmask))
3497 break;
3498
3499 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3500 if (unlikely(nv_alloc_rx_optimized(dev))) {
3501 spin_lock_irqsave(&np->lock, flags);
3502 if (!np->in_shutdown)
3503 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3504 spin_unlock_irqrestore(&np->lock, flags);
3505 }
3506 }
3507
3508 if (unlikely(i > max_interrupt_work)) {
3509 spin_lock_irqsave(&np->lock, flags);
3510 /* disable interrupts on the nic */
3511 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3512 pci_push(base);
3513
3514 if (!np->in_shutdown) {
3515 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3516 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3517 }
3518 spin_unlock_irqrestore(&np->lock, flags);
3519 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3520 __func__, i);
3521 break;
3522 }
3523 }
3524
3525 return IRQ_RETVAL(i);
3526 }
3527
3528 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3529 {
3530 struct net_device *dev = (struct net_device *) data;
3531 struct fe_priv *np = netdev_priv(dev);
3532 u8 __iomem *base = get_hwbase(dev);
3533 u32 events;
3534 int i;
3535 unsigned long flags;
3536
3537 for (i = 0;; i++) {
3538 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3539 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3540 if (!(events & np->irqmask))
3541 break;
3542
3543 /* check tx in case we reached max loop limit in tx isr */
3544 spin_lock_irqsave(&np->lock, flags);
3545 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3546 spin_unlock_irqrestore(&np->lock, flags);
3547
3548 if (events & NVREG_IRQ_LINK) {
3549 spin_lock_irqsave(&np->lock, flags);
3550 nv_link_irq(dev);
3551 spin_unlock_irqrestore(&np->lock, flags);
3552 }
3553 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3554 spin_lock_irqsave(&np->lock, flags);
3555 nv_linkchange(dev);
3556 spin_unlock_irqrestore(&np->lock, flags);
3557 np->link_timeout = jiffies + LINK_TIMEOUT;
3558 }
3559 if (events & NVREG_IRQ_RECOVER_ERROR) {
3560 spin_lock_irq(&np->lock);
3561 /* disable interrupts on the nic */
3562 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3563 pci_push(base);
3564
3565 if (!np->in_shutdown) {
3566 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3567 np->recover_error = 1;
3568 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3569 }
3570 spin_unlock_irq(&np->lock);
3571 break;
3572 }
3573 if (unlikely(i > max_interrupt_work)) {
3574 spin_lock_irqsave(&np->lock, flags);
3575 /* disable interrupts on the nic */
3576 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3577 pci_push(base);
3578
3579 if (!np->in_shutdown) {
3580 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3581 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3582 }
3583 spin_unlock_irqrestore(&np->lock, flags);
3584 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3585 __func__, i);
3586 break;
3587 }
3588
3589 }
3590
3591 return IRQ_RETVAL(i);
3592 }
3593
3594 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3595 {
3596 struct net_device *dev = (struct net_device *) data;
3597 struct fe_priv *np = netdev_priv(dev);
3598 u8 __iomem *base = get_hwbase(dev);
3599 u32 events;
3600
3601 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3602 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3603 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3604 } else {
3605 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3606 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3607 }
3608 pci_push(base);
3609 if (!(events & NVREG_IRQ_TIMER))
3610 return IRQ_RETVAL(0);
3611
3612 nv_msi_workaround(np);
3613
3614 spin_lock(&np->lock);
3615 np->intr_test = 1;
3616 spin_unlock(&np->lock);
3617
3618 return IRQ_RETVAL(1);
3619 }
3620
3621 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3622 {
3623 u8 __iomem *base = get_hwbase(dev);
3624 int i;
3625 u32 msixmap = 0;
3626
3627 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3628 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3629 * the remaining 8 interrupts.
3630 */
3631 for (i = 0; i < 8; i++) {
3632 if ((irqmask >> i) & 0x1)
3633 msixmap |= vector << (i << 2);
3634 }
3635 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3636
3637 msixmap = 0;
3638 for (i = 0; i < 8; i++) {
3639 if ((irqmask >> (i + 8)) & 0x1)
3640 msixmap |= vector << (i << 2);
3641 }
3642 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3643 }
3644
3645 static int nv_request_irq(struct net_device *dev, int intr_test)
3646 {
3647 struct fe_priv *np = get_nvpriv(dev);
3648 u8 __iomem *base = get_hwbase(dev);
3649 int ret = 1;
3650 int i;
3651 irqreturn_t (*handler)(int foo, void *data);
3652
3653 if (intr_test) {
3654 handler = nv_nic_irq_test;
3655 } else {
3656 if (nv_optimized(np))
3657 handler = nv_nic_irq_optimized;
3658 else
3659 handler = nv_nic_irq;
3660 }
3661
3662 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3663 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3664 np->msi_x_entry[i].entry = i;
3665 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3666 if (ret == 0) {
3667 np->msi_flags |= NV_MSI_X_ENABLED;
3668 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3669 /* Request irq for rx handling */
3670 sprintf(np->name_rx, "%s-rx", dev->name);
3671 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3672 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3673 netdev_info(dev,
3674 "request_irq failed for rx %d\n",
3675 ret);
3676 pci_disable_msix(np->pci_dev);
3677 np->msi_flags &= ~NV_MSI_X_ENABLED;
3678 goto out_err;
3679 }
3680 /* Request irq for tx handling */
3681 sprintf(np->name_tx, "%s-tx", dev->name);
3682 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3683 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3684 netdev_info(dev,
3685 "request_irq failed for tx %d\n",
3686 ret);
3687 pci_disable_msix(np->pci_dev);
3688 np->msi_flags &= ~NV_MSI_X_ENABLED;
3689 goto out_free_rx;
3690 }
3691 /* Request irq for link and timer handling */
3692 sprintf(np->name_other, "%s-other", dev->name);
3693 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3694 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3695 netdev_info(dev,
3696 "request_irq failed for link %d\n",
3697 ret);
3698 pci_disable_msix(np->pci_dev);
3699 np->msi_flags &= ~NV_MSI_X_ENABLED;
3700 goto out_free_tx;
3701 }
3702 /* map interrupts to their respective vector */
3703 writel(0, base + NvRegMSIXMap0);
3704 writel(0, base + NvRegMSIXMap1);
3705 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3706 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3707 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3708 } else {
3709 /* Request irq for all interrupts */
3710 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3711 netdev_info(dev,
3712 "request_irq failed %d\n",
3713 ret);
3714 pci_disable_msix(np->pci_dev);
3715 np->msi_flags &= ~NV_MSI_X_ENABLED;
3716 goto out_err;
3717 }
3718
3719 /* map interrupts to vector 0 */
3720 writel(0, base + NvRegMSIXMap0);
3721 writel(0, base + NvRegMSIXMap1);
3722 }
3723 }
3724 }
3725 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3726 ret = pci_enable_msi(np->pci_dev);
3727 if (ret == 0) {
3728 np->msi_flags |= NV_MSI_ENABLED;
3729 dev->irq = np->pci_dev->irq;
3730 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3731 netdev_info(dev, "request_irq failed %d\n",
3732 ret);
3733 pci_disable_msi(np->pci_dev);
3734 np->msi_flags &= ~NV_MSI_ENABLED;
3735 dev->irq = np->pci_dev->irq;
3736 goto out_err;
3737 }
3738
3739 /* map interrupts to vector 0 */
3740 writel(0, base + NvRegMSIMap0);
3741 writel(0, base + NvRegMSIMap1);
3742 /* enable msi vector 0 */
3743 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3744 }
3745 }
3746 if (ret != 0) {
3747 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3748 goto out_err;
3749
3750 }
3751
3752 return 0;
3753 out_free_tx:
3754 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3755 out_free_rx:
3756 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3757 out_err:
3758 return 1;
3759 }
3760
3761 static void nv_free_irq(struct net_device *dev)
3762 {
3763 struct fe_priv *np = get_nvpriv(dev);
3764 int i;
3765
3766 if (np->msi_flags & NV_MSI_X_ENABLED) {
3767 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3768 free_irq(np->msi_x_entry[i].vector, dev);
3769 pci_disable_msix(np->pci_dev);
3770 np->msi_flags &= ~NV_MSI_X_ENABLED;
3771 } else {
3772 free_irq(np->pci_dev->irq, dev);
3773 if (np->msi_flags & NV_MSI_ENABLED) {
3774 pci_disable_msi(np->pci_dev);
3775 np->msi_flags &= ~NV_MSI_ENABLED;
3776 }
3777 }
3778 }
3779
3780 static void nv_do_nic_poll(unsigned long data)
3781 {
3782 struct net_device *dev = (struct net_device *) data;
3783 struct fe_priv *np = netdev_priv(dev);
3784 u8 __iomem *base = get_hwbase(dev);
3785 u32 mask = 0;
3786
3787 /*
3788 * First disable irq(s) and then
3789 * reenable interrupts on the nic, we have to do this before calling
3790 * nv_nic_irq because that may decide to do otherwise
3791 */
3792
3793 if (!using_multi_irqs(dev)) {
3794 if (np->msi_flags & NV_MSI_X_ENABLED)
3795 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3796 else
3797 disable_irq_lockdep(np->pci_dev->irq);
3798 mask = np->irqmask;
3799 } else {
3800 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3801 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3802 mask |= NVREG_IRQ_RX_ALL;
3803 }
3804 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3805 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3806 mask |= NVREG_IRQ_TX_ALL;
3807 }
3808 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3809 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3810 mask |= NVREG_IRQ_OTHER;
3811 }
3812 }
3813 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3814
3815 if (np->recover_error) {
3816 np->recover_error = 0;
3817 netdev_info(dev, "MAC in recoverable error state\n");
3818 if (netif_running(dev)) {
3819 netif_tx_lock_bh(dev);
3820 netif_addr_lock(dev);
3821 spin_lock(&np->lock);
3822 /* stop engines */
3823 nv_stop_rxtx(dev);
3824 if (np->driver_data & DEV_HAS_POWER_CNTRL)
3825 nv_mac_reset(dev);
3826 nv_txrx_reset(dev);
3827 /* drain rx queue */
3828 nv_drain_rxtx(dev);
3829 /* reinit driver view of the rx queue */
3830 set_bufsize(dev);
3831 if (nv_init_ring(dev)) {
3832 if (!np->in_shutdown)
3833 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3834 }
3835 /* reinit nic view of the rx queue */
3836 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3837 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3838 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3839 base + NvRegRingSizes);
3840 pci_push(base);
3841 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3842 pci_push(base);
3843 /* clear interrupts */
3844 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3845 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3846 else
3847 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3848
3849 /* restart rx engine */
3850 nv_start_rxtx(dev);
3851 spin_unlock(&np->lock);
3852 netif_addr_unlock(dev);
3853 netif_tx_unlock_bh(dev);
3854 }
3855 }
3856
3857 writel(mask, base + NvRegIrqMask);
3858 pci_push(base);
3859
3860 if (!using_multi_irqs(dev)) {
3861 np->nic_poll_irq = 0;
3862 if (nv_optimized(np))
3863 nv_nic_irq_optimized(0, dev);
3864 else
3865 nv_nic_irq(0, dev);
3866 if (np->msi_flags & NV_MSI_X_ENABLED)
3867 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3868 else
3869 enable_irq_lockdep(np->pci_dev->irq);
3870 } else {
3871 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3872 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
3873 nv_nic_irq_rx(0, dev);
3874 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3875 }
3876 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3877 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
3878 nv_nic_irq_tx(0, dev);
3879 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3880 }
3881 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3882 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
3883 nv_nic_irq_other(0, dev);
3884 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3885 }
3886 }
3887
3888 }
3889
3890 #ifdef CONFIG_NET_POLL_CONTROLLER
3891 static void nv_poll_controller(struct net_device *dev)
3892 {
3893 nv_do_nic_poll((unsigned long) dev);
3894 }
3895 #endif
3896
3897 static void nv_do_stats_poll(unsigned long data)
3898 {
3899 struct net_device *dev = (struct net_device *) data;
3900 struct fe_priv *np = netdev_priv(dev);
3901
3902 nv_get_hw_stats(dev);
3903
3904 if (!np->in_shutdown)
3905 mod_timer(&np->stats_poll,
3906 round_jiffies(jiffies + STATS_INTERVAL));
3907 }
3908
3909 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3910 {
3911 struct fe_priv *np = netdev_priv(dev);
3912 strcpy(info->driver, DRV_NAME);
3913 strcpy(info->version, FORCEDETH_VERSION);
3914 strcpy(info->bus_info, pci_name(np->pci_dev));
3915 }
3916
3917 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3918 {
3919 struct fe_priv *np = netdev_priv(dev);
3920 wolinfo->supported = WAKE_MAGIC;
3921
3922 spin_lock_irq(&np->lock);
3923 if (np->wolenabled)
3924 wolinfo->wolopts = WAKE_MAGIC;
3925 spin_unlock_irq(&np->lock);
3926 }
3927
3928 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3929 {
3930 struct fe_priv *np = netdev_priv(dev);
3931 u8 __iomem *base = get_hwbase(dev);
3932 u32 flags = 0;
3933
3934 if (wolinfo->wolopts == 0) {
3935 np->wolenabled = 0;
3936 } else if (wolinfo->wolopts & WAKE_MAGIC) {
3937 np->wolenabled = 1;
3938 flags = NVREG_WAKEUPFLAGS_ENABLE;
3939 }
3940 if (netif_running(dev)) {
3941 spin_lock_irq(&np->lock);
3942 writel(flags, base + NvRegWakeUpFlags);
3943 spin_unlock_irq(&np->lock);
3944 }
3945 device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
3946 return 0;
3947 }
3948
3949 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3950 {
3951 struct fe_priv *np = netdev_priv(dev);
3952 u32 speed;
3953 int adv;
3954
3955 spin_lock_irq(&np->lock);
3956 ecmd->port = PORT_MII;
3957 if (!netif_running(dev)) {
3958 /* We do not track link speed / duplex setting if the
3959 * interface is disabled. Force a link check */
3960 if (nv_update_linkspeed(dev)) {
3961 if (!netif_carrier_ok(dev))
3962 netif_carrier_on(dev);
3963 } else {
3964 if (netif_carrier_ok(dev))
3965 netif_carrier_off(dev);
3966 }
3967 }
3968
3969 if (netif_carrier_ok(dev)) {
3970 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3971 case NVREG_LINKSPEED_10:
3972 speed = SPEED_10;
3973 break;
3974 case NVREG_LINKSPEED_100:
3975 speed = SPEED_100;
3976 break;
3977 case NVREG_LINKSPEED_1000:
3978 speed = SPEED_1000;
3979 break;
3980 default:
3981 speed = -1;
3982 break;
3983 }
3984 ecmd->duplex = DUPLEX_HALF;
3985 if (np->duplex)
3986 ecmd->duplex = DUPLEX_FULL;
3987 } else {
3988 speed = -1;
3989 ecmd->duplex = -1;
3990 }
3991 ethtool_cmd_speed_set(ecmd, speed);
3992 ecmd->autoneg = np->autoneg;
3993
3994 ecmd->advertising = ADVERTISED_MII;
3995 if (np->autoneg) {
3996 ecmd->advertising |= ADVERTISED_Autoneg;
3997 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3998 if (adv & ADVERTISE_10HALF)
3999 ecmd->advertising |= ADVERTISED_10baseT_Half;
4000 if (adv & ADVERTISE_10FULL)
4001 ecmd->advertising |= ADVERTISED_10baseT_Full;
4002 if (adv & ADVERTISE_100HALF)
4003 ecmd->advertising |= ADVERTISED_100baseT_Half;
4004 if (adv & ADVERTISE_100FULL)
4005 ecmd->advertising |= ADVERTISED_100baseT_Full;
4006 if (np->gigabit == PHY_GIGABIT) {
4007 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4008 if (adv & ADVERTISE_1000FULL)
4009 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4010 }
4011 }
4012 ecmd->supported = (SUPPORTED_Autoneg |
4013 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4014 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4015 SUPPORTED_MII);
4016 if (np->gigabit == PHY_GIGABIT)
4017 ecmd->supported |= SUPPORTED_1000baseT_Full;
4018
4019 ecmd->phy_address = np->phyaddr;
4020 ecmd->transceiver = XCVR_EXTERNAL;
4021
4022 /* ignore maxtxpkt, maxrxpkt for now */
4023 spin_unlock_irq(&np->lock);
4024 return 0;
4025 }
4026
4027 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4028 {
4029 struct fe_priv *np = netdev_priv(dev);
4030 u32 speed = ethtool_cmd_speed(ecmd);
4031
4032 if (ecmd->port != PORT_MII)
4033 return -EINVAL;
4034 if (ecmd->transceiver != XCVR_EXTERNAL)
4035 return -EINVAL;
4036 if (ecmd->phy_address != np->phyaddr) {
4037 /* TODO: support switching between multiple phys. Should be
4038 * trivial, but not enabled due to lack of test hardware. */
4039 return -EINVAL;
4040 }
4041 if (ecmd->autoneg == AUTONEG_ENABLE) {
4042 u32 mask;
4043
4044 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4045 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4046 if (np->gigabit == PHY_GIGABIT)
4047 mask |= ADVERTISED_1000baseT_Full;
4048
4049 if ((ecmd->advertising & mask) == 0)
4050 return -EINVAL;
4051
4052 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4053 /* Note: autonegotiation disable, speed 1000 intentionally
4054 * forbidden - no one should need that. */
4055
4056 if (speed != SPEED_10 && speed != SPEED_100)
4057 return -EINVAL;
4058 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4059 return -EINVAL;
4060 } else {
4061 return -EINVAL;
4062 }
4063
4064 netif_carrier_off(dev);
4065 if (netif_running(dev)) {
4066 unsigned long flags;
4067
4068 nv_disable_irq(dev);
4069 netif_tx_lock_bh(dev);
4070 netif_addr_lock(dev);
4071 /* with plain spinlock lockdep complains */
4072 spin_lock_irqsave(&np->lock, flags);
4073 /* stop engines */
4074 /* FIXME:
4075 * this can take some time, and interrupts are disabled
4076 * due to spin_lock_irqsave, but let's hope no daemon
4077 * is going to change the settings very often...
4078 * Worst case:
4079 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4080 * + some minor delays, which is up to a second approximately
4081 */
4082 nv_stop_rxtx(dev);
4083 spin_unlock_irqrestore(&np->lock, flags);
4084 netif_addr_unlock(dev);
4085 netif_tx_unlock_bh(dev);
4086 }
4087
4088 if (ecmd->autoneg == AUTONEG_ENABLE) {
4089 int adv, bmcr;
4090
4091 np->autoneg = 1;
4092
4093 /* advertise only what has been requested */
4094 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4095 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4096 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4097 adv |= ADVERTISE_10HALF;
4098 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4099 adv |= ADVERTISE_10FULL;
4100 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4101 adv |= ADVERTISE_100HALF;
4102 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4103 adv |= ADVERTISE_100FULL;
4104 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4105 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4106 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4107 adv |= ADVERTISE_PAUSE_ASYM;
4108 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4109
4110 if (np->gigabit == PHY_GIGABIT) {
4111 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4112 adv &= ~ADVERTISE_1000FULL;
4113 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4114 adv |= ADVERTISE_1000FULL;
4115 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4116 }
4117
4118 if (netif_running(dev))
4119 netdev_info(dev, "link down\n");
4120 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4121 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4122 bmcr |= BMCR_ANENABLE;
4123 /* reset the phy in order for settings to stick,
4124 * and cause autoneg to start */
4125 if (phy_reset(dev, bmcr)) {
4126 netdev_info(dev, "phy reset failed\n");
4127 return -EINVAL;
4128 }
4129 } else {
4130 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4131 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4132 }
4133 } else {
4134 int adv, bmcr;
4135
4136 np->autoneg = 0;
4137
4138 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4139 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4140 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4141 adv |= ADVERTISE_10HALF;
4142 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4143 adv |= ADVERTISE_10FULL;
4144 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4145 adv |= ADVERTISE_100HALF;
4146 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4147 adv |= ADVERTISE_100FULL;
4148 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4149 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
4150 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4151 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4152 }
4153 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4154 adv |= ADVERTISE_PAUSE_ASYM;
4155 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4156 }
4157 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4158 np->fixed_mode = adv;
4159
4160 if (np->gigabit == PHY_GIGABIT) {
4161 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4162 adv &= ~ADVERTISE_1000FULL;
4163 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4164 }
4165
4166 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4167 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4168 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4169 bmcr |= BMCR_FULLDPLX;
4170 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4171 bmcr |= BMCR_SPEED100;
4172 if (np->phy_oui == PHY_OUI_MARVELL) {
4173 /* reset the phy in order for forced mode settings to stick */
4174 if (phy_reset(dev, bmcr)) {
4175 netdev_info(dev, "phy reset failed\n");
4176 return -EINVAL;
4177 }
4178 } else {
4179 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4180 if (netif_running(dev)) {
4181 /* Wait a bit and then reconfigure the nic. */
4182 udelay(10);
4183 nv_linkchange(dev);
4184 }
4185 }
4186 }
4187
4188 if (netif_running(dev)) {
4189 nv_start_rxtx(dev);
4190 nv_enable_irq(dev);
4191 }
4192
4193 return 0;
4194 }
4195
4196 #define FORCEDETH_REGS_VER 1
4197
4198 static int nv_get_regs_len(struct net_device *dev)
4199 {
4200 struct fe_priv *np = netdev_priv(dev);
4201 return np->register_size;
4202 }
4203
4204 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4205 {
4206 struct fe_priv *np = netdev_priv(dev);
4207 u8 __iomem *base = get_hwbase(dev);
4208 u32 *rbuf = buf;
4209 int i;
4210
4211 regs->version = FORCEDETH_REGS_VER;
4212 spin_lock_irq(&np->lock);
4213 for (i = 0; i <= np->register_size/sizeof(u32); i++)
4214 rbuf[i] = readl(base + i*sizeof(u32));
4215 spin_unlock_irq(&np->lock);
4216 }
4217
4218 static int nv_nway_reset(struct net_device *dev)
4219 {
4220 struct fe_priv *np = netdev_priv(dev);
4221 int ret;
4222
4223 if (np->autoneg) {
4224 int bmcr;
4225
4226 netif_carrier_off(dev);
4227 if (netif_running(dev)) {
4228 nv_disable_irq(dev);
4229 netif_tx_lock_bh(dev);
4230 netif_addr_lock(dev);
4231 spin_lock(&np->lock);
4232 /* stop engines */
4233 nv_stop_rxtx(dev);
4234 spin_unlock(&np->lock);
4235 netif_addr_unlock(dev);
4236 netif_tx_unlock_bh(dev);
4237 netdev_info(dev, "link down\n");
4238 }
4239
4240 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4241 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4242 bmcr |= BMCR_ANENABLE;
4243 /* reset the phy in order for settings to stick*/
4244 if (phy_reset(dev, bmcr)) {
4245 netdev_info(dev, "phy reset failed\n");
4246 return -EINVAL;
4247 }
4248 } else {
4249 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4250 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4251 }
4252
4253 if (netif_running(dev)) {
4254 nv_start_rxtx(dev);
4255 nv_enable_irq(dev);
4256 }
4257 ret = 0;
4258 } else {
4259 ret = -EINVAL;
4260 }
4261
4262 return ret;
4263 }
4264
4265 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4266 {
4267 struct fe_priv *np = netdev_priv(dev);
4268
4269 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4270 ring->rx_mini_max_pending = 0;
4271 ring->rx_jumbo_max_pending = 0;
4272 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4273
4274 ring->rx_pending = np->rx_ring_size;
4275 ring->rx_mini_pending = 0;
4276 ring->rx_jumbo_pending = 0;
4277 ring->tx_pending = np->tx_ring_size;
4278 }
4279
4280 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4281 {
4282 struct fe_priv *np = netdev_priv(dev);
4283 u8 __iomem *base = get_hwbase(dev);
4284 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4285 dma_addr_t ring_addr;
4286
4287 if (ring->rx_pending < RX_RING_MIN ||
4288 ring->tx_pending < TX_RING_MIN ||
4289 ring->rx_mini_pending != 0 ||
4290 ring->rx_jumbo_pending != 0 ||
4291 (np->desc_ver == DESC_VER_1 &&
4292 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4293 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4294 (np->desc_ver != DESC_VER_1 &&
4295 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4296 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4297 return -EINVAL;
4298 }
4299
4300 /* allocate new rings */
4301 if (!nv_optimized(np)) {
4302 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4303 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4304 &ring_addr);
4305 } else {
4306 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4307 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4308 &ring_addr);
4309 }
4310 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4311 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4312 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4313 /* fall back to old rings */
4314 if (!nv_optimized(np)) {
4315 if (rxtx_ring)
4316 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4317 rxtx_ring, ring_addr);
4318 } else {
4319 if (rxtx_ring)
4320 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4321 rxtx_ring, ring_addr);
4322 }
4323
4324 kfree(rx_skbuff);
4325 kfree(tx_skbuff);
4326 goto exit;
4327 }
4328
4329 if (netif_running(dev)) {
4330 nv_disable_irq(dev);
4331 nv_napi_disable(dev);
4332 netif_tx_lock_bh(dev);
4333 netif_addr_lock(dev);
4334 spin_lock(&np->lock);
4335 /* stop engines */
4336 nv_stop_rxtx(dev);
4337 nv_txrx_reset(dev);
4338 /* drain queues */
4339 nv_drain_rxtx(dev);
4340 /* delete queues */
4341 free_rings(dev);
4342 }
4343
4344 /* set new values */
4345 np->rx_ring_size = ring->rx_pending;
4346 np->tx_ring_size = ring->tx_pending;
4347
4348 if (!nv_optimized(np)) {
4349 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4350 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4351 } else {
4352 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4353 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4354 }
4355 np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4356 np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4357 np->ring_addr = ring_addr;
4358
4359 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4360 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4361
4362 if (netif_running(dev)) {
4363 /* reinit driver view of the queues */
4364 set_bufsize(dev);
4365 if (nv_init_ring(dev)) {
4366 if (!np->in_shutdown)
4367 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4368 }
4369
4370 /* reinit nic view of the queues */
4371 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4372 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4373 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4374 base + NvRegRingSizes);
4375 pci_push(base);
4376 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4377 pci_push(base);
4378
4379 /* restart engines */
4380 nv_start_rxtx(dev);
4381 spin_unlock(&np->lock);
4382 netif_addr_unlock(dev);
4383 netif_tx_unlock_bh(dev);
4384 nv_napi_enable(dev);
4385 nv_enable_irq(dev);
4386 }
4387 return 0;
4388 exit:
4389 return -ENOMEM;
4390 }
4391
4392 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4393 {
4394 struct fe_priv *np = netdev_priv(dev);
4395
4396 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4397 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4398 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4399 }
4400
4401 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4402 {
4403 struct fe_priv *np = netdev_priv(dev);
4404 int adv, bmcr;
4405
4406 if ((!np->autoneg && np->duplex == 0) ||
4407 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4408 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4409 return -EINVAL;
4410 }
4411 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4412 netdev_info(dev, "hardware does not support tx pause frames\n");
4413 return -EINVAL;
4414 }
4415
4416 netif_carrier_off(dev);
4417 if (netif_running(dev)) {
4418 nv_disable_irq(dev);
4419 netif_tx_lock_bh(dev);
4420 netif_addr_lock(dev);
4421 spin_lock(&np->lock);
4422 /* stop engines */
4423 nv_stop_rxtx(dev);
4424 spin_unlock(&np->lock);
4425 netif_addr_unlock(dev);
4426 netif_tx_unlock_bh(dev);
4427 }
4428
4429 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4430 if (pause->rx_pause)
4431 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4432 if (pause->tx_pause)
4433 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4434
4435 if (np->autoneg && pause->autoneg) {
4436 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4437
4438 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4439 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4440 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4441 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4442 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4443 adv |= ADVERTISE_PAUSE_ASYM;
4444 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4445
4446 if (netif_running(dev))
4447 netdev_info(dev, "link down\n");
4448 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4449 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4450 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4451 } else {
4452 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4453 if (pause->rx_pause)
4454 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4455 if (pause->tx_pause)
4456 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4457
4458 if (!netif_running(dev))
4459 nv_update_linkspeed(dev);
4460 else
4461 nv_update_pause(dev, np->pause_flags);
4462 }
4463
4464 if (netif_running(dev)) {
4465 nv_start_rxtx(dev);
4466 nv_enable_irq(dev);
4467 }
4468 return 0;
4469 }
4470
4471 static u32 nv_fix_features(struct net_device *dev, u32 features)
4472 {
4473 /* vlan is dependent on rx checksum offload */
4474 if (features & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4475 features |= NETIF_F_RXCSUM;
4476
4477 return features;
4478 }
4479
4480 static void nv_vlan_mode(struct net_device *dev, u32 features)
4481 {
4482 struct fe_priv *np = get_nvpriv(dev);
4483
4484 spin_lock_irq(&np->lock);
4485
4486 if (features & NETIF_F_HW_VLAN_RX)
4487 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP;
4488 else
4489 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4490
4491 if (features & NETIF_F_HW_VLAN_TX)
4492 np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS;
4493 else
4494 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4495
4496 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4497
4498 spin_unlock_irq(&np->lock);
4499 }
4500
4501 static int nv_set_features(struct net_device *dev, u32 features)
4502 {
4503 struct fe_priv *np = netdev_priv(dev);
4504 u8 __iomem *base = get_hwbase(dev);
4505 u32 changed = dev->features ^ features;
4506
4507 if (changed & NETIF_F_RXCSUM) {
4508 spin_lock_irq(&np->lock);
4509
4510 if (features & NETIF_F_RXCSUM)
4511 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4512 else
4513 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4514
4515 if (netif_running(dev))
4516 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4517
4518 spin_unlock_irq(&np->lock);
4519 }
4520
4521 if (changed & (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX))
4522 nv_vlan_mode(dev, features);
4523
4524 return 0;
4525 }
4526
4527 static int nv_get_sset_count(struct net_device *dev, int sset)
4528 {
4529 struct fe_priv *np = netdev_priv(dev);
4530
4531 switch (sset) {
4532 case ETH_SS_TEST:
4533 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4534 return NV_TEST_COUNT_EXTENDED;
4535 else
4536 return NV_TEST_COUNT_BASE;
4537 case ETH_SS_STATS:
4538 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4539 return NV_DEV_STATISTICS_V3_COUNT;
4540 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4541 return NV_DEV_STATISTICS_V2_COUNT;
4542 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4543 return NV_DEV_STATISTICS_V1_COUNT;
4544 else
4545 return 0;
4546 default:
4547 return -EOPNOTSUPP;
4548 }
4549 }
4550
4551 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4552 {
4553 struct fe_priv *np = netdev_priv(dev);
4554
4555 /* update stats */
4556 nv_do_stats_poll((unsigned long)dev);
4557
4558 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4559 }
4560
4561 static int nv_link_test(struct net_device *dev)
4562 {
4563 struct fe_priv *np = netdev_priv(dev);
4564 int mii_status;
4565
4566 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4567 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4568
4569 /* check phy link status */
4570 if (!(mii_status & BMSR_LSTATUS))
4571 return 0;
4572 else
4573 return 1;
4574 }
4575
4576 static int nv_register_test(struct net_device *dev)
4577 {
4578 u8 __iomem *base = get_hwbase(dev);
4579 int i = 0;
4580 u32 orig_read, new_read;
4581
4582 do {
4583 orig_read = readl(base + nv_registers_test[i].reg);
4584
4585 /* xor with mask to toggle bits */
4586 orig_read ^= nv_registers_test[i].mask;
4587
4588 writel(orig_read, base + nv_registers_test[i].reg);
4589
4590 new_read = readl(base + nv_registers_test[i].reg);
4591
4592 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4593 return 0;
4594
4595 /* restore original value */
4596 orig_read ^= nv_registers_test[i].mask;
4597 writel(orig_read, base + nv_registers_test[i].reg);
4598
4599 } while (nv_registers_test[++i].reg != 0);
4600
4601 return 1;
4602 }
4603
4604 static int nv_interrupt_test(struct net_device *dev)
4605 {
4606 struct fe_priv *np = netdev_priv(dev);
4607 u8 __iomem *base = get_hwbase(dev);
4608 int ret = 1;
4609 int testcnt;
4610 u32 save_msi_flags, save_poll_interval = 0;
4611
4612 if (netif_running(dev)) {
4613 /* free current irq */
4614 nv_free_irq(dev);
4615 save_poll_interval = readl(base+NvRegPollingInterval);
4616 }
4617
4618 /* flag to test interrupt handler */
4619 np->intr_test = 0;
4620
4621 /* setup test irq */
4622 save_msi_flags = np->msi_flags;
4623 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4624 np->msi_flags |= 0x001; /* setup 1 vector */
4625 if (nv_request_irq(dev, 1))
4626 return 0;
4627
4628 /* setup timer interrupt */
4629 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4630 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4631
4632 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4633
4634 /* wait for at least one interrupt */
4635 msleep(100);
4636
4637 spin_lock_irq(&np->lock);
4638
4639 /* flag should be set within ISR */
4640 testcnt = np->intr_test;
4641 if (!testcnt)
4642 ret = 2;
4643
4644 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4645 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4646 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4647 else
4648 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4649
4650 spin_unlock_irq(&np->lock);
4651
4652 nv_free_irq(dev);
4653
4654 np->msi_flags = save_msi_flags;
4655
4656 if (netif_running(dev)) {
4657 writel(save_poll_interval, base + NvRegPollingInterval);
4658 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4659 /* restore original irq */
4660 if (nv_request_irq(dev, 0))
4661 return 0;
4662 }
4663
4664 return ret;
4665 }
4666
4667 static int nv_loopback_test(struct net_device *dev)
4668 {
4669 struct fe_priv *np = netdev_priv(dev);
4670 u8 __iomem *base = get_hwbase(dev);
4671 struct sk_buff *tx_skb, *rx_skb;
4672 dma_addr_t test_dma_addr;
4673 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4674 u32 flags;
4675 int len, i, pkt_len;
4676 u8 *pkt_data;
4677 u32 filter_flags = 0;
4678 u32 misc1_flags = 0;
4679 int ret = 1;
4680
4681 if (netif_running(dev)) {
4682 nv_disable_irq(dev);
4683 filter_flags = readl(base + NvRegPacketFilterFlags);
4684 misc1_flags = readl(base + NvRegMisc1);
4685 } else {
4686 nv_txrx_reset(dev);
4687 }
4688
4689 /* reinit driver view of the rx queue */
4690 set_bufsize(dev);
4691 nv_init_ring(dev);
4692
4693 /* setup hardware for loopback */
4694 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4695 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4696
4697 /* reinit nic view of the rx queue */
4698 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4699 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4700 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4701 base + NvRegRingSizes);
4702 pci_push(base);
4703
4704 /* restart rx engine */
4705 nv_start_rxtx(dev);
4706
4707 /* setup packet for tx */
4708 pkt_len = ETH_DATA_LEN;
4709 tx_skb = dev_alloc_skb(pkt_len);
4710 if (!tx_skb) {
4711 netdev_err(dev, "dev_alloc_skb() failed during loopback test\n");
4712 ret = 0;
4713 goto out;
4714 }
4715 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4716 skb_tailroom(tx_skb),
4717 PCI_DMA_FROMDEVICE);
4718 pkt_data = skb_put(tx_skb, pkt_len);
4719 for (i = 0; i < pkt_len; i++)
4720 pkt_data[i] = (u8)(i & 0xff);
4721
4722 if (!nv_optimized(np)) {
4723 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4724 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4725 } else {
4726 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4727 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4728 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4729 }
4730 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4731 pci_push(get_hwbase(dev));
4732
4733 msleep(500);
4734
4735 /* check for rx of the packet */
4736 if (!nv_optimized(np)) {
4737 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4738 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4739
4740 } else {
4741 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4742 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4743 }
4744
4745 if (flags & NV_RX_AVAIL) {
4746 ret = 0;
4747 } else if (np->desc_ver == DESC_VER_1) {
4748 if (flags & NV_RX_ERROR)
4749 ret = 0;
4750 } else {
4751 if (flags & NV_RX2_ERROR)
4752 ret = 0;
4753 }
4754
4755 if (ret) {
4756 if (len != pkt_len) {
4757 ret = 0;
4758 } else {
4759 rx_skb = np->rx_skb[0].skb;
4760 for (i = 0; i < pkt_len; i++) {
4761 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4762 ret = 0;
4763 break;
4764 }
4765 }
4766 }
4767 }
4768
4769 pci_unmap_single(np->pci_dev, test_dma_addr,
4770 (skb_end_pointer(tx_skb) - tx_skb->data),
4771 PCI_DMA_TODEVICE);
4772 dev_kfree_skb_any(tx_skb);
4773 out:
4774 /* stop engines */
4775 nv_stop_rxtx(dev);
4776 nv_txrx_reset(dev);
4777 /* drain rx queue */
4778 nv_drain_rxtx(dev);
4779
4780 if (netif_running(dev)) {
4781 writel(misc1_flags, base + NvRegMisc1);
4782 writel(filter_flags, base + NvRegPacketFilterFlags);
4783 nv_enable_irq(dev);
4784 }
4785
4786 return ret;
4787 }
4788
4789 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4790 {
4791 struct fe_priv *np = netdev_priv(dev);
4792 u8 __iomem *base = get_hwbase(dev);
4793 int result;
4794 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4795
4796 if (!nv_link_test(dev)) {
4797 test->flags |= ETH_TEST_FL_FAILED;
4798 buffer[0] = 1;
4799 }
4800
4801 if (test->flags & ETH_TEST_FL_OFFLINE) {
4802 if (netif_running(dev)) {
4803 netif_stop_queue(dev);
4804 nv_napi_disable(dev);
4805 netif_tx_lock_bh(dev);
4806 netif_addr_lock(dev);
4807 spin_lock_irq(&np->lock);
4808 nv_disable_hw_interrupts(dev, np->irqmask);
4809 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4810 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4811 else
4812 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4813 /* stop engines */
4814 nv_stop_rxtx(dev);
4815 nv_txrx_reset(dev);
4816 /* drain rx queue */
4817 nv_drain_rxtx(dev);
4818 spin_unlock_irq(&np->lock);
4819 netif_addr_unlock(dev);
4820 netif_tx_unlock_bh(dev);
4821 }
4822
4823 if (!nv_register_test(dev)) {
4824 test->flags |= ETH_TEST_FL_FAILED;
4825 buffer[1] = 1;
4826 }
4827
4828 result = nv_interrupt_test(dev);
4829 if (result != 1) {
4830 test->flags |= ETH_TEST_FL_FAILED;
4831 buffer[2] = 1;
4832 }
4833 if (result == 0) {
4834 /* bail out */
4835 return;
4836 }
4837
4838 if (!nv_loopback_test(dev)) {
4839 test->flags |= ETH_TEST_FL_FAILED;
4840 buffer[3] = 1;
4841 }
4842
4843 if (netif_running(dev)) {
4844 /* reinit driver view of the rx queue */
4845 set_bufsize(dev);
4846 if (nv_init_ring(dev)) {
4847 if (!np->in_shutdown)
4848 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4849 }
4850 /* reinit nic view of the rx queue */
4851 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4852 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4853 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4854 base + NvRegRingSizes);
4855 pci_push(base);
4856 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4857 pci_push(base);
4858 /* restart rx engine */
4859 nv_start_rxtx(dev);
4860 netif_start_queue(dev);
4861 nv_napi_enable(dev);
4862 nv_enable_hw_interrupts(dev, np->irqmask);
4863 }
4864 }
4865 }
4866
4867 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4868 {
4869 switch (stringset) {
4870 case ETH_SS_STATS:
4871 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
4872 break;
4873 case ETH_SS_TEST:
4874 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
4875 break;
4876 }
4877 }
4878
4879 static const struct ethtool_ops ops = {
4880 .get_drvinfo = nv_get_drvinfo,
4881 .get_link = ethtool_op_get_link,
4882 .get_wol = nv_get_wol,
4883 .set_wol = nv_set_wol,
4884 .get_settings = nv_get_settings,
4885 .set_settings = nv_set_settings,
4886 .get_regs_len = nv_get_regs_len,
4887 .get_regs = nv_get_regs,
4888 .nway_reset = nv_nway_reset,
4889 .get_ringparam = nv_get_ringparam,
4890 .set_ringparam = nv_set_ringparam,
4891 .get_pauseparam = nv_get_pauseparam,
4892 .set_pauseparam = nv_set_pauseparam,
4893 .get_strings = nv_get_strings,
4894 .get_ethtool_stats = nv_get_ethtool_stats,
4895 .get_sset_count = nv_get_sset_count,
4896 .self_test = nv_self_test,
4897 };
4898
4899 /* The mgmt unit and driver use a semaphore to access the phy during init */
4900 static int nv_mgmt_acquire_sema(struct net_device *dev)
4901 {
4902 struct fe_priv *np = netdev_priv(dev);
4903 u8 __iomem *base = get_hwbase(dev);
4904 int i;
4905 u32 tx_ctrl, mgmt_sema;
4906
4907 for (i = 0; i < 10; i++) {
4908 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4909 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4910 break;
4911 msleep(500);
4912 }
4913
4914 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4915 return 0;
4916
4917 for (i = 0; i < 2; i++) {
4918 tx_ctrl = readl(base + NvRegTransmitterControl);
4919 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4920 writel(tx_ctrl, base + NvRegTransmitterControl);
4921
4922 /* verify that semaphore was acquired */
4923 tx_ctrl = readl(base + NvRegTransmitterControl);
4924 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4925 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
4926 np->mgmt_sema = 1;
4927 return 1;
4928 } else
4929 udelay(50);
4930 }
4931
4932 return 0;
4933 }
4934
4935 static void nv_mgmt_release_sema(struct net_device *dev)
4936 {
4937 struct fe_priv *np = netdev_priv(dev);
4938 u8 __iomem *base = get_hwbase(dev);
4939 u32 tx_ctrl;
4940
4941 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
4942 if (np->mgmt_sema) {
4943 tx_ctrl = readl(base + NvRegTransmitterControl);
4944 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
4945 writel(tx_ctrl, base + NvRegTransmitterControl);
4946 }
4947 }
4948 }
4949
4950
4951 static int nv_mgmt_get_version(struct net_device *dev)
4952 {
4953 struct fe_priv *np = netdev_priv(dev);
4954 u8 __iomem *base = get_hwbase(dev);
4955 u32 data_ready = readl(base + NvRegTransmitterControl);
4956 u32 data_ready2 = 0;
4957 unsigned long start;
4958 int ready = 0;
4959
4960 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
4961 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
4962 start = jiffies;
4963 while (time_before(jiffies, start + 5*HZ)) {
4964 data_ready2 = readl(base + NvRegTransmitterControl);
4965 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
4966 ready = 1;
4967 break;
4968 }
4969 schedule_timeout_uninterruptible(1);
4970 }
4971
4972 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
4973 return 0;
4974
4975 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
4976
4977 return 1;
4978 }
4979
4980 static int nv_open(struct net_device *dev)
4981 {
4982 struct fe_priv *np = netdev_priv(dev);
4983 u8 __iomem *base = get_hwbase(dev);
4984 int ret = 1;
4985 int oom, i;
4986 u32 low;
4987
4988 /* power up phy */
4989 mii_rw(dev, np->phyaddr, MII_BMCR,
4990 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
4991
4992 nv_txrx_gate(dev, false);
4993 /* erase previous misconfiguration */
4994 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4995 nv_mac_reset(dev);
4996 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4997 writel(0, base + NvRegMulticastAddrB);
4998 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
4999 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5000 writel(0, base + NvRegPacketFilterFlags);
5001
5002 writel(0, base + NvRegTransmitterControl);
5003 writel(0, base + NvRegReceiverControl);
5004
5005 writel(0, base + NvRegAdapterControl);
5006
5007 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5008 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5009
5010 /* initialize descriptor rings */
5011 set_bufsize(dev);
5012 oom = nv_init_ring(dev);
5013
5014 writel(0, base + NvRegLinkSpeed);
5015 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5016 nv_txrx_reset(dev);
5017 writel(0, base + NvRegUnknownSetupReg6);
5018
5019 np->in_shutdown = 0;
5020
5021 /* give hw rings */
5022 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5023 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5024 base + NvRegRingSizes);
5025
5026 writel(np->linkspeed, base + NvRegLinkSpeed);
5027 if (np->desc_ver == DESC_VER_1)
5028 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5029 else
5030 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5031 writel(np->txrxctl_bits, base + NvRegTxRxControl);
5032 writel(np->vlanctl_bits, base + NvRegVlanControl);
5033 pci_push(base);
5034 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5035 if (reg_delay(dev, NvRegUnknownSetupReg5,
5036 NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5037 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5038 netdev_info(dev,
5039 "%s: SetupReg5, Bit 31 remained off\n", __func__);
5040
5041 writel(0, base + NvRegMIIMask);
5042 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5043 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5044
5045 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5046 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5047 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5048 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5049
5050 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5051
5052 get_random_bytes(&low, sizeof(low));
5053 low &= NVREG_SLOTTIME_MASK;
5054 if (np->desc_ver == DESC_VER_1) {
5055 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5056 } else {
5057 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5058 /* setup legacy backoff */
5059 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5060 } else {
5061 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5062 nv_gear_backoff_reseed(dev);
5063 }
5064 }
5065 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5066 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5067 if (poll_interval == -1) {
5068 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5069 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5070 else
5071 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5072 } else
5073 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5074 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5075 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5076 base + NvRegAdapterControl);
5077 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5078 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5079 if (np->wolenabled)
5080 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5081
5082 i = readl(base + NvRegPowerState);
5083 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5084 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5085
5086 pci_push(base);
5087 udelay(10);
5088 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5089
5090 nv_disable_hw_interrupts(dev, np->irqmask);
5091 pci_push(base);
5092 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5093 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5094 pci_push(base);
5095
5096 if (nv_request_irq(dev, 0))
5097 goto out_drain;
5098
5099 /* ask for interrupts */
5100 nv_enable_hw_interrupts(dev, np->irqmask);
5101
5102 spin_lock_irq(&np->lock);
5103 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5104 writel(0, base + NvRegMulticastAddrB);
5105 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5106 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5107 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5108 /* One manual link speed update: Interrupts are enabled, future link
5109 * speed changes cause interrupts and are handled by nv_link_irq().
5110 */
5111 {
5112 u32 miistat;
5113 miistat = readl(base + NvRegMIIStatus);
5114 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5115 }
5116 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5117 * to init hw */
5118 np->linkspeed = 0;
5119 ret = nv_update_linkspeed(dev);
5120 nv_start_rxtx(dev);
5121 netif_start_queue(dev);
5122 nv_napi_enable(dev);
5123
5124 if (ret) {
5125 netif_carrier_on(dev);
5126 } else {
5127 netdev_info(dev, "no link during initialization\n");
5128 netif_carrier_off(dev);
5129 }
5130 if (oom)
5131 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5132
5133 /* start statistics timer */
5134 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5135 mod_timer(&np->stats_poll,
5136 round_jiffies(jiffies + STATS_INTERVAL));
5137
5138 spin_unlock_irq(&np->lock);
5139
5140 return 0;
5141 out_drain:
5142 nv_drain_rxtx(dev);
5143 return ret;
5144 }
5145
5146 static int nv_close(struct net_device *dev)
5147 {
5148 struct fe_priv *np = netdev_priv(dev);
5149 u8 __iomem *base;
5150
5151 spin_lock_irq(&np->lock);
5152 np->in_shutdown = 1;
5153 spin_unlock_irq(&np->lock);
5154 nv_napi_disable(dev);
5155 synchronize_irq(np->pci_dev->irq);
5156
5157 del_timer_sync(&np->oom_kick);
5158 del_timer_sync(&np->nic_poll);
5159 del_timer_sync(&np->stats_poll);
5160
5161 netif_stop_queue(dev);
5162 spin_lock_irq(&np->lock);
5163 nv_stop_rxtx(dev);
5164 nv_txrx_reset(dev);
5165
5166 /* disable interrupts on the nic or we will lock up */
5167 base = get_hwbase(dev);
5168 nv_disable_hw_interrupts(dev, np->irqmask);
5169 pci_push(base);
5170
5171 spin_unlock_irq(&np->lock);
5172
5173 nv_free_irq(dev);
5174
5175 nv_drain_rxtx(dev);
5176
5177 if (np->wolenabled || !phy_power_down) {
5178 nv_txrx_gate(dev, false);
5179 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5180 nv_start_rx(dev);
5181 } else {
5182 /* power down phy */
5183 mii_rw(dev, np->phyaddr, MII_BMCR,
5184 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5185 nv_txrx_gate(dev, true);
5186 }
5187
5188 /* FIXME: power down nic */
5189
5190 return 0;
5191 }
5192
5193 static const struct net_device_ops nv_netdev_ops = {
5194 .ndo_open = nv_open,
5195 .ndo_stop = nv_close,
5196 .ndo_get_stats = nv_get_stats,
5197 .ndo_start_xmit = nv_start_xmit,
5198 .ndo_tx_timeout = nv_tx_timeout,
5199 .ndo_change_mtu = nv_change_mtu,
5200 .ndo_fix_features = nv_fix_features,
5201 .ndo_set_features = nv_set_features,
5202 .ndo_validate_addr = eth_validate_addr,
5203 .ndo_set_mac_address = nv_set_mac_address,
5204 .ndo_set_multicast_list = nv_set_multicast,
5205 #ifdef CONFIG_NET_POLL_CONTROLLER
5206 .ndo_poll_controller = nv_poll_controller,
5207 #endif
5208 };
5209
5210 static const struct net_device_ops nv_netdev_ops_optimized = {
5211 .ndo_open = nv_open,
5212 .ndo_stop = nv_close,
5213 .ndo_get_stats = nv_get_stats,
5214 .ndo_start_xmit = nv_start_xmit_optimized,
5215 .ndo_tx_timeout = nv_tx_timeout,
5216 .ndo_change_mtu = nv_change_mtu,
5217 .ndo_fix_features = nv_fix_features,
5218 .ndo_set_features = nv_set_features,
5219 .ndo_validate_addr = eth_validate_addr,
5220 .ndo_set_mac_address = nv_set_mac_address,
5221 .ndo_set_multicast_list = nv_set_multicast,
5222 #ifdef CONFIG_NET_POLL_CONTROLLER
5223 .ndo_poll_controller = nv_poll_controller,
5224 #endif
5225 };
5226
5227 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5228 {
5229 struct net_device *dev;
5230 struct fe_priv *np;
5231 unsigned long addr;
5232 u8 __iomem *base;
5233 int err, i;
5234 u32 powerstate, txreg;
5235 u32 phystate_orig = 0, phystate;
5236 int phyinitialized = 0;
5237 static int printed_version;
5238
5239 if (!printed_version++)
5240 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5241 FORCEDETH_VERSION);
5242
5243 dev = alloc_etherdev(sizeof(struct fe_priv));
5244 err = -ENOMEM;
5245 if (!dev)
5246 goto out;
5247
5248 np = netdev_priv(dev);
5249 np->dev = dev;
5250 np->pci_dev = pci_dev;
5251 spin_lock_init(&np->lock);
5252 SET_NETDEV_DEV(dev, &pci_dev->dev);
5253
5254 init_timer(&np->oom_kick);
5255 np->oom_kick.data = (unsigned long) dev;
5256 np->oom_kick.function = nv_do_rx_refill; /* timer handler */
5257 init_timer(&np->nic_poll);
5258 np->nic_poll.data = (unsigned long) dev;
5259 np->nic_poll.function = nv_do_nic_poll; /* timer handler */
5260 init_timer(&np->stats_poll);
5261 np->stats_poll.data = (unsigned long) dev;
5262 np->stats_poll.function = nv_do_stats_poll; /* timer handler */
5263
5264 err = pci_enable_device(pci_dev);
5265 if (err)
5266 goto out_free;
5267
5268 pci_set_master(pci_dev);
5269
5270 err = pci_request_regions(pci_dev, DRV_NAME);
5271 if (err < 0)
5272 goto out_disable;
5273
5274 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5275 np->register_size = NV_PCI_REGSZ_VER3;
5276 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5277 np->register_size = NV_PCI_REGSZ_VER2;
5278 else
5279 np->register_size = NV_PCI_REGSZ_VER1;
5280
5281 err = -EINVAL;
5282 addr = 0;
5283 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5284 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5285 pci_resource_len(pci_dev, i) >= np->register_size) {
5286 addr = pci_resource_start(pci_dev, i);
5287 break;
5288 }
5289 }
5290 if (i == DEVICE_COUNT_RESOURCE) {
5291 dev_info(&pci_dev->dev, "Couldn't find register window\n");
5292 goto out_relreg;
5293 }
5294
5295 /* copy of driver data */
5296 np->driver_data = id->driver_data;
5297 /* copy of device id */
5298 np->device_id = id->device;
5299
5300 /* handle different descriptor versions */
5301 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5302 /* packet format 3: supports 40-bit addressing */
5303 np->desc_ver = DESC_VER_3;
5304 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5305 if (dma_64bit) {
5306 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5307 dev_info(&pci_dev->dev,
5308 "64-bit DMA failed, using 32-bit addressing\n");
5309 else
5310 dev->features |= NETIF_F_HIGHDMA;
5311 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5312 dev_info(&pci_dev->dev,
5313 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5314 }
5315 }
5316 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5317 /* packet format 2: supports jumbo frames */
5318 np->desc_ver = DESC_VER_2;
5319 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5320 } else {
5321 /* original packet format */
5322 np->desc_ver = DESC_VER_1;
5323 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5324 }
5325
5326 np->pkt_limit = NV_PKTLIMIT_1;
5327 if (id->driver_data & DEV_HAS_LARGEDESC)
5328 np->pkt_limit = NV_PKTLIMIT_2;
5329
5330 if (id->driver_data & DEV_HAS_CHECKSUM) {
5331 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5332 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5333 NETIF_F_TSO | NETIF_F_RXCSUM;
5334 dev->features |= dev->hw_features;
5335 }
5336
5337 np->vlanctl_bits = 0;
5338 if (id->driver_data & DEV_HAS_VLAN) {
5339 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5340 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5341 }
5342
5343 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5344 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5345 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5346 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5347 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5348 }
5349
5350 err = -ENOMEM;
5351 np->base = ioremap(addr, np->register_size);
5352 if (!np->base)
5353 goto out_relreg;
5354 dev->base_addr = (unsigned long)np->base;
5355
5356 dev->irq = pci_dev->irq;
5357
5358 np->rx_ring_size = RX_RING_DEFAULT;
5359 np->tx_ring_size = TX_RING_DEFAULT;
5360
5361 if (!nv_optimized(np)) {
5362 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5363 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5364 &np->ring_addr);
5365 if (!np->rx_ring.orig)
5366 goto out_unmap;
5367 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5368 } else {
5369 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5370 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5371 &np->ring_addr);
5372 if (!np->rx_ring.ex)
5373 goto out_unmap;
5374 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5375 }
5376 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5377 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5378 if (!np->rx_skb || !np->tx_skb)
5379 goto out_freering;
5380
5381 if (!nv_optimized(np))
5382 dev->netdev_ops = &nv_netdev_ops;
5383 else
5384 dev->netdev_ops = &nv_netdev_ops_optimized;
5385
5386 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5387 SET_ETHTOOL_OPS(dev, &ops);
5388 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5389
5390 pci_set_drvdata(pci_dev, dev);
5391
5392 /* read the mac address */
5393 base = get_hwbase(dev);
5394 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5395 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5396
5397 /* check the workaround bit for correct mac address order */
5398 txreg = readl(base + NvRegTransmitPoll);
5399 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5400 /* mac address is already in correct order */
5401 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5402 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5403 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5404 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5405 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5406 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5407 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5408 /* mac address is already in correct order */
5409 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5410 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5411 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5412 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5413 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5414 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5415 /*
5416 * Set orig mac address back to the reversed version.
5417 * This flag will be cleared during low power transition.
5418 * Therefore, we should always put back the reversed address.
5419 */
5420 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5421 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5422 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5423 } else {
5424 /* need to reverse mac address to correct order */
5425 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5426 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5427 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5428 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5429 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5430 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5431 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5432 dev_dbg(&pci_dev->dev,
5433 "%s: set workaround bit for reversed mac addr\n",
5434 __func__);
5435 }
5436 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5437
5438 if (!is_valid_ether_addr(dev->perm_addr)) {
5439 /*
5440 * Bad mac address. At least one bios sets the mac address
5441 * to 01:23:45:67:89:ab
5442 */
5443 dev_err(&pci_dev->dev,
5444 "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5445 dev->dev_addr);
5446 random_ether_addr(dev->dev_addr);
5447 dev_err(&pci_dev->dev,
5448 "Using random MAC address: %pM\n", dev->dev_addr);
5449 }
5450
5451 /* set mac address */
5452 nv_copy_mac_to_hw(dev);
5453
5454 /* disable WOL */
5455 writel(0, base + NvRegWakeUpFlags);
5456 np->wolenabled = 0;
5457 device_set_wakeup_enable(&pci_dev->dev, false);
5458
5459 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5460
5461 /* take phy and nic out of low power mode */
5462 powerstate = readl(base + NvRegPowerState2);
5463 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5464 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5465 pci_dev->revision >= 0xA3)
5466 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5467 writel(powerstate, base + NvRegPowerState2);
5468 }
5469
5470 if (np->desc_ver == DESC_VER_1)
5471 np->tx_flags = NV_TX_VALID;
5472 else
5473 np->tx_flags = NV_TX2_VALID;
5474
5475 np->msi_flags = 0;
5476 if ((id->driver_data & DEV_HAS_MSI) && msi)
5477 np->msi_flags |= NV_MSI_CAPABLE;
5478
5479 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5480 /* msix has had reported issues when modifying irqmask
5481 as in the case of napi, therefore, disable for now
5482 */
5483 #if 0
5484 np->msi_flags |= NV_MSI_X_CAPABLE;
5485 #endif
5486 }
5487
5488 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5489 np->irqmask = NVREG_IRQMASK_CPU;
5490 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5491 np->msi_flags |= 0x0001;
5492 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5493 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5494 /* start off in throughput mode */
5495 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5496 /* remove support for msix mode */
5497 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5498 } else {
5499 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5500 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5501 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5502 np->msi_flags |= 0x0003;
5503 }
5504
5505 if (id->driver_data & DEV_NEED_TIMERIRQ)
5506 np->irqmask |= NVREG_IRQ_TIMER;
5507 if (id->driver_data & DEV_NEED_LINKTIMER) {
5508 np->need_linktimer = 1;
5509 np->link_timeout = jiffies + LINK_TIMEOUT;
5510 } else {
5511 np->need_linktimer = 0;
5512 }
5513
5514 /* Limit the number of tx's outstanding for hw bug */
5515 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5516 np->tx_limit = 1;
5517 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5518 pci_dev->revision >= 0xA2)
5519 np->tx_limit = 0;
5520 }
5521
5522 /* clear phy state and temporarily halt phy interrupts */
5523 writel(0, base + NvRegMIIMask);
5524 phystate = readl(base + NvRegAdapterControl);
5525 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5526 phystate_orig = 1;
5527 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5528 writel(phystate, base + NvRegAdapterControl);
5529 }
5530 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5531
5532 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5533 /* management unit running on the mac? */
5534 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5535 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5536 nv_mgmt_acquire_sema(dev) &&
5537 nv_mgmt_get_version(dev)) {
5538 np->mac_in_use = 1;
5539 if (np->mgmt_version > 0)
5540 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5541 /* management unit setup the phy already? */
5542 if (np->mac_in_use &&
5543 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5544 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5545 /* phy is inited by mgmt unit */
5546 phyinitialized = 1;
5547 } else {
5548 /* we need to init the phy */
5549 }
5550 }
5551 }
5552
5553 /* find a suitable phy */
5554 for (i = 1; i <= 32; i++) {
5555 int id1, id2;
5556 int phyaddr = i & 0x1F;
5557
5558 spin_lock_irq(&np->lock);
5559 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5560 spin_unlock_irq(&np->lock);
5561 if (id1 < 0 || id1 == 0xffff)
5562 continue;
5563 spin_lock_irq(&np->lock);
5564 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5565 spin_unlock_irq(&np->lock);
5566 if (id2 < 0 || id2 == 0xffff)
5567 continue;
5568
5569 np->phy_model = id2 & PHYID2_MODEL_MASK;
5570 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5571 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5572 np->phyaddr = phyaddr;
5573 np->phy_oui = id1 | id2;
5574
5575 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5576 if (np->phy_oui == PHY_OUI_REALTEK2)
5577 np->phy_oui = PHY_OUI_REALTEK;
5578 /* Setup phy revision for Realtek */
5579 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5580 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5581
5582 break;
5583 }
5584 if (i == 33) {
5585 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
5586 goto out_error;
5587 }
5588
5589 if (!phyinitialized) {
5590 /* reset it */
5591 phy_init(dev);
5592 } else {
5593 /* see if it is a gigabit phy */
5594 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5595 if (mii_status & PHY_GIGABIT)
5596 np->gigabit = PHY_GIGABIT;
5597 }
5598
5599 /* set default link speed settings */
5600 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5601 np->duplex = 0;
5602 np->autoneg = 1;
5603
5604 err = register_netdev(dev);
5605 if (err) {
5606 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
5607 goto out_error;
5608 }
5609
5610 netif_carrier_off(dev);
5611
5612 dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
5613 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
5614
5615 dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5616 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5617 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5618 "csum " : "",
5619 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5620 "vlan " : "",
5621 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5622 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5623 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5624 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5625 np->need_linktimer ? "lnktim " : "",
5626 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5627 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5628 np->desc_ver);
5629
5630 return 0;
5631
5632 out_error:
5633 if (phystate_orig)
5634 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5635 pci_set_drvdata(pci_dev, NULL);
5636 out_freering:
5637 free_rings(dev);
5638 out_unmap:
5639 iounmap(get_hwbase(dev));
5640 out_relreg:
5641 pci_release_regions(pci_dev);
5642 out_disable:
5643 pci_disable_device(pci_dev);
5644 out_free:
5645 free_netdev(dev);
5646 out:
5647 return err;
5648 }
5649
5650 static void nv_restore_phy(struct net_device *dev)
5651 {
5652 struct fe_priv *np = netdev_priv(dev);
5653 u16 phy_reserved, mii_control;
5654
5655 if (np->phy_oui == PHY_OUI_REALTEK &&
5656 np->phy_model == PHY_MODEL_REALTEK_8201 &&
5657 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5658 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5659 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5660 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5661 phy_reserved |= PHY_REALTEK_INIT8;
5662 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5663 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5664
5665 /* restart auto negotiation */
5666 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5667 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5668 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5669 }
5670 }
5671
5672 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
5673 {
5674 struct net_device *dev = pci_get_drvdata(pci_dev);
5675 struct fe_priv *np = netdev_priv(dev);
5676 u8 __iomem *base = get_hwbase(dev);
5677
5678 /* special op: write back the misordered MAC address - otherwise
5679 * the next nv_probe would see a wrong address.
5680 */
5681 writel(np->orig_mac[0], base + NvRegMacAddrA);
5682 writel(np->orig_mac[1], base + NvRegMacAddrB);
5683 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5684 base + NvRegTransmitPoll);
5685 }
5686
5687 static void __devexit nv_remove(struct pci_dev *pci_dev)
5688 {
5689 struct net_device *dev = pci_get_drvdata(pci_dev);
5690
5691 unregister_netdev(dev);
5692
5693 nv_restore_mac_addr(pci_dev);
5694
5695 /* restore any phy related changes */
5696 nv_restore_phy(dev);
5697
5698 nv_mgmt_release_sema(dev);
5699
5700 /* free all structures */
5701 free_rings(dev);
5702 iounmap(get_hwbase(dev));
5703 pci_release_regions(pci_dev);
5704 pci_disable_device(pci_dev);
5705 free_netdev(dev);
5706 pci_set_drvdata(pci_dev, NULL);
5707 }
5708
5709 #ifdef CONFIG_PM_SLEEP
5710 static int nv_suspend(struct device *device)
5711 {
5712 struct pci_dev *pdev = to_pci_dev(device);
5713 struct net_device *dev = pci_get_drvdata(pdev);
5714 struct fe_priv *np = netdev_priv(dev);
5715 u8 __iomem *base = get_hwbase(dev);
5716 int i;
5717
5718 if (netif_running(dev)) {
5719 /* Gross. */
5720 nv_close(dev);
5721 }
5722 netif_device_detach(dev);
5723
5724 /* save non-pci configuration space */
5725 for (i = 0; i <= np->register_size/sizeof(u32); i++)
5726 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5727
5728 return 0;
5729 }
5730
5731 static int nv_resume(struct device *device)
5732 {
5733 struct pci_dev *pdev = to_pci_dev(device);
5734 struct net_device *dev = pci_get_drvdata(pdev);
5735 struct fe_priv *np = netdev_priv(dev);
5736 u8 __iomem *base = get_hwbase(dev);
5737 int i, rc = 0;
5738
5739 /* restore non-pci configuration space */
5740 for (i = 0; i <= np->register_size/sizeof(u32); i++)
5741 writel(np->saved_config_space[i], base+i*sizeof(u32));
5742
5743 if (np->driver_data & DEV_NEED_MSI_FIX)
5744 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
5745
5746 /* restore phy state, including autoneg */
5747 phy_init(dev);
5748
5749 netif_device_attach(dev);
5750 if (netif_running(dev)) {
5751 rc = nv_open(dev);
5752 nv_set_multicast(dev);
5753 }
5754 return rc;
5755 }
5756
5757 static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
5758 #define NV_PM_OPS (&nv_pm_ops)
5759
5760 #else
5761 #define NV_PM_OPS NULL
5762 #endif /* CONFIG_PM_SLEEP */
5763
5764 #ifdef CONFIG_PM
5765 static void nv_shutdown(struct pci_dev *pdev)
5766 {
5767 struct net_device *dev = pci_get_drvdata(pdev);
5768 struct fe_priv *np = netdev_priv(dev);
5769
5770 if (netif_running(dev))
5771 nv_close(dev);
5772
5773 /*
5774 * Restore the MAC so a kernel started by kexec won't get confused.
5775 * If we really go for poweroff, we must not restore the MAC,
5776 * otherwise the MAC for WOL will be reversed at least on some boards.
5777 */
5778 if (system_state != SYSTEM_POWER_OFF)
5779 nv_restore_mac_addr(pdev);
5780
5781 pci_disable_device(pdev);
5782 /*
5783 * Apparently it is not possible to reinitialise from D3 hot,
5784 * only put the device into D3 if we really go for poweroff.
5785 */
5786 if (system_state == SYSTEM_POWER_OFF) {
5787 pci_wake_from_d3(pdev, np->wolenabled);
5788 pci_set_power_state(pdev, PCI_D3hot);
5789 }
5790 }
5791 #else
5792 #define nv_shutdown NULL
5793 #endif /* CONFIG_PM */
5794
5795 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
5796 { /* nForce Ethernet Controller */
5797 PCI_DEVICE(0x10DE, 0x01C3),
5798 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5799 },
5800 { /* nForce2 Ethernet Controller */
5801 PCI_DEVICE(0x10DE, 0x0066),
5802 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5803 },
5804 { /* nForce3 Ethernet Controller */
5805 PCI_DEVICE(0x10DE, 0x00D6),
5806 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5807 },
5808 { /* nForce3 Ethernet Controller */
5809 PCI_DEVICE(0x10DE, 0x0086),
5810 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5811 },
5812 { /* nForce3 Ethernet Controller */
5813 PCI_DEVICE(0x10DE, 0x008C),
5814 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5815 },
5816 { /* nForce3 Ethernet Controller */
5817 PCI_DEVICE(0x10DE, 0x00E6),
5818 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5819 },
5820 { /* nForce3 Ethernet Controller */
5821 PCI_DEVICE(0x10DE, 0x00DF),
5822 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5823 },
5824 { /* CK804 Ethernet Controller */
5825 PCI_DEVICE(0x10DE, 0x0056),
5826 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5827 },
5828 { /* CK804 Ethernet Controller */
5829 PCI_DEVICE(0x10DE, 0x0057),
5830 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5831 },
5832 { /* MCP04 Ethernet Controller */
5833 PCI_DEVICE(0x10DE, 0x0037),
5834 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5835 },
5836 { /* MCP04 Ethernet Controller */
5837 PCI_DEVICE(0x10DE, 0x0038),
5838 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5839 },
5840 { /* MCP51 Ethernet Controller */
5841 PCI_DEVICE(0x10DE, 0x0268),
5842 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
5843 },
5844 { /* MCP51 Ethernet Controller */
5845 PCI_DEVICE(0x10DE, 0x0269),
5846 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
5847 },
5848 { /* MCP55 Ethernet Controller */
5849 PCI_DEVICE(0x10DE, 0x0372),
5850 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
5851 },
5852 { /* MCP55 Ethernet Controller */
5853 PCI_DEVICE(0x10DE, 0x0373),
5854 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
5855 },
5856 { /* MCP61 Ethernet Controller */
5857 PCI_DEVICE(0x10DE, 0x03E5),
5858 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5859 },
5860 { /* MCP61 Ethernet Controller */
5861 PCI_DEVICE(0x10DE, 0x03E6),
5862 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5863 },
5864 { /* MCP61 Ethernet Controller */
5865 PCI_DEVICE(0x10DE, 0x03EE),
5866 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5867 },
5868 { /* MCP61 Ethernet Controller */
5869 PCI_DEVICE(0x10DE, 0x03EF),
5870 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5871 },
5872 { /* MCP65 Ethernet Controller */
5873 PCI_DEVICE(0x10DE, 0x0450),
5874 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5875 },
5876 { /* MCP65 Ethernet Controller */
5877 PCI_DEVICE(0x10DE, 0x0451),
5878 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5879 },
5880 { /* MCP65 Ethernet Controller */
5881 PCI_DEVICE(0x10DE, 0x0452),
5882 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5883 },
5884 { /* MCP65 Ethernet Controller */
5885 PCI_DEVICE(0x10DE, 0x0453),
5886 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5887 },
5888 { /* MCP67 Ethernet Controller */
5889 PCI_DEVICE(0x10DE, 0x054C),
5890 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5891 },
5892 { /* MCP67 Ethernet Controller */
5893 PCI_DEVICE(0x10DE, 0x054D),
5894 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5895 },
5896 { /* MCP67 Ethernet Controller */
5897 PCI_DEVICE(0x10DE, 0x054E),
5898 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5899 },
5900 { /* MCP67 Ethernet Controller */
5901 PCI_DEVICE(0x10DE, 0x054F),
5902 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5903 },
5904 { /* MCP73 Ethernet Controller */
5905 PCI_DEVICE(0x10DE, 0x07DC),
5906 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5907 },
5908 { /* MCP73 Ethernet Controller */
5909 PCI_DEVICE(0x10DE, 0x07DD),
5910 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5911 },
5912 { /* MCP73 Ethernet Controller */
5913 PCI_DEVICE(0x10DE, 0x07DE),
5914 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5915 },
5916 { /* MCP73 Ethernet Controller */
5917 PCI_DEVICE(0x10DE, 0x07DF),
5918 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5919 },
5920 { /* MCP77 Ethernet Controller */
5921 PCI_DEVICE(0x10DE, 0x0760),
5922 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5923 },
5924 { /* MCP77 Ethernet Controller */
5925 PCI_DEVICE(0x10DE, 0x0761),
5926 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5927 },
5928 { /* MCP77 Ethernet Controller */
5929 PCI_DEVICE(0x10DE, 0x0762),
5930 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5931 },
5932 { /* MCP77 Ethernet Controller */
5933 PCI_DEVICE(0x10DE, 0x0763),
5934 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5935 },
5936 { /* MCP79 Ethernet Controller */
5937 PCI_DEVICE(0x10DE, 0x0AB0),
5938 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5939 },
5940 { /* MCP79 Ethernet Controller */
5941 PCI_DEVICE(0x10DE, 0x0AB1),
5942 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5943 },
5944 { /* MCP79 Ethernet Controller */
5945 PCI_DEVICE(0x10DE, 0x0AB2),
5946 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5947 },
5948 { /* MCP79 Ethernet Controller */
5949 PCI_DEVICE(0x10DE, 0x0AB3),
5950 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5951 },
5952 { /* MCP89 Ethernet Controller */
5953 PCI_DEVICE(0x10DE, 0x0D7D),
5954 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
5955 },
5956 {0,},
5957 };
5958
5959 static struct pci_driver driver = {
5960 .name = DRV_NAME,
5961 .id_table = pci_tbl,
5962 .probe = nv_probe,
5963 .remove = __devexit_p(nv_remove),
5964 .shutdown = nv_shutdown,
5965 .driver.pm = NV_PM_OPS,
5966 };
5967
5968 static int __init init_nic(void)
5969 {
5970 return pci_register_driver(&driver);
5971 }
5972
5973 static void __exit exit_nic(void)
5974 {
5975 pci_unregister_driver(&driver);
5976 }
5977
5978 module_param(max_interrupt_work, int, 0);
5979 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5980 module_param(optimization_mode, int, 0);
5981 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
5982 module_param(poll_interval, int, 0);
5983 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5984 module_param(msi, int, 0);
5985 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5986 module_param(msix, int, 0);
5987 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5988 module_param(dma_64bit, int, 0);
5989 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
5990 module_param(phy_cross, int, 0);
5991 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
5992 module_param(phy_power_down, int, 0);
5993 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
5994
5995 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
5996 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
5997 MODULE_LICENSE("GPL");
5998
5999 MODULE_DEVICE_TABLE(pci, pci_tbl);
6000
6001 module_init(init_nic);
6002 module_exit(exit_nic);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree