2 * Copyright (C) 2005 - 2010 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
22 int beiscsi_pci_soft_reset(struct beiscsi_hba
*phba
)
25 u8
*pci_reset_offset
= 0;
26 u8
*pci_online0_offset
= 0;
27 u8
*pci_online1_offset
= 0;
32 pci_reset_offset
= (u8
*)phba
->pci_va
+ BE2_SOFT_RESET
;
33 pci_online0_offset
= (u8
*)phba
->pci_va
+ BE2_PCI_ONLINE0
;
34 pci_online1_offset
= (u8
*)phba
->pci_va
+ BE2_PCI_ONLINE1
;
35 sreset
= readl((void *)pci_reset_offset
);
36 sreset
|= BE2_SET_RESET
;
37 writel(sreset
, (void *)pci_reset_offset
);
40 while (sreset
& BE2_SET_RESET
) {
44 sreset
= readl((void *)pci_reset_offset
);
48 if (sreset
& BE2_SET_RESET
) {
49 printk(KERN_ERR
"Soft Reset did not deassert\n");
52 pconline1
= BE2_MPU_IRAM_ONLINE
;
53 writel(pconline0
, (void *)pci_online0_offset
);
54 writel(pconline1
, (void *)pci_online1_offset
);
56 sreset
= BE2_SET_RESET
;
57 writel(sreset
, (void *)pci_reset_offset
);
60 while (sreset
& BE2_SET_RESET
) {
64 sreset
= readl((void *)pci_reset_offset
);
67 if (sreset
& BE2_SET_RESET
) {
68 printk(KERN_ERR
"MPU Online Soft Reset did not deassert\n");
74 int be_chk_reset_complete(struct beiscsi_hba
*phba
)
76 unsigned int num_loop
;
81 mpu_sem
= (u8
*)phba
->csr_va
+ MPU_EP_SEMAPHORE
;
85 status
= readl((void *)mpu_sem
);
87 if ((status
& 0x80000000) || (status
& 0x0000FFFF) == 0xC000)
93 if ((status
& 0x80000000) || (!num_loop
)) {
94 printk(KERN_ERR
"Failed in be_chk_reset_complete"
95 "status = 0x%x\n", status
);
102 void be_mcc_notify(struct beiscsi_hba
*phba
)
104 struct be_queue_info
*mccq
= &phba
->ctrl
.mcc_obj
.q
;
107 val
|= mccq
->id
& DB_MCCQ_RING_ID_MASK
;
108 val
|= 1 << DB_MCCQ_NUM_POSTED_SHIFT
;
109 iowrite32(val
, phba
->db_va
+ DB_MCCQ_OFFSET
);
112 unsigned int alloc_mcc_tag(struct beiscsi_hba
*phba
)
114 unsigned int tag
= 0;
116 if (phba
->ctrl
.mcc_tag_available
) {
117 tag
= phba
->ctrl
.mcc_tag
[phba
->ctrl
.mcc_alloc_index
];
118 phba
->ctrl
.mcc_tag
[phba
->ctrl
.mcc_alloc_index
] = 0;
119 phba
->ctrl
.mcc_numtag
[tag
] = 0;
122 phba
->ctrl
.mcc_tag_available
--;
123 if (phba
->ctrl
.mcc_alloc_index
== (MAX_MCC_CMD
- 1))
124 phba
->ctrl
.mcc_alloc_index
= 0;
126 phba
->ctrl
.mcc_alloc_index
++;
131 void free_mcc_tag(struct be_ctrl_info
*ctrl
, unsigned int tag
)
133 spin_lock(&ctrl
->mbox_lock
);
134 tag
= tag
& 0x000000FF;
135 ctrl
->mcc_tag
[ctrl
->mcc_free_index
] = tag
;
136 if (ctrl
->mcc_free_index
== (MAX_MCC_CMD
- 1))
137 ctrl
->mcc_free_index
= 0;
139 ctrl
->mcc_free_index
++;
140 ctrl
->mcc_tag_available
++;
141 spin_unlock(&ctrl
->mbox_lock
);
144 bool is_link_state_evt(u32 trailer
)
146 return (((trailer
>> ASYNC_TRAILER_EVENT_CODE_SHIFT
) &
147 ASYNC_TRAILER_EVENT_CODE_MASK
) ==
148 ASYNC_EVENT_CODE_LINK_STATE
);
151 static inline bool be_mcc_compl_is_new(struct be_mcc_compl
*compl)
153 if (compl->flags
!= 0) {
154 compl->flags
= le32_to_cpu(compl->flags
);
155 WARN_ON((compl->flags
& CQE_FLAGS_VALID_MASK
) == 0);
161 static inline void be_mcc_compl_use(struct be_mcc_compl
*compl)
166 static int be_mcc_compl_process(struct be_ctrl_info
*ctrl
,
167 struct be_mcc_compl
*compl)
169 u16 compl_status
, extd_status
;
171 be_dws_le_to_cpu(compl, 4);
173 compl_status
= (compl->status
>> CQE_STATUS_COMPL_SHIFT
) &
174 CQE_STATUS_COMPL_MASK
;
175 if (compl_status
!= MCC_STATUS_SUCCESS
) {
176 extd_status
= (compl->status
>> CQE_STATUS_EXTD_SHIFT
) &
177 CQE_STATUS_EXTD_MASK
;
178 dev_err(&ctrl
->pdev
->dev
,
179 "error in cmd completion: status(compl/extd)=%d/%d\n",
180 compl_status
, extd_status
);
186 int be_mcc_compl_process_isr(struct be_ctrl_info
*ctrl
,
187 struct be_mcc_compl
*compl)
189 u16 compl_status
, extd_status
;
192 be_dws_le_to_cpu(compl, 4);
194 compl_status
= (compl->status
>> CQE_STATUS_COMPL_SHIFT
) &
195 CQE_STATUS_COMPL_MASK
;
196 /* The ctrl.mcc_numtag[tag] is filled with
197 * [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status,
198 * [7:0] = compl_status
200 tag
= (compl->tag0
& 0x000000FF);
201 extd_status
= (compl->status
>> CQE_STATUS_EXTD_SHIFT
) &
202 CQE_STATUS_EXTD_MASK
;
204 ctrl
->mcc_numtag
[tag
] = 0x80000000;
205 ctrl
->mcc_numtag
[tag
] |= (compl->tag0
& 0x00FF0000);
206 ctrl
->mcc_numtag
[tag
] |= (extd_status
& 0x000000FF) << 8;
207 ctrl
->mcc_numtag
[tag
] |= (compl_status
& 0x000000FF);
208 wake_up_interruptible(&ctrl
->mcc_wait
[tag
]);
212 static struct be_mcc_compl
*be_mcc_compl_get(struct beiscsi_hba
*phba
)
214 struct be_queue_info
*mcc_cq
= &phba
->ctrl
.mcc_obj
.cq
;
215 struct be_mcc_compl
*compl = queue_tail_node(mcc_cq
);
217 if (be_mcc_compl_is_new(compl)) {
218 queue_tail_inc(mcc_cq
);
224 static void be2iscsi_fail_session(struct iscsi_cls_session
*cls_session
)
226 iscsi_session_failure(cls_session
->dd_data
, ISCSI_ERR_CONN_FAILED
);
229 void beiscsi_async_link_state_process(struct beiscsi_hba
*phba
,
230 struct be_async_event_link_state
*evt
)
232 switch (evt
->port_link_status
) {
233 case ASYNC_EVENT_LINK_DOWN
:
234 SE_DEBUG(DBG_LVL_1
, "Link Down on Physical Port %d\n",
236 phba
->state
|= BE_ADAPTER_LINK_DOWN
;
237 iscsi_host_for_each_session(phba
->shost
,
238 be2iscsi_fail_session
);
240 case ASYNC_EVENT_LINK_UP
:
241 phba
->state
= BE_ADAPTER_UP
;
242 SE_DEBUG(DBG_LVL_1
, "Link UP on Physical Port %d\n",
246 SE_DEBUG(DBG_LVL_1
, "Unexpected Async Notification %d on"
247 "Physical Port %d\n",
248 evt
->port_link_status
,
253 static void beiscsi_cq_notify(struct beiscsi_hba
*phba
, u16 qid
, bool arm
,
257 val
|= qid
& DB_CQ_RING_ID_MASK
;
259 val
|= 1 << DB_CQ_REARM_SHIFT
;
260 val
|= num_popped
<< DB_CQ_NUM_POPPED_SHIFT
;
261 iowrite32(val
, phba
->db_va
+ DB_CQ_OFFSET
);
265 int beiscsi_process_mcc(struct beiscsi_hba
*phba
)
267 struct be_mcc_compl
*compl;
268 int num
= 0, status
= 0;
269 struct be_ctrl_info
*ctrl
= &phba
->ctrl
;
271 spin_lock_bh(&phba
->ctrl
.mcc_cq_lock
);
272 while ((compl = be_mcc_compl_get(phba
))) {
273 if (compl->flags
& CQE_FLAGS_ASYNC_MASK
) {
274 /* Interpret flags as an async trailer */
275 if (is_link_state_evt(compl->flags
))
276 /* Interpret compl as a async link evt */
277 beiscsi_async_link_state_process(phba
,
278 (struct be_async_event_link_state
*) compl);
281 " Unsupported Async Event, flags"
282 " = 0x%08x\n", compl->flags
);
284 } else if (compl->flags
& CQE_FLAGS_COMPLETED_MASK
) {
285 status
= be_mcc_compl_process(ctrl
, compl);
286 atomic_dec(&phba
->ctrl
.mcc_obj
.q
.used
);
288 be_mcc_compl_use(compl);
293 beiscsi_cq_notify(phba
, phba
->ctrl
.mcc_obj
.cq
.id
, true, num
);
295 spin_unlock_bh(&phba
->ctrl
.mcc_cq_lock
);
299 /* Wait till no more pending mcc requests are present */
300 static int be_mcc_wait_compl(struct beiscsi_hba
*phba
)
303 for (i
= 0; i
< mcc_timeout
; i
++) {
304 status
= beiscsi_process_mcc(phba
);
308 if (atomic_read(&phba
->ctrl
.mcc_obj
.q
.used
) == 0)
312 if (i
== mcc_timeout
) {
313 dev_err(&phba
->pcidev
->dev
, "mccq poll timed out\n");
319 /* Notify MCC requests and wait for completion */
320 int be_mcc_notify_wait(struct beiscsi_hba
*phba
)
323 return be_mcc_wait_compl(phba
);
326 static int be_mbox_db_ready_wait(struct be_ctrl_info
*ctrl
)
328 #define long_delay 2000
329 void __iomem
*db
= ctrl
->db
+ MPU_MAILBOX_DB_OFFSET
;
330 int cnt
= 0, wait
= 5; /* in usecs */
334 ready
= ioread32(db
) & MPU_MAILBOX_DB_RDY_MASK
;
338 if (cnt
> 12000000) {
339 dev_err(&ctrl
->pdev
->dev
, "mbox_db poll timed out\n");
345 mdelay(long_delay
/ 1000);
353 int be_mbox_notify(struct be_ctrl_info
*ctrl
)
357 void __iomem
*db
= ctrl
->db
+ MPU_MAILBOX_DB_OFFSET
;
358 struct be_dma_mem
*mbox_mem
= &ctrl
->mbox_mem
;
359 struct be_mcc_mailbox
*mbox
= mbox_mem
->va
;
360 struct be_mcc_compl
*compl = &mbox
->compl;
362 val
&= ~MPU_MAILBOX_DB_RDY_MASK
;
363 val
|= MPU_MAILBOX_DB_HI_MASK
;
364 val
|= (upper_32_bits(mbox_mem
->dma
) >> 2) << 2;
367 status
= be_mbox_db_ready_wait(ctrl
);
369 SE_DEBUG(DBG_LVL_1
, " be_mbox_db_ready_wait failed\n");
373 val
&= ~MPU_MAILBOX_DB_RDY_MASK
;
374 val
&= ~MPU_MAILBOX_DB_HI_MASK
;
375 val
|= (u32
) (mbox_mem
->dma
>> 4) << 2;
378 status
= be_mbox_db_ready_wait(ctrl
);
380 SE_DEBUG(DBG_LVL_1
, " be_mbox_db_ready_wait failed\n");
383 if (be_mcc_compl_is_new(compl)) {
384 status
= be_mcc_compl_process(ctrl
, &mbox
->compl);
385 be_mcc_compl_use(compl);
387 SE_DEBUG(DBG_LVL_1
, "After be_mcc_compl_process\n");
391 dev_err(&ctrl
->pdev
->dev
, "invalid mailbox completion\n");
398 * Insert the mailbox address into the doorbell in two steps
399 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
401 static int be_mbox_notify_wait(struct beiscsi_hba
*phba
)
405 void __iomem
*db
= phba
->ctrl
.db
+ MPU_MAILBOX_DB_OFFSET
;
406 struct be_dma_mem
*mbox_mem
= &phba
->ctrl
.mbox_mem
;
407 struct be_mcc_mailbox
*mbox
= mbox_mem
->va
;
408 struct be_mcc_compl
*compl = &mbox
->compl;
409 struct be_ctrl_info
*ctrl
= &phba
->ctrl
;
411 val
|= MPU_MAILBOX_DB_HI_MASK
;
412 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
413 val
|= (upper_32_bits(mbox_mem
->dma
) >> 2) << 2;
416 /* wait for ready to be set */
417 status
= be_mbox_db_ready_wait(ctrl
);
422 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
423 val
|= (u32
)(mbox_mem
->dma
>> 4) << 2;
426 status
= be_mbox_db_ready_wait(ctrl
);
430 /* A cq entry has been made now */
431 if (be_mcc_compl_is_new(compl)) {
432 status
= be_mcc_compl_process(ctrl
, &mbox
->compl);
433 be_mcc_compl_use(compl);
437 dev_err(&phba
->pcidev
->dev
, "invalid mailbox completion\n");
443 void be_wrb_hdr_prepare(struct be_mcc_wrb
*wrb
, int payload_len
,
444 bool embedded
, u8 sge_cnt
)
447 wrb
->embedded
|= MCC_WRB_EMBEDDED_MASK
;
449 wrb
->embedded
|= (sge_cnt
& MCC_WRB_SGE_CNT_MASK
) <<
450 MCC_WRB_SGE_CNT_SHIFT
;
451 wrb
->payload_length
= payload_len
;
452 be_dws_cpu_to_le(wrb
, 8);
455 void be_cmd_hdr_prepare(struct be_cmd_req_hdr
*req_hdr
,
456 u8 subsystem
, u8 opcode
, int cmd_len
)
458 req_hdr
->opcode
= opcode
;
459 req_hdr
->subsystem
= subsystem
;
460 req_hdr
->request_length
= cpu_to_le32(cmd_len
- sizeof(*req_hdr
));
463 static void be_cmd_page_addrs_prepare(struct phys_addr
*pages
, u32 max_pages
,
464 struct be_dma_mem
*mem
)
467 u64 dma
= (u64
) mem
->dma
;
469 buf_pages
= min(PAGES_4K_SPANNED(mem
->va
, mem
->size
), max_pages
);
470 for (i
= 0; i
< buf_pages
; i
++) {
471 pages
[i
].lo
= cpu_to_le32(dma
& 0xFFFFFFFF);
472 pages
[i
].hi
= cpu_to_le32(upper_32_bits(dma
));
477 static u32
eq_delay_to_mult(u32 usec_delay
)
479 #define MAX_INTR_RATE 651042
480 const u32 round
= 10;
486 u32 interrupt_rate
= 1000000 / usec_delay
;
487 if (interrupt_rate
== 0)
490 multiplier
= (MAX_INTR_RATE
- interrupt_rate
) * round
;
491 multiplier
/= interrupt_rate
;
492 multiplier
= (multiplier
+ round
/ 2) / round
;
493 multiplier
= min(multiplier
, (u32
) 1023);
499 struct be_mcc_wrb
*wrb_from_mbox(struct be_dma_mem
*mbox_mem
)
501 return &((struct be_mcc_mailbox
*)(mbox_mem
->va
))->wrb
;
504 struct be_mcc_wrb
*wrb_from_mccq(struct beiscsi_hba
*phba
)
506 struct be_queue_info
*mccq
= &phba
->ctrl
.mcc_obj
.q
;
507 struct be_mcc_wrb
*wrb
;
509 BUG_ON(atomic_read(&mccq
->used
) >= mccq
->len
);
510 wrb
= queue_head_node(mccq
);
511 memset(wrb
, 0, sizeof(*wrb
));
512 wrb
->tag0
= (mccq
->head
& 0x000000FF) << 16;
513 queue_head_inc(mccq
);
514 atomic_inc(&mccq
->used
);
519 int beiscsi_cmd_eq_create(struct be_ctrl_info
*ctrl
,
520 struct be_queue_info
*eq
, int eq_delay
)
522 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
523 struct be_cmd_req_eq_create
*req
= embedded_payload(wrb
);
524 struct be_cmd_resp_eq_create
*resp
= embedded_payload(wrb
);
525 struct be_dma_mem
*q_mem
= &eq
->dma_mem
;
528 SE_DEBUG(DBG_LVL_8
, "In beiscsi_cmd_eq_create\n");
529 spin_lock(&ctrl
->mbox_lock
);
530 memset(wrb
, 0, sizeof(*wrb
));
532 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
534 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
535 OPCODE_COMMON_EQ_CREATE
, sizeof(*req
));
537 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
539 AMAP_SET_BITS(struct amap_eq_context
, func
, req
->context
,
540 PCI_FUNC(ctrl
->pdev
->devfn
));
541 AMAP_SET_BITS(struct amap_eq_context
, valid
, req
->context
, 1);
542 AMAP_SET_BITS(struct amap_eq_context
, size
, req
->context
, 0);
543 AMAP_SET_BITS(struct amap_eq_context
, count
, req
->context
,
544 __ilog2_u32(eq
->len
/ 256));
545 AMAP_SET_BITS(struct amap_eq_context
, delaymult
, req
->context
,
546 eq_delay_to_mult(eq_delay
));
547 be_dws_cpu_to_le(req
->context
, sizeof(req
->context
));
549 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
551 status
= be_mbox_notify(ctrl
);
553 eq
->id
= le16_to_cpu(resp
->eq_id
);
556 spin_unlock(&ctrl
->mbox_lock
);
560 int be_cmd_fw_initialize(struct be_ctrl_info
*ctrl
)
562 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
566 SE_DEBUG(DBG_LVL_8
, "In be_cmd_fw_initialize\n");
567 spin_lock(&ctrl
->mbox_lock
);
568 memset(wrb
, 0, sizeof(*wrb
));
570 endian_check
= (u8
*) wrb
;
571 *endian_check
++ = 0xFF;
572 *endian_check
++ = 0x12;
573 *endian_check
++ = 0x34;
574 *endian_check
++ = 0xFF;
575 *endian_check
++ = 0xFF;
576 *endian_check
++ = 0x56;
577 *endian_check
++ = 0x78;
578 *endian_check
++ = 0xFF;
579 be_dws_cpu_to_le(wrb
, sizeof(*wrb
));
581 status
= be_mbox_notify(ctrl
);
583 SE_DEBUG(DBG_LVL_1
, "be_cmd_fw_initialize Failed\n");
585 spin_unlock(&ctrl
->mbox_lock
);
589 int beiscsi_cmd_cq_create(struct be_ctrl_info
*ctrl
,
590 struct be_queue_info
*cq
, struct be_queue_info
*eq
,
591 bool sol_evts
, bool no_delay
, int coalesce_wm
)
593 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
594 struct be_cmd_req_cq_create
*req
= embedded_payload(wrb
);
595 struct be_cmd_resp_cq_create
*resp
= embedded_payload(wrb
);
596 struct be_dma_mem
*q_mem
= &cq
->dma_mem
;
597 void *ctxt
= &req
->context
;
600 SE_DEBUG(DBG_LVL_8
, "In beiscsi_cmd_cq_create\n");
601 spin_lock(&ctrl
->mbox_lock
);
602 memset(wrb
, 0, sizeof(*wrb
));
604 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
606 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
607 OPCODE_COMMON_CQ_CREATE
, sizeof(*req
));
609 SE_DEBUG(DBG_LVL_1
, "uninitialized q_mem->va\n");
611 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
613 AMAP_SET_BITS(struct amap_cq_context
, coalescwm
, ctxt
, coalesce_wm
);
614 AMAP_SET_BITS(struct amap_cq_context
, nodelay
, ctxt
, no_delay
);
615 AMAP_SET_BITS(struct amap_cq_context
, count
, ctxt
,
616 __ilog2_u32(cq
->len
/ 256));
617 AMAP_SET_BITS(struct amap_cq_context
, valid
, ctxt
, 1);
618 AMAP_SET_BITS(struct amap_cq_context
, solevent
, ctxt
, sol_evts
);
619 AMAP_SET_BITS(struct amap_cq_context
, eventable
, ctxt
, 1);
620 AMAP_SET_BITS(struct amap_cq_context
, eqid
, ctxt
, eq
->id
);
621 AMAP_SET_BITS(struct amap_cq_context
, armed
, ctxt
, 1);
622 AMAP_SET_BITS(struct amap_cq_context
, func
, ctxt
,
623 PCI_FUNC(ctrl
->pdev
->devfn
));
624 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
626 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
628 status
= be_mbox_notify(ctrl
);
630 cq
->id
= le16_to_cpu(resp
->cq_id
);
633 SE_DEBUG(DBG_LVL_1
, "In be_cmd_cq_create, status=ox%08x\n",
635 spin_unlock(&ctrl
->mbox_lock
);
640 static u32
be_encoded_q_len(int q_len
)
642 u32 len_encoded
= fls(q_len
); /* log2(len) + 1 */
643 if (len_encoded
== 16)
648 int beiscsi_cmd_mccq_create(struct beiscsi_hba
*phba
,
649 struct be_queue_info
*mccq
,
650 struct be_queue_info
*cq
)
652 struct be_mcc_wrb
*wrb
;
653 struct be_cmd_req_mcc_create
*req
;
654 struct be_dma_mem
*q_mem
= &mccq
->dma_mem
;
655 struct be_ctrl_info
*ctrl
;
659 spin_lock(&phba
->ctrl
.mbox_lock
);
661 wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
662 req
= embedded_payload(wrb
);
663 ctxt
= &req
->context
;
665 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
667 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
668 OPCODE_COMMON_MCC_CREATE
, sizeof(*req
));
670 req
->num_pages
= PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
);
672 AMAP_SET_BITS(struct amap_mcc_context
, fid
, ctxt
,
673 PCI_FUNC(phba
->pcidev
->devfn
));
674 AMAP_SET_BITS(struct amap_mcc_context
, valid
, ctxt
, 1);
675 AMAP_SET_BITS(struct amap_mcc_context
, ring_size
, ctxt
,
676 be_encoded_q_len(mccq
->len
));
677 AMAP_SET_BITS(struct amap_mcc_context
, cq_id
, ctxt
, cq
->id
);
679 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
681 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
683 status
= be_mbox_notify_wait(phba
);
685 struct be_cmd_resp_mcc_create
*resp
= embedded_payload(wrb
);
686 mccq
->id
= le16_to_cpu(resp
->id
);
687 mccq
->created
= true;
689 spin_unlock(&phba
->ctrl
.mbox_lock
);
694 int beiscsi_cmd_q_destroy(struct be_ctrl_info
*ctrl
, struct be_queue_info
*q
,
697 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
698 struct be_cmd_req_q_destroy
*req
= embedded_payload(wrb
);
699 u8 subsys
= 0, opcode
= 0;
702 SE_DEBUG(DBG_LVL_8
, "In beiscsi_cmd_q_destroy\n");
703 spin_lock(&ctrl
->mbox_lock
);
704 memset(wrb
, 0, sizeof(*wrb
));
705 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
707 switch (queue_type
) {
709 subsys
= CMD_SUBSYSTEM_COMMON
;
710 opcode
= OPCODE_COMMON_EQ_DESTROY
;
713 subsys
= CMD_SUBSYSTEM_COMMON
;
714 opcode
= OPCODE_COMMON_CQ_DESTROY
;
717 subsys
= CMD_SUBSYSTEM_COMMON
;
718 opcode
= OPCODE_COMMON_MCC_DESTROY
;
721 subsys
= CMD_SUBSYSTEM_ISCSI
;
722 opcode
= OPCODE_COMMON_ISCSI_WRBQ_DESTROY
;
725 subsys
= CMD_SUBSYSTEM_ISCSI
;
726 opcode
= OPCODE_COMMON_ISCSI_DEFQ_DESTROY
;
729 subsys
= CMD_SUBSYSTEM_ISCSI
;
730 opcode
= OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES
;
733 spin_unlock(&ctrl
->mbox_lock
);
737 be_cmd_hdr_prepare(&req
->hdr
, subsys
, opcode
, sizeof(*req
));
738 if (queue_type
!= QTYPE_SGL
)
739 req
->id
= cpu_to_le16(q
->id
);
741 status
= be_mbox_notify(ctrl
);
743 spin_unlock(&ctrl
->mbox_lock
);
747 int be_cmd_create_default_pdu_queue(struct be_ctrl_info
*ctrl
,
748 struct be_queue_info
*cq
,
749 struct be_queue_info
*dq
, int length
,
752 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
753 struct be_defq_create_req
*req
= embedded_payload(wrb
);
754 struct be_dma_mem
*q_mem
= &dq
->dma_mem
;
755 void *ctxt
= &req
->context
;
758 SE_DEBUG(DBG_LVL_8
, "In be_cmd_create_default_pdu_queue\n");
759 spin_lock(&ctrl
->mbox_lock
);
760 memset(wrb
, 0, sizeof(*wrb
));
762 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
764 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ISCSI
,
765 OPCODE_COMMON_ISCSI_DEFQ_CREATE
, sizeof(*req
));
767 req
->num_pages
= PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
);
768 AMAP_SET_BITS(struct amap_be_default_pdu_context
, rx_pdid
, ctxt
, 0);
769 AMAP_SET_BITS(struct amap_be_default_pdu_context
, rx_pdid_valid
, ctxt
,
771 AMAP_SET_BITS(struct amap_be_default_pdu_context
, pci_func_id
, ctxt
,
772 PCI_FUNC(ctrl
->pdev
->devfn
));
773 AMAP_SET_BITS(struct amap_be_default_pdu_context
, ring_size
, ctxt
,
774 be_encoded_q_len(length
/ sizeof(struct phys_addr
)));
775 AMAP_SET_BITS(struct amap_be_default_pdu_context
, default_buffer_size
,
777 AMAP_SET_BITS(struct amap_be_default_pdu_context
, cq_id_recv
, ctxt
,
780 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
782 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
784 status
= be_mbox_notify(ctrl
);
786 struct be_defq_create_resp
*resp
= embedded_payload(wrb
);
788 dq
->id
= le16_to_cpu(resp
->id
);
791 spin_unlock(&ctrl
->mbox_lock
);
796 int be_cmd_wrbq_create(struct be_ctrl_info
*ctrl
, struct be_dma_mem
*q_mem
,
797 struct be_queue_info
*wrbq
)
799 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
800 struct be_wrbq_create_req
*req
= embedded_payload(wrb
);
801 struct be_wrbq_create_resp
*resp
= embedded_payload(wrb
);
804 spin_lock(&ctrl
->mbox_lock
);
805 memset(wrb
, 0, sizeof(*wrb
));
807 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
809 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ISCSI
,
810 OPCODE_COMMON_ISCSI_WRBQ_CREATE
, sizeof(*req
));
811 req
->num_pages
= PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
);
812 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
814 status
= be_mbox_notify(ctrl
);
816 wrbq
->id
= le16_to_cpu(resp
->cid
);
817 wrbq
->created
= true;
819 spin_unlock(&ctrl
->mbox_lock
);
823 int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info
*ctrl
,
824 struct be_dma_mem
*q_mem
,
825 u32 page_offset
, u32 num_pages
)
827 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
828 struct be_post_sgl_pages_req
*req
= embedded_payload(wrb
);
830 unsigned int curr_pages
;
831 u32 internal_page_offset
= 0;
832 u32 temp_num_pages
= num_pages
;
834 if (num_pages
== 0xff)
837 spin_lock(&ctrl
->mbox_lock
);
839 memset(wrb
, 0, sizeof(*wrb
));
840 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
841 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ISCSI
,
842 OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES
,
844 curr_pages
= BE_NUMBER_OF_FIELD(struct be_post_sgl_pages_req
,
846 req
->num_pages
= min(num_pages
, curr_pages
);
847 req
->page_offset
= page_offset
;
848 be_cmd_page_addrs_prepare(req
->pages
, req
->num_pages
, q_mem
);
849 q_mem
->dma
= q_mem
->dma
+ (req
->num_pages
* PAGE_SIZE
);
850 internal_page_offset
+= req
->num_pages
;
851 page_offset
+= req
->num_pages
;
852 num_pages
-= req
->num_pages
;
854 if (temp_num_pages
== 0xff)
855 req
->num_pages
= temp_num_pages
;
857 status
= be_mbox_notify(ctrl
);
860 "FW CMD to map iscsi frags failed.\n");
863 } while (num_pages
> 0);
865 spin_unlock(&ctrl
->mbox_lock
);
867 beiscsi_cmd_q_destroy(ctrl
, NULL
, QTYPE_SGL
);