2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9002_phy.h"
20 static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw
*ah
)
22 return (ah
->eeprom
.map9287
.baseEepHeader
.version
>> 12) & 0xF;
25 static int ath9k_hw_AR9287_get_eeprom_rev(struct ath_hw
*ah
)
27 return (ah
->eeprom
.map9287
.baseEepHeader
.version
) & 0xFFF;
30 static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw
*ah
)
32 struct ar9287_eeprom
*eep
= &ah
->eeprom
.map9287
;
33 struct ath_common
*common
= ath9k_hw_common(ah
);
35 int addr
, eep_start_loc
= AR9287_EEP_START_LOC
;
36 eep_data
= (u16
*)eep
;
38 if (!ath9k_hw_use_flash(ah
)) {
39 ath_print(common
, ATH_DBG_EEPROM
,
40 "Reading from EEPROM, not flash\n");
43 for (addr
= 0; addr
< sizeof(struct ar9287_eeprom
) / sizeof(u16
);
45 if (!ath9k_hw_nvram_read(common
,
46 addr
+ eep_start_loc
, eep_data
)) {
47 ath_print(common
, ATH_DBG_EEPROM
,
48 "Unable to read eeprom region\n");
56 static int ath9k_hw_AR9287_check_eeprom(struct ath_hw
*ah
)
58 u32 sum
= 0, el
, integer
;
59 u16 temp
, word
, magic
, magic2
, *eepdata
;
61 bool need_swap
= false;
62 struct ar9287_eeprom
*eep
= &ah
->eeprom
.map9287
;
63 struct ath_common
*common
= ath9k_hw_common(ah
);
65 if (!ath9k_hw_use_flash(ah
)) {
66 if (!ath9k_hw_nvram_read(common
,
67 AR5416_EEPROM_MAGIC_OFFSET
, &magic
)) {
68 ath_print(common
, ATH_DBG_FATAL
,
69 "Reading Magic # failed\n");
73 ath_print(common
, ATH_DBG_EEPROM
,
74 "Read Magic = 0x%04X\n", magic
);
75 if (magic
!= AR5416_EEPROM_MAGIC
) {
76 magic2
= swab16(magic
);
78 if (magic2
== AR5416_EEPROM_MAGIC
) {
80 eepdata
= (u16
*)(&ah
->eeprom
);
83 addr
< sizeof(struct ar9287_eeprom
) / sizeof(u16
);
85 temp
= swab16(*eepdata
);
90 ath_print(common
, ATH_DBG_FATAL
,
91 "Invalid EEPROM Magic. "
92 "endianness mismatch.\n");
97 ath_print(common
, ATH_DBG_EEPROM
, "need_swap = %s.\n", need_swap
?
101 el
= swab16(ah
->eeprom
.map9287
.baseEepHeader
.length
);
103 el
= ah
->eeprom
.map9287
.baseEepHeader
.length
;
105 if (el
> sizeof(struct ar9287_eeprom
))
106 el
= sizeof(struct ar9287_eeprom
) / sizeof(u16
);
108 el
= el
/ sizeof(u16
);
110 eepdata
= (u16
*)(&ah
->eeprom
);
111 for (i
= 0; i
< el
; i
++)
115 word
= swab16(eep
->baseEepHeader
.length
);
116 eep
->baseEepHeader
.length
= word
;
118 word
= swab16(eep
->baseEepHeader
.checksum
);
119 eep
->baseEepHeader
.checksum
= word
;
121 word
= swab16(eep
->baseEepHeader
.version
);
122 eep
->baseEepHeader
.version
= word
;
124 word
= swab16(eep
->baseEepHeader
.regDmn
[0]);
125 eep
->baseEepHeader
.regDmn
[0] = word
;
127 word
= swab16(eep
->baseEepHeader
.regDmn
[1]);
128 eep
->baseEepHeader
.regDmn
[1] = word
;
130 word
= swab16(eep
->baseEepHeader
.rfSilent
);
131 eep
->baseEepHeader
.rfSilent
= word
;
133 word
= swab16(eep
->baseEepHeader
.blueToothOptions
);
134 eep
->baseEepHeader
.blueToothOptions
= word
;
136 word
= swab16(eep
->baseEepHeader
.deviceCap
);
137 eep
->baseEepHeader
.deviceCap
= word
;
139 integer
= swab32(eep
->modalHeader
.antCtrlCommon
);
140 eep
->modalHeader
.antCtrlCommon
= integer
;
142 for (i
= 0; i
< AR9287_MAX_CHAINS
; i
++) {
143 integer
= swab32(eep
->modalHeader
.antCtrlChain
[i
]);
144 eep
->modalHeader
.antCtrlChain
[i
] = integer
;
147 for (i
= 0; i
< AR9287_EEPROM_MODAL_SPURS
; i
++) {
148 word
= swab16(eep
->modalHeader
.spurChans
[i
].spurChan
);
149 eep
->modalHeader
.spurChans
[i
].spurChan
= word
;
153 if (sum
!= 0xffff || ah
->eep_ops
->get_eeprom_ver(ah
) != AR9287_EEP_VER
154 || ah
->eep_ops
->get_eeprom_rev(ah
) < AR5416_EEP_NO_BACK_VER
) {
155 ath_print(common
, ATH_DBG_FATAL
,
156 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
157 sum
, ah
->eep_ops
->get_eeprom_ver(ah
));
164 static u32
ath9k_hw_AR9287_get_eeprom(struct ath_hw
*ah
,
165 enum eeprom_param param
)
167 struct ar9287_eeprom
*eep
= &ah
->eeprom
.map9287
;
168 struct modal_eep_ar9287_header
*pModal
= &eep
->modalHeader
;
169 struct base_eep_ar9287_header
*pBase
= &eep
->baseEepHeader
;
172 ver_minor
= pBase
->version
& AR9287_EEP_VER_MINOR_MASK
;
175 return pModal
->noiseFloorThreshCh
[0];
177 return pBase
->macAddr
[0] << 8 | pBase
->macAddr
[1];
179 return pBase
->macAddr
[2] << 8 | pBase
->macAddr
[3];
181 return pBase
->macAddr
[4] << 8 | pBase
->macAddr
[5];
183 return pBase
->regDmn
[0];
185 return pBase
->regDmn
[1];
187 return pBase
->deviceCap
;
189 return pBase
->opCapFlags
;
191 return pBase
->rfSilent
;
195 return pBase
->txMask
;
197 return pBase
->rxMask
;
199 return pBase
->deviceType
;
201 return pBase
->openLoopPwrCntl
;
202 case EEP_TEMPSENSE_SLOPE
:
203 if (ver_minor
>= AR9287_EEP_MINOR_VER_2
)
204 return pBase
->tempSensSlope
;
207 case EEP_TEMPSENSE_SLOPE_PAL_ON
:
208 if (ver_minor
>= AR9287_EEP_MINOR_VER_3
)
209 return pBase
->tempSensSlopePalOn
;
218 static void ath9k_hw_get_AR9287_gain_boundaries_pdadcs(struct ath_hw
*ah
,
219 struct ath9k_channel
*chan
,
220 struct cal_data_per_freq_ar9287
*pRawDataSet
,
221 u8
*bChans
, u16 availPiers
,
222 u16 tPdGainOverlap
, int16_t *pMinCalPower
,
223 u16
*pPdGainBoundaries
, u8
*pPDADCValues
,
226 #define TMP_VAL_VPD_TABLE \
227 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
231 u16 idxL
= 0, idxR
= 0, numPiers
;
232 u8
*pVpdL
, *pVpdR
, *pPwrL
, *pPwrR
;
233 u8 minPwrT4
[AR9287_NUM_PD_GAINS
];
234 u8 maxPwrT4
[AR9287_NUM_PD_GAINS
];
237 u16 sizeCurrVpdTable
, maxIndex
, tgtIndex
;
239 int16_t minDelta
= 0;
240 struct chan_centers centers
;
241 static u8 vpdTableL
[AR5416_EEP4K_NUM_PD_GAINS
]
242 [AR5416_MAX_PWR_RANGE_IN_HALF_DB
];
243 static u8 vpdTableR
[AR5416_EEP4K_NUM_PD_GAINS
]
244 [AR5416_MAX_PWR_RANGE_IN_HALF_DB
];
245 static u8 vpdTableI
[AR5416_EEP4K_NUM_PD_GAINS
]
246 [AR5416_MAX_PWR_RANGE_IN_HALF_DB
];
248 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
250 for (numPiers
= 0; numPiers
< availPiers
; numPiers
++) {
251 if (bChans
[numPiers
] == AR9287_BCHAN_UNUSED
)
255 match
= ath9k_hw_get_lower_upper_index(
256 (u8
)FREQ2FBIN(centers
.synth_center
,
257 IS_CHAN_2GHZ(chan
)), bChans
, numPiers
,
261 for (i
= 0; i
< numXpdGains
; i
++) {
262 minPwrT4
[i
] = pRawDataSet
[idxL
].pwrPdg
[i
][0];
263 maxPwrT4
[i
] = pRawDataSet
[idxL
].pwrPdg
[i
][4];
264 ath9k_hw_fill_vpd_table(minPwrT4
[i
], maxPwrT4
[i
],
265 pRawDataSet
[idxL
].pwrPdg
[i
],
266 pRawDataSet
[idxL
].vpdPdg
[i
],
267 AR9287_PD_GAIN_ICEPTS
, vpdTableI
[i
]);
270 for (i
= 0; i
< numXpdGains
; i
++) {
271 pVpdL
= pRawDataSet
[idxL
].vpdPdg
[i
];
272 pPwrL
= pRawDataSet
[idxL
].pwrPdg
[i
];
273 pVpdR
= pRawDataSet
[idxR
].vpdPdg
[i
];
274 pPwrR
= pRawDataSet
[idxR
].pwrPdg
[i
];
276 minPwrT4
[i
] = max(pPwrL
[0], pPwrR
[0]);
279 min(pPwrL
[AR9287_PD_GAIN_ICEPTS
- 1],
280 pPwrR
[AR9287_PD_GAIN_ICEPTS
- 1]);
282 ath9k_hw_fill_vpd_table(minPwrT4
[i
], maxPwrT4
[i
],
284 AR9287_PD_GAIN_ICEPTS
,
286 ath9k_hw_fill_vpd_table(minPwrT4
[i
], maxPwrT4
[i
],
288 AR9287_PD_GAIN_ICEPTS
,
291 for (j
= 0; j
<= (maxPwrT4
[i
] - minPwrT4
[i
]) / 2; j
++) {
293 (u8
)(ath9k_hw_interpolate((u16
)
294 FREQ2FBIN(centers
. synth_center
,
296 bChans
[idxL
], bChans
[idxR
],
297 vpdTableL
[i
][j
], vpdTableR
[i
][j
]));
301 *pMinCalPower
= (int16_t)(minPwrT4
[0] / 2);
304 for (i
= 0; i
< numXpdGains
; i
++) {
305 if (i
== (numXpdGains
- 1))
306 pPdGainBoundaries
[i
] = (u16
)(maxPwrT4
[i
] / 2);
308 pPdGainBoundaries
[i
] = (u16
)((maxPwrT4
[i
] +
311 pPdGainBoundaries
[i
] = min((u16
)AR5416_MAX_RATE_POWER
,
312 pPdGainBoundaries
[i
]);
315 if ((i
== 0) && !AR_SREV_5416_20_OR_LATER(ah
)) {
316 minDelta
= pPdGainBoundaries
[0] - 23;
317 pPdGainBoundaries
[0] = 23;
322 if (AR_SREV_9280_10_OR_LATER(ah
))
323 ss
= (int16_t)(0 - (minPwrT4
[i
] / 2));
327 ss
= (int16_t)((pPdGainBoundaries
[i
-1] -
329 tPdGainOverlap
+ 1 + minDelta
);
331 vpdStep
= (int16_t)(vpdTableI
[i
][1] - vpdTableI
[i
][0]);
332 vpdStep
= (int16_t)((vpdStep
< 1) ? 1 : vpdStep
);
333 while ((ss
< 0) && (k
< (AR9287_NUM_PDADC_VALUES
- 1))) {
334 tmpVal
= (int16_t)(vpdTableI
[i
][0] + ss
* vpdStep
);
335 pPDADCValues
[k
++] = (u8
)((tmpVal
< 0) ? 0 : tmpVal
);
339 sizeCurrVpdTable
= (u8
)((maxPwrT4
[i
] - minPwrT4
[i
]) / 2 + 1);
340 tgtIndex
= (u8
)(pPdGainBoundaries
[i
] +
341 tPdGainOverlap
- (minPwrT4
[i
] / 2));
342 maxIndex
= (tgtIndex
< sizeCurrVpdTable
) ?
343 tgtIndex
: sizeCurrVpdTable
;
345 while ((ss
< maxIndex
) && (k
< (AR9287_NUM_PDADC_VALUES
- 1)))
346 pPDADCValues
[k
++] = vpdTableI
[i
][ss
++];
348 vpdStep
= (int16_t)(vpdTableI
[i
][sizeCurrVpdTable
- 1] -
349 vpdTableI
[i
][sizeCurrVpdTable
- 2]);
350 vpdStep
= (int16_t)((vpdStep
< 1) ? 1 : vpdStep
);
351 if (tgtIndex
> maxIndex
) {
352 while ((ss
<= tgtIndex
) &&
353 (k
< (AR9287_NUM_PDADC_VALUES
- 1))) {
354 tmpVal
= (int16_t) TMP_VAL_VPD_TABLE
;
355 pPDADCValues
[k
++] = (u8
)((tmpVal
> 255) ?
362 while (i
< AR9287_PD_GAINS_IN_MASK
) {
363 pPdGainBoundaries
[i
] = pPdGainBoundaries
[i
-1];
367 while (k
< AR9287_NUM_PDADC_VALUES
) {
368 pPDADCValues
[k
] = pPDADCValues
[k
-1];
372 #undef TMP_VAL_VPD_TABLE
375 static void ar9287_eeprom_get_tx_gain_index(struct ath_hw
*ah
,
376 struct ath9k_channel
*chan
,
377 struct cal_data_op_loop_ar9287
*pRawDatasetOpLoop
,
378 u8
*pCalChans
, u16 availPiers
,
381 u16 idxL
= 0, idxR
= 0, numPiers
;
383 struct chan_centers centers
;
385 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
387 for (numPiers
= 0; numPiers
< availPiers
; numPiers
++) {
388 if (pCalChans
[numPiers
] == AR9287_BCHAN_UNUSED
)
392 match
= ath9k_hw_get_lower_upper_index(
393 (u8
)FREQ2FBIN(centers
.synth_center
, IS_CHAN_2GHZ(chan
)),
398 *pPwr
= (int8_t) pRawDatasetOpLoop
[idxL
].pwrPdg
[0][0];
400 *pPwr
= ((int8_t) pRawDatasetOpLoop
[idxL
].pwrPdg
[0][0] +
401 (int8_t) pRawDatasetOpLoop
[idxR
].pwrPdg
[0][0])/2;
406 static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw
*ah
,
407 int32_t txPower
, u16 chain
)
412 tmpVal
= REG_READ(ah
, 0xa270);
413 tmpVal
= tmpVal
& 0xFCFFFFFF;
414 tmpVal
= tmpVal
| (0x3 << 24);
415 REG_WRITE(ah
, 0xa270, tmpVal
);
417 tmpVal
= REG_READ(ah
, 0xb270);
418 tmpVal
= tmpVal
& 0xFCFFFFFF;
419 tmpVal
= tmpVal
| (0x3 << 24);
420 REG_WRITE(ah
, 0xb270, tmpVal
);
423 tmpVal
= REG_READ(ah
, 0xa398);
424 tmpVal
= tmpVal
& 0xff00ffff;
426 tmpVal
= tmpVal
| (a
<< 16);
427 REG_WRITE(ah
, 0xa398, tmpVal
);
431 tmpVal
= REG_READ(ah
, 0xb398);
432 tmpVal
= tmpVal
& 0xff00ffff;
434 tmpVal
= tmpVal
| (a
<< 16);
435 REG_WRITE(ah
, 0xb398, tmpVal
);
439 static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw
*ah
,
440 struct ath9k_channel
*chan
,
441 int16_t *pTxPowerIndexOffset
)
443 struct ath_common
*common
= ath9k_hw_common(ah
);
444 struct cal_data_per_freq_ar9287
*pRawDataset
;
445 struct cal_data_op_loop_ar9287
*pRawDatasetOpenLoop
;
446 u8
*pCalBChans
= NULL
;
447 u16 pdGainOverlap_t2
;
448 u8 pdadcValues
[AR9287_NUM_PDADC_VALUES
];
449 u16 gainBoundaries
[AR9287_PD_GAINS_IN_MASK
];
450 u16 numPiers
= 0, i
, j
;
451 int16_t tMinCalPower
;
452 u16 numXpdGain
, xpdMask
;
453 u16 xpdGainValues
[AR9287_NUM_PD_GAINS
] = {0, 0, 0, 0};
454 u32 reg32
, regOffset
, regChainOffset
;
455 int16_t modalIdx
, diff
= 0;
456 struct ar9287_eeprom
*pEepData
= &ah
->eeprom
.map9287
;
457 modalIdx
= IS_CHAN_2GHZ(chan
) ? 1 : 0;
458 xpdMask
= pEepData
->modalHeader
.xpdGain
;
459 if ((pEepData
->baseEepHeader
.version
& AR9287_EEP_VER_MINOR_MASK
) >=
460 AR9287_EEP_MINOR_VER_2
)
461 pdGainOverlap_t2
= pEepData
->modalHeader
.pdGainOverlap
;
463 pdGainOverlap_t2
= (u16
)(MS(REG_READ(ah
, AR_PHY_TPCRG5
),
464 AR_PHY_TPCRG5_PD_GAIN_OVERLAP
));
466 if (IS_CHAN_2GHZ(chan
)) {
467 pCalBChans
= pEepData
->calFreqPier2G
;
468 numPiers
= AR9287_NUM_2G_CAL_PIERS
;
469 if (ath9k_hw_AR9287_get_eeprom(ah
, EEP_OL_PWRCTRL
)) {
470 pRawDatasetOpenLoop
=
471 (struct cal_data_op_loop_ar9287
*)
472 pEepData
->calPierData2G
[0];
473 ah
->initPDADC
= pRawDatasetOpenLoop
->vpdPdg
[0][0];
478 for (i
= 1; i
<= AR9287_PD_GAINS_IN_MASK
; i
++) {
479 if ((xpdMask
>> (AR9287_PD_GAINS_IN_MASK
- i
)) & 1) {
480 if (numXpdGain
>= AR9287_NUM_PD_GAINS
)
482 xpdGainValues
[numXpdGain
] =
483 (u16
)(AR9287_PD_GAINS_IN_MASK
-i
);
488 REG_RMW_FIELD(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_NUM_PD_GAIN
,
489 (numXpdGain
- 1) & 0x3);
490 REG_RMW_FIELD(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_PD_GAIN_1
,
492 REG_RMW_FIELD(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_PD_GAIN_2
,
494 REG_RMW_FIELD(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_PD_GAIN_3
,
497 for (i
= 0; i
< AR9287_MAX_CHAINS
; i
++) {
498 regChainOffset
= i
* 0x1000;
499 if (pEepData
->baseEepHeader
.txMask
& (1 << i
)) {
500 pRawDatasetOpenLoop
= (struct cal_data_op_loop_ar9287
*)
501 pEepData
->calPierData2G
[i
];
502 if (ath9k_hw_AR9287_get_eeprom(ah
, EEP_OL_PWRCTRL
)) {
504 ar9287_eeprom_get_tx_gain_index(ah
, chan
,
506 pCalBChans
, numPiers
,
508 ar9287_eeprom_olpc_set_pdadcs(ah
, txPower
, i
);
511 (struct cal_data_per_freq_ar9287
*)
512 pEepData
->calPierData2G
[i
];
513 ath9k_hw_get_AR9287_gain_boundaries_pdadcs(
514 ah
, chan
, pRawDataset
,
515 pCalBChans
, numPiers
,
517 &tMinCalPower
, gainBoundaries
,
518 pdadcValues
, numXpdGain
);
522 if (!ath9k_hw_AR9287_get_eeprom(
523 ah
, EEP_OL_PWRCTRL
)) {
524 REG_WRITE(ah
, AR_PHY_TPCRG5
+
527 AR_PHY_TPCRG5_PD_GAIN_OVERLAP
) |
528 SM(gainBoundaries
[0],
529 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1
)
530 | SM(gainBoundaries
[1],
531 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2
)
532 | SM(gainBoundaries
[2],
533 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3
)
534 | SM(gainBoundaries
[3],
535 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4
));
539 if ((int32_t)AR9287_PWR_TABLE_OFFSET_DB
!=
540 pEepData
->baseEepHeader
.pwrTableOffset
) {
542 (pEepData
->baseEepHeader
.pwrTableOffset
543 - (int32_t)AR9287_PWR_TABLE_OFFSET_DB
);
547 j
< ((u16
)AR9287_NUM_PDADC_VALUES
-diff
);
549 pdadcValues
[j
] = pdadcValues
[j
+diff
];
551 for (j
= (u16
)(AR9287_NUM_PDADC_VALUES
-diff
);
552 j
< AR9287_NUM_PDADC_VALUES
; j
++)
555 AR9287_NUM_PDADC_VALUES
-diff
];
558 if (!ath9k_hw_AR9287_get_eeprom(ah
, EEP_OL_PWRCTRL
)) {
559 regOffset
= AR_PHY_BASE
+ (672 << 2) +
561 for (j
= 0; j
< 32; j
++) {
562 reg32
= ((pdadcValues
[4*j
+ 0]
564 ((pdadcValues
[4*j
+ 1]
566 ((pdadcValues
[4*j
+ 2]
568 ((pdadcValues
[4*j
+ 3]
570 REG_WRITE(ah
, regOffset
, reg32
);
572 ath_print(common
, ATH_DBG_EEPROM
,
573 "PDADC (%d,%4x): %4.4x "
575 i
, regChainOffset
, regOffset
,
578 ath_print(common
, ATH_DBG_EEPROM
,
580 "PDADC %3d Value %3d | "
581 "PDADC %3d Value %3d | "
582 "PDADC %3d Value %3d | "
583 "PDADC %3d Value %3d |\n",
584 i
, 4 * j
, pdadcValues
[4 * j
],
586 pdadcValues
[4 * j
+ 1],
588 pdadcValues
[4 * j
+ 2],
590 pdadcValues
[4 * j
+ 3]);
598 *pTxPowerIndexOffset
= 0;
601 static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw
*ah
,
602 struct ath9k_channel
*chan
, int16_t *ratesArray
, u16 cfgCtl
,
603 u16 AntennaReduction
, u16 twiceMaxRegulatoryPower
,
606 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6
607 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10
608 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
609 u16 twiceMaxEdgePower
= AR5416_MAX_RATE_POWER
;
610 static const u16 tpScaleReductionTable
[5] =
611 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER
};
613 int16_t twiceLargestAntenna
;
614 struct cal_ctl_data_ar9287
*rep
;
615 struct cal_target_power_leg targetPowerOfdm
= {0, {0, 0, 0, 0} },
616 targetPowerCck
= {0, {0, 0, 0, 0} };
617 struct cal_target_power_leg targetPowerOfdmExt
= {0, {0, 0, 0, 0} },
618 targetPowerCckExt
= {0, {0, 0, 0, 0} };
619 struct cal_target_power_ht targetPowerHt20
,
620 targetPowerHt40
= {0, {0, 0, 0, 0} };
621 u16 scaledPower
= 0, minCtlPower
, maxRegAllowedPower
;
622 u16 ctlModesFor11g
[] =
623 {CTL_11B
, CTL_11G
, CTL_2GHT20
,
624 CTL_11B_EXT
, CTL_11G_EXT
, CTL_2GHT40
};
625 u16 numCtlModes
= 0, *pCtlMode
= NULL
, ctlMode
, freq
;
626 struct chan_centers centers
;
628 u16 twiceMinEdgePower
;
629 struct ar9287_eeprom
*pEepData
= &ah
->eeprom
.map9287
;
630 tx_chainmask
= ah
->txchainmask
;
632 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
634 twiceLargestAntenna
= max(pEepData
->modalHeader
.antennaGainCh
[0],
635 pEepData
->modalHeader
.antennaGainCh
[1]);
637 twiceLargestAntenna
= (int16_t)min((AntennaReduction
) -
638 twiceLargestAntenna
, 0);
640 maxRegAllowedPower
= twiceMaxRegulatoryPower
+ twiceLargestAntenna
;
641 if (regulatory
->tp_scale
!= ATH9K_TP_SCALE_MAX
)
642 maxRegAllowedPower
-=
643 (tpScaleReductionTable
[(regulatory
->tp_scale
)] * 2);
645 scaledPower
= min(powerLimit
, maxRegAllowedPower
);
647 switch (ar5416_get_ntxchains(tx_chainmask
)) {
651 scaledPower
-= REDUCE_SCALED_POWER_BY_TWO_CHAIN
;
654 scaledPower
-= REDUCE_SCALED_POWER_BY_THREE_CHAIN
;
657 scaledPower
= max((u16
)0, scaledPower
);
659 if (IS_CHAN_2GHZ(chan
)) {
661 ARRAY_SIZE(ctlModesFor11g
) - SUB_NUM_CTL_MODES_AT_2G_40
;
662 pCtlMode
= ctlModesFor11g
;
664 ath9k_hw_get_legacy_target_powers(ah
, chan
,
665 pEepData
->calTargetPowerCck
,
666 AR9287_NUM_2G_CCK_TARGET_POWERS
,
667 &targetPowerCck
, 4, false);
668 ath9k_hw_get_legacy_target_powers(ah
, chan
,
669 pEepData
->calTargetPower2G
,
670 AR9287_NUM_2G_20_TARGET_POWERS
,
671 &targetPowerOfdm
, 4, false);
672 ath9k_hw_get_target_powers(ah
, chan
,
673 pEepData
->calTargetPower2GHT20
,
674 AR9287_NUM_2G_20_TARGET_POWERS
,
675 &targetPowerHt20
, 8, false);
677 if (IS_CHAN_HT40(chan
)) {
678 numCtlModes
= ARRAY_SIZE(ctlModesFor11g
);
679 ath9k_hw_get_target_powers(ah
, chan
,
680 pEepData
->calTargetPower2GHT40
,
681 AR9287_NUM_2G_40_TARGET_POWERS
,
682 &targetPowerHt40
, 8, true);
683 ath9k_hw_get_legacy_target_powers(ah
, chan
,
684 pEepData
->calTargetPowerCck
,
685 AR9287_NUM_2G_CCK_TARGET_POWERS
,
686 &targetPowerCckExt
, 4, true);
687 ath9k_hw_get_legacy_target_powers(ah
, chan
,
688 pEepData
->calTargetPower2G
,
689 AR9287_NUM_2G_20_TARGET_POWERS
,
690 &targetPowerOfdmExt
, 4, true);
694 for (ctlMode
= 0; ctlMode
< numCtlModes
; ctlMode
++) {
695 bool isHt40CtlMode
= (pCtlMode
[ctlMode
] == CTL_5GHT40
) ||
696 (pCtlMode
[ctlMode
] == CTL_2GHT40
);
698 freq
= centers
.synth_center
;
699 else if (pCtlMode
[ctlMode
] & EXT_ADDITIVE
)
700 freq
= centers
.ext_center
;
702 freq
= centers
.ctl_center
;
704 if (ah
->eep_ops
->get_eeprom_ver(ah
) == 14 &&
705 ah
->eep_ops
->get_eeprom_rev(ah
) <= 2)
706 twiceMaxEdgePower
= AR5416_MAX_RATE_POWER
;
708 for (i
= 0; (i
< AR9287_NUM_CTLS
) && pEepData
->ctlIndex
[i
]; i
++) {
709 if ((((cfgCtl
& ~CTL_MODE_M
) |
710 (pCtlMode
[ctlMode
] & CTL_MODE_M
)) ==
711 pEepData
->ctlIndex
[i
]) ||
712 (((cfgCtl
& ~CTL_MODE_M
) |
713 (pCtlMode
[ctlMode
] & CTL_MODE_M
)) ==
714 ((pEepData
->ctlIndex
[i
] &
715 CTL_MODE_M
) | SD_NO_CTL
))) {
717 rep
= &(pEepData
->ctlData
[i
]);
718 twiceMinEdgePower
= ath9k_hw_get_max_edge_power(
720 rep
->ctlEdges
[ar5416_get_ntxchains(
722 IS_CHAN_2GHZ(chan
), AR5416_NUM_BAND_EDGES
);
724 if ((cfgCtl
& ~CTL_MODE_M
) == SD_NO_CTL
)
725 twiceMaxEdgePower
= min(
729 twiceMaxEdgePower
= twiceMinEdgePower
;
735 minCtlPower
= (u8
)min(twiceMaxEdgePower
, scaledPower
);
737 switch (pCtlMode
[ctlMode
]) {
740 i
< ARRAY_SIZE(targetPowerCck
.tPow2x
);
742 targetPowerCck
.tPow2x
[i
] = (u8
)min(
743 (u16
)targetPowerCck
.tPow2x
[i
],
750 i
< ARRAY_SIZE(targetPowerOfdm
.tPow2x
);
752 targetPowerOfdm
.tPow2x
[i
] = (u8
)min(
753 (u16
)targetPowerOfdm
.tPow2x
[i
],
760 i
< ARRAY_SIZE(targetPowerHt20
.tPow2x
);
762 targetPowerHt20
.tPow2x
[i
] = (u8
)min(
763 (u16
)targetPowerHt20
.tPow2x
[i
],
768 targetPowerCckExt
.tPow2x
[0] = (u8
)min(
769 (u16
)targetPowerCckExt
.tPow2x
[0],
774 targetPowerOfdmExt
.tPow2x
[0] = (u8
)min(
775 (u16
)targetPowerOfdmExt
.tPow2x
[0],
781 i
< ARRAY_SIZE(targetPowerHt40
.tPow2x
);
783 targetPowerHt40
.tPow2x
[i
] = (u8
)min(
784 (u16
)targetPowerHt40
.tPow2x
[i
],
793 ratesArray
[rate6mb
] =
794 ratesArray
[rate9mb
] =
795 ratesArray
[rate12mb
] =
796 ratesArray
[rate18mb
] =
797 ratesArray
[rate24mb
] =
798 targetPowerOfdm
.tPow2x
[0];
800 ratesArray
[rate36mb
] = targetPowerOfdm
.tPow2x
[1];
801 ratesArray
[rate48mb
] = targetPowerOfdm
.tPow2x
[2];
802 ratesArray
[rate54mb
] = targetPowerOfdm
.tPow2x
[3];
803 ratesArray
[rateXr
] = targetPowerOfdm
.tPow2x
[0];
805 for (i
= 0; i
< ARRAY_SIZE(targetPowerHt20
.tPow2x
); i
++)
806 ratesArray
[rateHt20_0
+ i
] = targetPowerHt20
.tPow2x
[i
];
808 if (IS_CHAN_2GHZ(chan
)) {
809 ratesArray
[rate1l
] = targetPowerCck
.tPow2x
[0];
810 ratesArray
[rate2s
] = ratesArray
[rate2l
] =
811 targetPowerCck
.tPow2x
[1];
812 ratesArray
[rate5_5s
] = ratesArray
[rate5_5l
] =
813 targetPowerCck
.tPow2x
[2];
814 ratesArray
[rate11s
] = ratesArray
[rate11l
] =
815 targetPowerCck
.tPow2x
[3];
817 if (IS_CHAN_HT40(chan
)) {
818 for (i
= 0; i
< ARRAY_SIZE(targetPowerHt40
.tPow2x
); i
++)
819 ratesArray
[rateHt40_0
+ i
] = targetPowerHt40
.tPow2x
[i
];
821 ratesArray
[rateDupOfdm
] = targetPowerHt40
.tPow2x
[0];
822 ratesArray
[rateDupCck
] = targetPowerHt40
.tPow2x
[0];
823 ratesArray
[rateExtOfdm
] = targetPowerOfdmExt
.tPow2x
[0];
824 if (IS_CHAN_2GHZ(chan
))
825 ratesArray
[rateExtCck
] = targetPowerCckExt
.tPow2x
[0];
828 #undef REDUCE_SCALED_POWER_BY_TWO_CHAIN
829 #undef REDUCE_SCALED_POWER_BY_THREE_CHAIN
832 static void ath9k_hw_AR9287_set_txpower(struct ath_hw
*ah
,
833 struct ath9k_channel
*chan
, u16 cfgCtl
,
834 u8 twiceAntennaReduction
,
835 u8 twiceMaxRegulatoryPower
,
838 #define INCREASE_MAXPOW_BY_TWO_CHAIN 6
839 #define INCREASE_MAXPOW_BY_THREE_CHAIN 10
840 struct ath_common
*common
= ath9k_hw_common(ah
);
841 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
842 struct ar9287_eeprom
*pEepData
= &ah
->eeprom
.map9287
;
843 struct modal_eep_ar9287_header
*pModal
= &pEepData
->modalHeader
;
844 int16_t ratesArray
[Ar5416RateSize
];
845 int16_t txPowerIndexOffset
= 0;
846 u8 ht40PowerIncForPdadc
= 2;
849 memset(ratesArray
, 0, sizeof(ratesArray
));
851 if ((pEepData
->baseEepHeader
.version
& AR9287_EEP_VER_MINOR_MASK
) >=
852 AR9287_EEP_MINOR_VER_2
)
853 ht40PowerIncForPdadc
= pModal
->ht40PowerIncForPdadc
;
855 ath9k_hw_set_AR9287_power_per_rate_table(ah
, chan
,
856 &ratesArray
[0], cfgCtl
,
857 twiceAntennaReduction
,
858 twiceMaxRegulatoryPower
,
861 ath9k_hw_set_AR9287_power_cal_table(ah
, chan
, &txPowerIndexOffset
);
863 for (i
= 0; i
< ARRAY_SIZE(ratesArray
); i
++) {
864 ratesArray
[i
] = (int16_t)(txPowerIndexOffset
+ ratesArray
[i
]);
865 if (ratesArray
[i
] > AR9287_MAX_RATE_POWER
)
866 ratesArray
[i
] = AR9287_MAX_RATE_POWER
;
869 if (AR_SREV_9280_10_OR_LATER(ah
)) {
870 for (i
= 0; i
< Ar5416RateSize
; i
++)
871 ratesArray
[i
] -= AR9287_PWR_TABLE_OFFSET_DB
* 2;
874 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE1
,
875 ATH9K_POW_SM(ratesArray
[rate18mb
], 24)
876 | ATH9K_POW_SM(ratesArray
[rate12mb
], 16)
877 | ATH9K_POW_SM(ratesArray
[rate9mb
], 8)
878 | ATH9K_POW_SM(ratesArray
[rate6mb
], 0));
880 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE2
,
881 ATH9K_POW_SM(ratesArray
[rate54mb
], 24)
882 | ATH9K_POW_SM(ratesArray
[rate48mb
], 16)
883 | ATH9K_POW_SM(ratesArray
[rate36mb
], 8)
884 | ATH9K_POW_SM(ratesArray
[rate24mb
], 0));
886 if (IS_CHAN_2GHZ(chan
)) {
887 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE3
,
888 ATH9K_POW_SM(ratesArray
[rate2s
], 24)
889 | ATH9K_POW_SM(ratesArray
[rate2l
], 16)
890 | ATH9K_POW_SM(ratesArray
[rateXr
], 8)
891 | ATH9K_POW_SM(ratesArray
[rate1l
], 0));
892 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE4
,
893 ATH9K_POW_SM(ratesArray
[rate11s
], 24)
894 | ATH9K_POW_SM(ratesArray
[rate11l
], 16)
895 | ATH9K_POW_SM(ratesArray
[rate5_5s
], 8)
896 | ATH9K_POW_SM(ratesArray
[rate5_5l
], 0));
899 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE5
,
900 ATH9K_POW_SM(ratesArray
[rateHt20_3
], 24)
901 | ATH9K_POW_SM(ratesArray
[rateHt20_2
], 16)
902 | ATH9K_POW_SM(ratesArray
[rateHt20_1
], 8)
903 | ATH9K_POW_SM(ratesArray
[rateHt20_0
], 0));
905 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE6
,
906 ATH9K_POW_SM(ratesArray
[rateHt20_7
], 24)
907 | ATH9K_POW_SM(ratesArray
[rateHt20_6
], 16)
908 | ATH9K_POW_SM(ratesArray
[rateHt20_5
], 8)
909 | ATH9K_POW_SM(ratesArray
[rateHt20_4
], 0));
911 if (IS_CHAN_HT40(chan
)) {
912 if (ath9k_hw_AR9287_get_eeprom(ah
, EEP_OL_PWRCTRL
)) {
913 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE7
,
914 ATH9K_POW_SM(ratesArray
[rateHt40_3
], 24)
915 | ATH9K_POW_SM(ratesArray
[rateHt40_2
], 16)
916 | ATH9K_POW_SM(ratesArray
[rateHt40_1
], 8)
917 | ATH9K_POW_SM(ratesArray
[rateHt40_0
], 0));
919 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE8
,
920 ATH9K_POW_SM(ratesArray
[rateHt40_7
], 24)
921 | ATH9K_POW_SM(ratesArray
[rateHt40_6
], 16)
922 | ATH9K_POW_SM(ratesArray
[rateHt40_5
], 8)
923 | ATH9K_POW_SM(ratesArray
[rateHt40_4
], 0));
925 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE7
,
926 ATH9K_POW_SM(ratesArray
[rateHt40_3
] +
927 ht40PowerIncForPdadc
, 24)
928 | ATH9K_POW_SM(ratesArray
[rateHt40_2
] +
929 ht40PowerIncForPdadc
, 16)
930 | ATH9K_POW_SM(ratesArray
[rateHt40_1
] +
931 ht40PowerIncForPdadc
, 8)
932 | ATH9K_POW_SM(ratesArray
[rateHt40_0
] +
933 ht40PowerIncForPdadc
, 0));
935 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE8
,
936 ATH9K_POW_SM(ratesArray
[rateHt40_7
] +
937 ht40PowerIncForPdadc
, 24)
938 | ATH9K_POW_SM(ratesArray
[rateHt40_6
] +
939 ht40PowerIncForPdadc
, 16)
940 | ATH9K_POW_SM(ratesArray
[rateHt40_5
] +
941 ht40PowerIncForPdadc
, 8)
942 | ATH9K_POW_SM(ratesArray
[rateHt40_4
] +
943 ht40PowerIncForPdadc
, 0));
946 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE9
,
947 ATH9K_POW_SM(ratesArray
[rateExtOfdm
], 24)
948 | ATH9K_POW_SM(ratesArray
[rateExtCck
], 16)
949 | ATH9K_POW_SM(ratesArray
[rateDupOfdm
], 8)
950 | ATH9K_POW_SM(ratesArray
[rateDupCck
], 0));
953 if (IS_CHAN_2GHZ(chan
))
958 if (AR_SREV_9280_10_OR_LATER(ah
))
959 regulatory
->max_power_level
=
960 ratesArray
[i
] + AR9287_PWR_TABLE_OFFSET_DB
* 2;
962 regulatory
->max_power_level
= ratesArray
[i
];
964 switch (ar5416_get_ntxchains(ah
->txchainmask
)) {
968 regulatory
->max_power_level
+=
969 INCREASE_MAXPOW_BY_TWO_CHAIN
;
972 regulatory
->max_power_level
+=
973 INCREASE_MAXPOW_BY_THREE_CHAIN
;
976 ath_print(common
, ATH_DBG_EEPROM
,
977 "Invalid chainmask configuration\n");
982 static void ath9k_hw_AR9287_set_addac(struct ath_hw
*ah
,
983 struct ath9k_channel
*chan
)
987 static void ath9k_hw_AR9287_set_board_values(struct ath_hw
*ah
,
988 struct ath9k_channel
*chan
)
990 struct ar9287_eeprom
*eep
= &ah
->eeprom
.map9287
;
991 struct modal_eep_ar9287_header
*pModal
= &eep
->modalHeader
;
992 u16 antWrites
[AR9287_ANT_16S
];
995 int i
, j
, offset_num
;
997 pModal
= &eep
->modalHeader
;
999 antWrites
[0] = (u16
)((pModal
->antCtrlCommon
>> 28) & 0xF);
1000 antWrites
[1] = (u16
)((pModal
->antCtrlCommon
>> 24) & 0xF);
1001 antWrites
[2] = (u16
)((pModal
->antCtrlCommon
>> 20) & 0xF);
1002 antWrites
[3] = (u16
)((pModal
->antCtrlCommon
>> 16) & 0xF);
1003 antWrites
[4] = (u16
)((pModal
->antCtrlCommon
>> 12) & 0xF);
1004 antWrites
[5] = (u16
)((pModal
->antCtrlCommon
>> 8) & 0xF);
1005 antWrites
[6] = (u16
)((pModal
->antCtrlCommon
>> 4) & 0xF);
1006 antWrites
[7] = (u16
)(pModal
->antCtrlCommon
& 0xF);
1010 for (i
= 0, j
= offset_num
; i
< AR9287_MAX_CHAINS
; i
++) {
1011 antWrites
[j
++] = (u16
)((pModal
->antCtrlChain
[i
] >> 28) & 0xf);
1012 antWrites
[j
++] = (u16
)((pModal
->antCtrlChain
[i
] >> 10) & 0x3);
1013 antWrites
[j
++] = (u16
)((pModal
->antCtrlChain
[i
] >> 8) & 0x3);
1015 antWrites
[j
++] = (u16
)((pModal
->antCtrlChain
[i
] >> 6) & 0x3);
1016 antWrites
[j
++] = (u16
)((pModal
->antCtrlChain
[i
] >> 4) & 0x3);
1017 antWrites
[j
++] = (u16
)((pModal
->antCtrlChain
[i
] >> 2) & 0x3);
1018 antWrites
[j
++] = (u16
)(pModal
->antCtrlChain
[i
] & 0x3);
1021 REG_WRITE(ah
, AR_PHY_SWITCH_COM
,
1022 ah
->eep_ops
->get_eeprom_antenna_cfg(ah
, chan
));
1024 for (i
= 0; i
< AR9287_MAX_CHAINS
; i
++) {
1025 regChainOffset
= i
* 0x1000;
1027 REG_WRITE(ah
, AR_PHY_SWITCH_CHAIN_0
+ regChainOffset
,
1028 pModal
->antCtrlChain
[i
]);
1030 REG_WRITE(ah
, AR_PHY_TIMING_CTRL4(0) + regChainOffset
,
1031 (REG_READ(ah
, AR_PHY_TIMING_CTRL4(0) + regChainOffset
)
1032 & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF
|
1033 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF
)) |
1034 SM(pModal
->iqCalICh
[i
],
1035 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF
) |
1036 SM(pModal
->iqCalQCh
[i
],
1037 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF
));
1039 txRxAttenLocal
= pModal
->txRxAttenCh
[i
];
1041 REG_RMW_FIELD(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
1042 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN
,
1043 pModal
->bswMargin
[i
]);
1044 REG_RMW_FIELD(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
1045 AR_PHY_GAIN_2GHZ_XATTEN1_DB
,
1046 pModal
->bswAtten
[i
]);
1047 REG_RMW_FIELD(ah
, AR_PHY_RXGAIN
+ regChainOffset
,
1048 AR9280_PHY_RXGAIN_TXRX_ATTEN
,
1050 REG_RMW_FIELD(ah
, AR_PHY_RXGAIN
+ regChainOffset
,
1051 AR9280_PHY_RXGAIN_TXRX_MARGIN
,
1052 pModal
->rxTxMarginCh
[i
]);
1056 if (IS_CHAN_HT40(chan
))
1057 REG_RMW_FIELD(ah
, AR_PHY_SETTLING
,
1058 AR_PHY_SETTLING_SWITCH
, pModal
->swSettleHt40
);
1060 REG_RMW_FIELD(ah
, AR_PHY_SETTLING
,
1061 AR_PHY_SETTLING_SWITCH
, pModal
->switchSettling
);
1063 REG_RMW_FIELD(ah
, AR_PHY_DESIRED_SZ
,
1064 AR_PHY_DESIRED_SZ_ADC
, pModal
->adcDesiredSize
);
1066 REG_WRITE(ah
, AR_PHY_RF_CTL4
,
1067 SM(pModal
->txEndToXpaOff
, AR_PHY_RF_CTL4_TX_END_XPAA_OFF
)
1068 | SM(pModal
->txEndToXpaOff
, AR_PHY_RF_CTL4_TX_END_XPAB_OFF
)
1069 | SM(pModal
->txFrameToXpaOn
, AR_PHY_RF_CTL4_FRAME_XPAA_ON
)
1070 | SM(pModal
->txFrameToXpaOn
, AR_PHY_RF_CTL4_FRAME_XPAB_ON
));
1072 REG_RMW_FIELD(ah
, AR_PHY_RF_CTL3
,
1073 AR_PHY_TX_END_TO_A2_RX_ON
, pModal
->txEndToRxOn
);
1075 REG_RMW_FIELD(ah
, AR_PHY_CCA
,
1076 AR9280_PHY_CCA_THRESH62
, pModal
->thresh62
);
1077 REG_RMW_FIELD(ah
, AR_PHY_EXT_CCA0
,
1078 AR_PHY_EXT_CCA0_THRESH62
, pModal
->thresh62
);
1080 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_RF2G3_CH0
, AR9287_AN_RF2G3_DB1
,
1081 AR9287_AN_RF2G3_DB1_S
, pModal
->db1
);
1082 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_RF2G3_CH0
, AR9287_AN_RF2G3_DB2
,
1083 AR9287_AN_RF2G3_DB2_S
, pModal
->db2
);
1084 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_RF2G3_CH0
,
1085 AR9287_AN_RF2G3_OB_CCK
,
1086 AR9287_AN_RF2G3_OB_CCK_S
, pModal
->ob_cck
);
1087 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_RF2G3_CH0
,
1088 AR9287_AN_RF2G3_OB_PSK
,
1089 AR9287_AN_RF2G3_OB_PSK_S
, pModal
->ob_psk
);
1090 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_RF2G3_CH0
,
1091 AR9287_AN_RF2G3_OB_QAM
,
1092 AR9287_AN_RF2G3_OB_QAM_S
, pModal
->ob_qam
);
1093 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_RF2G3_CH0
,
1094 AR9287_AN_RF2G3_OB_PAL_OFF
,
1095 AR9287_AN_RF2G3_OB_PAL_OFF_S
,
1096 pModal
->ob_pal_off
);
1098 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_RF2G3_CH1
,
1099 AR9287_AN_RF2G3_DB1
, AR9287_AN_RF2G3_DB1_S
,
1101 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_RF2G3_CH1
, AR9287_AN_RF2G3_DB2
,
1102 AR9287_AN_RF2G3_DB2_S
, pModal
->db2
);
1103 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_RF2G3_CH1
,
1104 AR9287_AN_RF2G3_OB_CCK
,
1105 AR9287_AN_RF2G3_OB_CCK_S
, pModal
->ob_cck
);
1106 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_RF2G3_CH1
,
1107 AR9287_AN_RF2G3_OB_PSK
,
1108 AR9287_AN_RF2G3_OB_PSK_S
, pModal
->ob_psk
);
1109 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_RF2G3_CH1
,
1110 AR9287_AN_RF2G3_OB_QAM
,
1111 AR9287_AN_RF2G3_OB_QAM_S
, pModal
->ob_qam
);
1112 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_RF2G3_CH1
,
1113 AR9287_AN_RF2G3_OB_PAL_OFF
,
1114 AR9287_AN_RF2G3_OB_PAL_OFF_S
,
1115 pModal
->ob_pal_off
);
1117 REG_RMW_FIELD(ah
, AR_PHY_RF_CTL2
,
1118 AR_PHY_TX_END_DATA_START
, pModal
->txFrameToDataStart
);
1119 REG_RMW_FIELD(ah
, AR_PHY_RF_CTL2
,
1120 AR_PHY_TX_END_PA_ON
, pModal
->txFrameToPaOn
);
1122 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_TOP2
,
1123 AR9287_AN_TOP2_XPABIAS_LVL
,
1124 AR9287_AN_TOP2_XPABIAS_LVL_S
,
1125 pModal
->xpaBiasLvl
);
1128 static u8
ath9k_hw_AR9287_get_num_ant_config(struct ath_hw
*ah
,
1129 enum ieee80211_band freq_band
)
1134 static u16
ath9k_hw_AR9287_get_eeprom_antenna_cfg(struct ath_hw
*ah
,
1135 struct ath9k_channel
*chan
)
1137 struct ar9287_eeprom
*eep
= &ah
->eeprom
.map9287
;
1138 struct modal_eep_ar9287_header
*pModal
= &eep
->modalHeader
;
1140 return pModal
->antCtrlCommon
& 0xFFFF;
1143 static u16
ath9k_hw_AR9287_get_spur_channel(struct ath_hw
*ah
,
1146 #define EEP_MAP9287_SPURCHAN \
1147 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
1148 struct ath_common
*common
= ath9k_hw_common(ah
);
1149 u16 spur_val
= AR_NO_SPUR
;
1151 ath_print(common
, ATH_DBG_ANI
,
1152 "Getting spur idx %d is2Ghz. %d val %x\n",
1153 i
, is2GHz
, ah
->config
.spurchans
[i
][is2GHz
]);
1155 switch (ah
->config
.spurmode
) {
1158 case SPUR_ENABLE_IOCTL
:
1159 spur_val
= ah
->config
.spurchans
[i
][is2GHz
];
1160 ath_print(common
, ATH_DBG_ANI
,
1161 "Getting spur val from new loc. %d\n", spur_val
);
1163 case SPUR_ENABLE_EEPROM
:
1164 spur_val
= EEP_MAP9287_SPURCHAN
;
1170 #undef EEP_MAP9287_SPURCHAN
1173 const struct eeprom_ops eep_ar9287_ops
= {
1174 .check_eeprom
= ath9k_hw_AR9287_check_eeprom
,
1175 .get_eeprom
= ath9k_hw_AR9287_get_eeprom
,
1176 .fill_eeprom
= ath9k_hw_AR9287_fill_eeprom
,
1177 .get_eeprom_ver
= ath9k_hw_AR9287_get_eeprom_ver
,
1178 .get_eeprom_rev
= ath9k_hw_AR9287_get_eeprom_rev
,
1179 .get_num_ant_config
= ath9k_hw_AR9287_get_num_ant_config
,
1180 .get_eeprom_antenna_cfg
= ath9k_hw_AR9287_get_eeprom_antenna_cfg
,
1181 .set_board_values
= ath9k_hw_AR9287_set_board_values
,
1182 .set_addac
= ath9k_hw_AR9287_set_addac
,
1183 .set_txpower
= ath9k_hw_AR9287_set_txpower
,
1184 .get_spur_channel
= ath9k_hw_AR9287_get_spur_channel