arch/x86/oprofile/nmi_int.c

   1 /**
   2  * @file nmi_int.c
   3  *
   4  * @remark Copyright 2002-2009 OProfile authors
   5  * @remark Read the file COPYING
   6  *
   7  * @author John Levon <levon@movementarian.org>
   8  * @author Robert Richter <robert.richter@amd.com>
   9  * @author Barry Kasindorf <barry.kasindorf@amd.com>
  10  * @author Jason Yeh <jason.yeh@amd.com>
  11  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/notifier.h>
  16 #include <linux/smp.h>
  17 #include <linux/oprofile.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/slab.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/cpu.h>
  23 #include <asm/nmi.h>
  24 #include <asm/msr.h>
  25 #include <asm/apic.h>
  26
  27 #include "op_counter.h"
  28 #include "op_x86_model.h"
  29
  30 static struct op_x86_model_spec const *model;
  31 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
  32 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
  33
  34 /* 0 == registered but off, 1 == registered and on */
  35 static int nmi_enabled = 0;
  36
  37
  38 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
  39 extern atomic_t multiplex_counter;
  40 #endif
  41
  42 struct op_counter_config counter_config[OP_MAX_COUNTER];
  43
  44 /* common functions */
  45
  46 u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
  47                     struct op_counter_config *counter_config)
  48 {
  49         u64 val = 0;
  50         u16 event = (u16)counter_config->event;
  51
  52         val |= ARCH_PERFMON_EVENTSEL_INT;
  53         val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
  54         val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
  55         val |= (counter_config->unit_mask & 0xFF) << 8;
  56         event &= model->event_mask ? model->event_mask : 0xFF;
  57         val |= event & 0xFF;
  58         val |= (event & 0x0F00) << 24;
  59
  60         return val;
  61 }
  62
  63
  64 static int profile_exceptions_notify(struct notifier_block *self,
  65                                      unsigned long val, void *data)
  66 {
  67         struct die_args *args = (struct die_args *)data;
  68         int ret = NOTIFY_DONE;
  69         int cpu = smp_processor_id();
  70
  71         switch (val) {
  72         case DIE_NMI:
  73         case DIE_NMI_IPI:
  74                 model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
  75                 ret = NOTIFY_STOP;
  76                 break;
  77         default:
  78                 break;
  79         }
  80         return ret;
  81 }
  82
  83 static void nmi_cpu_save_registers(struct op_msrs *msrs)
  84 {
  85         struct op_msr *counters = msrs->counters;
  86         struct op_msr *controls = msrs->controls;
  87         unsigned int i;
  88
  89         for (i = 0; i < model->num_counters; ++i) {
  90                 if (counters[i].addr)
  91                         rdmsrl(counters[i].addr, counters[i].saved);
  92         }
  93
  94         for (i = 0; i < model->num_controls; ++i) {
  95                 if (controls[i].addr)
  96                         rdmsrl(controls[i].addr, controls[i].saved);
  97         }
  98 }
  99
 100 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 101
 102 static DEFINE_PER_CPU(int, switch_index);
 103
 104 inline int op_x86_phys_to_virt(int phys)
 105 {
 106         return __get_cpu_var(switch_index) + phys;
 107 }
 108
 109 static void nmi_shutdown_mux(void)
 110 {
 111         int i;
 112         for_each_possible_cpu(i) {
 113                 kfree(per_cpu(cpu_msrs, i).multiplex);
 114                 per_cpu(cpu_msrs, i).multiplex = NULL;
 115                 per_cpu(switch_index, i) = 0;
 116         }
 117 }
 118
 119 static int nmi_setup_mux(void)
 120 {
 121         size_t multiplex_size =
 122                 sizeof(struct op_msr) * model->num_virt_counters;
 123         int i;
 124         for_each_possible_cpu(i) {
 125                 per_cpu(cpu_msrs, i).multiplex =
 126                         kmalloc(multiplex_size, GFP_KERNEL);
 127                 if (!per_cpu(cpu_msrs, i).multiplex)
 128                         return 0;
 129         }
 130         return 1;
 131 }
 132
 133 static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
 134 {
 135         int i;
 136         struct op_msr *multiplex = msrs->multiplex;
 137
 138         for (i = 0; i < model->num_virt_counters; ++i) {
 139                 if (counter_config[i].enabled) {
 140                         multiplex[i].saved = -(u64)counter_config[i].count;
 141                 } else {
 142                         multiplex[i].addr  = 0;
 143                         multiplex[i].saved = 0;
 144                 }
 145         }
 146
 147         per_cpu(switch_index, cpu) = 0;
 148 }
 149
 150 #else
 151
 152 inline int op_x86_phys_to_virt(int phys) { return phys; }
 153 static inline void nmi_shutdown_mux(void) { }
 154 static inline int nmi_setup_mux(void) { return 1; }
 155 static inline void
 156 nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
 157
 158 #endif
 159
 160 static void free_msrs(void)
 161 {
 162         int i;
 163         for_each_possible_cpu(i) {
 164                 kfree(per_cpu(cpu_msrs, i).counters);
 165                 per_cpu(cpu_msrs, i).counters = NULL;
 166                 kfree(per_cpu(cpu_msrs, i).controls);
 167                 per_cpu(cpu_msrs, i).controls = NULL;
 168         }
 169 }
 170
 171 static int allocate_msrs(void)
 172 {
 173         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
 174         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
 175
 176         int i;
 177         for_each_possible_cpu(i) {
 178                 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
 179                                                         GFP_KERNEL);
 180                 if (!per_cpu(cpu_msrs, i).counters)
 181                         return 0;
 182                 per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
 183                                                         GFP_KERNEL);
 184                 if (!per_cpu(cpu_msrs, i).controls)
 185                         return 0;
 186         }
 187
 188         return 1;
 189 }
 190
 191 static void nmi_cpu_setup(void *dummy)
 192 {
 193         int cpu = smp_processor_id();
 194         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 195         nmi_cpu_save_registers(msrs);
 196         spin_lock(&oprofilefs_lock);
 197         model->setup_ctrs(model, msrs);
 198         nmi_cpu_setup_mux(cpu, msrs);
 199         spin_unlock(&oprofilefs_lock);
 200         per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
 201         apic_write(APIC_LVTPC, APIC_DM_NMI);
 202 }
 203
 204 static struct notifier_block profile_exceptions_nb = {
 205         .notifier_call = profile_exceptions_notify,
 206         .next = NULL,
 207         .priority = 2
 208 };
 209
 210 static int nmi_setup(void)
 211 {
 212         int err = 0;
 213         int cpu;
 214
 215         if (!allocate_msrs())
 216                 err = -ENOMEM;
 217         else if (!nmi_setup_mux())
 218                 err = -ENOMEM;
 219         else
 220                 err = register_die_notifier(&profile_exceptions_nb);
 221
 222         if (err) {
 223                 free_msrs();
 224                 nmi_shutdown_mux();
 225                 return err;
 226         }
 227
 228         /* We need to serialize save and setup for HT because the subset
 229          * of msrs are distinct for save and setup operations
 230          */
 231
 232         /* Assume saved/restored counters are the same on all CPUs */
 233         model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
 234         for_each_possible_cpu(cpu) {
 235                 if (cpu != 0) {
 236                         memcpy(per_cpu(cpu_msrs, cpu).counters,
 237                                 per_cpu(cpu_msrs, 0).counters,
 238                                 sizeof(struct op_msr) * model->num_counters);
 239
 240                         memcpy(per_cpu(cpu_msrs, cpu).controls,
 241                                 per_cpu(cpu_msrs, 0).controls,
 242                                 sizeof(struct op_msr) * model->num_controls);
 243 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 244                         memcpy(per_cpu(cpu_msrs, cpu).multiplex,
 245                                 per_cpu(cpu_msrs, 0).multiplex,
 246                                 sizeof(struct op_msr) * model->num_virt_counters);
 247 #endif
 248                 }
 249         }
 250         on_each_cpu(nmi_cpu_setup, NULL, 1);
 251         nmi_enabled = 1;
 252         return 0;
 253 }
 254
 255 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 256
 257 static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
 258 {
 259         struct op_msr *multiplex = msrs->multiplex;
 260         int i;
 261
 262         for (i = 0; i < model->num_counters; ++i) {
 263                 int virt = op_x86_phys_to_virt(i);
 264                 if (multiplex[virt].addr)
 265                         rdmsrl(multiplex[virt].addr, multiplex[virt].saved);
 266         }
 267 }
 268
 269 static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
 270 {
 271         struct op_msr *multiplex = msrs->multiplex;
 272         int i;
 273
 274         for (i = 0; i < model->num_counters; ++i) {
 275                 int virt = op_x86_phys_to_virt(i);
 276                 if (multiplex[virt].addr)
 277                         wrmsrl(multiplex[virt].addr, multiplex[virt].saved);
 278         }
 279 }
 280
 281 #endif
 282
 283 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
 284 {
 285         struct op_msr *counters = msrs->counters;
 286         struct op_msr *controls = msrs->controls;
 287         unsigned int i;
 288
 289         for (i = 0; i < model->num_controls; ++i) {
 290                 if (controls[i].addr)
 291                         wrmsrl(controls[i].addr, controls[i].saved);
 292         }
 293
 294         for (i = 0; i < model->num_counters; ++i) {
 295                 if (counters[i].addr)
 296                         wrmsrl(counters[i].addr, counters[i].saved);
 297         }
 298 }
 299
 300 static void nmi_cpu_shutdown(void *dummy)
 301 {
 302         unsigned int v;
 303         int cpu = smp_processor_id();
 304         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 305
 306         /* restoring APIC_LVTPC can trigger an apic error because the delivery
 307          * mode and vector nr combination can be illegal. That's by design: on
 308          * power on apic lvt contain a zero vector nr which are legal only for
 309          * NMI delivery mode. So inhibit apic err before restoring lvtpc
 310          */
 311         v = apic_read(APIC_LVTERR);
 312         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
 313         apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
 314         apic_write(APIC_LVTERR, v);
 315         nmi_cpu_restore_registers(msrs);
 316 }
 317
 318 static void nmi_shutdown(void)
 319 {
 320         struct op_msrs *msrs;
 321
 322         nmi_enabled = 0;
 323         on_each_cpu(nmi_cpu_shutdown, NULL, 1);
 324         unregister_die_notifier(&profile_exceptions_nb);
 325         nmi_shutdown_mux();
 326         msrs = &get_cpu_var(cpu_msrs);
 327         model->shutdown(msrs);
 328         free_msrs();
 329         put_cpu_var(cpu_msrs);
 330 }
 331
 332 static void nmi_cpu_start(void *dummy)
 333 {
 334         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 335         model->start(msrs);
 336 }
 337
 338 static int nmi_start(void)
 339 {
 340         on_each_cpu(nmi_cpu_start, NULL, 1);
 341         return 0;
 342 }
 343
 344 static void nmi_cpu_stop(void *dummy)
 345 {
 346         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 347         model->stop(msrs);
 348 }
 349
 350 static void nmi_stop(void)
 351 {
 352         on_each_cpu(nmi_cpu_stop, NULL, 1);
 353 }
 354
 355 static int nmi_create_files(struct super_block *sb, struct dentry *root)
 356 {
 357         unsigned int i;
 358
 359         for (i = 0; i < model->num_virt_counters; ++i) {
 360                 struct dentry *dir;
 361                 char buf[4];
 362
 363 #ifndef CONFIG_OPROFILE_EVENT_MULTIPLEX
 364                 /* quick little hack to _not_ expose a counter if it is not
 365                  * available for use.  This should protect userspace app.
 366                  * NOTE:  assumes 1:1 mapping here (that counters are organized
 367                  *        sequentially in their struct assignment).
 368                  */
 369                 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
 370                         continue;
 371 #endif /* CONFIG_OPROFILE_EVENT_MULTIPLEX */
 372
 373                 snprintf(buf,  sizeof(buf), "%d", i);
 374                 dir = oprofilefs_mkdir(sb, root, buf);
 375                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
 376                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
 377                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
 378                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
 379                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
 380                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
 381         }
 382
 383         return 0;
 384 }
 385
 386 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 387
 388 static void nmi_cpu_switch(void *dummy)
 389 {
 390         int cpu = smp_processor_id();
 391         int si = per_cpu(switch_index, cpu);
 392         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 393
 394         nmi_cpu_stop(NULL);
 395         nmi_cpu_save_mpx_registers(msrs);
 396
 397         /* move to next set */
 398         si += model->num_counters;
 399         if ((si > model->num_virt_counters) || (counter_config[si].count == 0))
 400                 per_cpu(switch_index, cpu) = 0;
 401         else
 402                 per_cpu(switch_index, cpu) = si;
 403
 404         model->switch_ctrl(model, msrs);
 405         nmi_cpu_restore_mpx_registers(msrs);
 406
 407         nmi_cpu_start(NULL);
 408 }
 409
 410
 411 /*
 412  * Quick check to see if multiplexing is necessary.
 413  * The check should be sufficient since counters are used
 414  * in ordre.
 415  */
 416 static int nmi_multiplex_on(void)
 417 {
 418         return counter_config[model->num_counters].count ? 0 : -EINVAL;
 419 }
 420
 421 static int nmi_switch_event(void)
 422 {
 423         if (!model->switch_ctrl)
 424                 return -ENOSYS;         /* not implemented */
 425         if (nmi_multiplex_on() < 0)
 426                 return -EINVAL;         /* not necessary */
 427
 428         on_each_cpu(nmi_cpu_switch, NULL, 1);
 429
 430         atomic_inc(&multiplex_counter);
 431
 432         return 0;
 433 }
 434
 435 #endif
 436
 437 #ifdef CONFIG_SMP
 438 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
 439                                  void *data)
 440 {
 441         int cpu = (unsigned long)data;
 442         switch (action) {
 443         case CPU_DOWN_FAILED:
 444         case CPU_ONLINE:
 445                 smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
 446                 break;
 447         case CPU_DOWN_PREPARE:
 448                 smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
 449                 break;
 450         }
 451         return NOTIFY_DONE;
 452 }
 453
 454 static struct notifier_block oprofile_cpu_nb = {
 455         .notifier_call = oprofile_cpu_notifier
 456 };
 457 #endif
 458
 459 #ifdef CONFIG_PM
 460
 461 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
 462 {
 463         /* Only one CPU left, just stop that one */
 464         if (nmi_enabled == 1)
 465                 nmi_cpu_stop(NULL);
 466         return 0;
 467 }
 468
 469 static int nmi_resume(struct sys_device *dev)
 470 {
 471         if (nmi_enabled == 1)
 472                 nmi_cpu_start(NULL);
 473         return 0;
 474 }
 475
 476 static struct sysdev_class oprofile_sysclass = {
 477         .name           = "oprofile",
 478         .resume         = nmi_resume,
 479         .suspend        = nmi_suspend,
 480 };
 481
 482 static struct sys_device device_oprofile = {
 483         .id     = 0,
 484         .cls    = &oprofile_sysclass,
 485 };
 486
 487 static int __init init_sysfs(void)
 488 {
 489         int error;
 490
 491         error = sysdev_class_register(&oprofile_sysclass);
 492         if (!error)
 493                 error = sysdev_register(&device_oprofile);
 494         return error;
 495 }
 496
 497 static void exit_sysfs(void)
 498 {
 499         sysdev_unregister(&device_oprofile);
 500         sysdev_class_unregister(&oprofile_sysclass);
 501 }
 502
 503 #else
 504 #define init_sysfs() do { } while (0)
 505 #define exit_sysfs() do { } while (0)
 506 #endif /* CONFIG_PM */
 507
 508 static int __init p4_init(char **cpu_type)
 509 {
 510         __u8 cpu_model = boot_cpu_data.x86_model;
 511
 512         if (cpu_model > 6 || cpu_model == 5)
 513                 return 0;
 514
 515 #ifndef CONFIG_SMP
 516         *cpu_type = "i386/p4";
 517         model = &op_p4_spec;
 518         return 1;
 519 #else
 520         switch (smp_num_siblings) {
 521         case 1:
 522                 *cpu_type = "i386/p4";
 523                 model = &op_p4_spec;
 524                 return 1;
 525
 526         case 2:
 527                 *cpu_type = "i386/p4-ht";
 528                 model = &op_p4_ht2_spec;
 529                 return 1;
 530         }
 531 #endif
 532
 533         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
 534         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
 535         return 0;
 536 }
 537
 538 static int force_arch_perfmon;
 539 static int force_cpu_type(const char *str, struct kernel_param *kp)
 540 {
 541         if (!strcmp(str, "arch_perfmon")) {
 542                 force_arch_perfmon = 1;
 543                 printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
 544         }
 545
 546         return 0;
 547 }
 548 module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
 549
 550 static int __init ppro_init(char **cpu_type)
 551 {
 552         __u8 cpu_model = boot_cpu_data.x86_model;
 553         struct op_x86_model_spec const *spec = &op_ppro_spec;   /* default */
 554
 555         if (force_arch_perfmon && cpu_has_arch_perfmon)
 556                 return 0;
 557
 558         switch (cpu_model) {
 559         case 0 ... 2:
 560                 *cpu_type = "i386/ppro";
 561                 break;
 562         case 3 ... 5:
 563                 *cpu_type = "i386/pii";
 564                 break;
 565         case 6 ... 8:
 566         case 10 ... 11:
 567                 *cpu_type = "i386/piii";
 568                 break;
 569         case 9:
 570         case 13:
 571                 *cpu_type = "i386/p6_mobile";
 572                 break;
 573         case 14:
 574                 *cpu_type = "i386/core";
 575                 break;
 576         case 15: case 23:
 577                 *cpu_type = "i386/core_2";
 578                 break;
 579         case 26:
 580                 spec = &op_arch_perfmon_spec;
 581                 *cpu_type = "i386/core_i7";
 582                 break;
 583         case 28:
 584                 *cpu_type = "i386/atom";
 585                 break;
 586         default:
 587                 /* Unknown */
 588                 return 0;
 589         }
 590
 591         model = spec;
 592         return 1;
 593 }
 594
 595 /* in order to get sysfs right */
 596 static int using_nmi;
 597
 598 int __init op_nmi_init(struct oprofile_operations *ops)
 599 {
 600         __u8 vendor = boot_cpu_data.x86_vendor;
 601         __u8 family = boot_cpu_data.x86;
 602         char *cpu_type = NULL;
 603         int ret = 0;
 604
 605         if (!cpu_has_apic)
 606                 return -ENODEV;
 607
 608         switch (vendor) {
 609         case X86_VENDOR_AMD:
 610                 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
 611
 612                 switch (family) {
 613                 case 6:
 614                         cpu_type = "i386/athlon";
 615                         break;
 616                 case 0xf:
 617                         /*
 618                          * Actually it could be i386/hammer too, but
 619                          * give user space an consistent name.
 620                          */
 621                         cpu_type = "x86-64/hammer";
 622                         break;
 623                 case 0x10:
 624                         cpu_type = "x86-64/family10";
 625                         break;
 626                 case 0x11:
 627                         cpu_type = "x86-64/family11h";
 628                         break;
 629                 default:
 630                         return -ENODEV;
 631                 }
 632                 model = &op_amd_spec;
 633                 break;
 634
 635         case X86_VENDOR_INTEL:
 636                 switch (family) {
 637                         /* Pentium IV */
 638                 case 0xf:
 639                         p4_init(&cpu_type);
 640                         break;
 641
 642                         /* A P6-class processor */
 643                 case 6:
 644                         ppro_init(&cpu_type);
 645                         break;
 646
 647                 default:
 648                         break;
 649                 }
 650
 651                 if (cpu_type)
 652                         break;
 653
 654                 if (!cpu_has_arch_perfmon)
 655                         return -ENODEV;
 656
 657                 /* use arch perfmon as fallback */
 658                 cpu_type = "i386/arch_perfmon";
 659                 model = &op_arch_perfmon_spec;
 660                 break;
 661
 662         default:
 663                 return -ENODEV;
 664         }
 665
 666 #ifdef CONFIG_SMP
 667         register_cpu_notifier(&oprofile_cpu_nb);
 668 #endif
 669         /* default values, can be overwritten by model */
 670         ops->create_files       = nmi_create_files;
 671         ops->setup              = nmi_setup;
 672         ops->shutdown           = nmi_shutdown;
 673         ops->start              = nmi_start;
 674         ops->stop               = nmi_stop;
 675         ops->cpu_type           = cpu_type;
 676 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 677         ops->switch_events      = nmi_switch_event;
 678 #endif
 679
 680         if (model->init)
 681                 ret = model->init(ops);
 682         if (ret)
 683                 return ret;
 684
 685         init_sysfs();
 686         using_nmi = 1;
 687         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
 688         return 0;
 689 }
 690
 691 void op_nmi_exit(void)
 692 {
 693         if (using_nmi) {
 694                 exit_sysfs();
 695 #ifdef CONFIG_SMP
 696                 unregister_cpu_notifier(&oprofile_cpu_nb);
 697 #endif
 698         }
 699         if (model->exit)
 700                 model->exit();
 701 }