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[CPUFREQ] Longhaul - Check ACPI "BM DMA in progress" bit
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / i386 / kernel / cpu / cpufreq / longhaul.c
blobff4829666472d1f7df65e57cd00dcb580c2ce27e
1 /*
2 * (C) 2001-2004 Dave Jones. <davej@codemonkey.org.uk>
3 * (C) 2002 Padraig Brady. <padraig@antefacto.com>
4 *
5 * Licensed under the terms of the GNU GPL License version 2.
6 * Based upon datasheets & sample CPUs kindly provided by VIA.
7 *
8 * VIA have currently 3 different versions of Longhaul.
9 * Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
10 * It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
11 * Version 2 of longhaul is backward compatible with v1, but adds
12 * LONGHAUL MSR for purpose of both frequency and voltage scaling.
13 * Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C).
14 * Version 3 of longhaul got renamed to Powersaver and redesigned
15 * to use only the POWERSAVER MSR at 0x110a.
16 * It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
17 * It's pretty much the same feature wise to longhaul v2, though
18 * there is provision for scaling FSB too, but this doesn't work
19 * too well in practice so we don't even try to use this.
20 *
21 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/cpufreq.h>
29 #include <linux/pci.h>
30 #include <linux/slab.h>
31 #include <linux/string.h>
32
33 #include <asm/msr.h>
34 #include <asm/timex.h>
35 #include <asm/io.h>
36 #include <asm/acpi.h>
37 #include <linux/acpi.h>
38 #include <acpi/processor.h>
39
40 #include "longhaul.h"
41
42 #define PFX "longhaul: "
43
44 #define TYPE_LONGHAUL_V1 1
45 #define TYPE_LONGHAUL_V2 2
46 #define TYPE_POWERSAVER 3
47
48 #define CPU_SAMUEL 1
49 #define CPU_SAMUEL2 2
50 #define CPU_EZRA 3
51 #define CPU_EZRA_T 4
52 #define CPU_NEHEMIAH 5
53 #define CPU_NEHEMIAH_C 6
54
55 /* Flags */
56 #define USE_ACPI_C3 (1 << 1)
57 #define USE_NORTHBRIDGE (1 << 2)
58
59 static int cpu_model;
60 static unsigned int numscales=16;
61 static unsigned int fsb;
62
63 static const struct mV_pos *vrm_mV_table;
64 static const unsigned char *mV_vrm_table;
65 struct f_msr {
66 u8 vrm;
67 u8 pos;
68 };
69 static struct f_msr f_msr_table[32];
70
71 static unsigned int highest_speed, lowest_speed; /* kHz */
72 static unsigned int minmult, maxmult;
73 static int can_scale_voltage;
74 static struct acpi_processor *pr = NULL;
75 static struct acpi_processor_cx *cx = NULL;
76 static u8 longhaul_flags;
77 static u8 longhaul_pos;
78
79 /* Module parameters */
80 static int scale_voltage;
81
82 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg)
83
84
85 /* Clock ratios multiplied by 10 */
86 static int clock_ratio[32];
87 static int eblcr_table[32];
88 static int longhaul_version;
89 static struct cpufreq_frequency_table *longhaul_table;
90 static unsigned int old_ratio = -1;
91
92 #ifdef CONFIG_CPU_FREQ_DEBUG
93 static char speedbuffer[8];
94
95 static char *print_speed(int speed)
96 {
97 if (speed < 1000) {
98 snprintf(speedbuffer, sizeof(speedbuffer),"%dMHz", speed);
99 return speedbuffer;
100 }
101
102 if (speed%1000 == 0)
103 snprintf(speedbuffer, sizeof(speedbuffer),
104 "%dGHz", speed/1000);
105 else
106 snprintf(speedbuffer, sizeof(speedbuffer),
107 "%d.%dGHz", speed/1000, (speed%1000)/100);
108
109 return speedbuffer;
110 }
111 #endif
112
113
114 static unsigned int calc_speed(int mult)
115 {
116 int khz;
117 khz = (mult/10)*fsb;
118 if (mult%10)
119 khz += fsb/2;
120 khz *= 1000;
121 return khz;
122 }
123
124
125 static int longhaul_get_cpu_mult(void)
126 {
127 unsigned long invalue=0,lo, hi;
128
129 rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi);
130 invalue = (lo & (1<<22|1<<23|1<<24|1<<25)) >>22;
131 if (longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) {
132 if (lo & (1<<27))
133 invalue+=16;
134 }
135 return eblcr_table[invalue];
136 }
137
138 /* For processor with BCR2 MSR */
139
140 static void do_longhaul1(unsigned int clock_ratio_index)
141 {
142 union msr_bcr2 bcr2;
143
144 rdmsrl(MSR_VIA_BCR2, bcr2.val);
145 /* Enable software clock multiplier */
146 bcr2.bits.ESOFTBF = 1;
147 bcr2.bits.CLOCKMUL = clock_ratio_index;
148
149 /* Sync to timer tick */
150 safe_halt();
151 /* Change frequency on next halt or sleep */
152 wrmsrl(MSR_VIA_BCR2, bcr2.val);
153 /* Invoke transition */
154 ACPI_FLUSH_CPU_CACHE();
155 halt();
156
157 /* Disable software clock multiplier */
158 local_irq_disable();
159 rdmsrl(MSR_VIA_BCR2, bcr2.val);
160 bcr2.bits.ESOFTBF = 0;
161 wrmsrl(MSR_VIA_BCR2, bcr2.val);
162 }
163
164 /* For processor with Longhaul MSR */
165
166 static void do_powersaver(int cx_address, unsigned int clock_ratio_index)
167 {
168 union msr_longhaul longhaul;
169 u8 dest_pos;
170 u32 t;
171
172 dest_pos = f_msr_table[clock_ratio_index].pos;
173
174 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
175 /* Setup new frequency */
176 longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
177 longhaul.bits.SoftBusRatio = clock_ratio_index & 0xf;
178 longhaul.bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;
179 /* Setup new voltage */
180 if (can_scale_voltage)
181 longhaul.bits.SoftVID = f_msr_table[clock_ratio_index].vrm;
182 /* Sync to timer tick */
183 safe_halt();
184 /* Raise voltage if necessary */
185 if (can_scale_voltage && longhaul_pos < dest_pos) {
186 longhaul.bits.EnableSoftVID = 1;
187 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
188 /* Change voltage */
189 if (!cx_address) {
190 ACPI_FLUSH_CPU_CACHE();
191 halt();
192 } else {
193 ACPI_FLUSH_CPU_CACHE();
194 /* Invoke C3 */
195 inb(cx_address);
196 /* Dummy op - must do something useless after P_LVL3
197 * read */
198 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
199 }
200 longhaul.bits.EnableSoftVID = 0;
201 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
202 longhaul_pos = dest_pos;
203 }
204
205 /* Change frequency on next halt or sleep */
206 longhaul.bits.EnableSoftBusRatio = 1;
207 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
208 if (!cx_address) {
209 ACPI_FLUSH_CPU_CACHE();
210 halt();
211 } else {
212 ACPI_FLUSH_CPU_CACHE();
213 /* Invoke C3 */
214 inb(cx_address);
215 /* Dummy op - must do something useless after P_LVL3 read */
216 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
217 }
218 /* Disable bus ratio bit */
219 longhaul.bits.EnableSoftBusRatio = 0;
220 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
221
222 /* Reduce voltage if necessary */
223 if (can_scale_voltage && longhaul_pos > dest_pos) {
224 longhaul.bits.EnableSoftVID = 1;
225 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
226 /* Change voltage */
227 if (!cx_address) {
228 ACPI_FLUSH_CPU_CACHE();
229 halt();
230 } else {
231 ACPI_FLUSH_CPU_CACHE();
232 /* Invoke C3 */
233 inb(cx_address);
234 /* Dummy op - must do something useless after P_LVL3
235 * read */
236 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
237 }
238 longhaul.bits.EnableSoftVID = 0;
239 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
240 longhaul_pos = dest_pos;
241 }
242 }
243
244 /**
245 * longhaul_set_cpu_frequency()
246 * @clock_ratio_index : bitpattern of the new multiplier.
247 *
248 * Sets a new clock ratio.
249 */
250
251 static void longhaul_setstate(unsigned int clock_ratio_index)
252 {
253 int speed, mult;
254 struct cpufreq_freqs freqs;
255 unsigned long flags;
256 unsigned int pic1_mask, pic2_mask;
257 u32 bm_status = 0;
258 u32 bm_timeout = 100000;
259
260 if (old_ratio == clock_ratio_index)
261 return;
262 old_ratio = clock_ratio_index;
263
264 mult = clock_ratio[clock_ratio_index];
265 if (mult == -1)
266 return;
267
268 speed = calc_speed(mult);
269 if ((speed > highest_speed) || (speed < lowest_speed))
270 return;
271
272 freqs.old = calc_speed(longhaul_get_cpu_mult());
273 freqs.new = speed;
274 freqs.cpu = 0; /* longhaul.c is UP only driver */
275
276 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
277
278 dprintk ("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
279 fsb, mult/10, mult%10, print_speed(speed/1000));
280
281 preempt_disable();
282 local_irq_save(flags);
283
284 pic2_mask = inb(0xA1);
285 pic1_mask = inb(0x21); /* works on C3. save mask. */
286 outb(0xFF,0xA1); /* Overkill */
287 outb(0xFE,0x21); /* TMR0 only */
288
289 /* Wait while PCI bus is busy. */
290 if (longhaul_flags & USE_NORTHBRIDGE
291 || ((pr != NULL) && pr->flags.bm_control)) {
292 acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status);
293 while (bm_status && bm_timeout) {
294 acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1);
295 bm_timeout--;
296 acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS,
297 &bm_status);
298 }
299 }
300
301 if (longhaul_flags & USE_NORTHBRIDGE) {
302 /* Disable AGP and PCI arbiters */
303 outb(3, 0x22);
304 } else if ((pr != NULL) && pr->flags.bm_control) {
305 /* Disable bus master arbitration */
306 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
307 }
308 switch (longhaul_version) {
309
310 /*
311 * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
312 * Software controlled multipliers only.
313 */
314 case TYPE_LONGHAUL_V1:
315 do_longhaul1(clock_ratio_index);
316 break;
317
318 /*
319 * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5B] and Ezra [C5C]
320 *
321 * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
322 * Nehemiah can do FSB scaling too, but this has never been proven
323 * to work in practice.
324 */
325 case TYPE_LONGHAUL_V2:
326 case TYPE_POWERSAVER:
327 if (longhaul_flags & USE_ACPI_C3) {
328 /* Don't allow wakeup */
329 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
330 do_powersaver(cx->address, clock_ratio_index);
331 } else {
332 do_powersaver(0, clock_ratio_index);
333 }
334 break;
335 }
336
337 if (longhaul_flags & USE_NORTHBRIDGE) {
338 /* Enable arbiters */
339 outb(0, 0x22);
340 } else if ((pr != NULL) && pr->flags.bm_control) {
341 /* Enable bus master arbitration */
342 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
343 }
344 outb(pic2_mask,0xA1); /* restore mask */
345 outb(pic1_mask,0x21);
346
347 local_irq_restore(flags);
348 preempt_enable();
349
350 freqs.new = calc_speed(longhaul_get_cpu_mult());
351 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
352
353 if (!bm_timeout)
354 printk(KERN_INFO PFX "Warning: Timeout while waiting for "
355 "idle PCI bus.\n");
356 }
357
358 /*
359 * Centaur decided to make life a little more tricky.
360 * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
361 * Samuel2 and above have to try and guess what the FSB is.
362 * We do this by assuming we booted at maximum multiplier, and interpolate
363 * between that value multiplied by possible FSBs and cpu_mhz which
364 * was calculated at boot time. Really ugly, but no other way to do this.
365 */
366
367 #define ROUNDING 0xf
368
369 static int guess_fsb(int mult)
370 {
371 int speed = cpu_khz / 1000;
372 int i;
373 int speeds[] = { 666, 1000, 1333, 2000 };
374 int f_max, f_min;
375
376 for (i = 0; i < 4; i++) {
377 f_max = ((speeds[i] * mult) + 50) / 100;
378 f_max += (ROUNDING / 2);
379 f_min = f_max - ROUNDING;
380 if ((speed <= f_max) && (speed >= f_min))
381 return speeds[i] / 10;
382 }
383 return 0;
384 }
385
386
387 static int __init longhaul_get_ranges(void)
388 {
389 unsigned int j, k = 0;
390 int mult;
391
392 /* Get current frequency */
393 mult = longhaul_get_cpu_mult();
394 if (mult == -1) {
395 printk(KERN_INFO PFX "Invalid (reserved) multiplier!\n");
396 return -EINVAL;
397 }
398 fsb = guess_fsb(mult);
399 if (fsb == 0) {
400 printk(KERN_INFO PFX "Invalid (reserved) FSB!\n");
401 return -EINVAL;
402 }
403 /* Get max multiplier - as we always did.
404 * Longhaul MSR is usefull only when voltage scaling is enabled.
405 * C3 is booting at max anyway. */
406 maxmult = mult;
407 /* Get min multiplier */
408 switch (cpu_model) {
409 case CPU_NEHEMIAH:
410 minmult = 50;
411 break;
412 case CPU_NEHEMIAH_C:
413 minmult = 40;
414 break;
415 default:
416 minmult = 30;
417 break;
418 }
419
420 dprintk ("MinMult:%d.%dx MaxMult:%d.%dx\n",
421 minmult/10, minmult%10, maxmult/10, maxmult%10);
422
423 highest_speed = calc_speed(maxmult);
424 lowest_speed = calc_speed(minmult);
425 dprintk ("FSB:%dMHz Lowest speed: %s Highest speed:%s\n", fsb,
426 print_speed(lowest_speed/1000),
427 print_speed(highest_speed/1000));
428
429 if (lowest_speed == highest_speed) {
430 printk (KERN_INFO PFX "highestspeed == lowest, aborting.\n");
431 return -EINVAL;
432 }
433 if (lowest_speed > highest_speed) {
434 printk (KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
435 lowest_speed, highest_speed);
436 return -EINVAL;
437 }
438
439 longhaul_table = kmalloc((numscales + 1) * sizeof(struct cpufreq_frequency_table), GFP_KERNEL);
440 if(!longhaul_table)
441 return -ENOMEM;
442
443 for (j=0; j < numscales; j++) {
444 unsigned int ratio;
445 ratio = clock_ratio[j];
446 if (ratio == -1)
447 continue;
448 if (ratio > maxmult || ratio < minmult)
449 continue;
450 longhaul_table[k].frequency = calc_speed(ratio);
451 longhaul_table[k].index = j;
452 k++;
453 }
454
455 longhaul_table[k].frequency = CPUFREQ_TABLE_END;
456 if (!k) {
457 kfree (longhaul_table);
458 return -EINVAL;
459 }
460
461 return 0;
462 }
463
464
465 static void __init longhaul_setup_voltagescaling(void)
466 {
467 union msr_longhaul longhaul;
468 struct mV_pos minvid, maxvid;
469 unsigned int j, speed, pos, kHz_step, numvscales;
470 int min_vid_speed;
471
472 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
473 if (!(longhaul.bits.RevisionID & 1)) {
474 printk(KERN_INFO PFX "Voltage scaling not supported by CPU.\n");
475 return;
476 }
477
478 if (!longhaul.bits.VRMRev) {
479 printk (KERN_INFO PFX "VRM 8.5\n");
480 vrm_mV_table = &vrm85_mV[0];
481 mV_vrm_table = &mV_vrm85[0];
482 } else {
483 printk (KERN_INFO PFX "Mobile VRM\n");
484 if (cpu_model < CPU_NEHEMIAH)
485 return;
486 vrm_mV_table = &mobilevrm_mV[0];
487 mV_vrm_table = &mV_mobilevrm[0];
488 }
489
490 minvid = vrm_mV_table[longhaul.bits.MinimumVID];
491 maxvid = vrm_mV_table[longhaul.bits.MaximumVID];
492
493 if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) {
494 printk (KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
495 "Voltage scaling disabled.\n",
496 minvid.mV/1000, minvid.mV%1000, maxvid.mV/1000, maxvid.mV%1000);
497 return;
498 }
499
500 if (minvid.mV == maxvid.mV) {
501 printk (KERN_INFO PFX "Claims to support voltage scaling but min & max are "
502 "both %d.%03d. Voltage scaling disabled\n",
503 maxvid.mV/1000, maxvid.mV%1000);
504 return;
505 }
506
507 /* How many voltage steps */
508 numvscales = maxvid.pos - minvid.pos + 1;
509 printk(KERN_INFO PFX
510 "Max VID=%d.%03d "
511 "Min VID=%d.%03d, "
512 "%d possible voltage scales\n",
513 maxvid.mV/1000, maxvid.mV%1000,
514 minvid.mV/1000, minvid.mV%1000,
515 numvscales);
516
517 /* Calculate max frequency at min voltage */
518 j = longhaul.bits.MinMHzBR;
519 if (longhaul.bits.MinMHzBR4)
520 j += 16;
521 min_vid_speed = eblcr_table[j];
522 if (min_vid_speed == -1)
523 return;
524 switch (longhaul.bits.MinMHzFSB) {
525 case 0:
526 min_vid_speed *= 13333;
527 break;
528 case 1:
529 min_vid_speed *= 10000;
530 break;
531 case 3:
532 min_vid_speed *= 6666;
533 break;
534 default:
535 return;
536 break;
537 }
538 if (min_vid_speed >= highest_speed)
539 return;
540 /* Calculate kHz for one voltage step */
541 kHz_step = (highest_speed - min_vid_speed) / numvscales;
542
543
544 j = 0;
545 while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) {
546 speed = longhaul_table[j].frequency;
547 if (speed > min_vid_speed)
548 pos = (speed - min_vid_speed) / kHz_step + minvid.pos;
549 else
550 pos = minvid.pos;
551 f_msr_table[longhaul_table[j].index].vrm = mV_vrm_table[pos];
552 f_msr_table[longhaul_table[j].index].pos = pos;
553 j++;
554 }
555
556 longhaul_pos = maxvid.pos;
557 can_scale_voltage = 1;
558 printk(KERN_INFO PFX "Voltage scaling enabled. "
559 "Use of \"conservative\" governor is highly recommended.\n");
560 }
561
562
563 static int longhaul_verify(struct cpufreq_policy *policy)
564 {
565 return cpufreq_frequency_table_verify(policy, longhaul_table);
566 }
567
568
569 static int longhaul_target(struct cpufreq_policy *policy,
570 unsigned int target_freq, unsigned int relation)
571 {
572 unsigned int table_index = 0;
573 unsigned int new_clock_ratio = 0;
574
575 if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq, relation, &table_index))
576 return -EINVAL;
577
578 new_clock_ratio = longhaul_table[table_index].index & 0xFF;
579
580 longhaul_setstate(new_clock_ratio);
581
582 return 0;
583 }
584
585
586 static unsigned int longhaul_get(unsigned int cpu)
587 {
588 if (cpu)
589 return 0;
590 return calc_speed(longhaul_get_cpu_mult());
591 }
592
593 static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
594 u32 nesting_level,
595 void *context, void **return_value)
596 {
597 struct acpi_device *d;
598
599 if ( acpi_bus_get_device(obj_handle, &d) ) {
600 return 0;
601 }
602 *return_value = (void *)acpi_driver_data(d);
603 return 1;
604 }
605
606 /* VIA don't support PM2 reg, but have something similar */
607 static int enable_arbiter_disable(void)
608 {
609 struct pci_dev *dev;
610 int status;
611 int reg;
612 u8 pci_cmd;
613
614 status = 1;
615 /* Find PLE133 host bridge */
616 reg = 0x78;
617 dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0,
618 NULL);
619 /* Find CLE266 host bridge */
620 if (dev == NULL) {
621 reg = 0x76;
622 dev = pci_get_device(PCI_VENDOR_ID_VIA,
623 PCI_DEVICE_ID_VIA_862X_0, NULL);
624 /* Find CN400 V-Link host bridge */
625 if (dev == NULL)
626 dev = pci_get_device(PCI_VENDOR_ID_VIA, 0x7259, NULL);
627 }
628 if (dev != NULL) {
629 /* Enable access to port 0x22 */
630 pci_read_config_byte(dev, reg, &pci_cmd);
631 if (!(pci_cmd & 1<<7)) {
632 pci_cmd |= 1<<7;
633 pci_write_config_byte(dev, reg, pci_cmd);
634 pci_read_config_byte(dev, reg, &pci_cmd);
635 if (!(pci_cmd & 1<<7)) {
636 printk(KERN_ERR PFX
637 "Can't enable access to port 0x22.\n");
638 status = 0;
639 }
640 }
641 pci_dev_put(dev);
642 return status;
643 }
644 return 0;
645 }
646
647 static int longhaul_setup_southbridge(void)
648 {
649 struct pci_dev *dev;
650 u8 pci_cmd;
651
652 /* Find VT8235 southbridge */
653 dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, NULL);
654 if (dev == NULL)
655 /* Find VT8237 southbridge */
656 dev = pci_get_device(PCI_VENDOR_ID_VIA,
657 PCI_DEVICE_ID_VIA_8237, NULL);
658 if (dev != NULL) {
659 /* Set transition time to max */
660 pci_read_config_byte(dev, 0xec, &pci_cmd);
661 pci_cmd &= ~(1 << 2);
662 pci_write_config_byte(dev, 0xec, pci_cmd);
663 pci_read_config_byte(dev, 0xe4, &pci_cmd);
664 pci_cmd &= ~(1 << 7);
665 pci_write_config_byte(dev, 0xe4, pci_cmd);
666 pci_read_config_byte(dev, 0xe5, &pci_cmd);
667 pci_cmd |= 1 << 7;
668 pci_write_config_byte(dev, 0xe5, pci_cmd);
669 pci_dev_put(dev);
670 return 1;
671 }
672 return 0;
673 }
674
675 static int __init longhaul_cpu_init(struct cpufreq_policy *policy)
676 {
677 struct cpuinfo_x86 *c = cpu_data;
678 char *cpuname=NULL;
679 int ret;
680 u32 lo, hi;
681
682 /* Check what we have on this motherboard */
683 switch (c->x86_model) {
684 case 6:
685 cpu_model = CPU_SAMUEL;
686 cpuname = "C3 'Samuel' [C5A]";
687 longhaul_version = TYPE_LONGHAUL_V1;
688 memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
689 memcpy (eblcr_table, samuel1_eblcr, sizeof(samuel1_eblcr));
690 break;
691
692 case 7:
693 switch (c->x86_mask) {
694 case 0:
695 longhaul_version = TYPE_LONGHAUL_V1;
696 cpu_model = CPU_SAMUEL2;
697 cpuname = "C3 'Samuel 2' [C5B]";
698 /* Note, this is not a typo, early Samuel2's had
699 * Samuel1 ratios. */
700 memcpy(clock_ratio, samuel1_clock_ratio,
701 sizeof(samuel1_clock_ratio));
702 memcpy(eblcr_table, samuel2_eblcr,
703 sizeof(samuel2_eblcr));
704 break;
705 case 1 ... 15:
706 longhaul_version = TYPE_LONGHAUL_V1;
707 if (c->x86_mask < 8) {
708 cpu_model = CPU_SAMUEL2;
709 cpuname = "C3 'Samuel 2' [C5B]";
710 } else {
711 cpu_model = CPU_EZRA;
712 cpuname = "C3 'Ezra' [C5C]";
713 }
714 memcpy(clock_ratio, ezra_clock_ratio,
715 sizeof(ezra_clock_ratio));
716 memcpy(eblcr_table, ezra_eblcr,
717 sizeof(ezra_eblcr));
718 break;
719 }
720 break;
721
722 case 8:
723 cpu_model = CPU_EZRA_T;
724 cpuname = "C3 'Ezra-T' [C5M]";
725 longhaul_version = TYPE_POWERSAVER;
726 numscales=32;
727 memcpy (clock_ratio, ezrat_clock_ratio, sizeof(ezrat_clock_ratio));
728 memcpy (eblcr_table, ezrat_eblcr, sizeof(ezrat_eblcr));
729 break;
730
731 case 9:
732 longhaul_version = TYPE_POWERSAVER;
733 numscales = 32;
734 memcpy(clock_ratio,
735 nehemiah_clock_ratio,
736 sizeof(nehemiah_clock_ratio));
737 memcpy(eblcr_table, nehemiah_eblcr, sizeof(nehemiah_eblcr));
738 switch (c->x86_mask) {
739 case 0 ... 1:
740 cpu_model = CPU_NEHEMIAH;
741 cpuname = "C3 'Nehemiah A' [C5XLOE]";
742 break;
743 case 2 ... 4:
744 cpu_model = CPU_NEHEMIAH;
745 cpuname = "C3 'Nehemiah B' [C5XLOH]";
746 break;
747 case 5 ... 15:
748 cpu_model = CPU_NEHEMIAH_C;
749 cpuname = "C3 'Nehemiah C' [C5P]";
750 break;
751 }
752 break;
753
754 default:
755 cpuname = "Unknown";
756 break;
757 }
758 /* Check Longhaul ver. 2 */
759 if (longhaul_version == TYPE_LONGHAUL_V2) {
760 rdmsr(MSR_VIA_LONGHAUL, lo, hi);
761 if (lo == 0 && hi == 0)
762 /* Looks like MSR isn't present */
763 longhaul_version = TYPE_LONGHAUL_V1;
764 }
765
766 printk (KERN_INFO PFX "VIA %s CPU detected. ", cpuname);
767 switch (longhaul_version) {
768 case TYPE_LONGHAUL_V1:
769 case TYPE_LONGHAUL_V2:
770 printk ("Longhaul v%d supported.\n", longhaul_version);
771 break;
772 case TYPE_POWERSAVER:
773 printk ("Powersaver supported.\n");
774 break;
775 };
776
777 /* Doesn't hurt */
778 longhaul_setup_southbridge();
779
780 /* Find ACPI data for processor */
781 acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
782 ACPI_UINT32_MAX, &longhaul_walk_callback,
783 NULL, (void *)&pr);
784
785 /* Check ACPI support for C3 state */
786 if (pr != NULL && longhaul_version == TYPE_POWERSAVER) {
787 cx = &pr->power.states[ACPI_STATE_C3];
788 if (cx->address > 0 && cx->latency <= 1000)
789 longhaul_flags |= USE_ACPI_C3;
790 }
791 /* Check if northbridge is friendly */
792 if (enable_arbiter_disable())
793 longhaul_flags |= USE_NORTHBRIDGE;
794
795 /* Check ACPI support for bus master arbiter disable */
796 if (!(longhaul_flags & USE_ACPI_C3
797 || longhaul_flags & USE_NORTHBRIDGE)
798 && ((pr == NULL) || !(pr->flags.bm_control))) {
799 printk(KERN_ERR PFX
800 "No ACPI support. Unsupported northbridge.\n");
801 return -ENODEV;
802 }
803
804 if (longhaul_flags & USE_NORTHBRIDGE)
805 printk(KERN_INFO PFX "Using northbridge support.\n");
806 if (longhaul_flags & USE_ACPI_C3)
807 printk(KERN_INFO PFX "Using ACPI support.\n");
808
809 ret = longhaul_get_ranges();
810 if (ret != 0)
811 return ret;
812
813 if ((longhaul_version != TYPE_LONGHAUL_V1) && (scale_voltage != 0))
814 longhaul_setup_voltagescaling();
815
816 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
817 policy->cpuinfo.transition_latency = 200000; /* nsec */
818 policy->cur = calc_speed(longhaul_get_cpu_mult());
819
820 ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
821 if (ret)
822 return ret;
823
824 cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu);
825
826 return 0;
827 }
828
829 static int __devexit longhaul_cpu_exit(struct cpufreq_policy *policy)
830 {
831 cpufreq_frequency_table_put_attr(policy->cpu);
832 return 0;
833 }
834
835 static struct freq_attr* longhaul_attr[] = {
836 &cpufreq_freq_attr_scaling_available_freqs,
837 NULL,
838 };
839
840 static struct cpufreq_driver longhaul_driver = {
841 .verify = longhaul_verify,
842 .target = longhaul_target,
843 .get = longhaul_get,
844 .init = longhaul_cpu_init,
845 .exit = __devexit_p(longhaul_cpu_exit),
846 .name = "longhaul",
847 .owner = THIS_MODULE,
848 .attr = longhaul_attr,
849 };
850
851
852 static int __init longhaul_init(void)
853 {
854 struct cpuinfo_x86 *c = cpu_data;
855
856 if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6)
857 return -ENODEV;
858
859 #ifdef CONFIG_SMP
860 if (num_online_cpus() > 1) {
861 printk(KERN_ERR PFX "More than 1 CPU detected, longhaul disabled.\n");
862 return -ENODEV;
863 }
864 #endif
865 #ifdef CONFIG_X86_IO_APIC
866 if (cpu_has_apic) {
867 printk(KERN_ERR PFX "APIC detected. Longhaul is currently broken in this configuration.\n");
868 return -ENODEV;
869 }
870 #endif
871 switch (c->x86_model) {
872 case 6 ... 9:
873 return cpufreq_register_driver(&longhaul_driver);
874 case 10:
875 printk(KERN_ERR PFX "Use acpi-cpufreq driver for VIA C7\n");
876 default:
877 ;;
878 }
879
880 return -ENODEV;
881 }
882
883
884 static void __exit longhaul_exit(void)
885 {
886 int i;
887
888 for (i=0; i < numscales; i++) {
889 if (clock_ratio[i] == maxmult) {
890 longhaul_setstate(i);
891 break;
892 }
893 }
894
895 cpufreq_unregister_driver(&longhaul_driver);
896 kfree(longhaul_table);
897 }
898
899 module_param (scale_voltage, int, 0644);
900 MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor");
901
902 MODULE_AUTHOR ("Dave Jones <davej@codemonkey.org.uk>");
903 MODULE_DESCRIPTION ("Longhaul driver for VIA Cyrix processors.");
904 MODULE_LICENSE ("GPL");
905
906 late_initcall(longhaul_init);
907 module_exit(longhaul_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree