2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
51 #if (SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F
52 # error SPURIOUS_APIC_VECTOR definition error
56 * Knob to control our willingness to enable the local APIC.
58 * -1=force-disable, +1=force-enable
60 static int enable_local_apic __initdata
= 0;
62 /* Local APIC timer verification ok */
63 static int local_apic_timer_verify_ok
;
64 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
65 static int local_apic_timer_disabled
;
66 /* Local APIC timer works in C2 */
67 int local_apic_timer_c2_ok
;
68 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
71 * Debug level, exported for io_apic.c
75 static unsigned int calibration_result
;
77 static int lapic_next_event(unsigned long delta
,
78 struct clock_event_device
*evt
);
79 static void lapic_timer_setup(enum clock_event_mode mode
,
80 struct clock_event_device
*evt
);
81 static void lapic_timer_broadcast(cpumask_t mask
);
82 static void apic_pm_activate(void);
85 * The local apic timer can be used for any function which is CPU local.
87 static struct clock_event_device lapic_clockevent
= {
89 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
90 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
92 .set_mode
= lapic_timer_setup
,
93 .set_next_event
= lapic_next_event
,
94 .broadcast
= lapic_timer_broadcast
,
98 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
100 /* Local APIC was disabled by the BIOS and enabled by the kernel */
101 static int enabled_via_apicbase
;
104 * Get the LAPIC version
106 static inline int lapic_get_version(void)
108 return GET_APIC_VERSION(apic_read(APIC_LVR
));
112 * Check, if the APIC is integrated or a seperate chip
114 static inline int lapic_is_integrated(void)
116 return APIC_INTEGRATED(lapic_get_version());
120 * Check, whether this is a modern or a first generation APIC
122 static int modern_apic(void)
124 /* AMD systems use old APIC versions, so check the CPU */
125 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
126 boot_cpu_data
.x86
>= 0xf)
128 return lapic_get_version() >= 0x14;
131 void apic_wait_icr_idle(void)
133 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
137 unsigned long safe_apic_wait_icr_idle(void)
139 unsigned long send_status
;
144 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
148 } while (timeout
++ < 1000);
154 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
156 void enable_NMI_through_LVT0 (void * dummy
)
158 unsigned int v
= APIC_DM_NMI
;
160 /* Level triggered for 82489DX */
161 if (!lapic_is_integrated())
162 v
|= APIC_LVT_LEVEL_TRIGGER
;
163 apic_write_around(APIC_LVT0
, v
);
167 * get_physical_broadcast - Get number of physical broadcast IDs
169 int get_physical_broadcast(void)
171 return modern_apic() ? 0xff : 0xf;
175 * lapic_get_maxlvt - get the maximum number of local vector table entries
177 int lapic_get_maxlvt(void)
179 unsigned int v
= apic_read(APIC_LVR
);
181 /* 82489DXs do not report # of LVT entries. */
182 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
189 /* Clock divisor is set to 16 */
190 #define APIC_DIVISOR 16
193 * This function sets up the local APIC timer, with a timeout of
194 * 'clocks' APIC bus clock. During calibration we actually call
195 * this function twice on the boot CPU, once with a bogus timeout
196 * value, second time for real. The other (noncalibrating) CPUs
197 * call this function only once, with the real, calibrated value.
199 * We do reads before writes even if unnecessary, to get around the
200 * P5 APIC double write bug.
202 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
204 unsigned int lvtt_value
, tmp_value
;
206 lvtt_value
= LOCAL_TIMER_VECTOR
;
208 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
209 if (!lapic_is_integrated())
210 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
213 lvtt_value
|= APIC_LVT_MASKED
;
215 apic_write_around(APIC_LVTT
, lvtt_value
);
220 tmp_value
= apic_read(APIC_TDCR
);
221 apic_write_around(APIC_TDCR
, (tmp_value
222 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
226 apic_write_around(APIC_TMICT
, clocks
/APIC_DIVISOR
);
230 * Program the next event, relative to now
232 static int lapic_next_event(unsigned long delta
,
233 struct clock_event_device
*evt
)
235 apic_write_around(APIC_TMICT
, delta
);
240 * Setup the lapic timer in periodic or oneshot mode
242 static void lapic_timer_setup(enum clock_event_mode mode
,
243 struct clock_event_device
*evt
)
248 /* Lapic used for broadcast ? */
249 if (!local_apic_timer_verify_ok
)
252 local_irq_save(flags
);
255 case CLOCK_EVT_MODE_PERIODIC
:
256 case CLOCK_EVT_MODE_ONESHOT
:
257 __setup_APIC_LVTT(calibration_result
,
258 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
260 case CLOCK_EVT_MODE_UNUSED
:
261 case CLOCK_EVT_MODE_SHUTDOWN
:
262 v
= apic_read(APIC_LVTT
);
263 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
264 apic_write_around(APIC_LVTT
, v
);
268 local_irq_restore(flags
);
272 * Local APIC timer broadcast function
274 static void lapic_timer_broadcast(cpumask_t mask
)
277 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
282 * Setup the local APIC timer for this CPU. Copy the initilized values
283 * of the boot CPU and register the clock event in the framework.
285 static void __devinit
setup_APIC_timer(void)
287 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
289 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
290 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
292 clockevents_register_device(levt
);
296 * In this functions we calibrate APIC bus clocks to the external timer.
298 * We want to do the calibration only once since we want to have local timer
299 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
302 * This was previously done by reading the PIT/HPET and waiting for a wrap
303 * around to find out, that a tick has elapsed. I have a box, where the PIT
304 * readout is broken, so it never gets out of the wait loop again. This was
305 * also reported by others.
307 * Monitoring the jiffies value is inaccurate and the clockevents
308 * infrastructure allows us to do a simple substitution of the interrupt
311 * The calibration routine also uses the pm_timer when possible, as the PIT
312 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
313 * back to normal later in the boot process).
316 #define LAPIC_CAL_LOOPS (HZ/10)
318 static __initdata
volatile int lapic_cal_loops
= -1;
319 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
320 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
321 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
322 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
325 * Temporary interrupt handler.
327 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
329 unsigned long long tsc
= 0;
330 long tapic
= apic_read(APIC_TMCCT
);
331 unsigned long pm
= acpi_pm_read_early();
336 switch (lapic_cal_loops
++) {
338 lapic_cal_t1
= tapic
;
339 lapic_cal_tsc1
= tsc
;
341 lapic_cal_j1
= jiffies
;
344 case LAPIC_CAL_LOOPS
:
345 lapic_cal_t2
= tapic
;
346 lapic_cal_tsc2
= tsc
;
347 if (pm
< lapic_cal_pm1
)
348 pm
+= ACPI_PM_OVRRUN
;
350 lapic_cal_j2
= jiffies
;
356 * Setup the boot APIC
358 * Calibrate and verify the result.
360 void __init
setup_boot_APIC_clock(void)
362 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
363 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/10;
364 const long pm_thresh
= pm_100ms
/100;
365 void (*real_handler
)(struct clock_event_device
*dev
);
366 unsigned long deltaj
;
368 int pm_referenced
= 0;
370 if (boot_cpu_has(X86_FEATURE_LAPIC_TIMER_BROKEN
))
371 local_apic_timer_disabled
= 1;
374 * The local apic timer can be disabled via the kernel
375 * commandline or from the test above. Register the lapic
376 * timer as a dummy clock event source on SMP systems, so the
377 * broadcast mechanism is used. On UP systems simply ignore it.
379 if (local_apic_timer_disabled
) {
380 /* No broadcast on UP ! */
381 if (num_possible_cpus() > 1)
386 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
387 "calibrating APIC timer ...\n");
391 /* Replace the global interrupt handler */
392 real_handler
= global_clock_event
->event_handler
;
393 global_clock_event
->event_handler
= lapic_cal_handler
;
396 * Setup the APIC counter to 1e9. There is no way the lapic
397 * can underflow in the 100ms detection time frame
399 __setup_APIC_LVTT(1000000000, 0, 0);
401 /* Let the interrupts run */
404 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
409 /* Restore the real event handler */
410 global_clock_event
->event_handler
= real_handler
;
412 /* Build delta t1-t2 as apic timer counts down */
413 delta
= lapic_cal_t1
- lapic_cal_t2
;
414 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
416 /* Check, if the PM timer is available */
417 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
418 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
424 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
426 if (deltapm
> (pm_100ms
- pm_thresh
) &&
427 deltapm
< (pm_100ms
+ pm_thresh
)) {
428 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
430 res
= (((u64
) deltapm
) * mult
) >> 22;
431 do_div(res
, 1000000);
432 printk(KERN_WARNING
"APIC calibration not consistent "
433 "with PM Timer: %ldms instead of 100ms\n",
435 /* Correct the lapic counter value */
436 res
= (((u64
) delta
) * pm_100ms
);
437 do_div(res
, deltapm
);
438 printk(KERN_INFO
"APIC delta adjusted to PM-Timer: "
439 "%lu (%ld)\n", (unsigned long) res
, delta
);
445 /* Calculate the scaled math multiplication factor */
446 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
, 32);
447 lapic_clockevent
.max_delta_ns
=
448 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
449 lapic_clockevent
.min_delta_ns
=
450 clockevent_delta2ns(0xF, &lapic_clockevent
);
452 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
454 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
455 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
456 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
460 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
461 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
463 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
464 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
467 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
469 calibration_result
/ (1000000 / HZ
),
470 calibration_result
% (1000000 / HZ
));
472 local_apic_timer_verify_ok
= 1;
474 /* We trust the pm timer based calibration */
475 if (!pm_referenced
) {
476 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
479 * Setup the apic timer manually
481 levt
->event_handler
= lapic_cal_handler
;
482 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
483 lapic_cal_loops
= -1;
485 /* Let the interrupts run */
488 while(lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
493 /* Stop the lapic timer */
494 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
499 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
500 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
502 /* Check, if the jiffies result is consistent */
503 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
504 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
506 local_apic_timer_verify_ok
= 0;
510 if (!local_apic_timer_verify_ok
) {
512 "APIC timer disabled due to verification failure.\n");
513 /* No broadcast on UP ! */
514 if (num_possible_cpus() == 1)
518 * If nmi_watchdog is set to IO_APIC, we need the
519 * PIT/HPET going. Otherwise register lapic as a dummy
522 if (nmi_watchdog
!= NMI_IO_APIC
)
523 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
526 /* Setup the lapic or request the broadcast */
530 void __devinit
setup_secondary_APIC_clock(void)
536 * The guts of the apic timer interrupt
538 static void local_apic_timer_interrupt(void)
540 int cpu
= smp_processor_id();
541 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
544 * Normally we should not be here till LAPIC has been initialized but
545 * in some cases like kdump, its possible that there is a pending LAPIC
546 * timer interrupt from previous kernel's context and is delivered in
547 * new kernel the moment interrupts are enabled.
549 * Interrupts are enabled early and LAPIC is setup much later, hence
550 * its possible that when we get here evt->event_handler is NULL.
551 * Check for event_handler being NULL and discard the interrupt as
554 if (!evt
->event_handler
) {
556 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
558 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
562 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
564 evt
->event_handler(evt
);
568 * Local APIC timer interrupt. This is the most natural way for doing
569 * local interrupts, but local timer interrupts can be emulated by
570 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
572 * [ if a single-CPU system runs an SMP kernel then we call the local
573 * interrupt as well. Thus we cannot inline the local irq ... ]
576 void fastcall
smp_apic_timer_interrupt(struct pt_regs
*regs
)
578 struct pt_regs
*old_regs
= set_irq_regs(regs
);
581 * NOTE! We'd better ACK the irq immediately,
582 * because timer handling can be slow.
586 * update_process_times() expects us to have done irq_enter().
587 * Besides, if we don't timer interrupts ignore the global
588 * interrupt lock, which is the WrongThing (tm) to do.
591 local_apic_timer_interrupt();
594 set_irq_regs(old_regs
);
597 int setup_profiling_timer(unsigned int multiplier
)
603 * Local APIC start and shutdown
607 * clear_local_APIC - shutdown the local APIC
609 * This is called, when a CPU is disabled and before rebooting, so the state of
610 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
611 * leftovers during boot.
613 void clear_local_APIC(void)
615 int maxlvt
= lapic_get_maxlvt();
619 * Masking an LVT entry can trigger a local APIC error
620 * if the vector is zero. Mask LVTERR first to prevent this.
623 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
624 apic_write_around(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
627 * Careful: we have to set masks only first to deassert
628 * any level-triggered sources.
630 v
= apic_read(APIC_LVTT
);
631 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
632 v
= apic_read(APIC_LVT0
);
633 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
634 v
= apic_read(APIC_LVT1
);
635 apic_write_around(APIC_LVT1
, v
| APIC_LVT_MASKED
);
637 v
= apic_read(APIC_LVTPC
);
638 apic_write_around(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
641 /* lets not touch this if we didn't frob it */
642 #ifdef CONFIG_X86_MCE_P4THERMAL
644 v
= apic_read(APIC_LVTTHMR
);
645 apic_write_around(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
649 * Clean APIC state for other OSs:
651 apic_write_around(APIC_LVTT
, APIC_LVT_MASKED
);
652 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
653 apic_write_around(APIC_LVT1
, APIC_LVT_MASKED
);
655 apic_write_around(APIC_LVTERR
, APIC_LVT_MASKED
);
657 apic_write_around(APIC_LVTPC
, APIC_LVT_MASKED
);
659 #ifdef CONFIG_X86_MCE_P4THERMAL
661 apic_write_around(APIC_LVTTHMR
, APIC_LVT_MASKED
);
663 /* Integrated APIC (!82489DX) ? */
664 if (lapic_is_integrated()) {
666 /* Clear ESR due to Pentium errata 3AP and 11AP */
667 apic_write(APIC_ESR
, 0);
673 * disable_local_APIC - clear and disable the local APIC
675 void disable_local_APIC(void)
682 * Disable APIC (implies clearing of registers
685 value
= apic_read(APIC_SPIV
);
686 value
&= ~APIC_SPIV_APIC_ENABLED
;
687 apic_write_around(APIC_SPIV
, value
);
690 * When LAPIC was disabled by the BIOS and enabled by the kernel,
691 * restore the disabled state.
693 if (enabled_via_apicbase
) {
696 rdmsr(MSR_IA32_APICBASE
, l
, h
);
697 l
&= ~MSR_IA32_APICBASE_ENABLE
;
698 wrmsr(MSR_IA32_APICBASE
, l
, h
);
703 * If Linux enabled the LAPIC against the BIOS default disable it down before
704 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
705 * not power-off. Additionally clear all LVT entries before disable_local_APIC
706 * for the case where Linux didn't enable the LAPIC.
708 void lapic_shutdown(void)
715 local_irq_save(flags
);
718 if (enabled_via_apicbase
)
719 disable_local_APIC();
721 local_irq_restore(flags
);
725 * This is to verify that we're looking at a real local APIC.
726 * Check these against your board if the CPUs aren't getting
727 * started for no apparent reason.
729 int __init
verify_local_APIC(void)
731 unsigned int reg0
, reg1
;
734 * The version register is read-only in a real APIC.
736 reg0
= apic_read(APIC_LVR
);
737 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
738 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
739 reg1
= apic_read(APIC_LVR
);
740 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
743 * The two version reads above should print the same
744 * numbers. If the second one is different, then we
745 * poke at a non-APIC.
751 * Check if the version looks reasonably.
753 reg1
= GET_APIC_VERSION(reg0
);
754 if (reg1
== 0x00 || reg1
== 0xff)
756 reg1
= lapic_get_maxlvt();
757 if (reg1
< 0x02 || reg1
== 0xff)
761 * The ID register is read/write in a real APIC.
763 reg0
= apic_read(APIC_ID
);
764 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
767 * The next two are just to see if we have sane values.
768 * They're only really relevant if we're in Virtual Wire
769 * compatibility mode, but most boxes are anymore.
771 reg0
= apic_read(APIC_LVT0
);
772 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
773 reg1
= apic_read(APIC_LVT1
);
774 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
780 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
782 void __init
sync_Arb_IDs(void)
785 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
793 apic_wait_icr_idle();
795 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
796 apic_write_around(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
801 * An initial setup of the virtual wire mode.
803 void __init
init_bsp_APIC(void)
808 * Don't do the setup now if we have a SMP BIOS as the
809 * through-I/O-APIC virtual wire mode might be active.
811 if (smp_found_config
|| !cpu_has_apic
)
815 * Do not trust the local APIC being empty at bootup.
822 value
= apic_read(APIC_SPIV
);
823 value
&= ~APIC_VECTOR_MASK
;
824 value
|= APIC_SPIV_APIC_ENABLED
;
826 /* This bit is reserved on P4/Xeon and should be cleared */
827 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
828 (boot_cpu_data
.x86
== 15))
829 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
831 value
|= APIC_SPIV_FOCUS_DISABLED
;
832 value
|= SPURIOUS_APIC_VECTOR
;
833 apic_write_around(APIC_SPIV
, value
);
836 * Set up the virtual wire mode.
838 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
840 if (!lapic_is_integrated()) /* 82489DX */
841 value
|= APIC_LVT_LEVEL_TRIGGER
;
842 apic_write_around(APIC_LVT1
, value
);
846 * setup_local_APIC - setup the local APIC
848 void __devinit
setup_local_APIC(void)
850 unsigned long oldvalue
, value
, maxlvt
, integrated
;
853 /* Pound the ESR really hard over the head with a big hammer - mbligh */
855 apic_write(APIC_ESR
, 0);
856 apic_write(APIC_ESR
, 0);
857 apic_write(APIC_ESR
, 0);
858 apic_write(APIC_ESR
, 0);
861 integrated
= lapic_is_integrated();
864 * Double-check whether this APIC is really registered.
866 if (!apic_id_registered())
870 * Intel recommends to set DFR, LDR and TPR before enabling
871 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
872 * document number 292116). So here it goes...
877 * Set Task Priority to 'accept all'. We never change this
880 value
= apic_read(APIC_TASKPRI
);
881 value
&= ~APIC_TPRI_MASK
;
882 apic_write_around(APIC_TASKPRI
, value
);
885 * After a crash, we no longer service the interrupts and a pending
886 * interrupt from previous kernel might still have ISR bit set.
888 * Most probably by now CPU has serviced that pending interrupt and
889 * it might not have done the ack_APIC_irq() because it thought,
890 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
891 * does not clear the ISR bit and cpu thinks it has already serivced
892 * the interrupt. Hence a vector might get locked. It was noticed
893 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
895 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
896 value
= apic_read(APIC_ISR
+ i
*0x10);
897 for (j
= 31; j
>= 0; j
--) {
904 * Now that we are all set up, enable the APIC
906 value
= apic_read(APIC_SPIV
);
907 value
&= ~APIC_VECTOR_MASK
;
911 value
|= APIC_SPIV_APIC_ENABLED
;
914 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
915 * certain networking cards. If high frequency interrupts are
916 * happening on a particular IOAPIC pin, plus the IOAPIC routing
917 * entry is masked/unmasked at a high rate as well then sooner or
918 * later IOAPIC line gets 'stuck', no more interrupts are received
919 * from the device. If focus CPU is disabled then the hang goes
922 * [ This bug can be reproduced easily with a level-triggered
923 * PCI Ne2000 networking cards and PII/PIII processors, dual
927 * Actually disabling the focus CPU check just makes the hang less
928 * frequent as it makes the interrupt distributon model be more
929 * like LRU than MRU (the short-term load is more even across CPUs).
930 * See also the comment in end_level_ioapic_irq(). --macro
933 /* Enable focus processor (bit==0) */
934 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
937 * Set spurious IRQ vector
939 value
|= SPURIOUS_APIC_VECTOR
;
940 apic_write_around(APIC_SPIV
, value
);
945 * set up through-local-APIC on the BP's LINT0. This is not
946 * strictly necessery in pure symmetric-IO mode, but sometimes
947 * we delegate interrupts to the 8259A.
950 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
952 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
953 if (!smp_processor_id() && (pic_mode
|| !value
)) {
954 value
= APIC_DM_EXTINT
;
955 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
958 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
959 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
962 apic_write_around(APIC_LVT0
, value
);
965 * only the BP should see the LINT1 NMI signal, obviously.
967 if (!smp_processor_id())
970 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
971 if (!integrated
) /* 82489DX */
972 value
|= APIC_LVT_LEVEL_TRIGGER
;
973 apic_write_around(APIC_LVT1
, value
);
975 if (integrated
&& !esr_disable
) { /* !82489DX */
976 maxlvt
= lapic_get_maxlvt();
977 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
978 apic_write(APIC_ESR
, 0);
979 oldvalue
= apic_read(APIC_ESR
);
981 /* enables sending errors */
982 value
= ERROR_APIC_VECTOR
;
983 apic_write_around(APIC_LVTERR
, value
);
985 * spec says clear errors after enabling vector.
988 apic_write(APIC_ESR
, 0);
989 value
= apic_read(APIC_ESR
);
990 if (value
!= oldvalue
)
991 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
992 "vector: 0x%08lx after: 0x%08lx\n",
997 * Something untraceble is creating bad interrupts on
998 * secondary quads ... for the moment, just leave the
999 * ESR disabled - we can't do anything useful with the
1000 * errors anyway - mbligh
1002 printk(KERN_INFO
"Leaving ESR disabled.\n");
1004 printk(KERN_INFO
"No ESR for 82489DX.\n");
1007 /* Disable the local apic timer */
1008 value
= apic_read(APIC_LVTT
);
1009 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1010 apic_write_around(APIC_LVTT
, value
);
1012 setup_apic_nmi_watchdog(NULL
);
1017 * Detect and initialize APIC
1019 static int __init
detect_init_APIC (void)
1023 /* Disabled by kernel option? */
1024 if (enable_local_apic
< 0)
1027 switch (boot_cpu_data
.x86_vendor
) {
1028 case X86_VENDOR_AMD
:
1029 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1030 (boot_cpu_data
.x86
== 15))
1033 case X86_VENDOR_INTEL
:
1034 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1035 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1042 if (!cpu_has_apic
) {
1044 * Over-ride BIOS and try to enable the local APIC only if
1045 * "lapic" specified.
1047 if (enable_local_apic
<= 0) {
1048 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1049 "you can enable it with \"lapic\"\n");
1053 * Some BIOSes disable the local APIC in the APIC_BASE
1054 * MSR. This can only be done in software for Intel P6 or later
1055 * and AMD K7 (Model > 1) or later.
1057 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1058 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1060 "Local APIC disabled by BIOS -- reenabling.\n");
1061 l
&= ~MSR_IA32_APICBASE_BASE
;
1062 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1063 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1064 enabled_via_apicbase
= 1;
1068 * The APIC feature bit should now be enabled
1071 features
= cpuid_edx(1);
1072 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1073 printk(KERN_WARNING
"Could not enable APIC!\n");
1076 set_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1077 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1079 /* The BIOS may have set up the APIC at some other address */
1080 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1081 if (l
& MSR_IA32_APICBASE_ENABLE
)
1082 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1084 if (nmi_watchdog
!= NMI_NONE
)
1085 nmi_watchdog
= NMI_LOCAL_APIC
;
1087 printk(KERN_INFO
"Found and enabled local APIC!\n");
1094 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1099 * init_apic_mappings - initialize APIC mappings
1101 void __init
init_apic_mappings(void)
1103 unsigned long apic_phys
;
1106 * If no local APIC can be found then set up a fake all
1107 * zeroes page to simulate the local APIC and another
1108 * one for the IO-APIC.
1110 if (!smp_found_config
&& detect_init_APIC()) {
1111 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1112 apic_phys
= __pa(apic_phys
);
1114 apic_phys
= mp_lapic_addr
;
1116 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1117 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
1121 * Fetch the APIC ID of the BSP in case we have a
1122 * default configuration (or the MP table is broken).
1124 if (boot_cpu_physical_apicid
== -1U)
1125 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1127 #ifdef CONFIG_X86_IO_APIC
1129 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
1132 for (i
= 0; i
< nr_ioapics
; i
++) {
1133 if (smp_found_config
) {
1134 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
1137 "WARNING: bogus zero IO-APIC "
1138 "address found in MPTABLE, "
1139 "disabling IO/APIC support!\n");
1140 smp_found_config
= 0;
1141 skip_ioapic_setup
= 1;
1142 goto fake_ioapic_page
;
1146 ioapic_phys
= (unsigned long)
1147 alloc_bootmem_pages(PAGE_SIZE
);
1148 ioapic_phys
= __pa(ioapic_phys
);
1150 set_fixmap_nocache(idx
, ioapic_phys
);
1151 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
1152 __fix_to_virt(idx
), ioapic_phys
);
1160 * This initializes the IO-APIC and APIC hardware if this is
1163 int __init
APIC_init_uniprocessor (void)
1165 if (enable_local_apic
< 0)
1166 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1168 if (!smp_found_config
&& !cpu_has_apic
)
1172 * Complain if the BIOS pretends there is one.
1174 if (!cpu_has_apic
&&
1175 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1176 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1177 boot_cpu_physical_apicid
);
1178 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1182 verify_local_APIC();
1187 * Hack: In case of kdump, after a crash, kernel might be booting
1188 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1189 * might be zero if read from MP tables. Get it from LAPIC.
1191 #ifdef CONFIG_CRASH_DUMP
1192 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1194 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
1198 #ifdef CONFIG_X86_IO_APIC
1199 if (smp_found_config
)
1200 if (!skip_ioapic_setup
&& nr_ioapics
)
1209 * APIC command line parameters
1211 static int __init
parse_lapic(char *arg
)
1213 enable_local_apic
= 1;
1216 early_param("lapic", parse_lapic
);
1218 static int __init
parse_nolapic(char *arg
)
1220 enable_local_apic
= -1;
1221 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1224 early_param("nolapic", parse_nolapic
);
1226 static int __init
parse_disable_lapic_timer(char *arg
)
1228 local_apic_timer_disabled
= 1;
1231 early_param("nolapic_timer", parse_disable_lapic_timer
);
1233 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1235 local_apic_timer_c2_ok
= 1;
1238 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1240 static int __init
apic_set_verbosity(char *str
)
1242 if (strcmp("debug", str
) == 0)
1243 apic_verbosity
= APIC_DEBUG
;
1244 else if (strcmp("verbose", str
) == 0)
1245 apic_verbosity
= APIC_VERBOSE
;
1249 __setup("apic=", apic_set_verbosity
);
1253 * Local APIC interrupts
1257 * This interrupt should _never_ happen with our APIC/SMP architecture
1259 void smp_spurious_interrupt(struct pt_regs
*regs
)
1265 * Check if this really is a spurious interrupt and ACK it
1266 * if it is a vectored one. Just in case...
1267 * Spurious interrupts should not be ACKed.
1269 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1270 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1273 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1274 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, "
1275 "should never happen.\n", smp_processor_id());
1280 * This interrupt should never happen with our APIC/SMP architecture
1282 void smp_error_interrupt(struct pt_regs
*regs
)
1284 unsigned long v
, v1
;
1287 /* First tickle the hardware, only then report what went on. -- REW */
1288 v
= apic_read(APIC_ESR
);
1289 apic_write(APIC_ESR
, 0);
1290 v1
= apic_read(APIC_ESR
);
1292 atomic_inc(&irq_err_count
);
1294 /* Here is what the APIC error bits mean:
1297 2: Send accept error
1298 3: Receive accept error
1300 5: Send illegal vector
1301 6: Received illegal vector
1302 7: Illegal register address
1304 printk (KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1305 smp_processor_id(), v
, v1
);
1310 * Initialize APIC interrupts
1312 void __init
apic_intr_init(void)
1317 /* self generated IPI for local APIC timer */
1318 set_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
1320 /* IPI vectors for APIC spurious and error interrupts */
1321 set_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
1322 set_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
1324 /* thermal monitor LVT interrupt */
1325 #ifdef CONFIG_X86_MCE_P4THERMAL
1326 set_intr_gate(THERMAL_APIC_VECTOR
, thermal_interrupt
);
1331 * connect_bsp_APIC - attach the APIC to the interrupt system
1333 void __init
connect_bsp_APIC(void)
1337 * Do not trust the local APIC being empty at bootup.
1341 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1342 * local APIC to INT and NMI lines.
1344 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1345 "enabling APIC mode.\n");
1353 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1354 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1356 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1359 void disconnect_bsp_APIC(int virt_wire_setup
)
1363 * Put the board back into PIC mode (has an effect only on
1364 * certain older boards). Note that APIC interrupts, including
1365 * IPIs, won't work beyond this point! The only exception are
1368 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1369 "entering PIC mode.\n");
1373 /* Go back to Virtual Wire compatibility mode */
1374 unsigned long value
;
1376 /* For the spurious interrupt use vector F, and enable it */
1377 value
= apic_read(APIC_SPIV
);
1378 value
&= ~APIC_VECTOR_MASK
;
1379 value
|= APIC_SPIV_APIC_ENABLED
;
1381 apic_write_around(APIC_SPIV
, value
);
1383 if (!virt_wire_setup
) {
1385 * For LVT0 make it edge triggered, active high,
1386 * external and enabled
1388 value
= apic_read(APIC_LVT0
);
1389 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1390 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1391 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1392 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1393 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1394 apic_write_around(APIC_LVT0
, value
);
1397 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
1401 * For LVT1 make it edge triggered, active high, nmi and
1404 value
= apic_read(APIC_LVT1
);
1406 APIC_MODE_MASK
| APIC_SEND_PENDING
|
1407 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1408 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1409 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1410 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1411 apic_write_around(APIC_LVT1
, value
);
1422 /* r/w apic fields */
1423 unsigned int apic_id
;
1424 unsigned int apic_taskpri
;
1425 unsigned int apic_ldr
;
1426 unsigned int apic_dfr
;
1427 unsigned int apic_spiv
;
1428 unsigned int apic_lvtt
;
1429 unsigned int apic_lvtpc
;
1430 unsigned int apic_lvt0
;
1431 unsigned int apic_lvt1
;
1432 unsigned int apic_lvterr
;
1433 unsigned int apic_tmict
;
1434 unsigned int apic_tdcr
;
1435 unsigned int apic_thmr
;
1438 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1440 unsigned long flags
;
1443 if (!apic_pm_state
.active
)
1446 maxlvt
= lapic_get_maxlvt();
1448 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1449 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1450 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1451 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1452 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1453 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1455 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1456 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1457 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1458 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1459 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1460 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1461 #ifdef CONFIG_X86_MCE_P4THERMAL
1463 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1466 local_irq_save(flags
);
1467 disable_local_APIC();
1468 local_irq_restore(flags
);
1472 static int lapic_resume(struct sys_device
*dev
)
1475 unsigned long flags
;
1478 if (!apic_pm_state
.active
)
1481 maxlvt
= lapic_get_maxlvt();
1483 local_irq_save(flags
);
1486 * Make sure the APICBASE points to the right address
1488 * FIXME! This will be wrong if we ever support suspend on
1489 * SMP! We'll need to do this as part of the CPU restore!
1491 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1492 l
&= ~MSR_IA32_APICBASE_BASE
;
1493 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1494 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1496 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1497 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1498 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1499 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1500 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1501 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1502 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1503 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1504 #ifdef CONFIG_X86_MCE_P4THERMAL
1506 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1509 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1510 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1511 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1512 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1513 apic_write(APIC_ESR
, 0);
1514 apic_read(APIC_ESR
);
1515 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1516 apic_write(APIC_ESR
, 0);
1517 apic_read(APIC_ESR
);
1518 local_irq_restore(flags
);
1523 * This device has no shutdown method - fully functioning local APICs
1524 * are needed on every CPU up until machine_halt/restart/poweroff.
1527 static struct sysdev_class lapic_sysclass
= {
1528 set_kset_name("lapic"),
1529 .resume
= lapic_resume
,
1530 .suspend
= lapic_suspend
,
1533 static struct sys_device device_lapic
= {
1535 .cls
= &lapic_sysclass
,
1538 static void __devinit
apic_pm_activate(void)
1540 apic_pm_state
.active
= 1;
1543 static int __init
init_lapic_sysfs(void)
1549 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1551 error
= sysdev_class_register(&lapic_sysclass
);
1553 error
= sysdev_register(&device_lapic
);
1556 device_initcall(init_lapic_sysfs
);
1558 #else /* CONFIG_PM */
1560 static void apic_pm_activate(void) { }
1562 #endif /* CONFIG_PM */