4 #include <linux/kernel.h>
5 #include <linux/spinlock.h>
6 #include <linux/interrupt.h>
7 #include <linux/hw_random.h>
8 #include <linux/ssb/ssb.h>
9 #include <net/mac80211.h>
16 #include "phy_common.h"
19 /* The unique identifier of the firmware that's officially supported by
20 * this driver version. */
21 #define B43_SUPPORTED_FIRMWARE_ID "FW13"
24 #ifdef CONFIG_B43_DEBUG
31 #define B43_MMIO_DMA0_REASON 0x20
32 #define B43_MMIO_DMA0_IRQ_MASK 0x24
33 #define B43_MMIO_DMA1_REASON 0x28
34 #define B43_MMIO_DMA1_IRQ_MASK 0x2C
35 #define B43_MMIO_DMA2_REASON 0x30
36 #define B43_MMIO_DMA2_IRQ_MASK 0x34
37 #define B43_MMIO_DMA3_REASON 0x38
38 #define B43_MMIO_DMA3_IRQ_MASK 0x3C
39 #define B43_MMIO_DMA4_REASON 0x40
40 #define B43_MMIO_DMA4_IRQ_MASK 0x44
41 #define B43_MMIO_DMA5_REASON 0x48
42 #define B43_MMIO_DMA5_IRQ_MASK 0x4C
43 #define B43_MMIO_MACCTL 0x120 /* MAC control */
44 #define B43_MMIO_MACCMD 0x124 /* MAC command */
45 #define B43_MMIO_GEN_IRQ_REASON 0x128
46 #define B43_MMIO_GEN_IRQ_MASK 0x12C
47 #define B43_MMIO_RAM_CONTROL 0x130
48 #define B43_MMIO_RAM_DATA 0x134
49 #define B43_MMIO_PS_STATUS 0x140
50 #define B43_MMIO_RADIO_HWENABLED_HI 0x158
51 #define B43_MMIO_SHM_CONTROL 0x160
52 #define B43_MMIO_SHM_DATA 0x164
53 #define B43_MMIO_SHM_DATA_UNALIGNED 0x166
54 #define B43_MMIO_XMITSTAT_0 0x170
55 #define B43_MMIO_XMITSTAT_1 0x174
56 #define B43_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
57 #define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
58 #define B43_MMIO_TSF_CFP_REP 0x188
59 #define B43_MMIO_TSF_CFP_START 0x18C
60 #define B43_MMIO_TSF_CFP_MAXDUR 0x190
63 #define B43_MMIO_DMA32_BASE0 0x200
64 #define B43_MMIO_DMA32_BASE1 0x220
65 #define B43_MMIO_DMA32_BASE2 0x240
66 #define B43_MMIO_DMA32_BASE3 0x260
67 #define B43_MMIO_DMA32_BASE4 0x280
68 #define B43_MMIO_DMA32_BASE5 0x2A0
70 #define B43_MMIO_DMA64_BASE0 0x200
71 #define B43_MMIO_DMA64_BASE1 0x240
72 #define B43_MMIO_DMA64_BASE2 0x280
73 #define B43_MMIO_DMA64_BASE3 0x2C0
74 #define B43_MMIO_DMA64_BASE4 0x300
75 #define B43_MMIO_DMA64_BASE5 0x340
77 /* PIO on core rev < 11 */
78 #define B43_MMIO_PIO_BASE0 0x300
79 #define B43_MMIO_PIO_BASE1 0x310
80 #define B43_MMIO_PIO_BASE2 0x320
81 #define B43_MMIO_PIO_BASE3 0x330
82 #define B43_MMIO_PIO_BASE4 0x340
83 #define B43_MMIO_PIO_BASE5 0x350
84 #define B43_MMIO_PIO_BASE6 0x360
85 #define B43_MMIO_PIO_BASE7 0x370
86 /* PIO on core rev >= 11 */
87 #define B43_MMIO_PIO11_BASE0 0x200
88 #define B43_MMIO_PIO11_BASE1 0x240
89 #define B43_MMIO_PIO11_BASE2 0x280
90 #define B43_MMIO_PIO11_BASE3 0x2C0
91 #define B43_MMIO_PIO11_BASE4 0x300
92 #define B43_MMIO_PIO11_BASE5 0x340
94 #define B43_MMIO_PHY_VER 0x3E0
95 #define B43_MMIO_PHY_RADIO 0x3E2
96 #define B43_MMIO_PHY0 0x3E6
97 #define B43_MMIO_ANTENNA 0x3E8
98 #define B43_MMIO_CHANNEL 0x3F0
99 #define B43_MMIO_CHANNEL_EXT 0x3F4
100 #define B43_MMIO_RADIO_CONTROL 0x3F6
101 #define B43_MMIO_RADIO_DATA_HIGH 0x3F8
102 #define B43_MMIO_RADIO_DATA_LOW 0x3FA
103 #define B43_MMIO_PHY_CONTROL 0x3FC
104 #define B43_MMIO_PHY_DATA 0x3FE
105 #define B43_MMIO_MACFILTER_CONTROL 0x420
106 #define B43_MMIO_MACFILTER_DATA 0x422
107 #define B43_MMIO_RCMTA_COUNT 0x43C
108 #define B43_MMIO_PSM_PHY_HDR 0x492
109 #define B43_MMIO_RADIO_HWENABLED_LO 0x49A
110 #define B43_MMIO_GPIO_CONTROL 0x49C
111 #define B43_MMIO_GPIO_MASK 0x49E
112 #define B43_MMIO_TSF_CFP_START_LOW 0x604
113 #define B43_MMIO_TSF_CFP_START_HIGH 0x606
114 #define B43_MMIO_TSF_CFP_PRETBTT 0x612
115 #define B43_MMIO_TSF_0 0x632 /* core rev < 3 only */
116 #define B43_MMIO_TSF_1 0x634 /* core rev < 3 only */
117 #define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */
118 #define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */
119 #define B43_MMIO_RNG 0x65A
120 #define B43_MMIO_IFSSLOT 0x684 /* Interframe slot time */
121 #define B43_MMIO_IFSCTL 0x688 /* Interframe space control */
122 #define B43_MMIO_IFSCTL_USE_EDCF 0x0004
123 #define B43_MMIO_POWERUP_DELAY 0x6A8
124 #define B43_MMIO_BTCOEX_CTL 0x6B4 /* Bluetooth Coexistence Control */
125 #define B43_MMIO_BTCOEX_STAT 0x6B6 /* Bluetooth Coexistence Status */
126 #define B43_MMIO_BTCOEX_TXCTL 0x6B8 /* Bluetooth Coexistence Transmit Control */
128 /* SPROM boardflags_lo values */
129 #define B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
130 #define B43_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
131 #define B43_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
132 #define B43_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
133 #define B43_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
134 #define B43_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
135 #define B43_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
136 #define B43_BFL_ENETADM 0x0080 /* has ADMtek switch */
137 #define B43_BFL_ENETVLAN 0x0100 /* can do vlan */
138 #define B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
139 #define B43_BFL_NOPCI 0x0400 /* leaves PCI floating */
140 #define B43_BFL_FEM 0x0800 /* supports the Front End Module */
141 #define B43_BFL_EXTLNA 0x1000 /* has an external LNA */
142 #define B43_BFL_HGPA 0x2000 /* had high gain PA */
143 #define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
144 #define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
146 /* SPROM boardflags_hi values */
147 #define B43_BFH_NOPA 0x0001 /* has no PA */
148 #define B43_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
149 #define B43_BFH_PAREF 0x0004 /* uses the PARef LDO */
150 #define B43_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared
152 #define B43_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
153 #define B43_BFH_BUCKBOOST 0x0020 /* has buck/booster */
154 #define B43_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna
157 /* SPROM boardflags2_lo values */
158 #define B43_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
159 #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
160 #define B43_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
161 #define B43_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
162 #define B43_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
163 #define B43_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
164 #define B43_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
165 #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
166 #define B43_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
167 #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
168 #define B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
170 /* GPIO register offset, in both ChipCommon and PCI core. */
171 #define B43_GPIO_CONTROL 0x6c
175 B43_SHM_UCODE
, /* Microcode memory */
176 B43_SHM_SHARED
, /* Shared memory */
177 B43_SHM_SCRATCH
, /* Scratch memory */
178 B43_SHM_HW
, /* Internal hardware register */
179 B43_SHM_RCMTA
, /* Receive match transmitter address (rev >= 5 only) */
181 /* SHM Routing modifiers */
182 #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
183 #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
184 #define B43_SHM_AUTOINC_RW (B43_SHM_AUTOINC_R | \
187 /* Misc SHM_SHARED offsets */
188 #define B43_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
189 #define B43_SHM_SH_PCTLWDPOS 0x0008
190 #define B43_SHM_SH_RXPADOFF 0x0034 /* RX Padding data offset (PIO only) */
191 #define B43_SHM_SH_FWCAPA 0x0042 /* Firmware capabilities (Opensource firmware only) */
192 #define B43_SHM_SH_PHYVER 0x0050 /* PHY version */
193 #define B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */
194 #define B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */
195 #define B43_SHM_SH_HOSTFLO 0x005E /* Hostflags for ucode options (low) */
196 #define B43_SHM_SH_HOSTFMI 0x0060 /* Hostflags for ucode options (middle) */
197 #define B43_SHM_SH_HOSTFHI 0x0062 /* Hostflags for ucode options (high) */
198 #define B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */
199 #define B43_SHM_SH_RADAR 0x0066 /* Radar register */
200 #define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */
201 #define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */
202 #define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */
203 #define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5 Ghz channel */
204 #define B43_SHM_SH_CHAN_40MHZ 0x0200 /* Bit set, if 40 Mhz channel width */
205 #define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */
206 /* TSSI information */
207 #define B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */
208 #define B43_SHM_SH_TSSI_OFDM_A 0x0068 /* TSSI for last 4 OFDM frames (32bit) */
209 #define B43_SHM_SH_TSSI_OFDM_G 0x0070 /* TSSI for last 4 OFDM frames (32bit) */
210 #define B43_TSSI_MAX 0x7F /* Max value for one TSSI value */
211 /* SHM_SHARED TX FIFO variables */
212 #define B43_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */
213 #define B43_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */
214 #define B43_SHM_SH_SIZE45 0x009C /* TX FIFO size for FIFO 4 and 5 */
215 #define B43_SHM_SH_SIZE67 0x009E /* TX FIFO size for FIFO 6 and 7 */
216 /* SHM_SHARED background noise */
217 #define B43_SHM_SH_JSSI0 0x0088 /* Measure JSSI 0 */
218 #define B43_SHM_SH_JSSI1 0x008A /* Measure JSSI 1 */
219 #define B43_SHM_SH_JSSIAUX 0x008C /* Measure JSSI AUX */
220 /* SHM_SHARED crypto engine */
221 #define B43_SHM_SH_DEFAULTIV 0x003C /* Default IV location */
222 #define B43_SHM_SH_NRRXTRANS 0x003E /* # of soft RX transmitter addresses (max 8) */
223 #define B43_SHM_SH_KTP 0x0056 /* Key table pointer */
224 #define B43_SHM_SH_TKIPTSCTTAK 0x0318
225 #define B43_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block (v4 firmware) */
226 #define B43_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */
227 /* SHM_SHARED WME variables */
228 #define B43_SHM_SH_EDCFSTAT 0x000E /* EDCF status */
229 #define B43_SHM_SH_TXFCUR 0x0030 /* TXF current index */
230 #define B43_SHM_SH_EDCFQ 0x0240 /* EDCF Q info */
231 /* SHM_SHARED powersave mode related */
232 #define B43_SHM_SH_SLOTT 0x0010 /* Slot time */
233 #define B43_SHM_SH_DTIMPER 0x0012 /* DTIM period */
234 #define B43_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */
235 /* SHM_SHARED beacon/AP variables */
236 #define B43_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
237 #define B43_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
238 #define B43_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
239 #define B43_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */
240 #define B43_SHM_SH_DTIMP 0x0012 /* DTIP period */
241 #define B43_SHM_SH_MCASTCOOKIE 0x00A8 /* Last bcast/mcast frame ID */
242 #define B43_SHM_SH_SFFBLIM 0x0044 /* Short frame fallback retry limit */
243 #define B43_SHM_SH_LFFBLIM 0x0046 /* Long frame fallback retry limit */
244 #define B43_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word (see PHY TX control) */
245 #define B43_SHM_SH_EXTNPHYCTL 0x00B0 /* Extended bytes for beacon PHY control (N) */
246 /* SHM_SHARED ACK/CTS control */
247 #define B43_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word (see PHY TX control) */
248 /* SHM_SHARED probe response variables */
249 #define B43_SHM_SH_PRSSID 0x0160 /* Probe Response SSID */
250 #define B43_SHM_SH_PRSSIDLEN 0x0048 /* Probe Response SSID length */
251 #define B43_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
252 #define B43_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
253 #define B43_SHM_SH_PRPHYCTL 0x0188 /* Probe Response PHY TX control word */
254 /* SHM_SHARED rate tables */
255 #define B43_SHM_SH_OFDMDIRECT 0x01C0 /* Pointer to OFDM direct map */
256 #define B43_SHM_SH_OFDMBASIC 0x01E0 /* Pointer to OFDM basic rate map */
257 #define B43_SHM_SH_CCKDIRECT 0x0200 /* Pointer to CCK direct map */
258 #define B43_SHM_SH_CCKBASIC 0x0220 /* Pointer to CCK basic rate map */
259 /* SHM_SHARED microcode soft registers */
260 #define B43_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
261 #define B43_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
262 #define B43_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
263 #define B43_SHM_SH_UCODETIME 0x0006 /* Microcode time */
264 #define B43_SHM_SH_UCODESTAT 0x0040 /* Microcode debug status code */
265 #define B43_SHM_SH_UCODESTAT_INVALID 0
266 #define B43_SHM_SH_UCODESTAT_INIT 1
267 #define B43_SHM_SH_UCODESTAT_ACTIVE 2
268 #define B43_SHM_SH_UCODESTAT_SUSP 3 /* suspended */
269 #define B43_SHM_SH_UCODESTAT_SLEEP 4 /* asleep (PS) */
270 #define B43_SHM_SH_MAXBFRAMES 0x0080 /* Maximum number of frames in a burst */
271 #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
272 #define B43_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
273 /* SHM_SHARED tx iq workarounds */
274 #define B43_SHM_SH_NPHY_TXIQW0 0x0700
275 #define B43_SHM_SH_NPHY_TXIQW1 0x0702
276 #define B43_SHM_SH_NPHY_TXIQW2 0x0704
277 #define B43_SHM_SH_NPHY_TXIQW3 0x0706
278 /* SHM_SHARED tx pwr ctrl */
279 #define B43_SHM_SH_NPHY_TXPWR_INDX0 0x0708
280 #define B43_SHM_SH_NPHY_TXPWR_INDX1 0x070E
282 /* SHM_SCRATCH offsets */
283 #define B43_SHM_SC_MINCONT 0x0003 /* Minimum contention window */
284 #define B43_SHM_SC_MAXCONT 0x0004 /* Maximum contention window */
285 #define B43_SHM_SC_CURCONT 0x0005 /* Current contention window */
286 #define B43_SHM_SC_SRLIMIT 0x0006 /* Short retry count limit */
287 #define B43_SHM_SC_LRLIMIT 0x0007 /* Long retry count limit */
288 #define B43_SHM_SC_DTIMC 0x0008 /* Current DTIM count */
289 #define B43_SHM_SC_BTL0LEN 0x0015 /* Beacon 0 template length */
290 #define B43_SHM_SC_BTL1LEN 0x0016 /* Beacon 1 template length */
291 #define B43_SHM_SC_SCFB 0x0017 /* Short frame transmit count threshold for rate fallback */
292 #define B43_SHM_SC_LCFB 0x0018 /* Long frame transmit count threshold for rate fallback */
294 /* Hardware Radio Enable masks */
295 #define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
296 #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
298 /* HostFlags. See b43_hf_read/write() */
299 #define B43_HF_ANTDIVHELP 0x000000000001ULL /* ucode antenna div helper */
300 #define B43_HF_SYMW 0x000000000002ULL /* G-PHY SYM workaround */
301 #define B43_HF_RXPULLW 0x000000000004ULL /* RX pullup workaround */
302 #define B43_HF_CCKBOOST 0x000000000008ULL /* 4dB CCK power boost (exclusive with OFDM boost) */
303 #define B43_HF_BTCOEX 0x000000000010ULL /* Bluetooth coexistance */
304 #define B43_HF_GDCW 0x000000000020ULL /* G-PHY DC canceller filter bw workaround */
305 #define B43_HF_OFDMPABOOST 0x000000000040ULL /* Enable PA gain boost for OFDM */
306 #define B43_HF_ACPR 0x000000000080ULL /* Disable for Japan, channel 14 */
307 #define B43_HF_EDCF 0x000000000100ULL /* on if WME and MAC suspended */
308 #define B43_HF_TSSIRPSMW 0x000000000200ULL /* TSSI reset PSM ucode workaround */
309 #define B43_HF_20IN40IQW 0x000000000200ULL /* 20 in 40 MHz I/Q workaround (rev >= 13 only) */
310 #define B43_HF_DSCRQ 0x000000000400ULL /* Disable slow clock request in ucode */
311 #define B43_HF_ACIW 0x000000000800ULL /* ACI workaround: shift bits by 2 on PHY CRS */
312 #define B43_HF_2060W 0x000000001000ULL /* 2060 radio workaround */
313 #define B43_HF_RADARW 0x000000002000ULL /* Radar workaround */
314 #define B43_HF_USEDEFKEYS 0x000000004000ULL /* Enable use of default keys */
315 #define B43_HF_AFTERBURNER 0x000000008000ULL /* Afterburner enabled */
316 #define B43_HF_BT4PRIOCOEX 0x000000010000ULL /* Bluetooth 4-priority coexistance */
317 #define B43_HF_FWKUP 0x000000020000ULL /* Fast wake-up ucode */
318 #define B43_HF_VCORECALC 0x000000040000ULL /* Force VCO recalculation when powering up synthpu */
319 #define B43_HF_PCISCW 0x000000080000ULL /* PCI slow clock workaround */
320 #define B43_HF_4318TSSI 0x000000200000ULL /* 4318 TSSI */
321 #define B43_HF_FBCMCFIFO 0x000000400000ULL /* Flush bcast/mcast FIFO immediately */
322 #define B43_HF_HWPCTL 0x000000800000ULL /* Enable hardwarre power control */
323 #define B43_HF_BTCOEXALT 0x000001000000ULL /* Bluetooth coexistance in alternate pins */
324 #define B43_HF_TXBTCHECK 0x000002000000ULL /* Bluetooth check during transmission */
325 #define B43_HF_SKCFPUP 0x000004000000ULL /* Skip CFP update */
326 #define B43_HF_N40W 0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */
327 #define B43_HF_ANTSEL 0x000020000000ULL /* Antenna selection (for testing antenna div.) */
328 #define B43_HF_BT3COEXT 0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */
329 #define B43_HF_BTCANT 0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */
330 #define B43_HF_ANTSELEN 0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */
331 #define B43_HF_ANTSELMODE 0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */
332 #define B43_HF_MLADVW 0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */
333 #define B43_HF_PR45960W 0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */
335 /* Firmware capabilities field in SHM (Opensource firmware only) */
336 #define B43_FWCAPA_HWCRYPTO 0x0001
337 #define B43_FWCAPA_QOS 0x0002
339 /* MacFilter offsets. */
340 #define B43_MACFILTER_SELF 0x0000
341 #define B43_MACFILTER_BSSID 0x0003
344 #define B43_PCTL_IN 0xB0
345 #define B43_PCTL_OUT 0xB4
346 #define B43_PCTL_OUTENABLE 0xB8
347 #define B43_PCTL_XTAL_POWERUP 0x40
348 #define B43_PCTL_PLL_POWERDOWN 0x80
350 /* PowerControl Clock Modes */
351 #define B43_PCTL_CLK_FAST 0x00
352 #define B43_PCTL_CLK_SLOW 0x01
353 #define B43_PCTL_CLK_DYNAMIC 0x02
355 #define B43_PCTL_FORCE_SLOW 0x0800
356 #define B43_PCTL_FORCE_PLL 0x1000
357 #define B43_PCTL_DYN_XTAL 0x2000
360 #define B43_PHYTYPE_A 0x00
361 #define B43_PHYTYPE_B 0x01
362 #define B43_PHYTYPE_G 0x02
363 #define B43_PHYTYPE_N 0x04
364 #define B43_PHYTYPE_LP 0x05
367 #define B43_PHY_ILT_A_CTRL 0x0072
368 #define B43_PHY_ILT_A_DATA1 0x0073
369 #define B43_PHY_ILT_A_DATA2 0x0074
370 #define B43_PHY_G_LO_CONTROL 0x0810
371 #define B43_PHY_ILT_G_CTRL 0x0472
372 #define B43_PHY_ILT_G_DATA1 0x0473
373 #define B43_PHY_ILT_G_DATA2 0x0474
374 #define B43_PHY_A_PCTL 0x007B
375 #define B43_PHY_G_PCTL 0x0029
376 #define B43_PHY_A_CRS 0x0029
377 #define B43_PHY_RADIO_BITFIELD 0x0401
378 #define B43_PHY_G_CRS 0x0429
379 #define B43_PHY_NRSSILT_CTRL 0x0803
380 #define B43_PHY_NRSSILT_DATA 0x0804
383 #define B43_RADIOCTL_ID 0x01
385 /* MAC Control bitfield */
386 #define B43_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
387 #define B43_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
388 #define B43_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
389 #define B43_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
390 #define B43_MACCTL_SHM_UPPER 0x00000200 /* SHM Upper */
391 #define B43_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
392 #define B43_MACCTL_PSM_DBG 0x00002000 /* Microcode debugging enabled */
393 #define B43_MACCTL_GPOUTSMSK 0x0000C000 /* GPOUT Select Mask */
394 #define B43_MACCTL_BE 0x00010000 /* Big Endian mode */
395 #define B43_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
396 #define B43_MACCTL_AP 0x00040000 /* AccessPoint mode */
397 #define B43_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
398 #define B43_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
399 #define B43_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */
400 #define B43_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
401 #define B43_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
402 #define B43_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
403 #define B43_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
404 #define B43_MACCTL_AWAKE 0x04000000 /* Device is awake */
405 #define B43_MACCTL_CLOSEDNET 0x08000000 /* Closed net (no SSID bcast) */
406 #define B43_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
407 #define B43_MACCTL_DISCTXSTAT 0x20000000 /* Discard TX status */
408 #define B43_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */
409 #define B43_MACCTL_GMODE 0x80000000 /* G Mode */
411 /* MAC Command bitfield */
412 #define B43_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */
413 #define B43_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */
414 #define B43_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */
415 #define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */
416 #define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */
418 /* 802.11 core specific TM State Low (SSB_TMSLOW) flags */
419 #define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
420 #define B43_TMSLOW_PHY_BANDWIDTH 0x00C00000 /* PHY band width and clock speed mask (N-PHY only) */
421 #define B43_TMSLOW_PHY_BANDWIDTH_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */
422 #define B43_TMSLOW_PHY_BANDWIDTH_20MHZ 0x00400000 /* 20 MHz bandwidth, 80 MHz PHY */
423 #define B43_TMSLOW_PHY_BANDWIDTH_40MHZ 0x00800000 /* 40 MHz bandwidth, 160 MHz PHY */
424 #define B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */
425 #define B43_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */
426 #define B43_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
427 #define B43_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
429 /* 802.11 core specific TM State High (SSB_TMSHIGH) flags */
430 #define B43_TMSHIGH_DUALBAND_PHY 0x00080000 /* Dualband PHY available */
431 #define B43_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5) */
432 #define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000 /* 5 GHz PHY available (rev >= 5) */
433 #define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000 /* 2.4 GHz PHY available (rev >= 5) */
435 /* Generic-Interrupt reasons. */
436 #define B43_IRQ_MAC_SUSPENDED 0x00000001
437 #define B43_IRQ_BEACON 0x00000002
438 #define B43_IRQ_TBTT_INDI 0x00000004
439 #define B43_IRQ_BEACON_TX_OK 0x00000008
440 #define B43_IRQ_BEACON_CANCEL 0x00000010
441 #define B43_IRQ_ATIM_END 0x00000020
442 #define B43_IRQ_PMQ 0x00000040
443 #define B43_IRQ_PIO_WORKAROUND 0x00000100
444 #define B43_IRQ_MAC_TXERR 0x00000200
445 #define B43_IRQ_PHY_TXERR 0x00000800
446 #define B43_IRQ_PMEVENT 0x00001000
447 #define B43_IRQ_TIMER0 0x00002000
448 #define B43_IRQ_TIMER1 0x00004000
449 #define B43_IRQ_DMA 0x00008000
450 #define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000
451 #define B43_IRQ_CCA_MEASURE_OK 0x00020000
452 #define B43_IRQ_NOISESAMPLE_OK 0x00040000
453 #define B43_IRQ_UCODE_DEBUG 0x08000000
454 #define B43_IRQ_RFKILL 0x10000000
455 #define B43_IRQ_TX_OK 0x20000000
456 #define B43_IRQ_PHY_G_CHANGED 0x40000000
457 #define B43_IRQ_TIMEOUT 0x80000000
459 #define B43_IRQ_ALL 0xFFFFFFFF
460 #define B43_IRQ_MASKTEMPLATE (B43_IRQ_TBTT_INDI | \
463 B43_IRQ_MAC_TXERR | \
464 B43_IRQ_PHY_TXERR | \
466 B43_IRQ_TXFIFO_FLUSH_OK | \
467 B43_IRQ_NOISESAMPLE_OK | \
468 B43_IRQ_UCODE_DEBUG | \
472 /* The firmware register to fetch the debug-IRQ reason from. */
473 #define B43_DEBUGIRQ_REASON_REG 63
474 /* Debug-IRQ reasons. */
475 #define B43_DEBUGIRQ_PANIC 0 /* The firmware panic'ed */
476 #define B43_DEBUGIRQ_DUMP_SHM 1 /* Dump shared SHM */
477 #define B43_DEBUGIRQ_DUMP_REGS 2 /* Dump the microcode registers */
478 #define B43_DEBUGIRQ_MARKER 3 /* A "marker" was thrown by the firmware. */
479 #define B43_DEBUGIRQ_ACK 0xFFFF /* The host writes that to ACK the IRQ */
481 /* The firmware register that contains the "marker" line. */
482 #define B43_MARKER_ID_REG 2
483 #define B43_MARKER_LINE_REG 3
485 /* The firmware register to fetch the panic reason from. */
486 #define B43_FWPANIC_REASON_REG 3
487 /* Firmware panic reason codes */
488 #define B43_FWPANIC_DIE 0 /* Firmware died. Don't auto-restart it. */
489 #define B43_FWPANIC_RESTART 1 /* Firmware died. Schedule a controller reset. */
491 /* The firmware register that contains the watchdog counter. */
492 #define B43_WATCHDOG_REG 1
494 /* Device specific rate values.
495 * The actual values defined here are (rate_in_mbps * 2).
496 * Some code depends on this. Don't change it. */
497 #define B43_CCK_RATE_1MB 0x02
498 #define B43_CCK_RATE_2MB 0x04
499 #define B43_CCK_RATE_5MB 0x0B
500 #define B43_CCK_RATE_11MB 0x16
501 #define B43_OFDM_RATE_6MB 0x0C
502 #define B43_OFDM_RATE_9MB 0x12
503 #define B43_OFDM_RATE_12MB 0x18
504 #define B43_OFDM_RATE_18MB 0x24
505 #define B43_OFDM_RATE_24MB 0x30
506 #define B43_OFDM_RATE_36MB 0x48
507 #define B43_OFDM_RATE_48MB 0x60
508 #define B43_OFDM_RATE_54MB 0x6C
509 /* Convert a b43 rate value to a rate in 100kbps */
510 #define B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
512 #define B43_DEFAULT_SHORT_RETRY_LIMIT 7
513 #define B43_DEFAULT_LONG_RETRY_LIMIT 4
515 #define B43_PHY_TX_BADNESS_LIMIT 1000
517 /* Max size of a security key */
518 #define B43_SEC_KEYSIZE 16
519 /* Max number of group keys */
520 #define B43_NR_GROUP_KEYS 4
521 /* Max number of pairwise keys */
522 #define B43_NR_PAIRWISE_KEYS 50
523 /* Security algorithms. */
525 B43_SEC_ALGO_NONE
= 0, /* unencrypted, as of TX header. */
530 B43_SEC_ALGO_AES_LEGACY
,
535 /* The firmware file header */
536 #define B43_FW_TYPE_UCODE 'u'
537 #define B43_FW_TYPE_PCM 'p'
538 #define B43_FW_TYPE_IV 'i'
539 struct b43_fw_header
{
542 /* File format version */
545 /* Size of the data. For ucode and PCM this is in bytes.
546 * For IV this is number-of-ivs. */
550 /* Initial Value file format */
551 #define B43_IV_OFFSET_MASK 0x7FFF
552 #define B43_IV_32BIT 0x8000
562 /* Data structures for DMA transmission, per 80211 core. */
564 struct b43_dmaring
*tx_ring_AC_BK
; /* Background */
565 struct b43_dmaring
*tx_ring_AC_BE
; /* Best Effort */
566 struct b43_dmaring
*tx_ring_AC_VI
; /* Video */
567 struct b43_dmaring
*tx_ring_AC_VO
; /* Voice */
568 struct b43_dmaring
*tx_ring_mcast
; /* Multicast */
570 struct b43_dmaring
*rx_ring
;
572 u32 translation
; /* Routing bits */
575 struct b43_pio_txqueue
;
576 struct b43_pio_rxqueue
;
578 /* Data structures for PIO transmission, per 80211 core. */
580 struct b43_pio_txqueue
*tx_queue_AC_BK
; /* Background */
581 struct b43_pio_txqueue
*tx_queue_AC_BE
; /* Best Effort */
582 struct b43_pio_txqueue
*tx_queue_AC_VI
; /* Video */
583 struct b43_pio_txqueue
*tx_queue_AC_VO
; /* Voice */
584 struct b43_pio_txqueue
*tx_queue_mcast
; /* Multicast */
586 struct b43_pio_rxqueue
*rx_queue
;
589 /* Context information for a noise calculation (Link Quality). */
590 struct b43_noise_calculation
{
591 bool calculation_running
;
601 /* If keyconf is NULL, this key is disabled.
602 * keyconf is a cookie. Don't derefenrence it outside of the set_key
603 * path, because b43 doesn't own it. */
604 struct ieee80211_key_conf
*keyconf
;
608 /* SHM offsets to the QOS data structures for the 4 different queues. */
609 #define B43_QOS_PARAMS(queue) (B43_SHM_SH_EDCFQ + \
610 (B43_NR_QOSPARAMS * sizeof(u16) * (queue)))
611 #define B43_QOS_BACKGROUND B43_QOS_PARAMS(0)
612 #define B43_QOS_BESTEFFORT B43_QOS_PARAMS(1)
613 #define B43_QOS_VIDEO B43_QOS_PARAMS(2)
614 #define B43_QOS_VOICE B43_QOS_PARAMS(3)
616 /* QOS parameter hardware data structure offsets. */
617 #define B43_NR_QOSPARAMS 16
619 B43_QOSPARAM_TXOP
= 0,
629 /* QOS parameters for a queue. */
630 struct b43_qos_params
{
631 /* The QOS parameters */
632 struct ieee80211_tx_queue_params p
;
637 /* The type of the firmware file. */
638 enum b43_firmware_file_type
{
639 B43_FWTYPE_PROPRIETARY
,
640 B43_FWTYPE_OPENSOURCE
,
644 /* Context data for fetching firmware. */
645 struct b43_request_fw_context
{
646 /* The device we are requesting the fw for. */
647 struct b43_wldev
*dev
;
648 /* The type of firmware to request. */
649 enum b43_firmware_file_type req_type
;
650 /* Error messages for each firmware type. */
651 char errors
[B43_NR_FWTYPES
][128];
652 /* Temporary buffer for storing the firmware name. */
654 /* A fatal error occurred while requesting. Firmware request
655 * can not continue, as any other request will also fail. */
659 /* In-memory representation of a cached microcode file. */
660 struct b43_firmware_file
{
661 const char *filename
;
662 const struct firmware
*data
;
663 /* Type of the firmware file name. Note that this does only indicate
664 * the type by the firmware name. NOT the file contents.
665 * If you want to check for proprietary vs opensource, use (struct b43_firmware)->opensource
666 * instead! The (struct b43_firmware)->opensource flag is derived from the actual firmware
667 * binary code, not just the filename.
669 enum b43_firmware_file_type type
;
672 /* Pointers to the firmware data and meta information about it. */
673 struct b43_firmware
{
675 struct b43_firmware_file ucode
;
677 struct b43_firmware_file pcm
;
678 /* Initial MMIO values for the firmware */
679 struct b43_firmware_file initvals
;
680 /* Initial MMIO values for the firmware, band-specific */
681 struct b43_firmware_file initvals_band
;
683 /* Firmware revision */
685 /* Firmware patchlevel */
688 /* Set to true, if we are using an opensource firmware.
689 * Use this to check for proprietary vs opensource. */
691 /* Set to true, if the core needs a PCM firmware, but
692 * we failed to load one. This is always false for
693 * core rev > 10, as these don't need PCM firmware. */
694 bool pcm_request_failed
;
697 /* Device (802.11 core) initialization status. */
699 B43_STAT_UNINIT
= 0, /* Uninitialized. */
700 B43_STAT_INITIALIZED
= 1, /* Initialized, but not started, yet. */
701 B43_STAT_STARTED
= 2, /* Up and running. */
703 #define b43_status(wldev) atomic_read(&(wldev)->__init_status)
704 #define b43_set_status(wldev, stat) do { \
705 atomic_set(&(wldev)->__init_status, (stat)); \
709 /* Data structure for one wireless device (802.11 core) */
711 struct ssb_device
*sdev
; /* TODO: remove when b43_bus_dev is ready */
712 struct b43_bus_dev
*dev
;
715 /* The device initialization status.
716 * Use b43_status() to query. */
717 atomic_t __init_status
;
719 bool bad_frames_preempt
; /* Use "Bad Frames Preemption" (default off) */
720 bool dfq_valid
; /* Directed frame queue valid (IBSS PS mode, ATIM) */
721 bool radio_hw_enable
; /* saved state of radio hardware enabled state */
722 bool qos_enabled
; /* TRUE, if QoS is used. */
723 bool hwcrypto_enabled
; /* TRUE, if HW crypto acceleration is enabled. */
724 bool use_pio
; /* TRUE if next init should use PIO */
726 /* PHY/Radio device. */
735 /* Use b43_using_pio_transfers() to check whether we are using
736 * DMA or PIO data transfers. */
737 bool __using_pio_transfers
;
739 /* Various statistics about the physical device. */
740 struct b43_stats stats
;
742 /* Reason code of the last interrupt. */
745 /* The currently active generic-interrupt mask. */
748 /* Link Quality calculation context. */
749 struct b43_noise_calculation noisecalc
;
750 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
754 struct delayed_work periodic_work
;
755 unsigned int periodic_state
;
757 struct work_struct restart_work
;
759 /* encryption/decryption */
760 u16 ktp
; /* Key table pointer */
761 struct b43_key key
[B43_NR_GROUP_KEYS
* 2 + B43_NR_PAIRWISE_KEYS
];
764 struct b43_firmware fw
;
766 /* Devicelist in struct b43_wl (all 802.11 cores) */
767 struct list_head list
;
769 /* Debugging stuff follows. */
770 #ifdef CONFIG_B43_DEBUG
771 struct b43_dfsentry
*dfsentry
;
772 unsigned int irq_count
;
773 unsigned int irq_bit_count
[32];
774 unsigned int tx_count
;
775 unsigned int rx_count
;
779 /* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */
781 /* Pointer to the active wireless device on this chip */
782 struct b43_wldev
*current_dev
;
783 /* Pointer to the ieee80211 hardware data structure */
784 struct ieee80211_hw
*hw
;
786 /* Global driver mutex. Every operation must run with this mutex locked. */
788 /* Hard-IRQ spinlock. This lock protects things used in the hard-IRQ
789 * handler, only. This basically is just the IRQ mask register. */
790 spinlock_t hardirq_lock
;
792 /* The number of queues that were registered with the mac80211 subsystem
793 * initially. This is a backup copy of hw->queues in case hw->queues has
794 * to be dynamically lowered at runtime (Firmware does not support QoS).
795 * hw->queues has to be restored to the original value before unregistering
796 * from the mac80211 subsystem. */
797 u16 mac80211_initially_registered_queues
;
799 /* We can only have one operating interface (802.11 core)
800 * at a time. General information about this interface follows.
803 struct ieee80211_vif
*vif
;
804 /* The MAC address of the operating interface. */
805 u8 mac_addr
[ETH_ALEN
];
808 /* Interface type. (NL80211_IFTYPE_XXX) */
810 /* Is the card operating in AP, STA or IBSS mode? */
813 unsigned int filter_flags
;
814 /* Stats about the wireless interface */
815 struct ieee80211_low_level_stats ieee_stats
;
817 #ifdef CONFIG_B43_HWRNG
819 bool rng_initialized
;
820 char rng_name
[30 + 1];
821 #endif /* CONFIG_B43_HWRNG */
823 /* List of all wireless devices on this chip */
824 struct list_head devlist
;
827 bool radiotap_enabled
;
830 /* The beacon we are currently using (AP or IBSS mode). */
831 struct sk_buff
*current_beacon
;
832 bool beacon0_uploaded
;
833 bool beacon1_uploaded
;
834 bool beacon_templates_virgin
; /* Never wrote the templates? */
835 struct work_struct beacon_update_trigger
;
837 /* The current QOS parameters for the 4 queues. */
838 struct b43_qos_params qos_params
[4];
840 /* Work for adjustment of the transmission power.
841 * This is scheduled when we determine that the actual TX output
842 * power doesn't match what we want. */
843 struct work_struct txpower_adjust_work
;
845 /* Packet transmit work */
846 struct work_struct tx_work
;
847 /* Queue of packets to be transmitted. */
848 struct sk_buff_head tx_queue
;
850 /* The device LEDs. */
851 struct b43_leds leds
;
853 /* Kmalloc'ed scratch space for PIO TX/RX. Protected by wl->mutex. */
854 u8 pio_scratchspace
[110] __attribute__((__aligned__(8)));
855 u8 pio_tailspace
[4] __attribute__((__aligned__(8)));
858 static inline struct b43_wl
*hw_to_b43_wl(struct ieee80211_hw
*hw
)
863 static inline struct b43_wldev
*dev_to_b43_wldev(struct device
*dev
)
865 struct ssb_device
*ssb_dev
= dev_to_ssb_dev(dev
);
866 return ssb_get_drvdata(ssb_dev
);
869 /* Is the device operating in a specified mode (NL80211_IFTYPE_XXX). */
870 static inline int b43_is_mode(struct b43_wl
*wl
, int type
)
872 return (wl
->operating
&& wl
->if_type
== type
);
876 * b43_current_band - Returns the currently used band.
877 * Returns one of IEEE80211_BAND_2GHZ and IEEE80211_BAND_5GHZ.
879 static inline enum ieee80211_band
b43_current_band(struct b43_wl
*wl
)
881 return wl
->hw
->conf
.channel
->band
;
884 static inline u16
b43_read16(struct b43_wldev
*dev
, u16 offset
)
886 return ssb_read16(dev
->sdev
, offset
);
889 static inline void b43_write16(struct b43_wldev
*dev
, u16 offset
, u16 value
)
891 ssb_write16(dev
->sdev
, offset
, value
);
894 static inline u32
b43_read32(struct b43_wldev
*dev
, u16 offset
)
896 return ssb_read32(dev
->sdev
, offset
);
899 static inline void b43_write32(struct b43_wldev
*dev
, u16 offset
, u32 value
)
901 ssb_write32(dev
->sdev
, offset
, value
);
904 static inline void b43_block_read(struct b43_wldev
*dev
, void *buffer
,
905 size_t count
, u16 offset
, u8 reg_width
)
907 ssb_block_read(dev
->sdev
, buffer
, count
, offset
, reg_width
);
910 static inline void b43_block_write(struct b43_wldev
*dev
, const void *buffer
,
911 size_t count
, u16 offset
, u8 reg_width
)
913 ssb_block_write(dev
->sdev
, buffer
, count
, offset
, reg_width
);
916 static inline bool b43_using_pio_transfers(struct b43_wldev
*dev
)
918 return dev
->__using_pio_transfers
;
921 #ifdef CONFIG_B43_FORCE_PIO
922 # define B43_PIO_DEFAULT 1
924 # define B43_PIO_DEFAULT 0
927 /* Message printing */
928 void b43info(struct b43_wl
*wl
, const char *fmt
, ...)
929 __attribute__ ((format(printf
, 2, 3)));
930 void b43err(struct b43_wl
*wl
, const char *fmt
, ...)
931 __attribute__ ((format(printf
, 2, 3)));
932 void b43warn(struct b43_wl
*wl
, const char *fmt
, ...)
933 __attribute__ ((format(printf
, 2, 3)));
934 void b43dbg(struct b43_wl
*wl
, const char *fmt
, ...)
935 __attribute__ ((format(printf
, 2, 3)));
938 /* A WARN_ON variant that vanishes when b43 debugging is disabled.
939 * This _also_ evaluates the arg with debugging disabled. */
941 # define B43_WARN_ON(x) WARN_ON(x)
943 static inline bool __b43_warn_on_dummy(bool x
) { return x
; }
944 # define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
947 /* Convert an integer to a Q5.2 value */
948 #define INT_TO_Q52(i) ((i) << 2)
949 /* Convert a Q5.2 value to an integer (precision loss!) */
950 #define Q52_TO_INT(q52) ((q52) >> 2)
951 /* Macros for printing a value in Q5.2 format */
952 #define Q52_FMT "%u.%u"
953 #define Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)