1 /*****************************************************************************
5 * $Date: 2005/06/22 01:08:36 $ *
7 * Various subroutines (intr,pio,etc.) used by Chelsio 10G Ethernet driver. *
8 * part of the Chelsio 10Gb Ethernet Driver. *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License, version 2, as *
12 * published by the Free Software Foundation. *
14 * You should have received a copy of the GNU General Public License along *
15 * with this program; if not, write to the Free Software Foundation, Inc., *
16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
19 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
22 * http://www.chelsio.com *
24 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
25 * All rights reserved. *
27 * Maintainers: maintainers@chelsio.com *
29 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
30 * Tina Yang <tainay@chelsio.com> *
31 * Felix Marti <felix@chelsio.com> *
32 * Scott Bardone <sbardone@chelsio.com> *
33 * Kurt Ottaway <kottaway@chelsio.com> *
34 * Frank DiMambro <frank@chelsio.com> *
38 ****************************************************************************/
50 * t1_wait_op_done - wait until an operation is completed
51 * @adapter: the adapter performing the operation
52 * @reg: the register to check for completion
53 * @mask: a single-bit field within @reg that indicates completion
54 * @polarity: the value of the field when the operation is completed
55 * @attempts: number of check iterations
56 * @delay: delay in usecs between iterations
58 * Wait until an operation is completed by checking a bit in a register
59 * up to @attempts times. Returns %0 if the operation completes and %1
62 static int t1_wait_op_done(adapter_t
*adapter
, int reg
, u32 mask
, int polarity
,
63 int attempts
, int delay
)
66 u32 val
= readl(adapter
->regs
+ reg
) & mask
;
68 if (!!val
== polarity
)
77 #define TPI_ATTEMPTS 50
80 * Write a register over the TPI interface (unlocked and locked versions).
82 int __t1_tpi_write(adapter_t
*adapter
, u32 addr
, u32 value
)
86 writel(addr
, adapter
->regs
+ A_TPI_ADDR
);
87 writel(value
, adapter
->regs
+ A_TPI_WR_DATA
);
88 writel(F_TPIWR
, adapter
->regs
+ A_TPI_CSR
);
90 tpi_busy
= t1_wait_op_done(adapter
, A_TPI_CSR
, F_TPIRDY
, 1,
93 pr_alert("%s: TPI write to 0x%x failed\n",
98 int t1_tpi_write(adapter_t
*adapter
, u32 addr
, u32 value
)
102 spin_lock(&adapter
->tpi_lock
);
103 ret
= __t1_tpi_write(adapter
, addr
, value
);
104 spin_unlock(&adapter
->tpi_lock
);
109 * Read a register over the TPI interface (unlocked and locked versions).
111 int __t1_tpi_read(adapter_t
*adapter
, u32 addr
, u32
*valp
)
115 writel(addr
, adapter
->regs
+ A_TPI_ADDR
);
116 writel(0, adapter
->regs
+ A_TPI_CSR
);
118 tpi_busy
= t1_wait_op_done(adapter
, A_TPI_CSR
, F_TPIRDY
, 1,
121 pr_alert("%s: TPI read from 0x%x failed\n",
122 adapter
->name
, addr
);
124 *valp
= readl(adapter
->regs
+ A_TPI_RD_DATA
);
128 int t1_tpi_read(adapter_t
*adapter
, u32 addr
, u32
*valp
)
132 spin_lock(&adapter
->tpi_lock
);
133 ret
= __t1_tpi_read(adapter
, addr
, valp
);
134 spin_unlock(&adapter
->tpi_lock
);
139 * Set a TPI parameter.
141 static void t1_tpi_par(adapter_t
*adapter
, u32 value
)
143 writel(V_TPIPAR(value
), adapter
->regs
+ A_TPI_PAR
);
147 * Called when a port's link settings change to propagate the new values to the
148 * associated PHY and MAC. After performing the common tasks it invokes an
149 * OS-specific handler.
151 void t1_link_changed(adapter_t
*adapter
, int port_id
)
153 int link_ok
, speed
, duplex
, fc
;
154 struct cphy
*phy
= adapter
->port
[port_id
].phy
;
155 struct link_config
*lc
= &adapter
->port
[port_id
].link_config
;
157 phy
->ops
->get_link_status(phy
, &link_ok
, &speed
, &duplex
, &fc
);
159 lc
->speed
= speed
< 0 ? SPEED_INVALID
: speed
;
160 lc
->duplex
= duplex
< 0 ? DUPLEX_INVALID
: duplex
;
161 if (!(lc
->requested_fc
& PAUSE_AUTONEG
))
162 fc
= lc
->requested_fc
& (PAUSE_RX
| PAUSE_TX
);
164 if (link_ok
&& speed
>= 0 && lc
->autoneg
== AUTONEG_ENABLE
) {
165 /* Set MAC speed, duplex, and flow control to match PHY. */
166 struct cmac
*mac
= adapter
->port
[port_id
].mac
;
168 mac
->ops
->set_speed_duplex_fc(mac
, speed
, duplex
, fc
);
169 lc
->fc
= (unsigned char)fc
;
171 t1_link_negotiated(adapter
, port_id
, link_ok
, speed
, duplex
, fc
);
174 static int t1_pci_intr_handler(adapter_t
*adapter
)
178 pci_read_config_dword(adapter
->pdev
, A_PCICFG_INTR_CAUSE
, &pcix_cause
);
181 pci_write_config_dword(adapter
->pdev
, A_PCICFG_INTR_CAUSE
,
183 t1_fatal_err(adapter
); /* PCI errors are fatal */
188 #ifdef CONFIG_CHELSIO_T1_1G
189 #include "fpga_defs.h"
192 * PHY interrupt handler for FPGA boards.
194 static int fpga_phy_intr_handler(adapter_t
*adapter
)
197 u32 cause
= readl(adapter
->regs
+ FPGA_GMAC_ADDR_INTERRUPT_CAUSE
);
199 for_each_port(adapter
, p
)
200 if (cause
& (1 << p
)) {
201 struct cphy
*phy
= adapter
->port
[p
].phy
;
202 int phy_cause
= phy
->ops
->interrupt_handler(phy
);
204 if (phy_cause
& cphy_cause_link_change
)
205 t1_link_changed(adapter
, p
);
207 writel(cause
, adapter
->regs
+ FPGA_GMAC_ADDR_INTERRUPT_CAUSE
);
212 * Slow path interrupt handler for FPGAs.
214 static int fpga_slow_intr(adapter_t
*adapter
)
216 u32 cause
= readl(adapter
->regs
+ A_PL_CAUSE
);
218 cause
&= ~F_PL_INTR_SGE_DATA
;
219 if (cause
& F_PL_INTR_SGE_ERR
)
220 t1_sge_intr_error_handler(adapter
->sge
);
222 if (cause
& FPGA_PCIX_INTERRUPT_GMAC
)
223 fpga_phy_intr_handler(adapter
);
225 if (cause
& FPGA_PCIX_INTERRUPT_TP
) {
227 * FPGA doesn't support MC4 interrupts and it requires
228 * this odd layer of indirection for MC5.
230 u32 tp_cause
= readl(adapter
->regs
+ FPGA_TP_ADDR_INTERRUPT_CAUSE
);
232 /* Clear TP interrupt */
233 writel(tp_cause
, adapter
->regs
+ FPGA_TP_ADDR_INTERRUPT_CAUSE
);
235 if (cause
& FPGA_PCIX_INTERRUPT_PCIX
)
236 t1_pci_intr_handler(adapter
);
238 /* Clear the interrupts just processed. */
240 writel(cause
, adapter
->regs
+ A_PL_CAUSE
);
247 * Wait until Elmer's MI1 interface is ready for new operations.
249 static int mi1_wait_until_ready(adapter_t
*adapter
, int mi1_reg
)
251 int attempts
= 100, busy
;
256 __t1_tpi_read(adapter
, mi1_reg
, &val
);
257 busy
= val
& F_MI1_OP_BUSY
;
260 } while (busy
&& --attempts
);
262 pr_alert("%s: MDIO operation timed out\n", adapter
->name
);
267 * MI1 MDIO initialization.
269 static void mi1_mdio_init(adapter_t
*adapter
, const struct board_info
*bi
)
271 u32 clkdiv
= bi
->clock_elmer0
/ (2 * bi
->mdio_mdc
) - 1;
272 u32 val
= F_MI1_PREAMBLE_ENABLE
| V_MI1_MDI_INVERT(bi
->mdio_mdiinv
) |
273 V_MI1_MDI_ENABLE(bi
->mdio_mdien
) | V_MI1_CLK_DIV(clkdiv
);
275 if (!(bi
->caps
& SUPPORTED_10000baseT_Full
))
277 t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_CFG
, val
);
280 #if defined(CONFIG_CHELSIO_T1_1G)
282 * Elmer MI1 MDIO read/write operations.
284 static int mi1_mdio_read(struct net_device
*dev
, int phy_addr
, int mmd_addr
,
287 struct adapter
*adapter
= dev
->ml_priv
;
288 u32 addr
= V_MI1_REG_ADDR(reg_addr
) | V_MI1_PHY_ADDR(phy_addr
);
291 spin_lock(&adapter
->tpi_lock
);
292 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_ADDR
, addr
);
293 __t1_tpi_write(adapter
,
294 A_ELMER0_PORT0_MI1_OP
, MI1_OP_DIRECT_READ
);
295 mi1_wait_until_ready(adapter
, A_ELMER0_PORT0_MI1_OP
);
296 __t1_tpi_read(adapter
, A_ELMER0_PORT0_MI1_DATA
, &val
);
297 spin_unlock(&adapter
->tpi_lock
);
301 static int mi1_mdio_write(struct net_device
*dev
, int phy_addr
, int mmd_addr
,
302 u16 reg_addr
, u16 val
)
304 struct adapter
*adapter
= dev
->ml_priv
;
305 u32 addr
= V_MI1_REG_ADDR(reg_addr
) | V_MI1_PHY_ADDR(phy_addr
);
307 spin_lock(&adapter
->tpi_lock
);
308 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_ADDR
, addr
);
309 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_DATA
, val
);
310 __t1_tpi_write(adapter
,
311 A_ELMER0_PORT0_MI1_OP
, MI1_OP_DIRECT_WRITE
);
312 mi1_wait_until_ready(adapter
, A_ELMER0_PORT0_MI1_OP
);
313 spin_unlock(&adapter
->tpi_lock
);
317 #if defined(CONFIG_CHELSIO_T1_1G)
318 static const struct mdio_ops mi1_mdio_ops
= {
319 .init
= mi1_mdio_init
,
320 .read
= mi1_mdio_read
,
321 .write
= mi1_mdio_write
,
322 .mode_support
= MDIO_SUPPORTS_C22
328 static int mi1_mdio_ext_read(struct net_device
*dev
, int phy_addr
, int mmd_addr
,
331 struct adapter
*adapter
= dev
->ml_priv
;
332 u32 addr
= V_MI1_REG_ADDR(mmd_addr
) | V_MI1_PHY_ADDR(phy_addr
);
335 spin_lock(&adapter
->tpi_lock
);
337 /* Write the address we want. */
338 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_ADDR
, addr
);
339 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_DATA
, reg_addr
);
340 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_OP
,
341 MI1_OP_INDIRECT_ADDRESS
);
342 mi1_wait_until_ready(adapter
, A_ELMER0_PORT0_MI1_OP
);
344 /* Write the operation we want. */
345 __t1_tpi_write(adapter
,
346 A_ELMER0_PORT0_MI1_OP
, MI1_OP_INDIRECT_READ
);
347 mi1_wait_until_ready(adapter
, A_ELMER0_PORT0_MI1_OP
);
350 __t1_tpi_read(adapter
, A_ELMER0_PORT0_MI1_DATA
, &val
);
351 spin_unlock(&adapter
->tpi_lock
);
355 static int mi1_mdio_ext_write(struct net_device
*dev
, int phy_addr
,
356 int mmd_addr
, u16 reg_addr
, u16 val
)
358 struct adapter
*adapter
= dev
->ml_priv
;
359 u32 addr
= V_MI1_REG_ADDR(mmd_addr
) | V_MI1_PHY_ADDR(phy_addr
);
361 spin_lock(&adapter
->tpi_lock
);
363 /* Write the address we want. */
364 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_ADDR
, addr
);
365 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_DATA
, reg_addr
);
366 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_OP
,
367 MI1_OP_INDIRECT_ADDRESS
);
368 mi1_wait_until_ready(adapter
, A_ELMER0_PORT0_MI1_OP
);
370 /* Write the data. */
371 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_DATA
, val
);
372 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_OP
, MI1_OP_INDIRECT_WRITE
);
373 mi1_wait_until_ready(adapter
, A_ELMER0_PORT0_MI1_OP
);
374 spin_unlock(&adapter
->tpi_lock
);
378 static const struct mdio_ops mi1_mdio_ext_ops
= {
379 .init
= mi1_mdio_init
,
380 .read
= mi1_mdio_ext_read
,
381 .write
= mi1_mdio_ext_write
,
382 .mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
394 static const struct board_info t1_board
[] = {
396 .board
= CHBT_BOARD_CHT110
,
398 .caps
= SUPPORTED_10000baseT_Full
,
399 .chip_term
= CHBT_TERM_T1
,
400 .chip_mac
= CHBT_MAC_PM3393
,
401 .chip_phy
= CHBT_PHY_MY3126
,
402 .clock_core
= 125000000,
403 .clock_mc3
= 150000000,
404 .clock_mc4
= 125000000,
410 .mdio_phybaseaddr
= 1,
411 .gmac
= &t1_pm3393_ops
,
412 .gphy
= &t1_my3126_ops
,
413 .mdio_ops
= &mi1_mdio_ext_ops
,
414 .desc
= "Chelsio T110 1x10GBase-CX4 TOE",
418 .board
= CHBT_BOARD_N110
,
420 .caps
= SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
,
421 .chip_term
= CHBT_TERM_T1
,
422 .chip_mac
= CHBT_MAC_PM3393
,
423 .chip_phy
= CHBT_PHY_88X2010
,
424 .clock_core
= 125000000,
430 .mdio_phybaseaddr
= 0,
431 .gmac
= &t1_pm3393_ops
,
432 .gphy
= &t1_mv88x201x_ops
,
433 .mdio_ops
= &mi1_mdio_ext_ops
,
434 .desc
= "Chelsio N110 1x10GBaseX NIC",
438 .board
= CHBT_BOARD_N210
,
440 .caps
= SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
,
441 .chip_term
= CHBT_TERM_T2
,
442 .chip_mac
= CHBT_MAC_PM3393
,
443 .chip_phy
= CHBT_PHY_88X2010
,
444 .clock_core
= 125000000,
450 .mdio_phybaseaddr
= 0,
451 .gmac
= &t1_pm3393_ops
,
452 .gphy
= &t1_mv88x201x_ops
,
453 .mdio_ops
= &mi1_mdio_ext_ops
,
454 .desc
= "Chelsio N210 1x10GBaseX NIC",
458 .board
= CHBT_BOARD_CHT210
,
460 .caps
= SUPPORTED_10000baseT_Full
,
461 .chip_term
= CHBT_TERM_T2
,
462 .chip_mac
= CHBT_MAC_PM3393
,
463 .chip_phy
= CHBT_PHY_88X2010
,
464 .clock_core
= 125000000,
465 .clock_mc3
= 133000000,
466 .clock_mc4
= 125000000,
472 .mdio_phybaseaddr
= 0,
473 .gmac
= &t1_pm3393_ops
,
474 .gphy
= &t1_mv88x201x_ops
,
475 .mdio_ops
= &mi1_mdio_ext_ops
,
476 .desc
= "Chelsio T210 1x10GBaseX TOE",
480 .board
= CHBT_BOARD_CHT210
,
482 .caps
= SUPPORTED_10000baseT_Full
,
483 .chip_term
= CHBT_TERM_T2
,
484 .chip_mac
= CHBT_MAC_PM3393
,
485 .chip_phy
= CHBT_PHY_MY3126
,
486 .clock_core
= 125000000,
487 .clock_mc3
= 133000000,
488 .clock_mc4
= 125000000,
494 .mdio_phybaseaddr
= 1,
495 .gmac
= &t1_pm3393_ops
,
496 .gphy
= &t1_my3126_ops
,
497 .mdio_ops
= &mi1_mdio_ext_ops
,
498 .desc
= "Chelsio T210 1x10GBase-CX4 TOE",
501 #ifdef CONFIG_CHELSIO_T1_1G
503 .board
= CHBT_BOARD_CHN204
,
505 .caps
= SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
506 | SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
507 | SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
|
508 SUPPORTED_PAUSE
| SUPPORTED_TP
,
509 .chip_term
= CHBT_TERM_T2
,
510 .chip_mac
= CHBT_MAC_VSC7321
,
511 .chip_phy
= CHBT_PHY_88E1111
,
512 .clock_core
= 100000000,
518 .mdio_phybaseaddr
= 4,
519 .gmac
= &t1_vsc7326_ops
,
520 .gphy
= &t1_mv88e1xxx_ops
,
521 .mdio_ops
= &mi1_mdio_ops
,
522 .desc
= "Chelsio N204 4x100/1000BaseT NIC",
528 DEFINE_PCI_DEVICE_TABLE(t1_pci_tbl
) = {
529 CH_DEVICE(8, 0, CH_BRD_T110_1CU
),
530 CH_DEVICE(8, 1, CH_BRD_T110_1CU
),
531 CH_DEVICE(7, 0, CH_BRD_N110_1F
),
532 CH_DEVICE(10, 1, CH_BRD_N210_1F
),
533 CH_DEVICE(11, 1, CH_BRD_T210_1F
),
534 CH_DEVICE(14, 1, CH_BRD_T210_1CU
),
535 CH_DEVICE(16, 1, CH_BRD_N204_4CU
),
539 MODULE_DEVICE_TABLE(pci
, t1_pci_tbl
);
542 * Return the board_info structure with a given index. Out-of-range indices
545 const struct board_info
*t1_get_board_info(unsigned int board_id
)
547 return board_id
< ARRAY_SIZE(t1_board
) ? &t1_board
[board_id
] : NULL
;
550 struct chelsio_vpd_t
{
552 u8 serial_number
[16];
553 u8 mac_base_address
[6];
554 u8 pad
[2]; /* make multiple-of-4 size requirement explicit */
557 #define EEPROMSIZE (8 * 1024)
558 #define EEPROM_MAX_POLL 4
561 * Read SEEPROM. A zero is written to the flag register when the addres is
562 * written to the Control register. The hardware device will set the flag to a
563 * one when 4B have been transferred to the Data register.
565 int t1_seeprom_read(adapter_t
*adapter
, u32 addr
, __le32
*data
)
567 int i
= EEPROM_MAX_POLL
;
571 if (addr
>= EEPROMSIZE
|| (addr
& 3))
574 pci_write_config_word(adapter
->pdev
, A_PCICFG_VPD_ADDR
, (u16
)addr
);
577 pci_read_config_word(adapter
->pdev
, A_PCICFG_VPD_ADDR
, &val
);
578 } while (!(val
& F_VPD_OP_FLAG
) && --i
);
580 if (!(val
& F_VPD_OP_FLAG
)) {
581 pr_err("%s: reading EEPROM address 0x%x failed\n",
582 adapter
->name
, addr
);
585 pci_read_config_dword(adapter
->pdev
, A_PCICFG_VPD_DATA
, &v
);
586 *data
= cpu_to_le32(v
);
590 static int t1_eeprom_vpd_get(adapter_t
*adapter
, struct chelsio_vpd_t
*vpd
)
594 for (addr
= 0; !ret
&& addr
< sizeof(*vpd
); addr
+= sizeof(u32
))
595 ret
= t1_seeprom_read(adapter
, addr
,
596 (__le32
*)((u8
*)vpd
+ addr
));
602 * Read a port's MAC address from the VPD ROM.
604 static int vpd_macaddress_get(adapter_t
*adapter
, int index
, u8 mac_addr
[])
606 struct chelsio_vpd_t vpd
;
608 if (t1_eeprom_vpd_get(adapter
, &vpd
))
610 memcpy(mac_addr
, vpd
.mac_base_address
, 5);
611 mac_addr
[5] = vpd
.mac_base_address
[5] + index
;
616 * Set up the MAC/PHY according to the requested link settings.
618 * If the PHY can auto-negotiate first decide what to advertise, then
619 * enable/disable auto-negotiation as desired and reset.
621 * If the PHY does not auto-negotiate we just reset it.
623 * If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
624 * otherwise do it later based on the outcome of auto-negotiation.
626 int t1_link_start(struct cphy
*phy
, struct cmac
*mac
, struct link_config
*lc
)
628 unsigned int fc
= lc
->requested_fc
& (PAUSE_RX
| PAUSE_TX
);
630 if (lc
->supported
& SUPPORTED_Autoneg
) {
631 lc
->advertising
&= ~(ADVERTISED_ASYM_PAUSE
| ADVERTISED_PAUSE
);
633 if (fc
== ((PAUSE_RX
| PAUSE_TX
) &
634 (mac
->adapter
->params
.nports
< 2)))
635 lc
->advertising
|= ADVERTISED_PAUSE
;
637 lc
->advertising
|= ADVERTISED_ASYM_PAUSE
;
639 lc
->advertising
|= ADVERTISED_PAUSE
;
642 phy
->ops
->advertise(phy
, lc
->advertising
);
644 if (lc
->autoneg
== AUTONEG_DISABLE
) {
645 lc
->speed
= lc
->requested_speed
;
646 lc
->duplex
= lc
->requested_duplex
;
647 lc
->fc
= (unsigned char)fc
;
648 mac
->ops
->set_speed_duplex_fc(mac
, lc
->speed
,
650 /* Also disables autoneg */
651 phy
->state
= PHY_AUTONEG_RDY
;
652 phy
->ops
->set_speed_duplex(phy
, lc
->speed
, lc
->duplex
);
653 phy
->ops
->reset(phy
, 0);
655 phy
->state
= PHY_AUTONEG_EN
;
656 phy
->ops
->autoneg_enable(phy
); /* also resets PHY */
659 phy
->state
= PHY_AUTONEG_RDY
;
660 mac
->ops
->set_speed_duplex_fc(mac
, -1, -1, fc
);
661 lc
->fc
= (unsigned char)fc
;
662 phy
->ops
->reset(phy
, 0);
668 * External interrupt handler for boards using elmer0.
670 int t1_elmer0_ext_intr_handler(adapter_t
*adapter
)
676 t1_tpi_read(adapter
, A_ELMER0_INT_CAUSE
, &cause
);
678 switch (board_info(adapter
)->board
) {
679 #ifdef CONFIG_CHELSIO_T1_1G
680 case CHBT_BOARD_CHT204
:
681 case CHBT_BOARD_CHT204E
:
682 case CHBT_BOARD_CHN204
:
683 case CHBT_BOARD_CHT204V
: {
685 for_each_port(adapter
, i
) {
687 if (!(cause
& (1 << port_bit
)))
690 phy
= adapter
->port
[i
].phy
;
691 phy_cause
= phy
->ops
->interrupt_handler(phy
);
692 if (phy_cause
& cphy_cause_link_change
)
693 t1_link_changed(adapter
, i
);
697 case CHBT_BOARD_CHT101
:
698 if (cause
& ELMER0_GP_BIT1
) { /* Marvell 88E1111 interrupt */
699 phy
= adapter
->port
[0].phy
;
700 phy_cause
= phy
->ops
->interrupt_handler(phy
);
701 if (phy_cause
& cphy_cause_link_change
)
702 t1_link_changed(adapter
, 0);
705 case CHBT_BOARD_7500
: {
708 * Elmer0's interrupt cause isn't useful here because there is
709 * only one bit that can be set for all 4 ports. This means
710 * we are forced to check every PHY's interrupt status
711 * register to see who initiated the interrupt.
713 for_each_port(adapter
, p
) {
714 phy
= adapter
->port
[p
].phy
;
715 phy_cause
= phy
->ops
->interrupt_handler(phy
);
716 if (phy_cause
& cphy_cause_link_change
)
717 t1_link_changed(adapter
, p
);
722 case CHBT_BOARD_CHT210
:
723 case CHBT_BOARD_N210
:
724 case CHBT_BOARD_N110
:
725 if (cause
& ELMER0_GP_BIT6
) { /* Marvell 88x2010 interrupt */
726 phy
= adapter
->port
[0].phy
;
727 phy_cause
= phy
->ops
->interrupt_handler(phy
);
728 if (phy_cause
& cphy_cause_link_change
)
729 t1_link_changed(adapter
, 0);
732 case CHBT_BOARD_8000
:
733 case CHBT_BOARD_CHT110
:
734 if (netif_msg_intr(adapter
))
735 dev_dbg(&adapter
->pdev
->dev
,
736 "External interrupt cause 0x%x\n", cause
);
737 if (cause
& ELMER0_GP_BIT1
) { /* PMC3393 INTB */
738 struct cmac
*mac
= adapter
->port
[0].mac
;
740 mac
->ops
->interrupt_handler(mac
);
742 if (cause
& ELMER0_GP_BIT5
) { /* XPAK MOD_DETECT */
746 A_ELMER0_GPI_STAT
, &mod_detect
);
747 if (netif_msg_link(adapter
))
748 dev_info(&adapter
->pdev
->dev
, "XPAK %s\n",
749 mod_detect
? "removed" : "inserted");
753 t1_tpi_write(adapter
, A_ELMER0_INT_CAUSE
, cause
);
757 /* Enables all interrupts. */
758 void t1_interrupts_enable(adapter_t
*adapter
)
762 adapter
->slow_intr_mask
= F_PL_INTR_SGE_ERR
| F_PL_INTR_TP
;
764 t1_sge_intr_enable(adapter
->sge
);
765 t1_tp_intr_enable(adapter
->tp
);
767 adapter
->slow_intr_mask
|= F_PL_INTR_ESPI
;
768 t1_espi_intr_enable(adapter
->espi
);
771 /* Enable MAC/PHY interrupts for each port. */
772 for_each_port(adapter
, i
) {
773 adapter
->port
[i
].mac
->ops
->interrupt_enable(adapter
->port
[i
].mac
);
774 adapter
->port
[i
].phy
->ops
->interrupt_enable(adapter
->port
[i
].phy
);
777 /* Enable PCIX & external chip interrupts on ASIC boards. */
778 if (t1_is_asic(adapter
)) {
779 u32 pl_intr
= readl(adapter
->regs
+ A_PL_ENABLE
);
781 /* PCI-X interrupts */
782 pci_write_config_dword(adapter
->pdev
, A_PCICFG_INTR_ENABLE
,
785 adapter
->slow_intr_mask
|= F_PL_INTR_EXT
| F_PL_INTR_PCIX
;
786 pl_intr
|= F_PL_INTR_EXT
| F_PL_INTR_PCIX
;
787 writel(pl_intr
, adapter
->regs
+ A_PL_ENABLE
);
791 /* Disables all interrupts. */
792 void t1_interrupts_disable(adapter_t
* adapter
)
796 t1_sge_intr_disable(adapter
->sge
);
797 t1_tp_intr_disable(adapter
->tp
);
799 t1_espi_intr_disable(adapter
->espi
);
801 /* Disable MAC/PHY interrupts for each port. */
802 for_each_port(adapter
, i
) {
803 adapter
->port
[i
].mac
->ops
->interrupt_disable(adapter
->port
[i
].mac
);
804 adapter
->port
[i
].phy
->ops
->interrupt_disable(adapter
->port
[i
].phy
);
807 /* Disable PCIX & external chip interrupts. */
808 if (t1_is_asic(adapter
))
809 writel(0, adapter
->regs
+ A_PL_ENABLE
);
811 /* PCI-X interrupts */
812 pci_write_config_dword(adapter
->pdev
, A_PCICFG_INTR_ENABLE
, 0);
814 adapter
->slow_intr_mask
= 0;
817 /* Clears all interrupts */
818 void t1_interrupts_clear(adapter_t
* adapter
)
822 t1_sge_intr_clear(adapter
->sge
);
823 t1_tp_intr_clear(adapter
->tp
);
825 t1_espi_intr_clear(adapter
->espi
);
827 /* Clear MAC/PHY interrupts for each port. */
828 for_each_port(adapter
, i
) {
829 adapter
->port
[i
].mac
->ops
->interrupt_clear(adapter
->port
[i
].mac
);
830 adapter
->port
[i
].phy
->ops
->interrupt_clear(adapter
->port
[i
].phy
);
833 /* Enable interrupts for external devices. */
834 if (t1_is_asic(adapter
)) {
835 u32 pl_intr
= readl(adapter
->regs
+ A_PL_CAUSE
);
837 writel(pl_intr
| F_PL_INTR_EXT
| F_PL_INTR_PCIX
,
838 adapter
->regs
+ A_PL_CAUSE
);
841 /* PCI-X interrupts */
842 pci_write_config_dword(adapter
->pdev
, A_PCICFG_INTR_CAUSE
, 0xffffffff);
846 * Slow path interrupt handler for ASICs.
848 static int asic_slow_intr(adapter_t
*adapter
)
850 u32 cause
= readl(adapter
->regs
+ A_PL_CAUSE
);
852 cause
&= adapter
->slow_intr_mask
;
855 if (cause
& F_PL_INTR_SGE_ERR
)
856 t1_sge_intr_error_handler(adapter
->sge
);
857 if (cause
& F_PL_INTR_TP
)
858 t1_tp_intr_handler(adapter
->tp
);
859 if (cause
& F_PL_INTR_ESPI
)
860 t1_espi_intr_handler(adapter
->espi
);
861 if (cause
& F_PL_INTR_PCIX
)
862 t1_pci_intr_handler(adapter
);
863 if (cause
& F_PL_INTR_EXT
)
864 t1_elmer0_ext_intr(adapter
);
866 /* Clear the interrupts just processed. */
867 writel(cause
, adapter
->regs
+ A_PL_CAUSE
);
868 readl(adapter
->regs
+ A_PL_CAUSE
); /* flush writes */
872 int t1_slow_intr_handler(adapter_t
*adapter
)
874 #ifdef CONFIG_CHELSIO_T1_1G
875 if (!t1_is_asic(adapter
))
876 return fpga_slow_intr(adapter
);
878 return asic_slow_intr(adapter
);
881 /* Power sequencing is a work-around for Intel's XPAKs. */
882 static void power_sequence_xpak(adapter_t
* adapter
)
888 t1_tpi_read(adapter
, A_ELMER0_GPI_STAT
, &mod_detect
);
889 if (!(ELMER0_GP_BIT5
& mod_detect
)) {
890 /* XPAK is present */
891 t1_tpi_read(adapter
, A_ELMER0_GPO
, &gpo
);
892 gpo
|= ELMER0_GP_BIT18
;
893 t1_tpi_write(adapter
, A_ELMER0_GPO
, gpo
);
897 int __devinit
t1_get_board_rev(adapter_t
*adapter
, const struct board_info
*bi
,
898 struct adapter_params
*p
)
900 p
->chip_version
= bi
->chip_term
;
901 p
->is_asic
= (p
->chip_version
!= CHBT_TERM_FPGA
);
902 if (p
->chip_version
== CHBT_TERM_T1
||
903 p
->chip_version
== CHBT_TERM_T2
||
904 p
->chip_version
== CHBT_TERM_FPGA
) {
905 u32 val
= readl(adapter
->regs
+ A_TP_PC_CONFIG
);
907 val
= G_TP_PC_REV(val
);
909 p
->chip_revision
= TERM_T1B
;
911 p
->chip_revision
= TERM_T2
;
920 * Enable board components other than the Chelsio chip, such as external MAC
923 static int board_init(adapter_t
*adapter
, const struct board_info
*bi
)
926 case CHBT_BOARD_8000
:
927 case CHBT_BOARD_N110
:
928 case CHBT_BOARD_N210
:
929 case CHBT_BOARD_CHT210
:
930 t1_tpi_par(adapter
, 0xf);
931 t1_tpi_write(adapter
, A_ELMER0_GPO
, 0x800);
933 case CHBT_BOARD_CHT110
:
934 t1_tpi_par(adapter
, 0xf);
935 t1_tpi_write(adapter
, A_ELMER0_GPO
, 0x1800);
937 /* TBD XXX Might not need. This fixes a problem
938 * described in the Intel SR XPAK errata.
940 power_sequence_xpak(adapter
);
942 #ifdef CONFIG_CHELSIO_T1_1G
943 case CHBT_BOARD_CHT204E
:
944 /* add config space write here */
945 case CHBT_BOARD_CHT204
:
946 case CHBT_BOARD_CHT204V
:
947 case CHBT_BOARD_CHN204
:
948 t1_tpi_par(adapter
, 0xf);
949 t1_tpi_write(adapter
, A_ELMER0_GPO
, 0x804);
951 case CHBT_BOARD_CHT101
:
952 case CHBT_BOARD_7500
:
953 t1_tpi_par(adapter
, 0xf);
954 t1_tpi_write(adapter
, A_ELMER0_GPO
, 0x1804);
962 * Initialize and configure the Terminator HW modules. Note that external
963 * MAC and PHYs are initialized separately.
965 int t1_init_hw_modules(adapter_t
*adapter
)
968 const struct board_info
*bi
= board_info(adapter
);
970 if (!bi
->clock_mc4
) {
971 u32 val
= readl(adapter
->regs
+ A_MC4_CFG
);
973 writel(val
| F_READY
| F_MC4_SLOW
, adapter
->regs
+ A_MC4_CFG
);
974 writel(F_M_BUS_ENABLE
| F_TCAM_RESET
,
975 adapter
->regs
+ A_MC5_CONFIG
);
978 if (adapter
->espi
&& t1_espi_init(adapter
->espi
, bi
->chip_mac
,
982 if (t1_tp_reset(adapter
->tp
, &adapter
->params
.tp
, bi
->clock_core
))
985 err
= t1_sge_configure(adapter
->sge
, &adapter
->params
.sge
);
995 * Determine a card's PCI mode.
997 static void __devinit
get_pci_mode(adapter_t
*adapter
, struct chelsio_pci_params
*p
)
999 static const unsigned short speed_map
[] = { 33, 66, 100, 133 };
1002 pci_read_config_dword(adapter
->pdev
, A_PCICFG_MODE
, &pci_mode
);
1003 p
->speed
= speed_map
[G_PCI_MODE_CLK(pci_mode
)];
1004 p
->width
= (pci_mode
& F_PCI_MODE_64BIT
) ? 64 : 32;
1005 p
->is_pcix
= (pci_mode
& F_PCI_MODE_PCIX
) != 0;
1009 * Release the structures holding the SW per-Terminator-HW-module state.
1011 void t1_free_sw_modules(adapter_t
*adapter
)
1015 for_each_port(adapter
, i
) {
1016 struct cmac
*mac
= adapter
->port
[i
].mac
;
1017 struct cphy
*phy
= adapter
->port
[i
].phy
;
1020 mac
->ops
->destroy(mac
);
1022 phy
->ops
->destroy(phy
);
1026 t1_sge_destroy(adapter
->sge
);
1028 t1_tp_destroy(adapter
->tp
);
1030 t1_espi_destroy(adapter
->espi
);
1033 static void __devinit
init_link_config(struct link_config
*lc
,
1034 const struct board_info
*bi
)
1036 lc
->supported
= bi
->caps
;
1037 lc
->requested_speed
= lc
->speed
= SPEED_INVALID
;
1038 lc
->requested_duplex
= lc
->duplex
= DUPLEX_INVALID
;
1039 lc
->requested_fc
= lc
->fc
= PAUSE_RX
| PAUSE_TX
;
1040 if (lc
->supported
& SUPPORTED_Autoneg
) {
1041 lc
->advertising
= lc
->supported
;
1042 lc
->autoneg
= AUTONEG_ENABLE
;
1043 lc
->requested_fc
|= PAUSE_AUTONEG
;
1045 lc
->advertising
= 0;
1046 lc
->autoneg
= AUTONEG_DISABLE
;
1051 * Allocate and initialize the data structures that hold the SW state of
1052 * the Terminator HW modules.
1054 int __devinit
t1_init_sw_modules(adapter_t
*adapter
,
1055 const struct board_info
*bi
)
1059 adapter
->params
.brd_info
= bi
;
1060 adapter
->params
.nports
= bi
->port_number
;
1061 adapter
->params
.stats_update_period
= bi
->gmac
->stats_update_period
;
1063 adapter
->sge
= t1_sge_create(adapter
, &adapter
->params
.sge
);
1064 if (!adapter
->sge
) {
1065 pr_err("%s: SGE initialization failed\n",
1070 if (bi
->espi_nports
&& !(adapter
->espi
= t1_espi_create(adapter
))) {
1071 pr_err("%s: ESPI initialization failed\n",
1076 adapter
->tp
= t1_tp_create(adapter
, &adapter
->params
.tp
);
1078 pr_err("%s: TP initialization failed\n",
1083 board_init(adapter
, bi
);
1084 bi
->mdio_ops
->init(adapter
, bi
);
1085 if (bi
->gphy
->reset
)
1086 bi
->gphy
->reset(adapter
);
1087 if (bi
->gmac
->reset
)
1088 bi
->gmac
->reset(adapter
);
1090 for_each_port(adapter
, i
) {
1093 int phy_addr
= bi
->mdio_phybaseaddr
+ i
;
1095 adapter
->port
[i
].phy
= bi
->gphy
->create(adapter
->port
[i
].dev
,
1096 phy_addr
, bi
->mdio_ops
);
1097 if (!adapter
->port
[i
].phy
) {
1098 pr_err("%s: PHY %d initialization failed\n",
1103 adapter
->port
[i
].mac
= mac
= bi
->gmac
->create(adapter
, i
);
1105 pr_err("%s: MAC %d initialization failed\n",
1111 * Get the port's MAC addresses either from the EEPROM if one
1112 * exists or the one hardcoded in the MAC.
1114 if (!t1_is_asic(adapter
) || bi
->chip_mac
== CHBT_MAC_DUMMY
)
1115 mac
->ops
->macaddress_get(mac
, hw_addr
);
1116 else if (vpd_macaddress_get(adapter
, i
, hw_addr
)) {
1117 pr_err("%s: could not read MAC address from VPD ROM\n",
1118 adapter
->port
[i
].dev
->name
);
1121 memcpy(adapter
->port
[i
].dev
->dev_addr
, hw_addr
, ETH_ALEN
);
1122 init_link_config(&adapter
->port
[i
].link_config
, bi
);
1125 get_pci_mode(adapter
, &adapter
->params
.pci
);
1126 t1_interrupts_clear(adapter
);
1130 t1_free_sw_modules(adapter
);