2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/uv/uv_hub.h>
63 #include <asm/uv/uv_irq.h>
67 #define __apicdebuginit(type) static type __init
70 * Is the SiS APIC rmw bug present ?
71 * -1 = don't know, 0 = no, 1 = yes
73 int sis_apic_bug
= -1;
75 static DEFINE_SPINLOCK(ioapic_lock
);
76 static DEFINE_SPINLOCK(vector_lock
);
79 * # of IRQ routing registers
81 int nr_ioapic_registers
[MAX_IO_APICS
];
83 /* I/O APIC entries */
84 struct mpc_ioapic mp_ioapics
[MAX_IO_APICS
];
87 /* MP IRQ source entries */
88 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
90 /* # of MP IRQ source entries */
93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
94 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
97 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
99 int skip_ioapic_setup
;
101 void arch_disable_smp_support(void)
105 noioapicreroute
= -1;
107 skip_ioapic_setup
= 1;
110 static int __init
parse_noapic(char *str
)
112 /* disable IO-APIC */
113 arch_disable_smp_support();
116 early_param("noapic", parse_noapic
);
121 * This is performance-critical, we want to do it O(1)
123 * the indexing order of this array favors 1:1 mappings
124 * between pins and IRQs.
127 struct irq_pin_list
{
129 struct irq_pin_list
*next
;
132 static struct irq_pin_list
*get_one_free_irq_2_pin(int node
)
134 struct irq_pin_list
*pin
;
136 pin
= kzalloc_node(sizeof(*pin
), GFP_ATOMIC
, node
);
142 struct irq_pin_list
*irq_2_pin
;
143 cpumask_var_t domain
;
144 cpumask_var_t old_domain
;
145 unsigned move_cleanup_count
;
147 u8 move_in_progress
: 1;
150 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
151 #ifdef CONFIG_SPARSE_IRQ
152 static struct irq_cfg irq_cfgx
[] = {
154 static struct irq_cfg irq_cfgx
[NR_IRQS
] = {
156 [0] = { .vector
= IRQ0_VECTOR
, },
157 [1] = { .vector
= IRQ1_VECTOR
, },
158 [2] = { .vector
= IRQ2_VECTOR
, },
159 [3] = { .vector
= IRQ3_VECTOR
, },
160 [4] = { .vector
= IRQ4_VECTOR
, },
161 [5] = { .vector
= IRQ5_VECTOR
, },
162 [6] = { .vector
= IRQ6_VECTOR
, },
163 [7] = { .vector
= IRQ7_VECTOR
, },
164 [8] = { .vector
= IRQ8_VECTOR
, },
165 [9] = { .vector
= IRQ9_VECTOR
, },
166 [10] = { .vector
= IRQ10_VECTOR
, },
167 [11] = { .vector
= IRQ11_VECTOR
, },
168 [12] = { .vector
= IRQ12_VECTOR
, },
169 [13] = { .vector
= IRQ13_VECTOR
, },
170 [14] = { .vector
= IRQ14_VECTOR
, },
171 [15] = { .vector
= IRQ15_VECTOR
, },
174 int __init
arch_early_irq_init(void)
177 struct irq_desc
*desc
;
182 count
= ARRAY_SIZE(irq_cfgx
);
184 for (i
= 0; i
< count
; i
++) {
185 desc
= irq_to_desc(i
);
186 desc
->chip_data
= &cfg
[i
];
187 alloc_bootmem_cpumask_var(&cfg
[i
].domain
);
188 alloc_bootmem_cpumask_var(&cfg
[i
].old_domain
);
189 if (i
< NR_IRQS_LEGACY
)
190 cpumask_setall(cfg
[i
].domain
);
196 #ifdef CONFIG_SPARSE_IRQ
197 static struct irq_cfg
*irq_cfg(unsigned int irq
)
199 struct irq_cfg
*cfg
= NULL
;
200 struct irq_desc
*desc
;
202 desc
= irq_to_desc(irq
);
204 cfg
= desc
->chip_data
;
209 static struct irq_cfg
*get_one_free_irq_cfg(int node
)
213 cfg
= kzalloc_node(sizeof(*cfg
), GFP_ATOMIC
, node
);
215 if (!alloc_cpumask_var_node(&cfg
->domain
, GFP_ATOMIC
, node
)) {
218 } else if (!alloc_cpumask_var_node(&cfg
->old_domain
,
220 free_cpumask_var(cfg
->domain
);
224 cpumask_clear(cfg
->domain
);
225 cpumask_clear(cfg
->old_domain
);
232 int arch_init_chip_data(struct irq_desc
*desc
, int node
)
236 cfg
= desc
->chip_data
;
238 desc
->chip_data
= get_one_free_irq_cfg(node
);
239 if (!desc
->chip_data
) {
240 printk(KERN_ERR
"can not alloc irq_cfg\n");
248 /* for move_irq_desc */
250 init_copy_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
, int node
)
252 struct irq_pin_list
*old_entry
, *head
, *tail
, *entry
;
254 cfg
->irq_2_pin
= NULL
;
255 old_entry
= old_cfg
->irq_2_pin
;
259 entry
= get_one_free_irq_2_pin(node
);
263 entry
->apic
= old_entry
->apic
;
264 entry
->pin
= old_entry
->pin
;
267 old_entry
= old_entry
->next
;
269 entry
= get_one_free_irq_2_pin(node
);
277 /* still use the old one */
280 entry
->apic
= old_entry
->apic
;
281 entry
->pin
= old_entry
->pin
;
284 old_entry
= old_entry
->next
;
288 cfg
->irq_2_pin
= head
;
291 static void free_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
)
293 struct irq_pin_list
*entry
, *next
;
295 if (old_cfg
->irq_2_pin
== cfg
->irq_2_pin
)
298 entry
= old_cfg
->irq_2_pin
;
305 old_cfg
->irq_2_pin
= NULL
;
308 void arch_init_copy_chip_data(struct irq_desc
*old_desc
,
309 struct irq_desc
*desc
, int node
)
312 struct irq_cfg
*old_cfg
;
314 cfg
= get_one_free_irq_cfg(node
);
319 desc
->chip_data
= cfg
;
321 old_cfg
= old_desc
->chip_data
;
323 memcpy(cfg
, old_cfg
, sizeof(struct irq_cfg
));
325 init_copy_irq_2_pin(old_cfg
, cfg
, node
);
328 static void free_irq_cfg(struct irq_cfg
*old_cfg
)
333 void arch_free_chip_data(struct irq_desc
*old_desc
, struct irq_desc
*desc
)
335 struct irq_cfg
*old_cfg
, *cfg
;
337 old_cfg
= old_desc
->chip_data
;
338 cfg
= desc
->chip_data
;
344 free_irq_2_pin(old_cfg
, cfg
);
345 free_irq_cfg(old_cfg
);
346 old_desc
->chip_data
= NULL
;
349 /* end for move_irq_desc */
352 static struct irq_cfg
*irq_cfg(unsigned int irq
)
354 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
361 unsigned int unused
[3];
363 unsigned int unused2
[11];
367 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
369 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
370 + (mp_ioapics
[idx
].apicaddr
& ~PAGE_MASK
);
373 static inline void io_apic_eoi(unsigned int apic
, unsigned int vector
)
375 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
376 writel(vector
, &io_apic
->eoi
);
379 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
381 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
382 writel(reg
, &io_apic
->index
);
383 return readl(&io_apic
->data
);
386 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
388 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
389 writel(reg
, &io_apic
->index
);
390 writel(value
, &io_apic
->data
);
394 * Re-write a value: to be used for read-modify-write
395 * cycles where the read already set up the index register.
397 * Older SiS APIC requires we rewrite the index register
399 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
401 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
404 writel(reg
, &io_apic
->index
);
405 writel(value
, &io_apic
->data
);
408 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
410 struct irq_pin_list
*entry
;
413 spin_lock_irqsave(&ioapic_lock
, flags
);
414 entry
= cfg
->irq_2_pin
;
422 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
423 /* Is the remote IRR bit set? */
424 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
425 spin_unlock_irqrestore(&ioapic_lock
, flags
);
432 spin_unlock_irqrestore(&ioapic_lock
, flags
);
438 struct { u32 w1
, w2
; };
439 struct IO_APIC_route_entry entry
;
442 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
444 union entry_union eu
;
446 spin_lock_irqsave(&ioapic_lock
, flags
);
447 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
448 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
449 spin_unlock_irqrestore(&ioapic_lock
, flags
);
454 * When we write a new IO APIC routing entry, we need to write the high
455 * word first! If the mask bit in the low word is clear, we will enable
456 * the interrupt, and we need to make sure the entry is fully populated
457 * before that happens.
460 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
462 union entry_union eu
;
464 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
465 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
468 void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
471 spin_lock_irqsave(&ioapic_lock
, flags
);
472 __ioapic_write_entry(apic
, pin
, e
);
473 spin_unlock_irqrestore(&ioapic_lock
, flags
);
477 * When we mask an IO APIC routing entry, we need to write the low
478 * word first, in order to set the mask bit before we change the
481 static void ioapic_mask_entry(int apic
, int pin
)
484 union entry_union eu
= { .entry
.mask
= 1 };
486 spin_lock_irqsave(&ioapic_lock
, flags
);
487 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
488 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
489 spin_unlock_irqrestore(&ioapic_lock
, flags
);
493 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
494 * shared ISA-space IRQs, so we have to support them. We are super
495 * fast in the common case, and fast for shared ISA-space IRQs.
497 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
499 struct irq_pin_list
*entry
;
501 entry
= cfg
->irq_2_pin
;
503 entry
= get_one_free_irq_2_pin(node
);
505 printk(KERN_ERR
"can not alloc irq_2_pin to add %d - %d\n",
509 cfg
->irq_2_pin
= entry
;
515 while (entry
->next
) {
516 /* not again, please */
517 if (entry
->apic
== apic
&& entry
->pin
== pin
)
523 entry
->next
= get_one_free_irq_2_pin(node
);
530 * Reroute an IRQ to a different pin.
532 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
533 int oldapic
, int oldpin
,
534 int newapic
, int newpin
)
536 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
540 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
541 entry
->apic
= newapic
;
544 /* every one is different, right? */
550 /* why? call replace before add? */
552 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
555 static inline void io_apic_modify_irq(struct irq_cfg
*cfg
,
556 int mask_and
, int mask_or
,
557 void (*final
)(struct irq_pin_list
*entry
))
560 struct irq_pin_list
*entry
;
562 for (entry
= cfg
->irq_2_pin
; entry
!= NULL
; entry
= entry
->next
) {
565 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
568 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
574 static void __unmask_IO_APIC_irq(struct irq_cfg
*cfg
)
576 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
580 static void io_apic_sync(struct irq_pin_list
*entry
)
583 * Synchronize the IO-APIC and the CPU by doing
584 * a dummy read from the IO-APIC
586 struct io_apic __iomem
*io_apic
;
587 io_apic
= io_apic_base(entry
->apic
);
588 readl(&io_apic
->data
);
591 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
593 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
595 #else /* CONFIG_X86_32 */
596 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
598 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, NULL
);
601 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg
*cfg
)
603 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
604 IO_APIC_REDIR_MASKED
, NULL
);
607 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg
*cfg
)
609 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
,
610 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
612 #endif /* CONFIG_X86_32 */
614 static void mask_IO_APIC_irq_desc(struct irq_desc
*desc
)
616 struct irq_cfg
*cfg
= desc
->chip_data
;
621 spin_lock_irqsave(&ioapic_lock
, flags
);
622 __mask_IO_APIC_irq(cfg
);
623 spin_unlock_irqrestore(&ioapic_lock
, flags
);
626 static void unmask_IO_APIC_irq_desc(struct irq_desc
*desc
)
628 struct irq_cfg
*cfg
= desc
->chip_data
;
631 spin_lock_irqsave(&ioapic_lock
, flags
);
632 __unmask_IO_APIC_irq(cfg
);
633 spin_unlock_irqrestore(&ioapic_lock
, flags
);
636 static void mask_IO_APIC_irq(unsigned int irq
)
638 struct irq_desc
*desc
= irq_to_desc(irq
);
640 mask_IO_APIC_irq_desc(desc
);
642 static void unmask_IO_APIC_irq(unsigned int irq
)
644 struct irq_desc
*desc
= irq_to_desc(irq
);
646 unmask_IO_APIC_irq_desc(desc
);
649 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
651 struct IO_APIC_route_entry entry
;
653 /* Check delivery_mode to be sure we're not clearing an SMI pin */
654 entry
= ioapic_read_entry(apic
, pin
);
655 if (entry
.delivery_mode
== dest_SMI
)
658 * Disable it in the IO-APIC irq-routing table:
660 ioapic_mask_entry(apic
, pin
);
663 static void clear_IO_APIC (void)
667 for (apic
= 0; apic
< nr_ioapics
; apic
++)
668 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
669 clear_IO_APIC_pin(apic
, pin
);
674 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
675 * specific CPU-side IRQs.
679 static int pirq_entries
[MAX_PIRQS
] = {
680 [0 ... MAX_PIRQS
- 1] = -1
683 static int __init
ioapic_pirq_setup(char *str
)
686 int ints
[MAX_PIRQS
+1];
688 get_options(str
, ARRAY_SIZE(ints
), ints
);
690 apic_printk(APIC_VERBOSE
, KERN_INFO
691 "PIRQ redirection, working around broken MP-BIOS.\n");
693 if (ints
[0] < MAX_PIRQS
)
696 for (i
= 0; i
< max
; i
++) {
697 apic_printk(APIC_VERBOSE
, KERN_DEBUG
698 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
700 * PIRQs are mapped upside down, usually.
702 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
707 __setup("pirq=", ioapic_pirq_setup
);
708 #endif /* CONFIG_X86_32 */
710 struct IO_APIC_route_entry
**alloc_ioapic_entries(void)
713 struct IO_APIC_route_entry
**ioapic_entries
;
715 ioapic_entries
= kzalloc(sizeof(*ioapic_entries
) * nr_ioapics
,
720 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
721 ioapic_entries
[apic
] =
722 kzalloc(sizeof(struct IO_APIC_route_entry
) *
723 nr_ioapic_registers
[apic
], GFP_ATOMIC
);
724 if (!ioapic_entries
[apic
])
728 return ioapic_entries
;
732 kfree(ioapic_entries
[apic
]);
733 kfree(ioapic_entries
);
739 * Saves all the IO-APIC RTE's
741 int save_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
748 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
749 if (!ioapic_entries
[apic
])
752 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
753 ioapic_entries
[apic
][pin
] =
754 ioapic_read_entry(apic
, pin
);
761 * Mask all IO APIC entries.
763 void mask_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
770 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
771 if (!ioapic_entries
[apic
])
774 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
775 struct IO_APIC_route_entry entry
;
777 entry
= ioapic_entries
[apic
][pin
];
780 ioapic_write_entry(apic
, pin
, entry
);
787 * Restore IO APIC entries which was saved in ioapic_entries.
789 int restore_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
796 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
797 if (!ioapic_entries
[apic
])
800 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
801 ioapic_write_entry(apic
, pin
,
802 ioapic_entries
[apic
][pin
]);
807 void free_ioapic_entries(struct IO_APIC_route_entry
**ioapic_entries
)
811 for (apic
= 0; apic
< nr_ioapics
; apic
++)
812 kfree(ioapic_entries
[apic
]);
814 kfree(ioapic_entries
);
818 * Find the IRQ entry number of a certain pin.
820 static int find_irq_entry(int apic
, int pin
, int type
)
824 for (i
= 0; i
< mp_irq_entries
; i
++)
825 if (mp_irqs
[i
].irqtype
== type
&&
826 (mp_irqs
[i
].dstapic
== mp_ioapics
[apic
].apicid
||
827 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
828 mp_irqs
[i
].dstirq
== pin
)
835 * Find the pin to which IRQ[irq] (ISA) is connected
837 static int __init
find_isa_irq_pin(int irq
, int type
)
841 for (i
= 0; i
< mp_irq_entries
; i
++) {
842 int lbus
= mp_irqs
[i
].srcbus
;
844 if (test_bit(lbus
, mp_bus_not_pci
) &&
845 (mp_irqs
[i
].irqtype
== type
) &&
846 (mp_irqs
[i
].srcbusirq
== irq
))
848 return mp_irqs
[i
].dstirq
;
853 static int __init
find_isa_irq_apic(int irq
, int type
)
857 for (i
= 0; i
< mp_irq_entries
; i
++) {
858 int lbus
= mp_irqs
[i
].srcbus
;
860 if (test_bit(lbus
, mp_bus_not_pci
) &&
861 (mp_irqs
[i
].irqtype
== type
) &&
862 (mp_irqs
[i
].srcbusirq
== irq
))
865 if (i
< mp_irq_entries
) {
867 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
868 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
)
876 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
878 * EISA Edge/Level control register, ELCR
880 static int EISA_ELCR(unsigned int irq
)
882 if (irq
< NR_IRQS_LEGACY
) {
883 unsigned int port
= 0x4d0 + (irq
>> 3);
884 return (inb(port
) >> (irq
& 7)) & 1;
886 apic_printk(APIC_VERBOSE
, KERN_INFO
887 "Broken MPtable reports ISA irq %d\n", irq
);
893 /* ISA interrupts are always polarity zero edge triggered,
894 * when listed as conforming in the MP table. */
896 #define default_ISA_trigger(idx) (0)
897 #define default_ISA_polarity(idx) (0)
899 /* EISA interrupts are always polarity zero and can be edge or level
900 * trigger depending on the ELCR value. If an interrupt is listed as
901 * EISA conforming in the MP table, that means its trigger type must
902 * be read in from the ELCR */
904 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
905 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
907 /* PCI interrupts are always polarity one level triggered,
908 * when listed as conforming in the MP table. */
910 #define default_PCI_trigger(idx) (1)
911 #define default_PCI_polarity(idx) (1)
913 /* MCA interrupts are always polarity zero level triggered,
914 * when listed as conforming in the MP table. */
916 #define default_MCA_trigger(idx) (1)
917 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
919 static int MPBIOS_polarity(int idx
)
921 int bus
= mp_irqs
[idx
].srcbus
;
925 * Determine IRQ line polarity (high active or low active):
927 switch (mp_irqs
[idx
].irqflag
& 3)
929 case 0: /* conforms, ie. bus-type dependent polarity */
930 if (test_bit(bus
, mp_bus_not_pci
))
931 polarity
= default_ISA_polarity(idx
);
933 polarity
= default_PCI_polarity(idx
);
935 case 1: /* high active */
940 case 2: /* reserved */
942 printk(KERN_WARNING
"broken BIOS!!\n");
946 case 3: /* low active */
951 default: /* invalid */
953 printk(KERN_WARNING
"broken BIOS!!\n");
961 static int MPBIOS_trigger(int idx
)
963 int bus
= mp_irqs
[idx
].srcbus
;
967 * Determine IRQ trigger mode (edge or level sensitive):
969 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
971 case 0: /* conforms, ie. bus-type dependent */
972 if (test_bit(bus
, mp_bus_not_pci
))
973 trigger
= default_ISA_trigger(idx
);
975 trigger
= default_PCI_trigger(idx
);
976 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
977 switch (mp_bus_id_to_type
[bus
]) {
978 case MP_BUS_ISA
: /* ISA pin */
980 /* set before the switch */
983 case MP_BUS_EISA
: /* EISA pin */
985 trigger
= default_EISA_trigger(idx
);
988 case MP_BUS_PCI
: /* PCI pin */
990 /* set before the switch */
993 case MP_BUS_MCA
: /* MCA pin */
995 trigger
= default_MCA_trigger(idx
);
1000 printk(KERN_WARNING
"broken BIOS!!\n");
1012 case 2: /* reserved */
1014 printk(KERN_WARNING
"broken BIOS!!\n");
1023 default: /* invalid */
1025 printk(KERN_WARNING
"broken BIOS!!\n");
1033 static inline int irq_polarity(int idx
)
1035 return MPBIOS_polarity(idx
);
1038 static inline int irq_trigger(int idx
)
1040 return MPBIOS_trigger(idx
);
1043 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1044 static int pin_2_irq(int idx
, int apic
, int pin
)
1047 int bus
= mp_irqs
[idx
].srcbus
;
1050 * Debugging check, we are in big trouble if this message pops up!
1052 if (mp_irqs
[idx
].dstirq
!= pin
)
1053 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1055 if (test_bit(bus
, mp_bus_not_pci
)) {
1056 irq
= mp_irqs
[idx
].srcbusirq
;
1059 * PCI IRQs are mapped in order
1063 irq
+= nr_ioapic_registers
[i
++];
1066 * For MPS mode, so far only needed by ES7000 platform
1068 if (ioapic_renumber_irq
)
1069 irq
= ioapic_renumber_irq(apic
, irq
);
1072 #ifdef CONFIG_X86_32
1074 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1076 if ((pin
>= 16) && (pin
<= 23)) {
1077 if (pirq_entries
[pin
-16] != -1) {
1078 if (!pirq_entries
[pin
-16]) {
1079 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1080 "disabling PIRQ%d\n", pin
-16);
1082 irq
= pirq_entries
[pin
-16];
1083 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1084 "using PIRQ%d -> IRQ %d\n",
1095 * Find a specific PCI IRQ entry.
1096 * Not an __init, possibly needed by modules
1098 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
,
1099 int *ioapic
, int *ioapic_pin
,
1100 int *trigger
, int *polarity
)
1102 int apic
, i
, best_guess
= -1;
1104 apic_printk(APIC_DEBUG
,
1105 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1107 if (test_bit(bus
, mp_bus_not_pci
)) {
1108 apic_printk(APIC_VERBOSE
,
1109 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1112 for (i
= 0; i
< mp_irq_entries
; i
++) {
1113 int lbus
= mp_irqs
[i
].srcbus
;
1115 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1116 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
||
1117 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
1120 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1121 !mp_irqs
[i
].irqtype
&&
1123 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1124 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].dstirq
);
1126 if (!(apic
|| IO_APIC_IRQ(irq
)))
1129 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1131 *ioapic_pin
= mp_irqs
[i
].dstirq
;
1132 *trigger
= irq_trigger(i
);
1133 *polarity
= irq_polarity(i
);
1137 * Use the first all-but-pin matching entry as a
1138 * best-guess fuzzy result for broken mptables.
1140 if (best_guess
< 0) {
1142 *ioapic_pin
= mp_irqs
[i
].dstirq
;
1143 *trigger
= irq_trigger(i
);
1144 *polarity
= irq_polarity(i
);
1151 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1153 void lock_vector_lock(void)
1155 /* Used to the online set of cpus does not change
1156 * during assign_irq_vector.
1158 spin_lock(&vector_lock
);
1161 void unlock_vector_lock(void)
1163 spin_unlock(&vector_lock
);
1167 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1170 * NOTE! The local APIC isn't very good at handling
1171 * multiple interrupts at the same interrupt level.
1172 * As the interrupt level is determined by taking the
1173 * vector number and shifting that right by 4, we
1174 * want to spread these out a bit so that they don't
1175 * all fall in the same interrupt level.
1177 * Also, we've got to be careful not to trash gate
1178 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1180 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1181 unsigned int old_vector
;
1183 cpumask_var_t tmp_mask
;
1185 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1188 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1191 old_vector
= cfg
->vector
;
1193 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1194 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1195 if (!cpumask_empty(tmp_mask
)) {
1196 free_cpumask_var(tmp_mask
);
1201 /* Only try and allocate irqs on cpus that are present */
1203 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1207 apic
->vector_allocation_domain(cpu
, tmp_mask
);
1209 vector
= current_vector
;
1210 offset
= current_offset
;
1213 if (vector
>= first_system_vector
) {
1214 /* If out of vectors on large boxen, must share them. */
1215 offset
= (offset
+ 1) % 8;
1216 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1218 if (unlikely(current_vector
== vector
))
1221 if (test_bit(vector
, used_vectors
))
1224 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1225 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1228 current_vector
= vector
;
1229 current_offset
= offset
;
1231 cfg
->move_in_progress
= 1;
1232 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1234 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1235 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1236 cfg
->vector
= vector
;
1237 cpumask_copy(cfg
->domain
, tmp_mask
);
1241 free_cpumask_var(tmp_mask
);
1246 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1249 unsigned long flags
;
1251 spin_lock_irqsave(&vector_lock
, flags
);
1252 err
= __assign_irq_vector(irq
, cfg
, mask
);
1253 spin_unlock_irqrestore(&vector_lock
, flags
);
1257 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1261 BUG_ON(!cfg
->vector
);
1263 vector
= cfg
->vector
;
1264 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1265 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1268 cpumask_clear(cfg
->domain
);
1270 if (likely(!cfg
->move_in_progress
))
1272 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1273 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1275 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1277 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1281 cfg
->move_in_progress
= 0;
1284 void __setup_vector_irq(int cpu
)
1286 /* Initialize vector_irq on a new cpu */
1287 /* This function must be called with vector_lock held */
1289 struct irq_cfg
*cfg
;
1290 struct irq_desc
*desc
;
1292 /* Mark the inuse vectors */
1293 for_each_irq_desc(irq
, desc
) {
1294 cfg
= desc
->chip_data
;
1295 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1297 vector
= cfg
->vector
;
1298 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1300 /* Mark the free vectors */
1301 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1302 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1307 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1308 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1312 static struct irq_chip ioapic_chip
;
1313 static struct irq_chip ir_ioapic_chip
;
1315 #define IOAPIC_AUTO -1
1316 #define IOAPIC_EDGE 0
1317 #define IOAPIC_LEVEL 1
1319 #ifdef CONFIG_X86_32
1320 static inline int IO_APIC_irq_trigger(int irq
)
1324 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1325 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1326 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1327 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1328 return irq_trigger(idx
);
1332 * nonexistent IRQs are edge default
1337 static inline int IO_APIC_irq_trigger(int irq
)
1343 static void ioapic_register_intr(int irq
, struct irq_desc
*desc
, unsigned long trigger
)
1346 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1347 trigger
== IOAPIC_LEVEL
)
1348 desc
->status
|= IRQ_LEVEL
;
1350 desc
->status
&= ~IRQ_LEVEL
;
1352 if (irq_remapped(irq
)) {
1353 desc
->status
|= IRQ_MOVE_PCNTXT
;
1355 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1359 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1360 handle_edge_irq
, "edge");
1364 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1365 trigger
== IOAPIC_LEVEL
)
1366 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1370 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1371 handle_edge_irq
, "edge");
1374 int setup_ioapic_entry(int apic_id
, int irq
,
1375 struct IO_APIC_route_entry
*entry
,
1376 unsigned int destination
, int trigger
,
1377 int polarity
, int vector
, int pin
)
1380 * add it to the IO-APIC irq-routing table:
1382 memset(entry
,0,sizeof(*entry
));
1384 if (intr_remapping_enabled
) {
1385 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic_id
);
1387 struct IR_IO_APIC_route_entry
*ir_entry
=
1388 (struct IR_IO_APIC_route_entry
*) entry
;
1392 panic("No mapping iommu for ioapic %d\n", apic_id
);
1394 index
= alloc_irte(iommu
, irq
, 1);
1396 panic("Failed to allocate IRTE for ioapic %d\n", apic_id
);
1398 memset(&irte
, 0, sizeof(irte
));
1401 irte
.dst_mode
= apic
->irq_dest_mode
;
1403 * Trigger mode in the IRTE will always be edge, and the
1404 * actual level or edge trigger will be setup in the IO-APIC
1405 * RTE. This will help simplify level triggered irq migration.
1406 * For more details, see the comments above explainig IO-APIC
1407 * irq migration in the presence of interrupt-remapping.
1409 irte
.trigger_mode
= 0;
1410 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
1411 irte
.vector
= vector
;
1412 irte
.dest_id
= IRTE_DEST(destination
);
1414 modify_irte(irq
, &irte
);
1416 ir_entry
->index2
= (index
>> 15) & 0x1;
1418 ir_entry
->format
= 1;
1419 ir_entry
->index
= (index
& 0x7fff);
1421 * IO-APIC RTE will be configured with virtual vector.
1422 * irq handler will do the explicit EOI to the io-apic.
1424 ir_entry
->vector
= pin
;
1426 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1427 entry
->dest_mode
= apic
->irq_dest_mode
;
1428 entry
->dest
= destination
;
1429 entry
->vector
= vector
;
1432 entry
->mask
= 0; /* enable IRQ */
1433 entry
->trigger
= trigger
;
1434 entry
->polarity
= polarity
;
1436 /* Mask level triggered irqs.
1437 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1444 static void setup_IO_APIC_irq(int apic_id
, int pin
, unsigned int irq
, struct irq_desc
*desc
,
1445 int trigger
, int polarity
)
1447 struct irq_cfg
*cfg
;
1448 struct IO_APIC_route_entry entry
;
1451 if (!IO_APIC_IRQ(irq
))
1454 cfg
= desc
->chip_data
;
1456 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1459 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
1461 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1462 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1463 "IRQ %d Mode:%i Active:%i)\n",
1464 apic_id
, mp_ioapics
[apic_id
].apicid
, pin
, cfg
->vector
,
1465 irq
, trigger
, polarity
);
1468 if (setup_ioapic_entry(mp_ioapics
[apic_id
].apicid
, irq
, &entry
,
1469 dest
, trigger
, polarity
, cfg
->vector
, pin
)) {
1470 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1471 mp_ioapics
[apic_id
].apicid
, pin
);
1472 __clear_irq_vector(irq
, cfg
);
1476 ioapic_register_intr(irq
, desc
, trigger
);
1477 if (irq
< NR_IRQS_LEGACY
)
1478 disable_8259A_irq(irq
);
1480 ioapic_write_entry(apic_id
, pin
, entry
);
1484 DECLARE_BITMAP(pin_programmed
, MP_MAX_IOAPIC_PIN
+ 1);
1485 } mp_ioapic_routing
[MAX_IO_APICS
];
1487 static void __init
setup_IO_APIC_irqs(void)
1489 int apic_id
= 0, pin
, idx
, irq
;
1491 struct irq_desc
*desc
;
1492 struct irq_cfg
*cfg
;
1493 int node
= cpu_to_node(boot_cpu_id
);
1495 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1498 if (!acpi_disabled
&& acpi_ioapic
) {
1499 apic_id
= mp_find_ioapic(0);
1505 for (pin
= 0; pin
< nr_ioapic_registers
[apic_id
]; pin
++) {
1506 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1510 apic_printk(APIC_VERBOSE
,
1511 KERN_DEBUG
" %d-%d",
1512 mp_ioapics
[apic_id
].apicid
, pin
);
1514 apic_printk(APIC_VERBOSE
, " %d-%d",
1515 mp_ioapics
[apic_id
].apicid
, pin
);
1519 apic_printk(APIC_VERBOSE
,
1520 " (apicid-pin) not connected\n");
1524 irq
= pin_2_irq(idx
, apic_id
, pin
);
1527 * Skip the timer IRQ if there's a quirk handler
1528 * installed and if it returns 1:
1530 if (apic
->multi_timer_check
&&
1531 apic
->multi_timer_check(apic_id
, irq
))
1534 desc
= irq_to_desc_alloc_node(irq
, node
);
1536 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1539 cfg
= desc
->chip_data
;
1540 add_pin_to_irq_node(cfg
, node
, apic_id
, pin
);
1541 set_bit(pin
, mp_ioapic_routing
[apic_id
].pin_programmed
);
1542 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1543 irq_trigger(idx
), irq_polarity(idx
));
1547 apic_printk(APIC_VERBOSE
,
1548 " (apicid-pin) not connected\n");
1552 * Set up the timer pin, possibly with the 8259A-master behind.
1554 static void __init
setup_timer_IRQ0_pin(unsigned int apic_id
, unsigned int pin
,
1557 struct IO_APIC_route_entry entry
;
1559 if (intr_remapping_enabled
)
1562 memset(&entry
, 0, sizeof(entry
));
1565 * We use logical delivery to get the timer IRQ
1568 entry
.dest_mode
= apic
->irq_dest_mode
;
1569 entry
.mask
= 0; /* don't mask IRQ for edge */
1570 entry
.dest
= apic
->cpu_mask_to_apicid(apic
->target_cpus());
1571 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1574 entry
.vector
= vector
;
1577 * The timer IRQ doesn't have to know that behind the
1578 * scene we may have a 8259A-master in AEOI mode ...
1580 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1583 * Add it to the IO-APIC irq-routing table:
1585 ioapic_write_entry(apic_id
, pin
, entry
);
1589 __apicdebuginit(void) print_IO_APIC(void)
1592 union IO_APIC_reg_00 reg_00
;
1593 union IO_APIC_reg_01 reg_01
;
1594 union IO_APIC_reg_02 reg_02
;
1595 union IO_APIC_reg_03 reg_03
;
1596 unsigned long flags
;
1597 struct irq_cfg
*cfg
;
1598 struct irq_desc
*desc
;
1601 if (apic_verbosity
== APIC_QUIET
)
1604 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1605 for (i
= 0; i
< nr_ioapics
; i
++)
1606 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1607 mp_ioapics
[i
].apicid
, nr_ioapic_registers
[i
]);
1610 * We are a bit conservative about what we expect. We have to
1611 * know about every hardware change ASAP.
1613 printk(KERN_INFO
"testing the IO APIC.......................\n");
1615 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1617 spin_lock_irqsave(&ioapic_lock
, flags
);
1618 reg_00
.raw
= io_apic_read(apic
, 0);
1619 reg_01
.raw
= io_apic_read(apic
, 1);
1620 if (reg_01
.bits
.version
>= 0x10)
1621 reg_02
.raw
= io_apic_read(apic
, 2);
1622 if (reg_01
.bits
.version
>= 0x20)
1623 reg_03
.raw
= io_apic_read(apic
, 3);
1624 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1627 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].apicid
);
1628 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1629 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1630 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1631 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1633 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1634 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1636 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1637 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1640 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1641 * but the value of reg_02 is read as the previous read register
1642 * value, so ignore it if reg_02 == reg_01.
1644 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1645 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1646 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1650 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1651 * or reg_03, but the value of reg_0[23] is read as the previous read
1652 * register value, so ignore it if reg_03 == reg_0[12].
1654 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1655 reg_03
.raw
!= reg_01
.raw
) {
1656 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1657 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1660 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1662 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1663 " Stat Dmod Deli Vect: \n");
1665 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1666 struct IO_APIC_route_entry entry
;
1668 entry
= ioapic_read_entry(apic
, i
);
1670 printk(KERN_DEBUG
" %02x %03X ",
1675 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1680 entry
.delivery_status
,
1682 entry
.delivery_mode
,
1687 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1688 for_each_irq_desc(irq
, desc
) {
1689 struct irq_pin_list
*entry
;
1691 cfg
= desc
->chip_data
;
1692 entry
= cfg
->irq_2_pin
;
1695 printk(KERN_DEBUG
"IRQ%d ", irq
);
1697 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1700 entry
= entry
->next
;
1705 printk(KERN_INFO
".................................... done.\n");
1710 __apicdebuginit(void) print_APIC_bitfield(int base
)
1715 if (apic_verbosity
== APIC_QUIET
)
1718 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1719 for (i
= 0; i
< 8; i
++) {
1720 v
= apic_read(base
+ i
*0x10);
1721 for (j
= 0; j
< 32; j
++) {
1731 __apicdebuginit(void) print_local_APIC(void *dummy
)
1733 unsigned int i
, v
, ver
, maxlvt
;
1736 if (apic_verbosity
== APIC_QUIET
)
1739 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1740 smp_processor_id(), hard_smp_processor_id());
1741 v
= apic_read(APIC_ID
);
1742 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1743 v
= apic_read(APIC_LVR
);
1744 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1745 ver
= GET_APIC_VERSION(v
);
1746 maxlvt
= lapic_get_maxlvt();
1748 v
= apic_read(APIC_TASKPRI
);
1749 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1751 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1752 if (!APIC_XAPIC(ver
)) {
1753 v
= apic_read(APIC_ARBPRI
);
1754 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1755 v
& APIC_ARBPRI_MASK
);
1757 v
= apic_read(APIC_PROCPRI
);
1758 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1762 * Remote read supported only in the 82489DX and local APIC for
1763 * Pentium processors.
1765 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1766 v
= apic_read(APIC_RRR
);
1767 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1770 v
= apic_read(APIC_LDR
);
1771 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1772 if (!x2apic_enabled()) {
1773 v
= apic_read(APIC_DFR
);
1774 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1776 v
= apic_read(APIC_SPIV
);
1777 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1779 printk(KERN_DEBUG
"... APIC ISR field:\n");
1780 print_APIC_bitfield(APIC_ISR
);
1781 printk(KERN_DEBUG
"... APIC TMR field:\n");
1782 print_APIC_bitfield(APIC_TMR
);
1783 printk(KERN_DEBUG
"... APIC IRR field:\n");
1784 print_APIC_bitfield(APIC_IRR
);
1786 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1787 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1788 apic_write(APIC_ESR
, 0);
1790 v
= apic_read(APIC_ESR
);
1791 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1794 icr
= apic_icr_read();
1795 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1796 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1798 v
= apic_read(APIC_LVTT
);
1799 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1801 if (maxlvt
> 3) { /* PC is LVT#4. */
1802 v
= apic_read(APIC_LVTPC
);
1803 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1805 v
= apic_read(APIC_LVT0
);
1806 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1807 v
= apic_read(APIC_LVT1
);
1808 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1810 if (maxlvt
> 2) { /* ERR is LVT#3. */
1811 v
= apic_read(APIC_LVTERR
);
1812 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1815 v
= apic_read(APIC_TMICT
);
1816 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1817 v
= apic_read(APIC_TMCCT
);
1818 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1819 v
= apic_read(APIC_TDCR
);
1820 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1822 if (boot_cpu_has(X86_FEATURE_EXTAPIC
)) {
1823 v
= apic_read(APIC_EFEAT
);
1824 maxlvt
= (v
>> 16) & 0xff;
1825 printk(KERN_DEBUG
"... APIC EFEAT: %08x\n", v
);
1826 v
= apic_read(APIC_ECTRL
);
1827 printk(KERN_DEBUG
"... APIC ECTRL: %08x\n", v
);
1828 for (i
= 0; i
< maxlvt
; i
++) {
1829 v
= apic_read(APIC_EILVTn(i
));
1830 printk(KERN_DEBUG
"... APIC EILVT%d: %08x\n", i
, v
);
1836 __apicdebuginit(void) print_all_local_APICs(void)
1841 for_each_online_cpu(cpu
)
1842 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1846 __apicdebuginit(void) print_PIC(void)
1849 unsigned long flags
;
1851 if (apic_verbosity
== APIC_QUIET
)
1854 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1856 spin_lock_irqsave(&i8259A_lock
, flags
);
1858 v
= inb(0xa1) << 8 | inb(0x21);
1859 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1861 v
= inb(0xa0) << 8 | inb(0x20);
1862 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1866 v
= inb(0xa0) << 8 | inb(0x20);
1870 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1872 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1874 v
= inb(0x4d1) << 8 | inb(0x4d0);
1875 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1878 __apicdebuginit(int) print_all_ICs(void)
1882 /* don't print out if apic is not there */
1883 if (!cpu_has_apic
|| disable_apic
)
1886 print_all_local_APICs();
1892 fs_initcall(print_all_ICs
);
1895 /* Where if anywhere is the i8259 connect in external int mode */
1896 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1898 void __init
enable_IO_APIC(void)
1900 union IO_APIC_reg_01 reg_01
;
1901 int i8259_apic
, i8259_pin
;
1903 unsigned long flags
;
1906 * The number of IO-APIC IRQ registers (== #pins):
1908 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1909 spin_lock_irqsave(&ioapic_lock
, flags
);
1910 reg_01
.raw
= io_apic_read(apic
, 1);
1911 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1912 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1914 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1916 /* See if any of the pins is in ExtINT mode */
1917 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1918 struct IO_APIC_route_entry entry
;
1919 entry
= ioapic_read_entry(apic
, pin
);
1921 /* If the interrupt line is enabled and in ExtInt mode
1922 * I have found the pin where the i8259 is connected.
1924 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1925 ioapic_i8259
.apic
= apic
;
1926 ioapic_i8259
.pin
= pin
;
1932 /* Look to see what if the MP table has reported the ExtINT */
1933 /* If we could not find the appropriate pin by looking at the ioapic
1934 * the i8259 probably is not connected the ioapic but give the
1935 * mptable a chance anyway.
1937 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1938 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1939 /* Trust the MP table if nothing is setup in the hardware */
1940 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1941 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1942 ioapic_i8259
.pin
= i8259_pin
;
1943 ioapic_i8259
.apic
= i8259_apic
;
1945 /* Complain if the MP table and the hardware disagree */
1946 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1947 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1949 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1953 * Do not trust the IO-APIC being empty at bootup
1959 * Not an __init, needed by the reboot code
1961 void disable_IO_APIC(void)
1964 * Clear the IO-APIC before rebooting:
1969 * If the i8259 is routed through an IOAPIC
1970 * Put that IOAPIC in virtual wire mode
1971 * so legacy interrupts can be delivered.
1973 * With interrupt-remapping, for now we will use virtual wire A mode,
1974 * as virtual wire B is little complex (need to configure both
1975 * IOAPIC RTE aswell as interrupt-remapping table entry).
1976 * As this gets called during crash dump, keep this simple for now.
1978 if (ioapic_i8259
.pin
!= -1 && !intr_remapping_enabled
) {
1979 struct IO_APIC_route_entry entry
;
1981 memset(&entry
, 0, sizeof(entry
));
1982 entry
.mask
= 0; /* Enabled */
1983 entry
.trigger
= 0; /* Edge */
1985 entry
.polarity
= 0; /* High */
1986 entry
.delivery_status
= 0;
1987 entry
.dest_mode
= 0; /* Physical */
1988 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1990 entry
.dest
= read_apic_id();
1993 * Add it to the IO-APIC irq-routing table:
1995 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1999 * Use virtual wire A mode when interrupt remapping is enabled.
2001 disconnect_bsp_APIC(!intr_remapping_enabled
&& ioapic_i8259
.pin
!= -1);
2004 #ifdef CONFIG_X86_32
2006 * function to set the IO-APIC physical IDs based on the
2007 * values stored in the MPC table.
2009 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2012 static void __init
setup_ioapic_ids_from_mpc(void)
2014 union IO_APIC_reg_00 reg_00
;
2015 physid_mask_t phys_id_present_map
;
2018 unsigned char old_id
;
2019 unsigned long flags
;
2021 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
2025 * Don't check I/O APIC IDs for xAPIC systems. They have
2026 * no meaning without the serial APIC bus.
2028 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2029 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2032 * This is broken; anything with a real cpu count has to
2033 * circumvent this idiocy regardless.
2035 phys_id_present_map
= apic
->ioapic_phys_id_map(phys_cpu_present_map
);
2038 * Set the IOAPIC ID to the value stored in the MPC table.
2040 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
2042 /* Read the register 0 value */
2043 spin_lock_irqsave(&ioapic_lock
, flags
);
2044 reg_00
.raw
= io_apic_read(apic_id
, 0);
2045 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2047 old_id
= mp_ioapics
[apic_id
].apicid
;
2049 if (mp_ioapics
[apic_id
].apicid
>= get_physical_broadcast()) {
2050 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2051 apic_id
, mp_ioapics
[apic_id
].apicid
);
2052 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2054 mp_ioapics
[apic_id
].apicid
= reg_00
.bits
.ID
;
2058 * Sanity check, is the ID really free? Every APIC in a
2059 * system must have a unique ID or we get lots of nice
2060 * 'stuck on smp_invalidate_needed IPI wait' messages.
2062 if (apic
->check_apicid_used(phys_id_present_map
,
2063 mp_ioapics
[apic_id
].apicid
)) {
2064 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2065 apic_id
, mp_ioapics
[apic_id
].apicid
);
2066 for (i
= 0; i
< get_physical_broadcast(); i
++)
2067 if (!physid_isset(i
, phys_id_present_map
))
2069 if (i
>= get_physical_broadcast())
2070 panic("Max APIC ID exceeded!\n");
2071 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2073 physid_set(i
, phys_id_present_map
);
2074 mp_ioapics
[apic_id
].apicid
= i
;
2077 tmp
= apic
->apicid_to_cpu_present(mp_ioapics
[apic_id
].apicid
);
2078 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2079 "phys_id_present_map\n",
2080 mp_ioapics
[apic_id
].apicid
);
2081 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2086 * We need to adjust the IRQ routing table
2087 * if the ID changed.
2089 if (old_id
!= mp_ioapics
[apic_id
].apicid
)
2090 for (i
= 0; i
< mp_irq_entries
; i
++)
2091 if (mp_irqs
[i
].dstapic
== old_id
)
2093 = mp_ioapics
[apic_id
].apicid
;
2096 * Read the right value from the MPC table and
2097 * write it into the ID register.
2099 apic_printk(APIC_VERBOSE
, KERN_INFO
2100 "...changing IO-APIC physical APIC ID to %d ...",
2101 mp_ioapics
[apic_id
].apicid
);
2103 reg_00
.bits
.ID
= mp_ioapics
[apic_id
].apicid
;
2104 spin_lock_irqsave(&ioapic_lock
, flags
);
2105 io_apic_write(apic_id
, 0, reg_00
.raw
);
2106 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2111 spin_lock_irqsave(&ioapic_lock
, flags
);
2112 reg_00
.raw
= io_apic_read(apic_id
, 0);
2113 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2114 if (reg_00
.bits
.ID
!= mp_ioapics
[apic_id
].apicid
)
2115 printk("could not set ID!\n");
2117 apic_printk(APIC_VERBOSE
, " ok.\n");
2122 int no_timer_check __initdata
;
2124 static int __init
notimercheck(char *s
)
2129 __setup("no_timer_check", notimercheck
);
2132 * There is a nasty bug in some older SMP boards, their mptable lies
2133 * about the timer IRQ. We do the following to work around the situation:
2135 * - timer IRQ defaults to IO-APIC IRQ
2136 * - if this function detects that timer IRQs are defunct, then we fall
2137 * back to ISA timer IRQs
2139 static int __init
timer_irq_works(void)
2141 unsigned long t1
= jiffies
;
2142 unsigned long flags
;
2147 local_save_flags(flags
);
2149 /* Let ten ticks pass... */
2150 mdelay((10 * 1000) / HZ
);
2151 local_irq_restore(flags
);
2154 * Expect a few ticks at least, to be sure some possible
2155 * glue logic does not lock up after one or two first
2156 * ticks in a non-ExtINT mode. Also the local APIC
2157 * might have cached one ExtINT interrupt. Finally, at
2158 * least one tick may be lost due to delays.
2162 if (time_after(jiffies
, t1
+ 4))
2168 * In the SMP+IOAPIC case it might happen that there are an unspecified
2169 * number of pending IRQ events unhandled. These cases are very rare,
2170 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2171 * better to do it this way as thus we do not have to be aware of
2172 * 'pending' interrupts in the IRQ path, except at this point.
2175 * Edge triggered needs to resend any interrupt
2176 * that was delayed but this is now handled in the device
2181 * Starting up a edge-triggered IO-APIC interrupt is
2182 * nasty - we need to make sure that we get the edge.
2183 * If it is already asserted for some reason, we need
2184 * return 1 to indicate that is was pending.
2186 * This is not complete - we should be able to fake
2187 * an edge even if it isn't on the 8259A...
2190 static unsigned int startup_ioapic_irq(unsigned int irq
)
2192 int was_pending
= 0;
2193 unsigned long flags
;
2194 struct irq_cfg
*cfg
;
2196 spin_lock_irqsave(&ioapic_lock
, flags
);
2197 if (irq
< NR_IRQS_LEGACY
) {
2198 disable_8259A_irq(irq
);
2199 if (i8259A_irq_pending(irq
))
2203 __unmask_IO_APIC_irq(cfg
);
2204 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2209 #ifdef CONFIG_X86_64
2210 static int ioapic_retrigger_irq(unsigned int irq
)
2213 struct irq_cfg
*cfg
= irq_cfg(irq
);
2214 unsigned long flags
;
2216 spin_lock_irqsave(&vector_lock
, flags
);
2217 apic
->send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2218 spin_unlock_irqrestore(&vector_lock
, flags
);
2223 static int ioapic_retrigger_irq(unsigned int irq
)
2225 apic
->send_IPI_self(irq_cfg(irq
)->vector
);
2232 * Level and edge triggered IO-APIC interrupts need different handling,
2233 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2234 * handled with the level-triggered descriptor, but that one has slightly
2235 * more overhead. Level-triggered interrupts cannot be handled with the
2236 * edge-triggered handler, without risking IRQ storms and other ugly
2241 static void send_cleanup_vector(struct irq_cfg
*cfg
)
2243 cpumask_var_t cleanup_mask
;
2245 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
2247 cfg
->move_cleanup_count
= 0;
2248 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2249 cfg
->move_cleanup_count
++;
2250 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2251 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
2253 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
2254 cfg
->move_cleanup_count
= cpumask_weight(cleanup_mask
);
2255 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2256 free_cpumask_var(cleanup_mask
);
2258 cfg
->move_in_progress
= 0;
2261 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
2264 struct irq_pin_list
*entry
;
2265 u8 vector
= cfg
->vector
;
2267 entry
= cfg
->irq_2_pin
;
2277 * With interrupt-remapping, destination information comes
2278 * from interrupt-remapping table entry.
2280 if (!irq_remapped(irq
))
2281 io_apic_write(apic
, 0x11 + pin
*2, dest
);
2282 reg
= io_apic_read(apic
, 0x10 + pin
*2);
2283 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
2285 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
2288 entry
= entry
->next
;
2293 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
);
2296 * Either sets desc->affinity to a valid value, and returns
2297 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2298 * leaves desc->affinity untouched.
2301 set_desc_affinity(struct irq_desc
*desc
, const struct cpumask
*mask
)
2303 struct irq_cfg
*cfg
;
2306 if (!cpumask_intersects(mask
, cpu_online_mask
))
2310 cfg
= desc
->chip_data
;
2311 if (assign_irq_vector(irq
, cfg
, mask
))
2314 cpumask_copy(desc
->affinity
, mask
);
2316 return apic
->cpu_mask_to_apicid_and(desc
->affinity
, cfg
->domain
);
2320 set_ioapic_affinity_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2322 struct irq_cfg
*cfg
;
2323 unsigned long flags
;
2329 cfg
= desc
->chip_data
;
2331 spin_lock_irqsave(&ioapic_lock
, flags
);
2332 dest
= set_desc_affinity(desc
, mask
);
2333 if (dest
!= BAD_APICID
) {
2334 /* Only the high 8 bits are valid. */
2335 dest
= SET_APIC_LOGICAL_ID(dest
);
2336 __target_IO_APIC_irq(irq
, dest
, cfg
);
2339 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2345 set_ioapic_affinity_irq(unsigned int irq
, const struct cpumask
*mask
)
2347 struct irq_desc
*desc
;
2349 desc
= irq_to_desc(irq
);
2351 return set_ioapic_affinity_irq_desc(desc
, mask
);
2354 #ifdef CONFIG_INTR_REMAP
2357 * Migrate the IO-APIC irq in the presence of intr-remapping.
2359 * For both level and edge triggered, irq migration is a simple atomic
2360 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2362 * For level triggered, we eliminate the io-apic RTE modification (with the
2363 * updated vector information), by using a virtual vector (io-apic pin number).
2364 * Real vector that is used for interrupting cpu will be coming from
2365 * the interrupt-remapping table entry.
2368 migrate_ioapic_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2370 struct irq_cfg
*cfg
;
2376 if (!cpumask_intersects(mask
, cpu_online_mask
))
2380 if (get_irte(irq
, &irte
))
2383 cfg
= desc
->chip_data
;
2384 if (assign_irq_vector(irq
, cfg
, mask
))
2387 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2389 irte
.vector
= cfg
->vector
;
2390 irte
.dest_id
= IRTE_DEST(dest
);
2393 * Modified the IRTE and flushes the Interrupt entry cache.
2395 modify_irte(irq
, &irte
);
2397 if (cfg
->move_in_progress
)
2398 send_cleanup_vector(cfg
);
2400 cpumask_copy(desc
->affinity
, mask
);
2406 * Migrates the IRQ destination in the process context.
2408 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2409 const struct cpumask
*mask
)
2411 return migrate_ioapic_irq_desc(desc
, mask
);
2413 static int set_ir_ioapic_affinity_irq(unsigned int irq
,
2414 const struct cpumask
*mask
)
2416 struct irq_desc
*desc
= irq_to_desc(irq
);
2418 return set_ir_ioapic_affinity_irq_desc(desc
, mask
);
2421 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2422 const struct cpumask
*mask
)
2428 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2430 unsigned vector
, me
;
2436 me
= smp_processor_id();
2437 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2440 struct irq_desc
*desc
;
2441 struct irq_cfg
*cfg
;
2442 irq
= __get_cpu_var(vector_irq
)[vector
];
2447 desc
= irq_to_desc(irq
);
2452 spin_lock(&desc
->lock
);
2453 if (!cfg
->move_cleanup_count
)
2456 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2459 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2461 * Check if the vector that needs to be cleanedup is
2462 * registered at the cpu's IRR. If so, then this is not
2463 * the best time to clean it up. Lets clean it up in the
2464 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2467 if (irr
& (1 << (vector
% 32))) {
2468 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2471 __get_cpu_var(vector_irq
)[vector
] = -1;
2472 cfg
->move_cleanup_count
--;
2474 spin_unlock(&desc
->lock
);
2480 static void irq_complete_move(struct irq_desc
**descp
)
2482 struct irq_desc
*desc
= *descp
;
2483 struct irq_cfg
*cfg
= desc
->chip_data
;
2484 unsigned vector
, me
;
2486 if (likely(!cfg
->move_in_progress
))
2489 vector
= ~get_irq_regs()->orig_ax
;
2490 me
= smp_processor_id();
2492 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2493 send_cleanup_vector(cfg
);
2496 static inline void irq_complete_move(struct irq_desc
**descp
) {}
2499 static void ack_apic_edge(unsigned int irq
)
2501 struct irq_desc
*desc
= irq_to_desc(irq
);
2503 irq_complete_move(&desc
);
2504 move_native_irq(irq
);
2508 atomic_t irq_mis_count
;
2510 static void ack_apic_level(unsigned int irq
)
2512 struct irq_desc
*desc
= irq_to_desc(irq
);
2514 #ifdef CONFIG_X86_32
2518 struct irq_cfg
*cfg
;
2519 int do_unmask_irq
= 0;
2521 irq_complete_move(&desc
);
2522 #ifdef CONFIG_GENERIC_PENDING_IRQ
2523 /* If we are moving the irq we need to mask it */
2524 if (unlikely(desc
->status
& IRQ_MOVE_PENDING
)) {
2526 mask_IO_APIC_irq_desc(desc
);
2530 #ifdef CONFIG_X86_32
2532 * It appears there is an erratum which affects at least version 0x11
2533 * of I/O APIC (that's the 82093AA and cores integrated into various
2534 * chipsets). Under certain conditions a level-triggered interrupt is
2535 * erroneously delivered as edge-triggered one but the respective IRR
2536 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2537 * message but it will never arrive and further interrupts are blocked
2538 * from the source. The exact reason is so far unknown, but the
2539 * phenomenon was observed when two consecutive interrupt requests
2540 * from a given source get delivered to the same CPU and the source is
2541 * temporarily disabled in between.
2543 * A workaround is to simulate an EOI message manually. We achieve it
2544 * by setting the trigger mode to edge and then to level when the edge
2545 * trigger mode gets detected in the TMR of a local APIC for a
2546 * level-triggered interrupt. We mask the source for the time of the
2547 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2548 * The idea is from Manfred Spraul. --macro
2550 cfg
= desc
->chip_data
;
2553 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2557 * We must acknowledge the irq before we move it or the acknowledge will
2558 * not propagate properly.
2562 /* Now we can move and renable the irq */
2563 if (unlikely(do_unmask_irq
)) {
2564 /* Only migrate the irq if the ack has been received.
2566 * On rare occasions the broadcast level triggered ack gets
2567 * delayed going to ioapics, and if we reprogram the
2568 * vector while Remote IRR is still set the irq will never
2571 * To prevent this scenario we read the Remote IRR bit
2572 * of the ioapic. This has two effects.
2573 * - On any sane system the read of the ioapic will
2574 * flush writes (and acks) going to the ioapic from
2576 * - We get to see if the ACK has actually been delivered.
2578 * Based on failed experiments of reprogramming the
2579 * ioapic entry from outside of irq context starting
2580 * with masking the ioapic entry and then polling until
2581 * Remote IRR was clear before reprogramming the
2582 * ioapic I don't trust the Remote IRR bit to be
2583 * completey accurate.
2585 * However there appears to be no other way to plug
2586 * this race, so if the Remote IRR bit is not
2587 * accurate and is causing problems then it is a hardware bug
2588 * and you can go talk to the chipset vendor about it.
2590 cfg
= desc
->chip_data
;
2591 if (!io_apic_level_ack_pending(cfg
))
2592 move_masked_irq(irq
);
2593 unmask_IO_APIC_irq_desc(desc
);
2596 #ifdef CONFIG_X86_32
2597 if (!(v
& (1 << (i
& 0x1f)))) {
2598 atomic_inc(&irq_mis_count
);
2599 spin_lock(&ioapic_lock
);
2600 __mask_and_edge_IO_APIC_irq(cfg
);
2601 __unmask_and_level_IO_APIC_irq(cfg
);
2602 spin_unlock(&ioapic_lock
);
2607 #ifdef CONFIG_INTR_REMAP
2608 static void __eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
2611 struct irq_pin_list
*entry
;
2613 entry
= cfg
->irq_2_pin
;
2621 io_apic_eoi(apic
, pin
);
2622 entry
= entry
->next
;
2627 eoi_ioapic_irq(struct irq_desc
*desc
)
2629 struct irq_cfg
*cfg
;
2630 unsigned long flags
;
2634 cfg
= desc
->chip_data
;
2636 spin_lock_irqsave(&ioapic_lock
, flags
);
2637 __eoi_ioapic_irq(irq
, cfg
);
2638 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2641 static void ir_ack_apic_edge(unsigned int irq
)
2646 static void ir_ack_apic_level(unsigned int irq
)
2648 struct irq_desc
*desc
= irq_to_desc(irq
);
2651 eoi_ioapic_irq(desc
);
2653 #endif /* CONFIG_INTR_REMAP */
2655 static struct irq_chip ioapic_chip __read_mostly
= {
2657 .startup
= startup_ioapic_irq
,
2658 .mask
= mask_IO_APIC_irq
,
2659 .unmask
= unmask_IO_APIC_irq
,
2660 .ack
= ack_apic_edge
,
2661 .eoi
= ack_apic_level
,
2663 .set_affinity
= set_ioapic_affinity_irq
,
2665 .retrigger
= ioapic_retrigger_irq
,
2668 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2669 .name
= "IR-IO-APIC",
2670 .startup
= startup_ioapic_irq
,
2671 .mask
= mask_IO_APIC_irq
,
2672 .unmask
= unmask_IO_APIC_irq
,
2673 #ifdef CONFIG_INTR_REMAP
2674 .ack
= ir_ack_apic_edge
,
2675 .eoi
= ir_ack_apic_level
,
2677 .set_affinity
= set_ir_ioapic_affinity_irq
,
2680 .retrigger
= ioapic_retrigger_irq
,
2683 static inline void init_IO_APIC_traps(void)
2686 struct irq_desc
*desc
;
2687 struct irq_cfg
*cfg
;
2690 * NOTE! The local APIC isn't very good at handling
2691 * multiple interrupts at the same interrupt level.
2692 * As the interrupt level is determined by taking the
2693 * vector number and shifting that right by 4, we
2694 * want to spread these out a bit so that they don't
2695 * all fall in the same interrupt level.
2697 * Also, we've got to be careful not to trash gate
2698 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2700 for_each_irq_desc(irq
, desc
) {
2701 cfg
= desc
->chip_data
;
2702 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2704 * Hmm.. We don't have an entry for this,
2705 * so default to an old-fashioned 8259
2706 * interrupt if we can..
2708 if (irq
< NR_IRQS_LEGACY
)
2709 make_8259A_irq(irq
);
2711 /* Strange. Oh, well.. */
2712 desc
->chip
= &no_irq_chip
;
2718 * The local APIC irq-chip implementation:
2721 static void mask_lapic_irq(unsigned int irq
)
2725 v
= apic_read(APIC_LVT0
);
2726 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2729 static void unmask_lapic_irq(unsigned int irq
)
2733 v
= apic_read(APIC_LVT0
);
2734 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2737 static void ack_lapic_irq(unsigned int irq
)
2742 static struct irq_chip lapic_chip __read_mostly
= {
2743 .name
= "local-APIC",
2744 .mask
= mask_lapic_irq
,
2745 .unmask
= unmask_lapic_irq
,
2746 .ack
= ack_lapic_irq
,
2749 static void lapic_register_intr(int irq
, struct irq_desc
*desc
)
2751 desc
->status
&= ~IRQ_LEVEL
;
2752 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2756 static void __init
setup_nmi(void)
2759 * Dirty trick to enable the NMI watchdog ...
2760 * We put the 8259A master into AEOI mode and
2761 * unmask on all local APICs LVT0 as NMI.
2763 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2764 * is from Maciej W. Rozycki - so we do not have to EOI from
2765 * the NMI handler or the timer interrupt.
2767 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2769 enable_NMI_through_LVT0();
2771 apic_printk(APIC_VERBOSE
, " done.\n");
2775 * This looks a bit hackish but it's about the only one way of sending
2776 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2777 * not support the ExtINT mode, unfortunately. We need to send these
2778 * cycles as some i82489DX-based boards have glue logic that keeps the
2779 * 8259A interrupt line asserted until INTA. --macro
2781 static inline void __init
unlock_ExtINT_logic(void)
2784 struct IO_APIC_route_entry entry0
, entry1
;
2785 unsigned char save_control
, save_freq_select
;
2787 pin
= find_isa_irq_pin(8, mp_INT
);
2792 apic
= find_isa_irq_apic(8, mp_INT
);
2798 entry0
= ioapic_read_entry(apic
, pin
);
2799 clear_IO_APIC_pin(apic
, pin
);
2801 memset(&entry1
, 0, sizeof(entry1
));
2803 entry1
.dest_mode
= 0; /* physical delivery */
2804 entry1
.mask
= 0; /* unmask IRQ now */
2805 entry1
.dest
= hard_smp_processor_id();
2806 entry1
.delivery_mode
= dest_ExtINT
;
2807 entry1
.polarity
= entry0
.polarity
;
2811 ioapic_write_entry(apic
, pin
, entry1
);
2813 save_control
= CMOS_READ(RTC_CONTROL
);
2814 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2815 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2817 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2822 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2826 CMOS_WRITE(save_control
, RTC_CONTROL
);
2827 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2828 clear_IO_APIC_pin(apic
, pin
);
2830 ioapic_write_entry(apic
, pin
, entry0
);
2833 static int disable_timer_pin_1 __initdata
;
2834 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2835 static int __init
disable_timer_pin_setup(char *arg
)
2837 disable_timer_pin_1
= 1;
2840 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2842 int timer_through_8259 __initdata
;
2845 * This code may look a bit paranoid, but it's supposed to cooperate with
2846 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2847 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2848 * fanatically on his truly buggy board.
2850 * FIXME: really need to revamp this for all platforms.
2852 static inline void __init
check_timer(void)
2854 struct irq_desc
*desc
= irq_to_desc(0);
2855 struct irq_cfg
*cfg
= desc
->chip_data
;
2856 int node
= cpu_to_node(boot_cpu_id
);
2857 int apic1
, pin1
, apic2
, pin2
;
2858 unsigned long flags
;
2861 local_irq_save(flags
);
2864 * get/set the timer IRQ vector:
2866 disable_8259A_irq(0);
2867 assign_irq_vector(0, cfg
, apic
->target_cpus());
2870 * As IRQ0 is to be enabled in the 8259A, the virtual
2871 * wire has to be disabled in the local APIC. Also
2872 * timer interrupts need to be acknowledged manually in
2873 * the 8259A for the i82489DX when using the NMI
2874 * watchdog as that APIC treats NMIs as level-triggered.
2875 * The AEOI mode will finish them in the 8259A
2878 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2880 #ifdef CONFIG_X86_32
2884 ver
= apic_read(APIC_LVR
);
2885 ver
= GET_APIC_VERSION(ver
);
2886 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2890 pin1
= find_isa_irq_pin(0, mp_INT
);
2891 apic1
= find_isa_irq_apic(0, mp_INT
);
2892 pin2
= ioapic_i8259
.pin
;
2893 apic2
= ioapic_i8259
.apic
;
2895 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2896 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2897 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2900 * Some BIOS writers are clueless and report the ExtINTA
2901 * I/O APIC input from the cascaded 8259A as the timer
2902 * interrupt input. So just in case, if only one pin
2903 * was found above, try it both directly and through the
2907 if (intr_remapping_enabled
)
2908 panic("BIOS bug: timer not connected to IO-APIC");
2912 } else if (pin2
== -1) {
2919 * Ok, does IRQ0 through the IOAPIC work?
2922 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
2923 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2925 /* for edge trigger, setup_IO_APIC_irq already
2926 * leave it unmasked.
2927 * so only need to unmask if it is level-trigger
2928 * do we really have level trigger timer?
2931 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2932 if (idx
!= -1 && irq_trigger(idx
))
2933 unmask_IO_APIC_irq_desc(desc
);
2935 if (timer_irq_works()) {
2936 if (nmi_watchdog
== NMI_IO_APIC
) {
2938 enable_8259A_irq(0);
2940 if (disable_timer_pin_1
> 0)
2941 clear_IO_APIC_pin(0, pin1
);
2944 if (intr_remapping_enabled
)
2945 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2946 local_irq_disable();
2947 clear_IO_APIC_pin(apic1
, pin1
);
2949 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2950 "8254 timer not connected to IO-APIC\n");
2952 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2953 "(IRQ0) through the 8259A ...\n");
2954 apic_printk(APIC_QUIET
, KERN_INFO
2955 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2957 * legacy devices should be connected to IO APIC #0
2959 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
2960 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2961 enable_8259A_irq(0);
2962 if (timer_irq_works()) {
2963 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2964 timer_through_8259
= 1;
2965 if (nmi_watchdog
== NMI_IO_APIC
) {
2966 disable_8259A_irq(0);
2968 enable_8259A_irq(0);
2973 * Cleanup, just in case ...
2975 local_irq_disable();
2976 disable_8259A_irq(0);
2977 clear_IO_APIC_pin(apic2
, pin2
);
2978 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2981 if (nmi_watchdog
== NMI_IO_APIC
) {
2982 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2983 "through the IO-APIC - disabling NMI Watchdog!\n");
2984 nmi_watchdog
= NMI_NONE
;
2986 #ifdef CONFIG_X86_32
2990 apic_printk(APIC_QUIET
, KERN_INFO
2991 "...trying to set up timer as Virtual Wire IRQ...\n");
2993 lapic_register_intr(0, desc
);
2994 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2995 enable_8259A_irq(0);
2997 if (timer_irq_works()) {
2998 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3001 local_irq_disable();
3002 disable_8259A_irq(0);
3003 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
3004 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
3006 apic_printk(APIC_QUIET
, KERN_INFO
3007 "...trying to set up timer as ExtINT IRQ...\n");
3011 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
3013 unlock_ExtINT_logic();
3015 if (timer_irq_works()) {
3016 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3019 local_irq_disable();
3020 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
3021 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3022 "report. Then try booting with the 'noapic' option.\n");
3024 local_irq_restore(flags
);
3028 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3029 * to devices. However there may be an I/O APIC pin available for
3030 * this interrupt regardless. The pin may be left unconnected, but
3031 * typically it will be reused as an ExtINT cascade interrupt for
3032 * the master 8259A. In the MPS case such a pin will normally be
3033 * reported as an ExtINT interrupt in the MP table. With ACPI
3034 * there is no provision for ExtINT interrupts, and in the absence
3035 * of an override it would be treated as an ordinary ISA I/O APIC
3036 * interrupt, that is edge-triggered and unmasked by default. We
3037 * used to do this, but it caused problems on some systems because
3038 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3039 * the same ExtINT cascade interrupt to drive the local APIC of the
3040 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3041 * the I/O APIC in all cases now. No actual device should request
3042 * it anyway. --macro
3044 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3046 void __init
setup_IO_APIC(void)
3050 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3053 io_apic_irqs
= ~PIC_IRQS
;
3055 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
3057 * Set up IO-APIC IRQ routing.
3059 #ifdef CONFIG_X86_32
3061 setup_ioapic_ids_from_mpc();
3064 setup_IO_APIC_irqs();
3065 init_IO_APIC_traps();
3070 * Called after all the initialization is done. If we didnt find any
3071 * APIC bugs then we can allow the modify fast path
3074 static int __init
io_apic_bug_finalize(void)
3076 if (sis_apic_bug
== -1)
3081 late_initcall(io_apic_bug_finalize
);
3083 struct sysfs_ioapic_data
{
3084 struct sys_device dev
;
3085 struct IO_APIC_route_entry entry
[0];
3087 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
3089 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
3091 struct IO_APIC_route_entry
*entry
;
3092 struct sysfs_ioapic_data
*data
;
3095 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3096 entry
= data
->entry
;
3097 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
3098 *entry
= ioapic_read_entry(dev
->id
, i
);
3103 static int ioapic_resume(struct sys_device
*dev
)
3105 struct IO_APIC_route_entry
*entry
;
3106 struct sysfs_ioapic_data
*data
;
3107 unsigned long flags
;
3108 union IO_APIC_reg_00 reg_00
;
3111 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3112 entry
= data
->entry
;
3114 spin_lock_irqsave(&ioapic_lock
, flags
);
3115 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3116 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].apicid
) {
3117 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].apicid
;
3118 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3120 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3121 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3122 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3127 static struct sysdev_class ioapic_sysdev_class
= {
3129 .suspend
= ioapic_suspend
,
3130 .resume
= ioapic_resume
,
3133 static int __init
ioapic_init_sysfs(void)
3135 struct sys_device
* dev
;
3138 error
= sysdev_class_register(&ioapic_sysdev_class
);
3142 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3143 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3144 * sizeof(struct IO_APIC_route_entry
);
3145 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3146 if (!mp_ioapic_data
[i
]) {
3147 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3150 dev
= &mp_ioapic_data
[i
]->dev
;
3152 dev
->cls
= &ioapic_sysdev_class
;
3153 error
= sysdev_register(dev
);
3155 kfree(mp_ioapic_data
[i
]);
3156 mp_ioapic_data
[i
] = NULL
;
3157 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3165 device_initcall(ioapic_init_sysfs
);
3167 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
3169 * Dynamic irq allocate and deallocation
3171 unsigned int create_irq_nr(unsigned int irq_want
, int node
)
3173 /* Allocate an unused irq */
3176 unsigned long flags
;
3177 struct irq_cfg
*cfg_new
= NULL
;
3178 struct irq_desc
*desc_new
= NULL
;
3181 if (irq_want
< nr_irqs_gsi
)
3182 irq_want
= nr_irqs_gsi
;
3184 spin_lock_irqsave(&vector_lock
, flags
);
3185 for (new = irq_want
; new < nr_irqs
; new++) {
3186 desc_new
= irq_to_desc_alloc_node(new, node
);
3188 printk(KERN_INFO
"can not get irq_desc for %d\n", new);
3191 cfg_new
= desc_new
->chip_data
;
3193 if (cfg_new
->vector
!= 0)
3196 desc_new
= move_irq_desc(desc_new
, node
);
3198 if (__assign_irq_vector(new, cfg_new
, apic
->target_cpus()) == 0)
3202 spin_unlock_irqrestore(&vector_lock
, flags
);
3205 dynamic_irq_init(irq
);
3206 /* restore it, in case dynamic_irq_init clear it */
3208 desc_new
->chip_data
= cfg_new
;
3213 int create_irq(void)
3215 int node
= cpu_to_node(boot_cpu_id
);
3216 unsigned int irq_want
;
3219 irq_want
= nr_irqs_gsi
;
3220 irq
= create_irq_nr(irq_want
, node
);
3228 void destroy_irq(unsigned int irq
)
3230 unsigned long flags
;
3231 struct irq_cfg
*cfg
;
3232 struct irq_desc
*desc
;
3234 /* store it, in case dynamic_irq_cleanup clear it */
3235 desc
= irq_to_desc(irq
);
3236 cfg
= desc
->chip_data
;
3237 dynamic_irq_cleanup(irq
);
3238 /* connect back irq_cfg */
3240 desc
->chip_data
= cfg
;
3243 spin_lock_irqsave(&vector_lock
, flags
);
3244 __clear_irq_vector(irq
, cfg
);
3245 spin_unlock_irqrestore(&vector_lock
, flags
);
3249 * MSI message composition
3251 #ifdef CONFIG_PCI_MSI
3252 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
3254 struct irq_cfg
*cfg
;
3262 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3266 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
3268 if (irq_remapped(irq
)) {
3273 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3274 BUG_ON(ir_index
== -1);
3276 memset (&irte
, 0, sizeof(irte
));
3279 irte
.dst_mode
= apic
->irq_dest_mode
;
3280 irte
.trigger_mode
= 0; /* edge */
3281 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
3282 irte
.vector
= cfg
->vector
;
3283 irte
.dest_id
= IRTE_DEST(dest
);
3285 modify_irte(irq
, &irte
);
3287 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3288 msg
->data
= sub_handle
;
3289 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3291 MSI_ADDR_IR_INDEX1(ir_index
) |
3292 MSI_ADDR_IR_INDEX2(ir_index
);
3294 if (x2apic_enabled())
3295 msg
->address_hi
= MSI_ADDR_BASE_HI
|
3296 MSI_ADDR_EXT_DEST_ID(dest
);
3298 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3302 ((apic
->irq_dest_mode
== 0) ?
3303 MSI_ADDR_DEST_MODE_PHYSICAL
:
3304 MSI_ADDR_DEST_MODE_LOGICAL
) |
3305 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3306 MSI_ADDR_REDIRECTION_CPU
:
3307 MSI_ADDR_REDIRECTION_LOWPRI
) |
3308 MSI_ADDR_DEST_ID(dest
);
3311 MSI_DATA_TRIGGER_EDGE
|
3312 MSI_DATA_LEVEL_ASSERT
|
3313 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3314 MSI_DATA_DELIVERY_FIXED
:
3315 MSI_DATA_DELIVERY_LOWPRI
) |
3316 MSI_DATA_VECTOR(cfg
->vector
);
3322 static int set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3324 struct irq_desc
*desc
= irq_to_desc(irq
);
3325 struct irq_cfg
*cfg
;
3329 dest
= set_desc_affinity(desc
, mask
);
3330 if (dest
== BAD_APICID
)
3333 cfg
= desc
->chip_data
;
3335 read_msi_msg_desc(desc
, &msg
);
3337 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3338 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3339 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3340 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3342 write_msi_msg_desc(desc
, &msg
);
3346 #ifdef CONFIG_INTR_REMAP
3348 * Migrate the MSI irq to another cpumask. This migration is
3349 * done in the process context using interrupt-remapping hardware.
3352 ir_set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3354 struct irq_desc
*desc
= irq_to_desc(irq
);
3355 struct irq_cfg
*cfg
= desc
->chip_data
;
3359 if (get_irte(irq
, &irte
))
3362 dest
= set_desc_affinity(desc
, mask
);
3363 if (dest
== BAD_APICID
)
3366 irte
.vector
= cfg
->vector
;
3367 irte
.dest_id
= IRTE_DEST(dest
);
3370 * atomically update the IRTE with the new destination and vector.
3372 modify_irte(irq
, &irte
);
3375 * After this point, all the interrupts will start arriving
3376 * at the new destination. So, time to cleanup the previous
3377 * vector allocation.
3379 if (cfg
->move_in_progress
)
3380 send_cleanup_vector(cfg
);
3386 #endif /* CONFIG_SMP */
3389 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3390 * which implement the MSI or MSI-X Capability Structure.
3392 static struct irq_chip msi_chip
= {
3394 .unmask
= unmask_msi_irq
,
3395 .mask
= mask_msi_irq
,
3396 .ack
= ack_apic_edge
,
3398 .set_affinity
= set_msi_irq_affinity
,
3400 .retrigger
= ioapic_retrigger_irq
,
3403 static struct irq_chip msi_ir_chip
= {
3404 .name
= "IR-PCI-MSI",
3405 .unmask
= unmask_msi_irq
,
3406 .mask
= mask_msi_irq
,
3407 #ifdef CONFIG_INTR_REMAP
3408 .ack
= ir_ack_apic_edge
,
3410 .set_affinity
= ir_set_msi_irq_affinity
,
3413 .retrigger
= ioapic_retrigger_irq
,
3417 * Map the PCI dev to the corresponding remapping hardware unit
3418 * and allocate 'nvec' consecutive interrupt-remapping table entries
3421 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3423 struct intel_iommu
*iommu
;
3426 iommu
= map_dev_to_ir(dev
);
3429 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3433 index
= alloc_irte(iommu
, irq
, nvec
);
3436 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3443 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3448 ret
= msi_compose_msg(dev
, irq
, &msg
);
3452 set_irq_msi(irq
, msidesc
);
3453 write_msi_msg(irq
, &msg
);
3455 if (irq_remapped(irq
)) {
3456 struct irq_desc
*desc
= irq_to_desc(irq
);
3458 * irq migration in process context
3460 desc
->status
|= IRQ_MOVE_PCNTXT
;
3461 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3463 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3465 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3470 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3473 int ret
, sub_handle
;
3474 struct msi_desc
*msidesc
;
3475 unsigned int irq_want
;
3476 struct intel_iommu
*iommu
= NULL
;
3480 /* x86 doesn't support multiple MSI yet */
3481 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3484 node
= dev_to_node(&dev
->dev
);
3485 irq_want
= nr_irqs_gsi
;
3487 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3488 irq
= create_irq_nr(irq_want
, node
);
3492 if (!intr_remapping_enabled
)
3497 * allocate the consecutive block of IRTE's
3500 index
= msi_alloc_irte(dev
, irq
, nvec
);
3506 iommu
= map_dev_to_ir(dev
);
3512 * setup the mapping between the irq and the IRTE
3513 * base index, the sub_handle pointing to the
3514 * appropriate interrupt remap table entry.
3516 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3519 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3531 void arch_teardown_msi_irq(unsigned int irq
)
3536 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3538 static int dmar_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3540 struct irq_desc
*desc
= irq_to_desc(irq
);
3541 struct irq_cfg
*cfg
;
3545 dest
= set_desc_affinity(desc
, mask
);
3546 if (dest
== BAD_APICID
)
3549 cfg
= desc
->chip_data
;
3551 dmar_msi_read(irq
, &msg
);
3553 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3554 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3555 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3556 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3558 dmar_msi_write(irq
, &msg
);
3563 #endif /* CONFIG_SMP */
3565 struct irq_chip dmar_msi_type
= {
3567 .unmask
= dmar_msi_unmask
,
3568 .mask
= dmar_msi_mask
,
3569 .ack
= ack_apic_edge
,
3571 .set_affinity
= dmar_msi_set_affinity
,
3573 .retrigger
= ioapic_retrigger_irq
,
3576 int arch_setup_dmar_msi(unsigned int irq
)
3581 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3584 dmar_msi_write(irq
, &msg
);
3585 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3591 #ifdef CONFIG_HPET_TIMER
3594 static int hpet_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3596 struct irq_desc
*desc
= irq_to_desc(irq
);
3597 struct irq_cfg
*cfg
;
3601 dest
= set_desc_affinity(desc
, mask
);
3602 if (dest
== BAD_APICID
)
3605 cfg
= desc
->chip_data
;
3607 hpet_msi_read(irq
, &msg
);
3609 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3610 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3611 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3612 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3614 hpet_msi_write(irq
, &msg
);
3619 #endif /* CONFIG_SMP */
3621 static struct irq_chip hpet_msi_type
= {
3623 .unmask
= hpet_msi_unmask
,
3624 .mask
= hpet_msi_mask
,
3625 .ack
= ack_apic_edge
,
3627 .set_affinity
= hpet_msi_set_affinity
,
3629 .retrigger
= ioapic_retrigger_irq
,
3632 int arch_setup_hpet_msi(unsigned int irq
)
3636 struct irq_desc
*desc
= irq_to_desc(irq
);
3638 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3642 hpet_msi_write(irq
, &msg
);
3643 desc
->status
|= IRQ_MOVE_PCNTXT
;
3644 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
, handle_edge_irq
,
3651 #endif /* CONFIG_PCI_MSI */
3653 * Hypertransport interrupt support
3655 #ifdef CONFIG_HT_IRQ
3659 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3661 struct ht_irq_msg msg
;
3662 fetch_ht_irq_msg(irq
, &msg
);
3664 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3665 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3667 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3668 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3670 write_ht_irq_msg(irq
, &msg
);
3673 static int set_ht_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3675 struct irq_desc
*desc
= irq_to_desc(irq
);
3676 struct irq_cfg
*cfg
;
3679 dest
= set_desc_affinity(desc
, mask
);
3680 if (dest
== BAD_APICID
)
3683 cfg
= desc
->chip_data
;
3685 target_ht_irq(irq
, dest
, cfg
->vector
);
3692 static struct irq_chip ht_irq_chip
= {
3694 .mask
= mask_ht_irq
,
3695 .unmask
= unmask_ht_irq
,
3696 .ack
= ack_apic_edge
,
3698 .set_affinity
= set_ht_irq_affinity
,
3700 .retrigger
= ioapic_retrigger_irq
,
3703 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3705 struct irq_cfg
*cfg
;
3712 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3714 struct ht_irq_msg msg
;
3717 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3718 apic
->target_cpus());
3720 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3724 HT_IRQ_LOW_DEST_ID(dest
) |
3725 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3726 ((apic
->irq_dest_mode
== 0) ?
3727 HT_IRQ_LOW_DM_PHYSICAL
:
3728 HT_IRQ_LOW_DM_LOGICAL
) |
3729 HT_IRQ_LOW_RQEOI_EDGE
|
3730 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3731 HT_IRQ_LOW_MT_FIXED
:
3732 HT_IRQ_LOW_MT_ARBITRATED
) |
3733 HT_IRQ_LOW_IRQ_MASKED
;
3735 write_ht_irq_msg(irq
, &msg
);
3737 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3738 handle_edge_irq
, "edge");
3740 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3744 #endif /* CONFIG_HT_IRQ */
3746 #ifdef CONFIG_X86_UV
3748 * Re-target the irq to the specified CPU and enable the specified MMR located
3749 * on the specified blade to allow the sending of MSIs to the specified CPU.
3751 int arch_enable_uv_irq(char *irq_name
, unsigned int irq
, int cpu
, int mmr_blade
,
3752 unsigned long mmr_offset
)
3754 const struct cpumask
*eligible_cpu
= cpumask_of(cpu
);
3755 struct irq_cfg
*cfg
;
3757 unsigned long mmr_value
;
3758 struct uv_IO_APIC_route_entry
*entry
;
3759 unsigned long flags
;
3762 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3766 err
= assign_irq_vector(irq
, cfg
, eligible_cpu
);
3770 spin_lock_irqsave(&vector_lock
, flags
);
3771 set_irq_chip_and_handler_name(irq
, &uv_irq_chip
, handle_percpu_irq
,
3773 spin_unlock_irqrestore(&vector_lock
, flags
);
3776 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3777 entry
->vector
= cfg
->vector
;
3778 entry
->delivery_mode
= apic
->irq_delivery_mode
;
3779 entry
->dest_mode
= apic
->irq_dest_mode
;
3780 entry
->polarity
= 0;
3783 entry
->dest
= apic
->cpu_mask_to_apicid(eligible_cpu
);
3785 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3786 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3792 * Disable the specified MMR located on the specified blade so that MSIs are
3793 * longer allowed to be sent.
3795 void arch_disable_uv_irq(int mmr_blade
, unsigned long mmr_offset
)
3797 unsigned long mmr_value
;
3798 struct uv_IO_APIC_route_entry
*entry
;
3801 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3804 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3807 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3808 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3810 #endif /* CONFIG_X86_64 */
3812 int __init
io_apic_get_redir_entries (int ioapic
)
3814 union IO_APIC_reg_01 reg_01
;
3815 unsigned long flags
;
3817 spin_lock_irqsave(&ioapic_lock
, flags
);
3818 reg_01
.raw
= io_apic_read(ioapic
, 1);
3819 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3821 return reg_01
.bits
.entries
;
3824 void __init
probe_nr_irqs_gsi(void)
3828 nr
= acpi_probe_gsi();
3829 if (nr
> nr_irqs_gsi
) {
3832 /* for acpi=off or acpi is not compiled in */
3836 for (idx
= 0; idx
< nr_ioapics
; idx
++)
3837 nr
+= io_apic_get_redir_entries(idx
) + 1;
3839 if (nr
> nr_irqs_gsi
)
3843 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3846 #ifdef CONFIG_SPARSE_IRQ
3847 int __init
arch_probe_nr_irqs(void)
3851 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3852 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3854 nr
= nr_irqs_gsi
+ 8 * nr_cpu_ids
;
3855 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3857 * for MSI and HT dyn irq
3859 nr
+= nr_irqs_gsi
* 16;
3868 static int __io_apic_set_pci_routing(struct device
*dev
, int ioapic
, int pin
, int irq
,
3869 int triggering
, int polarity
)
3871 struct irq_desc
*desc
;
3872 struct irq_cfg
*cfg
;
3875 if (!IO_APIC_IRQ(irq
)) {
3876 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3882 node
= dev_to_node(dev
);
3884 node
= cpu_to_node(boot_cpu_id
);
3886 desc
= irq_to_desc_alloc_node(irq
, node
);
3888 printk(KERN_INFO
"can not get irq_desc %d\n", irq
);
3893 * IRQs < 16 are already in the irq_2_pin[] map
3895 if (irq
>= NR_IRQS_LEGACY
) {
3896 cfg
= desc
->chip_data
;
3897 add_pin_to_irq_node(cfg
, node
, ioapic
, pin
);
3900 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
, triggering
, polarity
);
3905 int io_apic_set_pci_routing(struct device
*dev
, int ioapic
, int pin
, int irq
,
3906 int triggering
, int polarity
)
3910 * Avoid pin reprogramming. PRTs typically include entries
3911 * with redundant pin->gsi mappings (but unique PCI devices);
3912 * we only program the IOAPIC on the first.
3914 if (test_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
)) {
3915 pr_debug("Pin %d-%d already programmed\n",
3916 mp_ioapics
[ioapic
].apicid
, pin
);
3919 set_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
);
3921 return __io_apic_set_pci_routing(dev
, ioapic
, pin
, irq
,
3922 triggering
, polarity
);
3925 /* --------------------------------------------------------------------------
3926 ACPI-based IOAPIC Configuration
3927 -------------------------------------------------------------------------- */
3931 #ifdef CONFIG_X86_32
3932 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3934 union IO_APIC_reg_00 reg_00
;
3935 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3937 unsigned long flags
;
3941 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3942 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3943 * supports up to 16 on one shared APIC bus.
3945 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3946 * advantage of new APIC bus architecture.
3949 if (physids_empty(apic_id_map
))
3950 apic_id_map
= apic
->ioapic_phys_id_map(phys_cpu_present_map
);
3952 spin_lock_irqsave(&ioapic_lock
, flags
);
3953 reg_00
.raw
= io_apic_read(ioapic
, 0);
3954 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3956 if (apic_id
>= get_physical_broadcast()) {
3957 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3958 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3959 apic_id
= reg_00
.bits
.ID
;
3963 * Every APIC in a system must have a unique ID or we get lots of nice
3964 * 'stuck on smp_invalidate_needed IPI wait' messages.
3966 if (apic
->check_apicid_used(apic_id_map
, apic_id
)) {
3968 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3969 if (!apic
->check_apicid_used(apic_id_map
, i
))
3973 if (i
== get_physical_broadcast())
3974 panic("Max apic_id exceeded!\n");
3976 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3977 "trying %d\n", ioapic
, apic_id
, i
);
3982 tmp
= apic
->apicid_to_cpu_present(apic_id
);
3983 physids_or(apic_id_map
, apic_id_map
, tmp
);
3985 if (reg_00
.bits
.ID
!= apic_id
) {
3986 reg_00
.bits
.ID
= apic_id
;
3988 spin_lock_irqsave(&ioapic_lock
, flags
);
3989 io_apic_write(ioapic
, 0, reg_00
.raw
);
3990 reg_00
.raw
= io_apic_read(ioapic
, 0);
3991 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3994 if (reg_00
.bits
.ID
!= apic_id
) {
3995 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
4000 apic_printk(APIC_VERBOSE
, KERN_INFO
4001 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
4006 int __init
io_apic_get_version(int ioapic
)
4008 union IO_APIC_reg_01 reg_01
;
4009 unsigned long flags
;
4011 spin_lock_irqsave(&ioapic_lock
, flags
);
4012 reg_01
.raw
= io_apic_read(ioapic
, 1);
4013 spin_unlock_irqrestore(&ioapic_lock
, flags
);
4015 return reg_01
.bits
.version
;
4019 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
4023 if (skip_ioapic_setup
)
4026 for (i
= 0; i
< mp_irq_entries
; i
++)
4027 if (mp_irqs
[i
].irqtype
== mp_INT
&&
4028 mp_irqs
[i
].srcbusirq
== bus_irq
)
4030 if (i
>= mp_irq_entries
)
4033 *trigger
= irq_trigger(i
);
4034 *polarity
= irq_polarity(i
);
4038 #endif /* CONFIG_ACPI */
4041 * This function currently is only a helper for the i386 smp boot process where
4042 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4043 * so mask in all cases should simply be apic->target_cpus()
4046 void __init
setup_ioapic_dest(void)
4048 int pin
, ioapic
= 0, irq
, irq_entry
;
4049 struct irq_desc
*desc
;
4050 const struct cpumask
*mask
;
4052 if (skip_ioapic_setup
== 1)
4056 if (!acpi_disabled
&& acpi_ioapic
) {
4057 ioapic
= mp_find_ioapic(0);
4063 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
4064 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
4065 if (irq_entry
== -1)
4067 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
4069 desc
= irq_to_desc(irq
);
4072 * Honour affinities which have been set in early boot
4075 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
4076 mask
= desc
->affinity
;
4078 mask
= apic
->target_cpus();
4080 if (intr_remapping_enabled
)
4081 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
4083 set_ioapic_affinity_irq_desc(desc
, mask
);
4089 #define IOAPIC_RESOURCE_NAME_SIZE 11
4091 static struct resource
*ioapic_resources
;
4093 static struct resource
* __init
ioapic_setup_resources(void)
4096 struct resource
*res
;
4100 if (nr_ioapics
<= 0)
4103 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
4106 mem
= alloc_bootmem(n
);
4110 mem
+= sizeof(struct resource
) * nr_ioapics
;
4112 for (i
= 0; i
< nr_ioapics
; i
++) {
4114 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
4115 sprintf(mem
, "IOAPIC %u", i
);
4116 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
4120 ioapic_resources
= res
;
4125 void __init
ioapic_init_mappings(void)
4127 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
4128 struct resource
*ioapic_res
;
4131 ioapic_res
= ioapic_setup_resources();
4132 for (i
= 0; i
< nr_ioapics
; i
++) {
4133 if (smp_found_config
) {
4134 ioapic_phys
= mp_ioapics
[i
].apicaddr
;
4135 #ifdef CONFIG_X86_32
4138 "WARNING: bogus zero IO-APIC "
4139 "address found in MPTABLE, "
4140 "disabling IO/APIC support!\n");
4141 smp_found_config
= 0;
4142 skip_ioapic_setup
= 1;
4143 goto fake_ioapic_page
;
4147 #ifdef CONFIG_X86_32
4150 ioapic_phys
= (unsigned long)
4151 alloc_bootmem_pages(PAGE_SIZE
);
4152 ioapic_phys
= __pa(ioapic_phys
);
4154 set_fixmap_nocache(idx
, ioapic_phys
);
4155 apic_printk(APIC_VERBOSE
,
4156 "mapped IOAPIC to %08lx (%08lx)\n",
4157 __fix_to_virt(idx
), ioapic_phys
);
4160 if (ioapic_res
!= NULL
) {
4161 ioapic_res
->start
= ioapic_phys
;
4162 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
4168 static int __init
ioapic_insert_resources(void)
4171 struct resource
*r
= ioapic_resources
;
4174 if (nr_ioapics
> 0) {
4176 "IO APIC resources couldn't be allocated.\n");
4182 for (i
= 0; i
< nr_ioapics
; i
++) {
4183 insert_resource(&iomem_resource
, r
);
4190 /* Insert the IO APIC resources after PCI initialization has occured to handle
4191 * IO APICS that are mapped in on a BAR in PCI space. */
4192 late_initcall(ioapic_insert_resources
);