arch/x86/kvm/paging_tmpl.h

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * MMU support
   8  *
   9  * Copyright (C) 2006 Qumranet, Inc.
  10  *
  11  * Authors:
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *
  15  * This work is licensed under the terms of the GNU GPL, version 2.  See
  16  * the COPYING file in the top-level directory.
  17  *
  18  */
  19
  20 /*
  21  * We need the mmu code to access both 32-bit and 64-bit guest ptes,
  22  * so the code in this file is compiled twice, once per pte size.
  23  */
  24
  25 #if PTTYPE == 64
  26         #define pt_element_t u64
  27         #define guest_walker guest_walker64
  28         #define shadow_walker shadow_walker64
  29         #define FNAME(name) paging##64_##name
  30         #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
  31         #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
  32         #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
  33         #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
  34         #define PT_LEVEL_BITS PT64_LEVEL_BITS
  35         #ifdef CONFIG_X86_64
  36         #define PT_MAX_FULL_LEVELS 4
  37         #define CMPXCHG cmpxchg
  38         #else
  39         #define CMPXCHG cmpxchg64
  40         #define PT_MAX_FULL_LEVELS 2
  41         #endif
  42 #elif PTTYPE == 32
  43         #define pt_element_t u32
  44         #define guest_walker guest_walker32
  45         #define shadow_walker shadow_walker32
  46         #define FNAME(name) paging##32_##name
  47         #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
  48         #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
  49         #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
  50         #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
  51         #define PT_LEVEL_BITS PT32_LEVEL_BITS
  52         #define PT_MAX_FULL_LEVELS 2
  53         #define CMPXCHG cmpxchg
  54 #else
  55         #error Invalid PTTYPE value
  56 #endif
  57
  58 #define gpte_to_gfn FNAME(gpte_to_gfn)
  59 #define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)
  60
  61 /*
  62  * The guest_walker structure emulates the behavior of the hardware page
  63  * table walker.
  64  */
  65 struct guest_walker {
  66         int level;
  67         gfn_t table_gfn[PT_MAX_FULL_LEVELS];
  68         pt_element_t ptes[PT_MAX_FULL_LEVELS];
  69         gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
  70         unsigned pt_access;
  71         unsigned pte_access;
  72         gfn_t gfn;
  73         u32 error_code;
  74 };
  75
  76 struct shadow_walker {
  77         struct kvm_shadow_walk walker;
  78         struct guest_walker *guest_walker;
  79         int user_fault;
  80         int write_fault;
  81         int largepage;
  82         int *ptwrite;
  83         pfn_t pfn;
  84         u64 *sptep;
  85 };
  86
  87 static gfn_t gpte_to_gfn(pt_element_t gpte)
  88 {
  89         return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
  90 }
  91
  92 static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
  93 {
  94         return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
  95 }
  96
  97 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
  98                          gfn_t table_gfn, unsigned index,
  99                          pt_element_t orig_pte, pt_element_t new_pte)
 100 {
 101         pt_element_t ret;
 102         pt_element_t *table;
 103         struct page *page;
 104
 105         page = gfn_to_page(kvm, table_gfn);
 106
 107         table = kmap_atomic(page, KM_USER0);
 108         ret = CMPXCHG(&table[index], orig_pte, new_pte);
 109         kunmap_atomic(table, KM_USER0);
 110
 111         kvm_release_page_dirty(page);
 112
 113         return (ret != orig_pte);
 114 }
 115
 116 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
 117 {
 118         unsigned access;
 119
 120         access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
 121 #if PTTYPE == 64
 122         if (is_nx(vcpu))
 123                 access &= ~(gpte >> PT64_NX_SHIFT);
 124 #endif
 125         return access;
 126 }
 127
 128 /*
 129  * Fetch a guest pte for a guest virtual address
 130  */
 131 static int FNAME(walk_addr)(struct guest_walker *walker,
 132                             struct kvm_vcpu *vcpu, gva_t addr,
 133                             int write_fault, int user_fault, int fetch_fault)
 134 {
 135         pt_element_t pte;
 136         gfn_t table_gfn;
 137         unsigned index, pt_access, pte_access;
 138         gpa_t pte_gpa;
 139
 140         pgprintk("%s: addr %lx\n", __func__, addr);
 141 walk:
 142         walker->level = vcpu->arch.mmu.root_level;
 143         pte = vcpu->arch.cr3;
 144 #if PTTYPE == 64
 145         if (!is_long_mode(vcpu)) {
 146                 pte = vcpu->arch.pdptrs[(addr >> 30) & 3];
 147                 if (!is_present_pte(pte))
 148                         goto not_present;
 149                 --walker->level;
 150         }
 151 #endif
 152         ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
 153                (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
 154
 155         pt_access = ACC_ALL;
 156
 157         for (;;) {
 158                 index = PT_INDEX(addr, walker->level);
 159
 160                 table_gfn = gpte_to_gfn(pte);
 161                 pte_gpa = gfn_to_gpa(table_gfn);
 162                 pte_gpa += index * sizeof(pt_element_t);
 163                 walker->table_gfn[walker->level - 1] = table_gfn;
 164                 walker->pte_gpa[walker->level - 1] = pte_gpa;
 165                 pgprintk("%s: table_gfn[%d] %lx\n", __func__,
 166                          walker->level - 1, table_gfn);
 167
 168                 kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
 169
 170                 if (!is_present_pte(pte))
 171                         goto not_present;
 172
 173                 if (write_fault && !is_writeble_pte(pte))
 174                         if (user_fault || is_write_protection(vcpu))
 175                                 goto access_error;
 176
 177                 if (user_fault && !(pte & PT_USER_MASK))
 178                         goto access_error;
 179
 180 #if PTTYPE == 64
 181                 if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
 182                         goto access_error;
 183 #endif
 184
 185                 if (!(pte & PT_ACCESSED_MASK)) {
 186                         mark_page_dirty(vcpu->kvm, table_gfn);
 187                         if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
 188                             index, pte, pte|PT_ACCESSED_MASK))
 189                                 goto walk;
 190                         pte |= PT_ACCESSED_MASK;
 191                 }
 192
 193                 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
 194
 195                 walker->ptes[walker->level - 1] = pte;
 196
 197                 if (walker->level == PT_PAGE_TABLE_LEVEL) {
 198                         walker->gfn = gpte_to_gfn(pte);
 199                         break;
 200                 }
 201
 202                 if (walker->level == PT_DIRECTORY_LEVEL
 203                     && (pte & PT_PAGE_SIZE_MASK)
 204                     && (PTTYPE == 64 || is_pse(vcpu))) {
 205                         walker->gfn = gpte_to_gfn_pde(pte);
 206                         walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
 207                         if (PTTYPE == 32 && is_cpuid_PSE36())
 208                                 walker->gfn += pse36_gfn_delta(pte);
 209                         break;
 210                 }
 211
 212                 pt_access = pte_access;
 213                 --walker->level;
 214         }
 215
 216         if (write_fault && !is_dirty_pte(pte)) {
 217                 bool ret;
 218
 219                 mark_page_dirty(vcpu->kvm, table_gfn);
 220                 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
 221                             pte|PT_DIRTY_MASK);
 222                 if (ret)
 223                         goto walk;
 224                 pte |= PT_DIRTY_MASK;
 225                 kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
 226                 walker->ptes[walker->level - 1] = pte;
 227         }
 228
 229         walker->pt_access = pt_access;
 230         walker->pte_access = pte_access;
 231         pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
 232                  __func__, (u64)pte, pt_access, pte_access);
 233         return 1;
 234
 235 not_present:
 236         walker->error_code = 0;
 237         goto err;
 238
 239 access_error:
 240         walker->error_code = PFERR_PRESENT_MASK;
 241
 242 err:
 243         if (write_fault)
 244                 walker->error_code |= PFERR_WRITE_MASK;
 245         if (user_fault)
 246                 walker->error_code |= PFERR_USER_MASK;
 247         if (fetch_fault)
 248                 walker->error_code |= PFERR_FETCH_MASK;
 249         return 0;
 250 }
 251
 252 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
 253                               u64 *spte, const void *pte)
 254 {
 255         pt_element_t gpte;
 256         unsigned pte_access;
 257         pfn_t pfn;
 258         int largepage = vcpu->arch.update_pte.largepage;
 259
 260         gpte = *(const pt_element_t *)pte;
 261         if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
 262                 if (!is_present_pte(gpte))
 263                         set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
 264                 return;
 265         }
 266         pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
 267         pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
 268         if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
 269                 return;
 270         pfn = vcpu->arch.update_pte.pfn;
 271         if (is_error_pfn(pfn))
 272                 return;
 273         if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
 274                 return;
 275         kvm_get_pfn(pfn);
 276         mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
 277                      gpte & PT_DIRTY_MASK, NULL, largepage, gpte_to_gfn(gpte),
 278                      pfn, true);
 279 }
 280
 281 /*
 282  * Fetch a shadow pte for a specific level in the paging hierarchy.
 283  */
 284 static int FNAME(shadow_walk_entry)(struct kvm_shadow_walk *_sw,
 285                                     struct kvm_vcpu *vcpu, u64 addr,
 286                                     u64 *sptep, int level)
 287 {
 288         struct shadow_walker *sw =
 289                 container_of(_sw, struct shadow_walker, walker);
 290         struct guest_walker *gw = sw->guest_walker;
 291         unsigned access = gw->pt_access;
 292         struct kvm_mmu_page *shadow_page;
 293         u64 spte;
 294         int metaphysical;
 295         gfn_t table_gfn;
 296         int r;
 297         pt_element_t curr_pte;
 298
 299         if (level == PT_PAGE_TABLE_LEVEL
 300             || (sw->largepage && level == PT_DIRECTORY_LEVEL)) {
 301                 mmu_set_spte(vcpu, sptep, access, gw->pte_access & access,
 302                              sw->user_fault, sw->write_fault,
 303                              gw->ptes[gw->level-1] & PT_DIRTY_MASK,
 304                              sw->ptwrite, sw->largepage, gw->gfn, sw->pfn,
 305                              false);
 306                 sw->sptep = sptep;
 307                 return 1;
 308         }
 309
 310         if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep))
 311                 return 0;
 312
 313         if (is_large_pte(*sptep)) {
 314                 set_shadow_pte(sptep, shadow_trap_nonpresent_pte);
 315                 kvm_flush_remote_tlbs(vcpu->kvm);
 316                 rmap_remove(vcpu->kvm, sptep);
 317         }
 318
 319         if (level == PT_DIRECTORY_LEVEL && gw->level == PT_DIRECTORY_LEVEL) {
 320                 metaphysical = 1;
 321                 if (!is_dirty_pte(gw->ptes[level - 1]))
 322                         access &= ~ACC_WRITE_MASK;
 323                 table_gfn = gpte_to_gfn(gw->ptes[level - 1]);
 324         } else {
 325                 metaphysical = 0;
 326                 table_gfn = gw->table_gfn[level - 2];
 327         }
 328         shadow_page = kvm_mmu_get_page(vcpu, table_gfn, (gva_t)addr, level-1,
 329                                        metaphysical, access, sptep);
 330         if (!metaphysical) {
 331                 r = kvm_read_guest_atomic(vcpu->kvm, gw->pte_gpa[level - 2],
 332                                           &curr_pte, sizeof(curr_pte));
 333                 if (r || curr_pte != gw->ptes[level - 2]) {
 334                         kvm_release_pfn_clean(sw->pfn);
 335                         sw->sptep = NULL;
 336                         return 1;
 337                 }
 338         }
 339
 340         spte = __pa(shadow_page->spt) | PT_PRESENT_MASK | PT_ACCESSED_MASK
 341                 | PT_WRITABLE_MASK | PT_USER_MASK;
 342         *sptep = spte;
 343         return 0;
 344 }
 345
 346 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
 347                          struct guest_walker *guest_walker,
 348                          int user_fault, int write_fault, int largepage,
 349                          int *ptwrite, pfn_t pfn)
 350 {
 351         struct shadow_walker walker = {
 352                 .walker = { .entry = FNAME(shadow_walk_entry), },
 353                 .guest_walker = guest_walker,
 354                 .user_fault = user_fault,
 355                 .write_fault = write_fault,
 356                 .largepage = largepage,
 357                 .ptwrite = ptwrite,
 358                 .pfn = pfn,
 359         };
 360
 361         if (!is_present_pte(guest_walker->ptes[guest_walker->level - 1]))
 362                 return NULL;
 363
 364         walk_shadow(&walker.walker, vcpu, addr);
 365
 366         return walker.sptep;
 367 }
 368
 369 /*
 370  * Page fault handler.  There are several causes for a page fault:
 371  *   - there is no shadow pte for the guest pte
 372  *   - write access through a shadow pte marked read only so that we can set
 373  *     the dirty bit
 374  *   - write access to a shadow pte marked read only so we can update the page
 375  *     dirty bitmap, when userspace requests it
 376  *   - mmio access; in this case we will never install a present shadow pte
 377  *   - normal guest page fault due to the guest pte marked not present, not
 378  *     writable, or not executable
 379  *
 380  *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 381  *           a negative value on error.
 382  */
 383 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
 384                                u32 error_code)
 385 {
 386         int write_fault = error_code & PFERR_WRITE_MASK;
 387         int user_fault = error_code & PFERR_USER_MASK;
 388         int fetch_fault = error_code & PFERR_FETCH_MASK;
 389         struct guest_walker walker;
 390         u64 *shadow_pte;
 391         int write_pt = 0;
 392         int r;
 393         pfn_t pfn;
 394         int largepage = 0;
 395         unsigned long mmu_seq;
 396
 397         pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
 398         kvm_mmu_audit(vcpu, "pre page fault");
 399
 400         r = mmu_topup_memory_caches(vcpu);
 401         if (r)
 402                 return r;
 403
 404         /*
 405          * Look up the shadow pte for the faulting address.
 406          */
 407         r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
 408                              fetch_fault);
 409
 410         /*
 411          * The page is not mapped by the guest.  Let the guest handle it.
 412          */
 413         if (!r) {
 414                 pgprintk("%s: guest page fault\n", __func__);
 415                 inject_page_fault(vcpu, addr, walker.error_code);
 416                 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
 417                 return 0;
 418         }
 419
 420         if (walker.level == PT_DIRECTORY_LEVEL) {
 421                 gfn_t large_gfn;
 422                 large_gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE-1);
 423                 if (is_largepage_backed(vcpu, large_gfn)) {
 424                         walker.gfn = large_gfn;
 425                         largepage = 1;
 426                 }
 427         }
 428         mmu_seq = vcpu->kvm->mmu_notifier_seq;
 429         smp_rmb();
 430         pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
 431
 432         /* mmio */
 433         if (is_error_pfn(pfn)) {
 434                 pgprintk("gfn %lx is mmio\n", walker.gfn);
 435                 kvm_release_pfn_clean(pfn);
 436                 return 1;
 437         }
 438
 439         spin_lock(&vcpu->kvm->mmu_lock);
 440         if (mmu_notifier_retry(vcpu, mmu_seq))
 441                 goto out_unlock;
 442         kvm_mmu_free_some_pages(vcpu);
 443         shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
 444                                   largepage, &write_pt, pfn);
 445
 446         pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
 447                  shadow_pte, *shadow_pte, write_pt);
 448
 449         if (!write_pt)
 450                 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
 451
 452         ++vcpu->stat.pf_fixed;
 453         kvm_mmu_audit(vcpu, "post page fault (fixed)");
 454         spin_unlock(&vcpu->kvm->mmu_lock);
 455
 456         return write_pt;
 457
 458 out_unlock:
 459         spin_unlock(&vcpu->kvm->mmu_lock);
 460         kvm_release_pfn_clean(pfn);
 461         return 0;
 462 }
 463
 464 static int FNAME(shadow_invlpg_entry)(struct kvm_shadow_walk *_sw,
 465                                       struct kvm_vcpu *vcpu, u64 addr,
 466                                       u64 *sptep, int level)
 467 {
 468
 469         if (level == PT_PAGE_TABLE_LEVEL) {
 470                 if (is_shadow_present_pte(*sptep))
 471                         rmap_remove(vcpu->kvm, sptep);
 472                 set_shadow_pte(sptep, shadow_trap_nonpresent_pte);
 473                 return 1;
 474         }
 475         if (!is_shadow_present_pte(*sptep))
 476                 return 1;
 477         return 0;
 478 }
 479
 480 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
 481 {
 482         struct shadow_walker walker = {
 483                 .walker = { .entry = FNAME(shadow_invlpg_entry), },
 484         };
 485
 486         walk_shadow(&walker.walker, vcpu, gva);
 487 }
 488
 489 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
 490 {
 491         struct guest_walker walker;
 492         gpa_t gpa = UNMAPPED_GVA;
 493         int r;
 494
 495         r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
 496
 497         if (r) {
 498                 gpa = gfn_to_gpa(walker.gfn);
 499                 gpa |= vaddr & ~PAGE_MASK;
 500         }
 501
 502         return gpa;
 503 }
 504
 505 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
 506                                  struct kvm_mmu_page *sp)
 507 {
 508         int i, j, offset, r;
 509         pt_element_t pt[256 / sizeof(pt_element_t)];
 510         gpa_t pte_gpa;
 511
 512         if (sp->role.metaphysical
 513             || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
 514                 nonpaging_prefetch_page(vcpu, sp);
 515                 return;
 516         }
 517
 518         pte_gpa = gfn_to_gpa(sp->gfn);
 519         if (PTTYPE == 32) {
 520                 offset = sp->role.quadrant << PT64_LEVEL_BITS;
 521                 pte_gpa += offset * sizeof(pt_element_t);
 522         }
 523
 524         for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
 525                 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
 526                 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
 527                 for (j = 0; j < ARRAY_SIZE(pt); ++j)
 528                         if (r || is_present_pte(pt[j]))
 529                                 sp->spt[i+j] = shadow_trap_nonpresent_pte;
 530                         else
 531                                 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
 532         }
 533 }
 534
 535 /*
 536  * Using the cached information from sp->gfns is safe because:
 537  * - The spte has a reference to the struct page, so the pfn for a given gfn
 538  *   can't change unless all sptes pointing to it are nuked first.
 539  * - Alias changes zap the entire shadow cache.
 540  */
 541 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
 542 {
 543         int i, offset, nr_present;
 544
 545         offset = nr_present = 0;
 546
 547         if (PTTYPE == 32)
 548                 offset = sp->role.quadrant << PT64_LEVEL_BITS;
 549
 550         for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
 551                 unsigned pte_access;
 552                 pt_element_t gpte;
 553                 gpa_t pte_gpa;
 554                 gfn_t gfn = sp->gfns[i];
 555
 556                 if (!is_shadow_present_pte(sp->spt[i]))
 557                         continue;
 558
 559                 pte_gpa = gfn_to_gpa(sp->gfn);
 560                 pte_gpa += (i+offset) * sizeof(pt_element_t);
 561
 562                 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
 563                                           sizeof(pt_element_t)))
 564                         return -EINVAL;
 565
 566                 if (gpte_to_gfn(gpte) != gfn || !is_present_pte(gpte) ||
 567                     !(gpte & PT_ACCESSED_MASK)) {
 568                         u64 nonpresent;
 569
 570                         rmap_remove(vcpu->kvm, &sp->spt[i]);
 571                         if (is_present_pte(gpte))
 572                                 nonpresent = shadow_trap_nonpresent_pte;
 573                         else
 574                                 nonpresent = shadow_notrap_nonpresent_pte;
 575                         set_shadow_pte(&sp->spt[i], nonpresent);
 576                         continue;
 577                 }
 578
 579                 nr_present++;
 580                 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
 581                 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
 582                          is_dirty_pte(gpte), 0, gfn,
 583                          spte_to_pfn(sp->spt[i]), true, false);
 584         }
 585
 586         return !nr_present;
 587 }
 588
 589 #undef pt_element_t
 590 #undef guest_walker
 591 #undef shadow_walker
 592 #undef FNAME
 593 #undef PT_BASE_ADDR_MASK
 594 #undef PT_INDEX
 595 #undef PT_LEVEL_MASK
 596 #undef PT_DIR_BASE_ADDR_MASK
 597 #undef PT_LEVEL_BITS
 598 #undef PT_MAX_FULL_LEVELS
 599 #undef gpte_to_gfn
 600 #undef gpte_to_gfn_pde
 601 #undef CMPXCHG