2 * Defines, structures, APIs for edac_core module
4 * (C) 2007 Linux Networx (http://lnxi.com)
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
8 * Written by Thayne Harbaugh
9 * Based on work by Dan Hollis <goemon at anime dot net> and others.
10 * http://www.anime.net/~goemon/linux-ecc/
12 * NMI handling support added by
13 * Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
15 * Refactored for multi-source files:
16 * Doug Thompson <norsk5@xmission.com>
23 #include <linux/kernel.h>
24 #include <linux/types.h>
25 #include <linux/module.h>
26 #include <linux/spinlock.h>
27 #include <linux/smp.h>
28 #include <linux/pci.h>
29 #include <linux/time.h>
30 #include <linux/nmi.h>
31 #include <linux/rcupdate.h>
32 #include <linux/completion.h>
33 #include <linux/kobject.h>
34 #include <linux/platform_device.h>
35 #include <linux/sysdev.h>
36 #include <linux/workqueue.h>
38 #define EDAC_MC_LABEL_LEN 31
39 #define EDAC_DEVICE_NAME_LEN 31
40 #define EDAC_ATTRIB_VALUE_LEN 15
41 #define MC_PROC_NAME_MAX_LEN 7
44 #define PAGES_TO_MiB(pages) ((pages) >> (20 - PAGE_SHIFT))
45 #define MiB_TO_PAGES(mb) ((mb) << (20 - PAGE_SHIFT))
46 #else /* PAGE_SHIFT > 20 */
47 #define PAGES_TO_MiB(pages) ((pages) << (PAGE_SHIFT - 20))
48 #define MiB_TO_PAGES(mb) ((mb) >> (PAGE_SHIFT - 20))
51 #define edac_printk(level, prefix, fmt, arg...) \
52 printk(level "EDAC " prefix ": " fmt, ##arg)
54 #define edac_mc_printk(mci, level, fmt, arg...) \
55 printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
57 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
58 printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
60 #define edac_device_printk(ctl, level, fmt, arg...) \
61 printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
63 #define edac_pci_printk(ctl, level, fmt, arg...) \
64 printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
66 /* prefixes for edac_printk() and edac_mc_printk() */
68 #define EDAC_PCI "PCI"
69 #define EDAC_DEBUG "DEBUG"
71 extern const char *edac_mem_types
[];
73 #ifdef CONFIG_EDAC_DEBUG
74 extern int edac_debug_level
;
76 #define edac_debug_printk(level, fmt, arg...) \
78 if (level <= edac_debug_level) \
79 edac_printk(KERN_DEBUG, EDAC_DEBUG, \
80 "%s: " fmt, __func__, ##arg); \
83 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
84 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
85 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
86 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
87 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
89 #else /* !CONFIG_EDAC_DEBUG */
91 #define debugf0( ... )
92 #define debugf1( ... )
93 #define debugf2( ... )
94 #define debugf3( ... )
95 #define debugf4( ... )
97 #endif /* !CONFIG_EDAC_DEBUG */
99 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
100 PCI_DEVICE_ID_ ## vend ## _ ## dev
102 #define edac_dev_name(dev) (dev)->dev_name
112 DEV_X32
, /* Do these parts exist? */
113 DEV_X64
/* Do these parts exist? */
116 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
117 #define DEV_FLAG_X1 BIT(DEV_X1)
118 #define DEV_FLAG_X2 BIT(DEV_X2)
119 #define DEV_FLAG_X4 BIT(DEV_X4)
120 #define DEV_FLAG_X8 BIT(DEV_X8)
121 #define DEV_FLAG_X16 BIT(DEV_X16)
122 #define DEV_FLAG_X32 BIT(DEV_X32)
123 #define DEV_FLAG_X64 BIT(DEV_X64)
127 MEM_EMPTY
= 0, /* Empty csrow */
128 MEM_RESERVED
, /* Reserved csrow type */
129 MEM_UNKNOWN
, /* Unknown csrow type */
130 MEM_FPM
, /* Fast page mode */
131 MEM_EDO
, /* Extended data out */
132 MEM_BEDO
, /* Burst Extended data out */
133 MEM_SDR
, /* Single data rate SDRAM */
134 MEM_RDR
, /* Registered single data rate SDRAM */
135 MEM_DDR
, /* Double data rate SDRAM */
136 MEM_RDDR
, /* Registered Double data rate SDRAM */
137 MEM_RMBS
, /* Rambus DRAM */
138 MEM_DDR2
, /* DDR2 RAM */
139 MEM_FB_DDR2
, /* fully buffered DDR2 */
140 MEM_RDDR2
, /* Registered DDR2 RAM */
141 MEM_XDR
, /* Rambus XDR */
142 MEM_DDR3
, /* DDR3 RAM */
143 MEM_RDDR3
, /* Registered DDR3 RAM */
146 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
147 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
148 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
149 #define MEM_FLAG_FPM BIT(MEM_FPM)
150 #define MEM_FLAG_EDO BIT(MEM_EDO)
151 #define MEM_FLAG_BEDO BIT(MEM_BEDO)
152 #define MEM_FLAG_SDR BIT(MEM_SDR)
153 #define MEM_FLAG_RDR BIT(MEM_RDR)
154 #define MEM_FLAG_DDR BIT(MEM_DDR)
155 #define MEM_FLAG_RDDR BIT(MEM_RDDR)
156 #define MEM_FLAG_RMBS BIT(MEM_RMBS)
157 #define MEM_FLAG_DDR2 BIT(MEM_DDR2)
158 #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
159 #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
160 #define MEM_FLAG_XDR BIT(MEM_XDR)
161 #define MEM_FLAG_DDR3 BIT(MEM_DDR3)
162 #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
164 /* chipset Error Detection and Correction capabilities and mode */
166 EDAC_UNKNOWN
= 0, /* Unknown if ECC is available */
167 EDAC_NONE
, /* Doesn't support ECC */
168 EDAC_RESERVED
, /* Reserved ECC type */
169 EDAC_PARITY
, /* Detects parity errors */
170 EDAC_EC
, /* Error Checking - no correction */
171 EDAC_SECDED
, /* Single bit error correction, Double detection */
172 EDAC_S2ECD2ED
, /* Chipkill x2 devices - do these exist? */
173 EDAC_S4ECD4ED
, /* Chipkill x4 devices */
174 EDAC_S8ECD8ED
, /* Chipkill x8 devices */
175 EDAC_S16ECD16ED
, /* Chipkill x16 devices */
178 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
179 #define EDAC_FLAG_NONE BIT(EDAC_NONE)
180 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
181 #define EDAC_FLAG_EC BIT(EDAC_EC)
182 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
183 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
184 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
185 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
186 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
188 /* scrubbing capabilities */
190 SCRUB_UNKNOWN
= 0, /* Unknown if scrubber is available */
191 SCRUB_NONE
, /* No scrubber */
192 SCRUB_SW_PROG
, /* SW progressive (sequential) scrubbing */
193 SCRUB_SW_SRC
, /* Software scrub only errors */
194 SCRUB_SW_PROG_SRC
, /* Progressive software scrub from an error */
195 SCRUB_SW_TUNABLE
, /* Software scrub frequency is tunable */
196 SCRUB_HW_PROG
, /* HW progressive (sequential) scrubbing */
197 SCRUB_HW_SRC
, /* Hardware scrub only errors */
198 SCRUB_HW_PROG_SRC
, /* Progressive hardware scrub from an error */
199 SCRUB_HW_TUNABLE
/* Hardware scrub frequency is tunable */
202 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
203 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
204 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
205 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
206 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
207 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
208 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
209 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
211 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
213 /* EDAC internal operation states */
214 #define OP_ALLOC 0x100
215 #define OP_RUNNING_POLL 0x201
216 #define OP_RUNNING_INTERRUPT 0x202
217 #define OP_RUNNING_POLL_INTR 0x203
218 #define OP_OFFLINE 0x300
221 * There are several things to be aware of that aren't at all obvious:
224 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
226 * These are some of the many terms that are thrown about that don't always
227 * mean what people think they mean (Inconceivable!). In the interest of
228 * creating a common ground for discussion, terms and their definitions
229 * will be established.
231 * Memory devices: The individual chip on a memory stick. These devices
232 * commonly output 4 and 8 bits each. Grouping several
233 * of these in parallel provides 64 bits which is common
234 * for a memory stick.
236 * Memory Stick: A printed circuit board that aggregates multiple
237 * memory devices in parallel. This is the atomic
238 * memory component that is purchaseable by Joe consumer
239 * and loaded into a memory socket.
241 * Socket: A physical connector on the motherboard that accepts
242 * a single memory stick.
244 * Channel: Set of memory devices on a memory stick that must be
245 * grouped in parallel with one or more additional
246 * channels from other memory sticks. This parallel
247 * grouping of the output from multiple channels are
248 * necessary for the smallest granularity of memory access.
249 * Some memory controllers are capable of single channel -
250 * which means that memory sticks can be loaded
251 * individually. Other memory controllers are only
252 * capable of dual channel - which means that memory
253 * sticks must be loaded as pairs (see "socket set").
255 * Chip-select row: All of the memory devices that are selected together.
256 * for a single, minimum grain of memory access.
257 * This selects all of the parallel memory devices across
258 * all of the parallel channels. Common chip-select rows
259 * for single channel are 64 bits, for dual channel 128
262 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
263 * Motherboards commonly drive two chip-select pins to
264 * a memory stick. A single-ranked stick, will occupy
265 * only one of those rows. The other will be unused.
267 * Double-Ranked stick: A double-ranked stick has two chip-select rows which
268 * access different sets of memory devices. The two
269 * rows cannot be accessed concurrently.
271 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
272 * A double-sided stick has two chip-select rows which
273 * access different sets of memory devices. The two
274 * rows cannot be accessed concurrently. "Double-sided"
275 * is irrespective of the memory devices being mounted
276 * on both sides of the memory stick.
278 * Socket set: All of the memory sticks that are required for
279 * a single memory access or all of the memory sticks
280 * spanned by a chip-select row. A single socket set
281 * has two chip-select rows and if double-sided sticks
282 * are used these will occupy those chip-select rows.
284 * Bank: This term is avoided because it is unclear when
285 * needing to distinguish between chip-select rows and
295 * STRUCTURE ORGANIZATION AND CHOICES
299 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
302 struct channel_info
{
303 int chan_idx
; /* channel index */
304 u32 ce_count
; /* Correctable Errors for this CHANNEL */
305 char label
[EDAC_MC_LABEL_LEN
+ 1]; /* DIMM label on motherboard */
306 struct csrow_info
*csrow
; /* the parent */
310 unsigned long first_page
; /* first page number in dimm */
311 unsigned long last_page
; /* last page number in dimm */
312 unsigned long page_mask
; /* used for interleaving -
315 u32 nr_pages
; /* number of pages in csrow */
316 u32 grain
; /* granularity of reported error in bytes */
317 int csrow_idx
; /* the chip-select row */
318 enum dev_type dtype
; /* memory device type */
319 u32 ue_count
; /* Uncorrectable Errors for this csrow */
320 u32 ce_count
; /* Correctable Errors for this csrow */
321 enum mem_type mtype
; /* memory csrow type */
322 enum edac_type edac_mode
; /* EDAC mode for this csrow */
323 struct mem_ctl_info
*mci
; /* the parent */
325 struct kobject kobj
; /* sysfs kobject for this csrow */
327 /* channel information for this csrow */
329 struct channel_info
*channels
;
332 struct mcidev_sysfs_group
{
333 const char *name
; /* group name */
334 const struct mcidev_sysfs_attribute
*mcidev_attr
; /* group attributes */
337 struct mcidev_sysfs_group_kobj
{
338 struct list_head list
; /* list for all instances within a mc */
340 struct kobject kobj
; /* kobj for the group */
342 const struct mcidev_sysfs_group
*grp
; /* group description table */
343 struct mem_ctl_info
*mci
; /* the parent */
346 /* mcidev_sysfs_attribute structure
347 * used for driver sysfs attributes and in mem_ctl_info
348 * sysfs top level entries
350 struct mcidev_sysfs_attribute
{
351 /* It should use either attr or grp */
352 struct attribute attr
;
353 const struct mcidev_sysfs_group
*grp
; /* Points to a group of attributes */
355 /* Ops for show/store values at the attribute - not used on group */
356 ssize_t (*show
)(struct mem_ctl_info
*,char *);
357 ssize_t (*store
)(struct mem_ctl_info
*, const char *,size_t);
360 /* MEMORY controller information structure
362 struct mem_ctl_info
{
363 struct list_head link
; /* for global list of mem_ctl_info structs */
365 struct module
*owner
; /* Module owner of this control struct */
367 unsigned long mtype_cap
; /* memory types supported by mc */
368 unsigned long edac_ctl_cap
; /* Mem controller EDAC capabilities */
369 unsigned long edac_cap
; /* configuration capabilities - this is
370 * closely related to edac_ctl_cap. The
371 * difference is that the controller may be
372 * capable of s4ecd4ed which would be listed
373 * in edac_ctl_cap, but if channels aren't
374 * capable of s4ecd4ed then the edac_cap would
375 * not have that capability.
377 unsigned long scrub_cap
; /* chipset scrub capabilities */
378 enum scrub_type scrub_mode
; /* current scrub mode */
380 /* Translates sdram memory scrub rate given in bytes/sec to the
381 internal representation and configures whatever else needs
384 int (*set_sdram_scrub_rate
) (struct mem_ctl_info
* mci
, u32 bw
);
386 /* Get the current sdram memory scrub rate from the internal
387 representation and converts it to the closest matching
388 bandwidth in bytes/sec.
390 int (*get_sdram_scrub_rate
) (struct mem_ctl_info
* mci
);
393 /* pointer to edac checking routine */
394 void (*edac_check
) (struct mem_ctl_info
* mci
);
397 * Remaps memory pages: controller pages to physical pages.
398 * For most MC's, this will be NULL.
400 /* FIXME - why not send the phys page to begin with? */
401 unsigned long (*ctl_page_to_phys
) (struct mem_ctl_info
* mci
,
405 struct csrow_info
*csrows
;
407 * FIXME - what about controllers on other busses? - IDs must be
408 * unique. dev pointer should be sufficiently unique, but
409 * BUS:SLOT.FUNC numbers may not be unique.
412 const char *mod_name
;
414 const char *ctl_name
;
415 const char *dev_name
;
416 char proc_name
[MC_PROC_NAME_MAX_LEN
+ 1];
418 u32 ue_noinfo_count
; /* Uncorrectable Errors w/o info */
419 u32 ce_noinfo_count
; /* Correctable Errors w/o info */
420 u32 ue_count
; /* Total Uncorrectable Errors for this MC */
421 u32 ce_count
; /* Total Correctable Errors for this MC */
422 unsigned long start_time
; /* mci load start time (in jiffies) */
424 struct completion complete
;
426 /* edac sysfs device control */
427 struct kobject edac_mci_kobj
;
429 /* list for all grp instances within a mc */
430 struct list_head grp_kobj_list
;
432 /* Additional top controller level attributes, but specified
433 * by the low level driver.
435 * Set by the low level driver to provide attributes at the
436 * controller level, same level as 'ue_count' and 'ce_count' above.
437 * An array of structures, NULL terminated
439 * If attributes are desired, then set to array of attributes
440 * If no attributes are desired, leave NULL
442 const struct mcidev_sysfs_attribute
*mc_driver_sysfs_attributes
;
444 /* work struct for this MC */
445 struct delayed_work work
;
447 /* the internal state of this controller instance */
452 * The following are the structures to provide for a generic
453 * or abstract 'edac_device'. This set of structures and the
454 * code that implements the APIs for the same, provide for
455 * registering EDAC type devices which are NOT standard memory.
457 * CPU caches (L1 and L2)
460 * Fabric switch units
461 * PCIe interface controllers
462 * other EDAC/ECC type devices that can be monitored for
465 * It allows for a 2 level set of hiearchry. For example:
467 * cache could be composed of L1, L2 and L3 levels of cache.
468 * Each CPU core would have its own L1 cache, while sharing
469 * L2 and maybe L3 caches.
471 * View them arranged, via the sysfs presentation:
472 * /sys/devices/system/edac/..
474 * mc/ <existing memory device directory>
475 * cpu/cpu0/.. <L1 and L2 block directory>
480 * cpu/cpu1/.. <L1 and L2 block directory>
487 * the L1 and L2 directories would be "edac_device_block's"
490 struct edac_device_counter
{
495 /* forward reference */
496 struct edac_device_ctl_info
;
497 struct edac_device_block
;
499 /* edac_dev_sysfs_attribute structure
500 * used for driver sysfs attributes in mem_ctl_info
501 * for extra controls and attributes:
502 * like high level error Injection controls
504 struct edac_dev_sysfs_attribute
{
505 struct attribute attr
;
506 ssize_t (*show
)(struct edac_device_ctl_info
*, char *);
507 ssize_t (*store
)(struct edac_device_ctl_info
*, const char *, size_t);
510 /* edac_dev_sysfs_block_attribute structure
512 * used in leaf 'block' nodes for adding controls/attributes
514 * each block in each instance of the containing control structure
515 * can have an array of the following. The show and store functions
516 * will be filled in with the show/store function in the
519 * The 'value' field will be the actual value field used for
522 struct edac_dev_sysfs_block_attribute
{
523 struct attribute attr
;
524 ssize_t (*show
)(struct kobject
*, struct attribute
*, char *);
525 ssize_t (*store
)(struct kobject
*, struct attribute
*,
526 const char *, size_t);
527 struct edac_device_block
*block
;
532 /* device block control structure */
533 struct edac_device_block
{
534 struct edac_device_instance
*instance
; /* Up Pointer */
535 char name
[EDAC_DEVICE_NAME_LEN
+ 1];
537 struct edac_device_counter counters
; /* basic UE and CE counters */
539 int nr_attribs
; /* how many attributes */
541 /* this block's attributes, could be NULL */
542 struct edac_dev_sysfs_block_attribute
*block_attributes
;
544 /* edac sysfs device control */
548 /* device instance control structure */
549 struct edac_device_instance
{
550 struct edac_device_ctl_info
*ctl
; /* Up pointer */
551 char name
[EDAC_DEVICE_NAME_LEN
+ 4];
553 struct edac_device_counter counters
; /* instance counters */
555 u32 nr_blocks
; /* how many blocks */
556 struct edac_device_block
*blocks
; /* block array */
558 /* edac sysfs device control */
564 * Abstract edac_device control info structure
567 struct edac_device_ctl_info
{
568 /* for global list of edac_device_ctl_info structs */
569 struct list_head link
;
571 struct module
*owner
; /* Module owner of this control struct */
575 /* Per instance controls for this edac_device */
576 int log_ue
; /* boolean for logging UEs */
577 int log_ce
; /* boolean for logging CEs */
578 int panic_on_ue
; /* boolean for panic'ing on an UE */
579 unsigned poll_msec
; /* number of milliseconds to poll interval */
580 unsigned long delay
; /* number of jiffies for poll_msec */
582 /* Additional top controller level attributes, but specified
583 * by the low level driver.
585 * Set by the low level driver to provide attributes at the
586 * controller level, same level as 'ue_count' and 'ce_count' above.
587 * An array of structures, NULL terminated
589 * If attributes are desired, then set to array of attributes
590 * If no attributes are desired, leave NULL
592 struct edac_dev_sysfs_attribute
*sysfs_attributes
;
594 /* pointer to main 'edac' class in sysfs */
595 struct sysdev_class
*edac_class
;
597 /* the internal state of this controller instance */
599 /* work struct for this instance */
600 struct delayed_work work
;
602 /* pointer to edac polling checking routine:
603 * If NOT NULL: points to polling check routine
604 * If NULL: Then assumes INTERRUPT operation, where
605 * MC driver will receive events
607 void (*edac_check
) (struct edac_device_ctl_info
* edac_dev
);
609 struct device
*dev
; /* pointer to device structure */
611 const char *mod_name
; /* module name */
612 const char *ctl_name
; /* edac controller name */
613 const char *dev_name
; /* pci/platform/etc... name */
615 void *pvt_info
; /* pointer to 'private driver' info */
617 unsigned long start_time
; /* edac_device load start time (jiffies) */
619 struct completion removal_complete
;
621 /* sysfs top name under 'edac' directory
628 char name
[EDAC_DEVICE_NAME_LEN
+ 1];
630 /* Number of instances supported on this control structure
631 * and the array of those instances
634 struct edac_device_instance
*instances
;
636 /* Event counters for the this whole EDAC Device */
637 struct edac_device_counter counters
;
639 /* edac sysfs device control for the 'name'
640 * device this structure controls
645 /* To get from the instance's wq to the beginning of the ctl structure */
646 #define to_edac_mem_ctl_work(w) \
647 container_of(w, struct mem_ctl_info, work)
649 #define to_edac_device_ctl_work(w) \
650 container_of(w,struct edac_device_ctl_info,work)
653 * The alloc() and free() functions for the 'edac_device' control info
654 * structure. A MC driver will allocate one of these for each edac_device
655 * it is going to control/register with the EDAC CORE.
657 extern struct edac_device_ctl_info
*edac_device_alloc_ctl_info(
658 unsigned sizeof_private
,
659 char *edac_device_name
, unsigned nr_instances
,
660 char *edac_block_name
, unsigned nr_blocks
,
661 unsigned offset_value
,
662 struct edac_dev_sysfs_block_attribute
*block_attributes
,
666 /* The offset value can be:
667 * -1 indicating no offset value
668 * 0 for zero-based block numbers
669 * 1 for 1-based block number
670 * other for other-based block number
672 #define BLOCK_OFFSET_VALUE_OFF ((unsigned) -1)
674 extern void edac_device_free_ctl_info(struct edac_device_ctl_info
*ctl_info
);
678 struct edac_pci_counter
{
684 * Abstract edac_pci control info structure
687 struct edac_pci_ctl_info
{
688 /* for global list of edac_pci_ctl_info structs */
689 struct list_head link
;
693 struct sysdev_class
*edac_class
; /* pointer to class */
695 /* the internal state of this controller instance */
697 /* work struct for this instance */
698 struct delayed_work work
;
700 /* pointer to edac polling checking routine:
701 * If NOT NULL: points to polling check routine
702 * If NULL: Then assumes INTERRUPT operation, where
703 * MC driver will receive events
705 void (*edac_check
) (struct edac_pci_ctl_info
* edac_dev
);
707 struct device
*dev
; /* pointer to device structure */
709 const char *mod_name
; /* module name */
710 const char *ctl_name
; /* edac controller name */
711 const char *dev_name
; /* pci/platform/etc... name */
713 void *pvt_info
; /* pointer to 'private driver' info */
715 unsigned long start_time
; /* edac_pci load start time (jiffies) */
717 struct completion complete
;
719 /* sysfs top name under 'edac' directory
726 char name
[EDAC_DEVICE_NAME_LEN
+ 1];
728 /* Event counters for the this whole EDAC Device */
729 struct edac_pci_counter counters
;
731 /* edac sysfs device control for the 'name'
732 * device this structure controls
735 struct completion kobj_complete
;
738 #define to_edac_pci_ctl_work(w) \
739 container_of(w, struct edac_pci_ctl_info,work)
741 /* write all or some bits in a byte-register*/
742 static inline void pci_write_bits8(struct pci_dev
*pdev
, int offset
, u8 value
,
748 pci_read_config_byte(pdev
, offset
, &buf
);
754 pci_write_config_byte(pdev
, offset
, value
);
757 /* write all or some bits in a word-register*/
758 static inline void pci_write_bits16(struct pci_dev
*pdev
, int offset
,
761 if (mask
!= 0xffff) {
764 pci_read_config_word(pdev
, offset
, &buf
);
770 pci_write_config_word(pdev
, offset
, value
);
776 * edac local routine to do pci_write_config_dword, but adds
777 * a mask parameter. If mask is all ones, ignore the mask.
778 * Otherwise utilize the mask to isolate specified bits
780 * write all or some bits in a dword-register
782 static inline void pci_write_bits32(struct pci_dev
*pdev
, int offset
,
785 if (mask
!= 0xffffffff) {
788 pci_read_config_dword(pdev
, offset
, &buf
);
794 pci_write_config_dword(pdev
, offset
, value
);
797 #endif /* CONFIG_PCI */
799 extern struct mem_ctl_info
*edac_mc_alloc(unsigned sz_pvt
, unsigned nr_csrows
,
800 unsigned nr_chans
, int edac_index
);
801 extern int edac_mc_add_mc(struct mem_ctl_info
*mci
);
802 extern void edac_mc_free(struct mem_ctl_info
*mci
);
803 extern struct mem_ctl_info
*edac_mc_find(int idx
);
804 extern struct mem_ctl_info
*find_mci_by_dev(struct device
*dev
);
805 extern struct mem_ctl_info
*edac_mc_del_mc(struct device
*dev
);
806 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info
*mci
,
810 * The no info errors are used when error overflows are reported.
811 * There are a limited number of error logging registers that can
812 * be exausted. When all registers are exhausted and an additional
813 * error occurs then an error overflow register records that an
814 * error occurred and the type of error, but doesn't have any
815 * further information. The ce/ue versions make for cleaner
816 * reporting logic and function interface - reduces conditional
817 * statement clutter and extra function arguments.
819 extern void edac_mc_handle_ce(struct mem_ctl_info
*mci
,
820 unsigned long page_frame_number
,
821 unsigned long offset_in_page
,
822 unsigned long syndrome
, int row
, int channel
,
824 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info
*mci
,
826 extern void edac_mc_handle_ue(struct mem_ctl_info
*mci
,
827 unsigned long page_frame_number
,
828 unsigned long offset_in_page
, int row
,
830 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info
*mci
,
832 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info
*mci
, unsigned int csrow
,
833 unsigned int channel0
, unsigned int channel1
,
835 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info
*mci
, unsigned int csrow
,
836 unsigned int channel
, char *msg
);
841 extern int edac_device_add_device(struct edac_device_ctl_info
*edac_dev
);
842 extern struct edac_device_ctl_info
*edac_device_del_device(struct device
*dev
);
843 extern void edac_device_handle_ue(struct edac_device_ctl_info
*edac_dev
,
844 int inst_nr
, int block_nr
, const char *msg
);
845 extern void edac_device_handle_ce(struct edac_device_ctl_info
*edac_dev
,
846 int inst_nr
, int block_nr
, const char *msg
);
847 extern int edac_device_alloc_index(void);
852 extern struct edac_pci_ctl_info
*edac_pci_alloc_ctl_info(unsigned int sz_pvt
,
853 const char *edac_pci_name
);
855 extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info
*pci
);
857 extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info
*pci
,
858 unsigned long value
);
860 extern int edac_pci_alloc_index(void);
861 extern int edac_pci_add_device(struct edac_pci_ctl_info
*pci
, int edac_idx
);
862 extern struct edac_pci_ctl_info
*edac_pci_del_device(struct device
*dev
);
864 extern struct edac_pci_ctl_info
*edac_pci_create_generic_ctl(
866 const char *mod_name
);
868 extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info
*pci
);
869 extern int edac_pci_create_sysfs(struct edac_pci_ctl_info
*pci
);
870 extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info
*pci
);
875 extern char *edac_op_state_to_string(int op_state
);
877 #endif /* _EDAC_CORE_H_ */