2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
24 #include <linux/kallsyms.h>
25 #include <linux/dmi.h>
26 #include <linux/pci-aspm.h>
27 #include <linux/ioport.h>
30 int isa_dma_bridge_buggy
;
31 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
33 EXPORT_SYMBOL(pci_pci_problems
);
35 #ifdef CONFIG_PCI_QUIRKS
37 * This quirk function disables memory decoding and releases memory resources
38 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
39 * It also rounds up size to specified alignment.
40 * Later on, the kernel will assign page-aligned memory resource back
43 static void __devinit
quirk_resource_alignment(struct pci_dev
*dev
)
47 resource_size_t align
, size
;
50 if (!pci_is_reassigndev(dev
))
53 if (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
&&
54 (dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
) {
56 "Can't reassign resources to host bridge.\n");
61 "Disabling memory decoding and releasing memory resources.\n");
62 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
63 command
&= ~PCI_COMMAND_MEMORY
;
64 pci_write_config_word(dev
, PCI_COMMAND
, command
);
66 align
= pci_specified_resource_alignment(dev
);
67 for (i
=0; i
< PCI_BRIDGE_RESOURCES
; i
++) {
68 r
= &dev
->resource
[i
];
69 if (!(r
->flags
& IORESOURCE_MEM
))
71 size
= resource_size(r
);
75 "Rounding up size of resource #%d to %#llx.\n",
76 i
, (unsigned long long)size
);
81 /* Need to disable bridge's resource window,
82 * to enable the kernel to reassign new resource
85 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
&&
86 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
87 for (i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
88 r
= &dev
->resource
[i
];
89 if (!(r
->flags
& IORESOURCE_MEM
))
91 r
->end
= resource_size(r
) - 1;
94 pci_disable_bridge_window(dev
);
97 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, quirk_resource_alignment
);
99 /* The Mellanox Tavor device gives false positive parity errors
100 * Mark this device with a broken_parity_status, to allow
101 * PCI scanning code to "skip" this now blacklisted device.
103 static void __devinit
quirk_mellanox_tavor(struct pci_dev
*dev
)
105 dev
->broken_parity_status
= 1; /* This device gives false positives */
107 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
,PCI_DEVICE_ID_MELLANOX_TAVOR
,quirk_mellanox_tavor
);
108 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE
,quirk_mellanox_tavor
);
110 /* Deal with broken BIOS'es that neglect to enable passive release,
111 which can cause problems in combination with the 82441FX/PPro MTRRs */
112 static void quirk_passive_release(struct pci_dev
*dev
)
114 struct pci_dev
*d
= NULL
;
117 /* We have to make sure a particular bit is set in the PIIX3
118 ISA bridge, so we have to go out and find it. */
119 while ((d
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, d
))) {
120 pci_read_config_byte(d
, 0x82, &dlc
);
122 dev_info(&d
->dev
, "PIIX3: Enabling Passive Release\n");
124 pci_write_config_byte(d
, 0x82, dlc
);
128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
129 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
131 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
132 but VIA don't answer queries. If you happen to have good contacts at VIA
133 ask them for me please -- Alan
135 This appears to be BIOS not version dependent. So presumably there is a
138 static void __devinit
quirk_isa_dma_hangs(struct pci_dev
*dev
)
140 if (!isa_dma_bridge_buggy
) {
141 isa_dma_bridge_buggy
=1;
142 dev_info(&dev
->dev
, "Activating ISA DMA hang workarounds\n");
146 * Its not totally clear which chipsets are the problematic ones
147 * We know 82C586 and 82C596 variants are affected.
149 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_0
, quirk_isa_dma_hangs
);
150 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C596
, quirk_isa_dma_hangs
);
151 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, quirk_isa_dma_hangs
);
152 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1533
, quirk_isa_dma_hangs
);
153 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_1
, quirk_isa_dma_hangs
);
154 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_2
, quirk_isa_dma_hangs
);
155 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_3
, quirk_isa_dma_hangs
);
158 * Chipsets where PCI->PCI transfers vanish or hang
160 static void __devinit
quirk_nopcipci(struct pci_dev
*dev
)
162 if ((pci_pci_problems
& PCIPCI_FAIL
)==0) {
163 dev_info(&dev
->dev
, "Disabling direct PCI/PCI transfers\n");
164 pci_pci_problems
|= PCIPCI_FAIL
;
167 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_5597
, quirk_nopcipci
);
168 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_496
, quirk_nopcipci
);
170 static void __devinit
quirk_nopciamd(struct pci_dev
*dev
)
173 pci_read_config_byte(dev
, 0x08, &rev
);
176 dev_info(&dev
->dev
, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
177 pci_pci_problems
|= PCIAGP_FAIL
;
180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8151_0
, quirk_nopciamd
);
183 * Triton requires workarounds to be used by the drivers
185 static void __devinit
quirk_triton(struct pci_dev
*dev
)
187 if ((pci_pci_problems
&PCIPCI_TRITON
)==0) {
188 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
189 pci_pci_problems
|= PCIPCI_TRITON
;
192 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437
, quirk_triton
);
193 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437VX
, quirk_triton
);
194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439
, quirk_triton
);
195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439TX
, quirk_triton
);
198 * VIA Apollo KT133 needs PCI latency patch
199 * Made according to a windows driver based patch by George E. Breese
200 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
201 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
202 * the info on which Mr Breese based his work.
204 * Updated based on further information from the site and also on
205 * information provided by VIA
207 static void quirk_vialatency(struct pci_dev
*dev
)
211 /* Ok we have a potential problem chipset here. Now see if we have
212 a buggy southbridge */
214 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, NULL
);
216 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
217 /* Check for buggy part revisions */
218 if (p
->revision
< 0x40 || p
->revision
> 0x42)
221 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, NULL
);
222 if (p
==NULL
) /* No problem parts */
224 /* Check for buggy part revisions */
225 if (p
->revision
< 0x10 || p
->revision
> 0x12)
230 * Ok we have the problem. Now set the PCI master grant to
231 * occur every master grant. The apparent bug is that under high
232 * PCI load (quite common in Linux of course) you can get data
233 * loss when the CPU is held off the bus for 3 bus master requests
234 * This happens to include the IDE controllers....
236 * VIA only apply this fix when an SB Live! is present but under
237 * both Linux and Windows this isnt enough, and we have seen
238 * corruption without SB Live! but with things like 3 UDMA IDE
239 * controllers. So we ignore that bit of the VIA recommendation..
242 pci_read_config_byte(dev
, 0x76, &busarb
);
243 /* Set bit 4 and bi 5 of byte 76 to 0x01
244 "Master priority rotation on every PCI master grant */
247 pci_write_config_byte(dev
, 0x76, busarb
);
248 dev_info(&dev
->dev
, "Applying VIA southbridge workaround\n");
252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
253 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
255 /* Must restore this on a resume from RAM */
256 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
257 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
258 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
261 * VIA Apollo VP3 needs ETBF on BT848/878
263 static void __devinit
quirk_viaetbf(struct pci_dev
*dev
)
265 if ((pci_pci_problems
&PCIPCI_VIAETBF
)==0) {
266 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
267 pci_pci_problems
|= PCIPCI_VIAETBF
;
270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_viaetbf
);
272 static void __devinit
quirk_vsfx(struct pci_dev
*dev
)
274 if ((pci_pci_problems
&PCIPCI_VSFX
)==0) {
275 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
276 pci_pci_problems
|= PCIPCI_VSFX
;
279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C576
, quirk_vsfx
);
282 * Ali Magik requires workarounds to be used by the drivers
283 * that DMA to AGP space. Latency must be set to 0xA and triton
284 * workaround applied too
285 * [Info kindly provided by ALi]
287 static void __init
quirk_alimagik(struct pci_dev
*dev
)
289 if ((pci_pci_problems
&PCIPCI_ALIMAGIK
)==0) {
290 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
291 pci_pci_problems
|= PCIPCI_ALIMAGIK
|PCIPCI_TRITON
;
294 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1647
, quirk_alimagik
);
295 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1651
, quirk_alimagik
);
298 * Natoma has some interesting boundary conditions with Zoran stuff
301 static void __devinit
quirk_natoma(struct pci_dev
*dev
)
303 if ((pci_pci_problems
&PCIPCI_NATOMA
)==0) {
304 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
305 pci_pci_problems
|= PCIPCI_NATOMA
;
308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_natoma
);
309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_0
, quirk_natoma
);
310 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_1
, quirk_natoma
);
311 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_0
, quirk_natoma
);
312 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_1
, quirk_natoma
);
313 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_2
, quirk_natoma
);
316 * This chip can cause PCI parity errors if config register 0xA0 is read
317 * while DMAs are occurring.
319 static void __devinit
quirk_citrine(struct pci_dev
*dev
)
321 dev
->cfg_size
= 0xA0;
323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, PCI_DEVICE_ID_IBM_CITRINE
, quirk_citrine
);
326 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
327 * If it's needed, re-allocate the region.
329 static void __devinit
quirk_s3_64M(struct pci_dev
*dev
)
331 struct resource
*r
= &dev
->resource
[0];
333 if ((r
->start
& 0x3ffffff) || r
->end
!= r
->start
+ 0x3ffffff) {
338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_868
, quirk_s3_64M
);
339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_968
, quirk_s3_64M
);
342 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
343 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
344 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
345 * (which conflicts w/ BAR1's memory range).
347 static void __devinit
quirk_cs5536_vsa(struct pci_dev
*dev
)
349 if (pci_resource_len(dev
, 0) != 8) {
350 struct resource
*res
= &dev
->resource
[0];
351 res
->end
= res
->start
+ 8 - 1;
352 dev_info(&dev
->dev
, "CS5536 ISA bridge bug detected "
353 "(incorrect header); workaround applied.\n");
356 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_CS5536_ISA
, quirk_cs5536_vsa
);
358 static void __devinit
quirk_io_region(struct pci_dev
*dev
, unsigned region
,
359 unsigned size
, int nr
, const char *name
)
363 struct pci_bus_region bus_region
;
364 struct resource
*res
= dev
->resource
+ nr
;
366 res
->name
= pci_name(dev
);
368 res
->end
= region
+ size
- 1;
369 res
->flags
= IORESOURCE_IO
;
371 /* Convert from PCI bus to resource space. */
372 bus_region
.start
= res
->start
;
373 bus_region
.end
= res
->end
;
374 pcibios_bus_to_resource(dev
, res
, &bus_region
);
376 pci_claim_resource(dev
, nr
);
377 dev_info(&dev
->dev
, "quirk: %pR claimed by %s\n", res
, name
);
382 * ATI Northbridge setups MCE the processor if you even
383 * read somewhere between 0x3b0->0x3bb or read 0x3d3
385 static void __devinit
quirk_ati_exploding_mce(struct pci_dev
*dev
)
387 dev_info(&dev
->dev
, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
388 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
389 request_region(0x3b0, 0x0C, "RadeonIGP");
390 request_region(0x3d3, 0x01, "RadeonIGP");
392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS100
, quirk_ati_exploding_mce
);
395 * Let's make the southbridge information explicit instead
396 * of having to worry about people probing the ACPI areas,
397 * for example.. (Yes, it happens, and if you read the wrong
398 * ACPI register it will put the machine to sleep with no
399 * way of waking it up again. Bummer).
401 * ALI M7101: Two IO regions pointed to by words at
402 * 0xE0 (64 bytes of ACPI registers)
403 * 0xE2 (32 bytes of SMB registers)
405 static void __devinit
quirk_ali7101_acpi(struct pci_dev
*dev
)
409 pci_read_config_word(dev
, 0xE0, ®ion
);
410 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
, "ali7101 ACPI");
411 pci_read_config_word(dev
, 0xE2, ®ion
);
412 quirk_io_region(dev
, region
, 32, PCI_BRIDGE_RESOURCES
+1, "ali7101 SMB");
414 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M7101
, quirk_ali7101_acpi
);
416 static void piix4_io_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
419 u32 mask
, size
, base
;
421 pci_read_config_dword(dev
, port
, &devres
);
422 if ((devres
& enable
) != enable
)
424 mask
= (devres
>> 16) & 15;
425 base
= devres
& 0xffff;
428 unsigned bit
= size
>> 1;
429 if ((bit
& mask
) == bit
)
434 * For now we only print it out. Eventually we'll want to
435 * reserve it (at least if it's in the 0x1000+ range), but
436 * let's get enough confirmation reports first.
439 dev_info(&dev
->dev
, "%s PIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
442 static void piix4_mem_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
445 u32 mask
, size
, base
;
447 pci_read_config_dword(dev
, port
, &devres
);
448 if ((devres
& enable
) != enable
)
450 base
= devres
& 0xffff0000;
451 mask
= (devres
& 0x3f) << 16;
454 unsigned bit
= size
>> 1;
455 if ((bit
& mask
) == bit
)
460 * For now we only print it out. Eventually we'll want to
461 * reserve it, but let's get enough confirmation reports first.
464 dev_info(&dev
->dev
, "%s MMIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
468 * PIIX4 ACPI: Two IO regions pointed to by longwords at
469 * 0x40 (64 bytes of ACPI registers)
470 * 0x90 (16 bytes of SMB registers)
471 * and a few strange programmable PIIX4 device resources.
473 static void __devinit
quirk_piix4_acpi(struct pci_dev
*dev
)
477 pci_read_config_dword(dev
, 0x40, ®ion
);
478 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
, "PIIX4 ACPI");
479 pci_read_config_dword(dev
, 0x90, ®ion
);
480 quirk_io_region(dev
, region
, 16, PCI_BRIDGE_RESOURCES
+1, "PIIX4 SMB");
482 /* Device resource A has enables for some of the other ones */
483 pci_read_config_dword(dev
, 0x5c, &res_a
);
485 piix4_io_quirk(dev
, "PIIX4 devres B", 0x60, 3 << 21);
486 piix4_io_quirk(dev
, "PIIX4 devres C", 0x64, 3 << 21);
488 /* Device resource D is just bitfields for static resources */
490 /* Device 12 enabled? */
491 if (res_a
& (1 << 29)) {
492 piix4_io_quirk(dev
, "PIIX4 devres E", 0x68, 1 << 20);
493 piix4_mem_quirk(dev
, "PIIX4 devres F", 0x6c, 1 << 7);
495 /* Device 13 enabled? */
496 if (res_a
& (1 << 30)) {
497 piix4_io_quirk(dev
, "PIIX4 devres G", 0x70, 1 << 20);
498 piix4_mem_quirk(dev
, "PIIX4 devres H", 0x74, 1 << 7);
500 piix4_io_quirk(dev
, "PIIX4 devres I", 0x78, 1 << 20);
501 piix4_io_quirk(dev
, "PIIX4 devres J", 0x7c, 1 << 20);
503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_3
, quirk_piix4_acpi
);
504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443MX_3
, quirk_piix4_acpi
);
506 #define ICH_PMBASE 0x40
507 #define ICH_ACPI_CNTL 0x44
508 #define ICH4_ACPI_EN 0x10
509 #define ICH6_ACPI_EN 0x80
510 #define ICH4_GPIOBASE 0x58
511 #define ICH4_GPIO_CNTL 0x5c
512 #define ICH4_GPIO_EN 0x10
513 #define ICH6_GPIOBASE 0x48
514 #define ICH6_GPIO_CNTL 0x4c
515 #define ICH6_GPIO_EN 0x10
518 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
519 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
520 * 0x58 (64 bytes of GPIO I/O space)
522 static void __devinit
quirk_ich4_lpc_acpi(struct pci_dev
*dev
)
528 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
529 * with low legacy (and fixed) ports. We don't know the decoding
530 * priority and can't tell whether the legacy device or the one created
531 * here is really at that address. This happens on boards with broken
535 pci_read_config_byte(dev
, ICH_ACPI_CNTL
, &enable
);
536 if (enable
& ICH4_ACPI_EN
) {
537 pci_read_config_dword(dev
, ICH_PMBASE
, ®ion
);
538 region
&= PCI_BASE_ADDRESS_IO_MASK
;
539 if (region
>= PCIBIOS_MIN_IO
)
540 quirk_io_region(dev
, region
, 128, PCI_BRIDGE_RESOURCES
,
541 "ICH4 ACPI/GPIO/TCO");
544 pci_read_config_byte(dev
, ICH4_GPIO_CNTL
, &enable
);
545 if (enable
& ICH4_GPIO_EN
) {
546 pci_read_config_dword(dev
, ICH4_GPIOBASE
, ®ion
);
547 region
&= PCI_BASE_ADDRESS_IO_MASK
;
548 if (region
>= PCIBIOS_MIN_IO
)
549 quirk_io_region(dev
, region
, 64,
550 PCI_BRIDGE_RESOURCES
+ 1, "ICH4 GPIO");
553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, quirk_ich4_lpc_acpi
);
554 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_0
, quirk_ich4_lpc_acpi
);
555 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, quirk_ich4_lpc_acpi
);
556 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_10
, quirk_ich4_lpc_acpi
);
557 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, quirk_ich4_lpc_acpi
);
558 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, quirk_ich4_lpc_acpi
);
559 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, quirk_ich4_lpc_acpi
);
560 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, quirk_ich4_lpc_acpi
);
561 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, quirk_ich4_lpc_acpi
);
562 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_1
, quirk_ich4_lpc_acpi
);
564 static void __devinit
ich6_lpc_acpi_gpio(struct pci_dev
*dev
)
569 pci_read_config_byte(dev
, ICH_ACPI_CNTL
, &enable
);
570 if (enable
& ICH6_ACPI_EN
) {
571 pci_read_config_dword(dev
, ICH_PMBASE
, ®ion
);
572 region
&= PCI_BASE_ADDRESS_IO_MASK
;
573 if (region
>= PCIBIOS_MIN_IO
)
574 quirk_io_region(dev
, region
, 128, PCI_BRIDGE_RESOURCES
,
575 "ICH6 ACPI/GPIO/TCO");
578 pci_read_config_byte(dev
, ICH6_GPIO_CNTL
, &enable
);
579 if (enable
& ICH4_GPIO_EN
) {
580 pci_read_config_dword(dev
, ICH6_GPIOBASE
, ®ion
);
581 region
&= PCI_BASE_ADDRESS_IO_MASK
;
582 if (region
>= PCIBIOS_MIN_IO
)
583 quirk_io_region(dev
, region
, 64,
584 PCI_BRIDGE_RESOURCES
+ 1, "ICH6 GPIO");
588 static void __devinit
ich6_lpc_generic_decode(struct pci_dev
*dev
, unsigned reg
, const char *name
, int dynsize
)
593 pci_read_config_dword(dev
, reg
, &val
);
601 * This is not correct. It is 16, 32 or 64 bytes depending on
602 * register D31:F0:ADh bits 5:4.
604 * But this gets us at least _part_ of it.
612 /* Just print it out for now. We should reserve it after more debugging */
613 dev_info(&dev
->dev
, "%s PIO at %04x-%04x\n", name
, base
, base
+size
-1);
616 static void __devinit
quirk_ich6_lpc(struct pci_dev
*dev
)
618 /* Shared ACPI/GPIO decode with all ICH6+ */
619 ich6_lpc_acpi_gpio(dev
);
621 /* ICH6-specific generic IO decode */
622 ich6_lpc_generic_decode(dev
, 0x84, "LPC Generic IO decode 1", 0);
623 ich6_lpc_generic_decode(dev
, 0x88, "LPC Generic IO decode 2", 1);
625 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_0
, quirk_ich6_lpc
);
626 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, quirk_ich6_lpc
);
628 static void __devinit
ich7_lpc_generic_decode(struct pci_dev
*dev
, unsigned reg
, const char *name
)
633 pci_read_config_dword(dev
, reg
, &val
);
640 * IO base in bits 15:2, mask in bits 23:18, both
644 mask
= (val
>> 16) & 0xfc;
647 /* Just print it out for now. We should reserve it after more debugging */
648 dev_info(&dev
->dev
, "%s PIO at %04x (mask %04x)\n", name
, base
, mask
);
651 /* ICH7-10 has the same common LPC generic IO decode registers */
652 static void __devinit
quirk_ich7_lpc(struct pci_dev
*dev
)
654 /* We share the common ACPI/DPIO decode with ICH6 */
655 ich6_lpc_acpi_gpio(dev
);
657 /* And have 4 ICH7+ generic decodes */
658 ich7_lpc_generic_decode(dev
, 0x84, "ICH7 LPC Generic IO decode 1");
659 ich7_lpc_generic_decode(dev
, 0x88, "ICH7 LPC Generic IO decode 2");
660 ich7_lpc_generic_decode(dev
, 0x8c, "ICH7 LPC Generic IO decode 3");
661 ich7_lpc_generic_decode(dev
, 0x90, "ICH7 LPC Generic IO decode 4");
663 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_0
, quirk_ich7_lpc
);
664 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_1
, quirk_ich7_lpc
);
665 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_31
, quirk_ich7_lpc
);
666 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_0
, quirk_ich7_lpc
);
667 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_2
, quirk_ich7_lpc
);
668 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_3
, quirk_ich7_lpc
);
669 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_1
, quirk_ich7_lpc
);
670 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_4
, quirk_ich7_lpc
);
671 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_2
, quirk_ich7_lpc
);
672 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_4
, quirk_ich7_lpc
);
673 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_7
, quirk_ich7_lpc
);
674 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_8
, quirk_ich7_lpc
);
675 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH10_1
, quirk_ich7_lpc
);
678 * VIA ACPI: One IO region pointed to by longword at
679 * 0x48 or 0x20 (256 bytes of ACPI registers)
681 static void __devinit
quirk_vt82c586_acpi(struct pci_dev
*dev
)
685 if (dev
->revision
& 0x10) {
686 pci_read_config_dword(dev
, 0x48, ®ion
);
687 region
&= PCI_BASE_ADDRESS_IO_MASK
;
688 quirk_io_region(dev
, region
, 256, PCI_BRIDGE_RESOURCES
, "vt82c586 ACPI");
691 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_vt82c586_acpi
);
694 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
695 * 0x48 (256 bytes of ACPI registers)
696 * 0x70 (128 bytes of hardware monitoring register)
697 * 0x90 (16 bytes of SMB registers)
699 static void __devinit
quirk_vt82c686_acpi(struct pci_dev
*dev
)
704 quirk_vt82c586_acpi(dev
);
706 pci_read_config_word(dev
, 0x70, &hm
);
707 hm
&= PCI_BASE_ADDRESS_IO_MASK
;
708 quirk_io_region(dev
, hm
, 128, PCI_BRIDGE_RESOURCES
+ 1, "vt82c686 HW-mon");
710 pci_read_config_dword(dev
, 0x90, &smb
);
711 smb
&= PCI_BASE_ADDRESS_IO_MASK
;
712 quirk_io_region(dev
, smb
, 16, PCI_BRIDGE_RESOURCES
+ 2, "vt82c686 SMB");
714 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_vt82c686_acpi
);
717 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
718 * 0x88 (128 bytes of power management registers)
719 * 0xd0 (16 bytes of SMB registers)
721 static void __devinit
quirk_vt8235_acpi(struct pci_dev
*dev
)
725 pci_read_config_word(dev
, 0x88, &pm
);
726 pm
&= PCI_BASE_ADDRESS_IO_MASK
;
727 quirk_io_region(dev
, pm
, 128, PCI_BRIDGE_RESOURCES
, "vt8235 PM");
729 pci_read_config_word(dev
, 0xd0, &smb
);
730 smb
&= PCI_BASE_ADDRESS_IO_MASK
;
731 quirk_io_region(dev
, smb
, 16, PCI_BRIDGE_RESOURCES
+ 1, "vt8235 SMB");
733 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_vt8235_acpi
);
736 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
737 * Disable fast back-to-back on the secondary bus segment
739 static void __devinit
quirk_xio2000a(struct pci_dev
*dev
)
741 struct pci_dev
*pdev
;
744 dev_warn(&dev
->dev
, "TI XIO2000a quirk detected; "
745 "secondary bus fast back-to-back transfers disabled\n");
746 list_for_each_entry(pdev
, &dev
->subordinate
->devices
, bus_list
) {
747 pci_read_config_word(pdev
, PCI_COMMAND
, &command
);
748 if (command
& PCI_COMMAND_FAST_BACK
)
749 pci_write_config_word(pdev
, PCI_COMMAND
, command
& ~PCI_COMMAND_FAST_BACK
);
752 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI
, PCI_DEVICE_ID_TI_XIO2000A
,
755 #ifdef CONFIG_X86_IO_APIC
757 #include <asm/io_apic.h>
760 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
761 * devices to the external APIC.
763 * TODO: When we have device-specific interrupt routers,
764 * this code will go away from quirks.
766 static void quirk_via_ioapic(struct pci_dev
*dev
)
771 tmp
= 0; /* nothing routed to external APIC */
773 tmp
= 0x1f; /* all known bits (4-0) routed to external APIC */
775 dev_info(&dev
->dev
, "%sbling VIA external APIC routing\n",
776 tmp
== 0 ? "Disa" : "Ena");
778 /* Offset 0x58: External APIC IRQ output control */
779 pci_write_config_byte (dev
, 0x58, tmp
);
781 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
782 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
785 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
786 * This leads to doubled level interrupt rates.
787 * Set this bit to get rid of cycle wastage.
788 * Otherwise uncritical.
790 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev
*dev
)
793 #define BYPASS_APIC_DEASSERT 8
795 pci_read_config_byte(dev
, 0x5B, &misc_control2
);
796 if (!(misc_control2
& BYPASS_APIC_DEASSERT
)) {
797 dev_info(&dev
->dev
, "Bypassing VIA 8237 APIC De-Assert Message\n");
798 pci_write_config_byte(dev
, 0x5B, misc_control2
|BYPASS_APIC_DEASSERT
);
801 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
802 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
805 * The AMD io apic can hang the box when an apic irq is masked.
806 * We check all revs >= B0 (yet not in the pre production!) as the bug
807 * is currently marked NoFix
809 * We have multiple reports of hangs with this chipset that went away with
810 * noapic specified. For the moment we assume it's the erratum. We may be wrong
811 * of course. However the advice is demonstrably good even if so..
813 static void __devinit
quirk_amd_ioapic(struct pci_dev
*dev
)
815 if (dev
->revision
>= 0x02) {
816 dev_warn(&dev
->dev
, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
817 dev_warn(&dev
->dev
, " : booting with the \"noapic\" option\n");
820 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_VIPER_7410
, quirk_amd_ioapic
);
822 static void __init
quirk_ioapic_rmw(struct pci_dev
*dev
)
824 if (dev
->devfn
== 0 && dev
->bus
->number
== 0)
827 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_ANY_ID
, quirk_ioapic_rmw
);
828 #endif /* CONFIG_X86_IO_APIC */
831 * Some settings of MMRBC can lead to data corruption so block changes.
832 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
834 static void __init
quirk_amd_8131_mmrbc(struct pci_dev
*dev
)
836 if (dev
->subordinate
&& dev
->revision
<= 0x12) {
837 dev_info(&dev
->dev
, "AMD8131 rev %x detected; "
838 "disabling PCI-X MMRBC\n", dev
->revision
);
839 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MMRBC
;
842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_amd_8131_mmrbc
);
845 * FIXME: it is questionable that quirk_via_acpi
846 * is needed. It shows up as an ISA bridge, and does not
847 * support the PCI_INTERRUPT_LINE register at all. Therefore
848 * it seems like setting the pci_dev's 'irq' to the
849 * value of the ACPI SCI interrupt is only done for convenience.
852 static void __devinit
quirk_via_acpi(struct pci_dev
*d
)
855 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
858 pci_read_config_byte(d
, 0x42, &irq
);
860 if (irq
&& (irq
!= 2))
863 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_via_acpi
);
864 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_via_acpi
);
868 * VIA bridges which have VLink
871 static int via_vlink_dev_lo
= -1, via_vlink_dev_hi
= 18;
873 static void quirk_via_bridge(struct pci_dev
*dev
)
875 /* See what bridge we have and find the device ranges */
876 switch (dev
->device
) {
877 case PCI_DEVICE_ID_VIA_82C686
:
878 /* The VT82C686 is special, it attaches to PCI and can have
879 any device number. All its subdevices are functions of
880 that single device. */
881 via_vlink_dev_lo
= PCI_SLOT(dev
->devfn
);
882 via_vlink_dev_hi
= PCI_SLOT(dev
->devfn
);
884 case PCI_DEVICE_ID_VIA_8237
:
885 case PCI_DEVICE_ID_VIA_8237A
:
886 via_vlink_dev_lo
= 15;
888 case PCI_DEVICE_ID_VIA_8235
:
889 via_vlink_dev_lo
= 16;
891 case PCI_DEVICE_ID_VIA_8231
:
892 case PCI_DEVICE_ID_VIA_8233_0
:
893 case PCI_DEVICE_ID_VIA_8233A
:
894 case PCI_DEVICE_ID_VIA_8233C_0
:
895 via_vlink_dev_lo
= 17;
899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_bridge
);
900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, quirk_via_bridge
);
901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233_0
, quirk_via_bridge
);
902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233A
, quirk_via_bridge
);
903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233C_0
, quirk_via_bridge
);
904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_via_bridge
);
905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_bridge
);
906 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237A
, quirk_via_bridge
);
909 * quirk_via_vlink - VIA VLink IRQ number update
912 * If the device we are dealing with is on a PIC IRQ we need to
913 * ensure that the IRQ line register which usually is not relevant
914 * for PCI cards, is actually written so that interrupts get sent
915 * to the right place.
916 * We only do this on systems where a VIA south bridge was detected,
917 * and only for VIA devices on the motherboard (see quirk_via_bridge
921 static void quirk_via_vlink(struct pci_dev
*dev
)
925 /* Check if we have VLink at all */
926 if (via_vlink_dev_lo
== -1)
931 /* Don't quirk interrupts outside the legacy IRQ range */
932 if (!new_irq
|| new_irq
> 15)
935 /* Internal device ? */
936 if (dev
->bus
->number
!= 0 || PCI_SLOT(dev
->devfn
) > via_vlink_dev_hi
||
937 PCI_SLOT(dev
->devfn
) < via_vlink_dev_lo
)
940 /* This is an internal VLink device on a PIC interrupt. The BIOS
941 ought to have set this but may not have, so we redo it */
943 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
944 if (new_irq
!= irq
) {
945 dev_info(&dev
->dev
, "VIA VLink IRQ fixup, from %d to %d\n",
947 udelay(15); /* unknown if delay really needed */
948 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, new_irq
);
951 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
, quirk_via_vlink
);
954 * VIA VT82C598 has its device ID settable and many BIOSes
955 * set it to the ID of VT82C597 for backward compatibility.
956 * We need to switch it off to be able to recognize the real
959 static void __devinit
quirk_vt82c598_id(struct pci_dev
*dev
)
961 pci_write_config_byte(dev
, 0xfc, 0);
962 pci_read_config_word(dev
, PCI_DEVICE_ID
, &dev
->device
);
964 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_vt82c598_id
);
967 * CardBus controllers have a legacy base address that enables them
968 * to respond as i82365 pcmcia controllers. We don't want them to
969 * do this even if the Linux CardBus driver is not loaded, because
970 * the Linux i82365 driver does not (and should not) handle CardBus.
972 static void quirk_cardbus_legacy(struct pci_dev
*dev
)
974 if ((PCI_CLASS_BRIDGE_CARDBUS
<< 8) ^ dev
->class)
976 pci_write_config_dword(dev
, PCI_CB_LEGACY_MODE_BASE
, 0);
978 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID
, PCI_ANY_ID
, quirk_cardbus_legacy
);
979 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID
, PCI_ANY_ID
, quirk_cardbus_legacy
);
982 * Following the PCI ordering rules is optional on the AMD762. I'm not
983 * sure what the designers were smoking but let's not inhale...
985 * To be fair to AMD, it follows the spec by default, its BIOS people
988 static void quirk_amd_ordering(struct pci_dev
*dev
)
991 pci_read_config_dword(dev
, 0x4C, &pcic
);
994 dev_warn(&dev
->dev
, "BIOS failed to enable PCI standards compliance; fixing this error\n");
995 pci_write_config_dword(dev
, 0x4C, pcic
);
996 pci_read_config_dword(dev
, 0x84, &pcic
);
997 pcic
|= (1<<23); /* Required in this mode */
998 pci_write_config_dword(dev
, 0x84, pcic
);
1001 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
1002 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
1005 * DreamWorks provided workaround for Dunord I-3000 problem
1007 * This card decodes and responds to addresses not apparently
1008 * assigned to it. We force a larger allocation to ensure that
1009 * nothing gets put too close to it.
1011 static void __devinit
quirk_dunord ( struct pci_dev
* dev
)
1013 struct resource
*r
= &dev
->resource
[1];
1017 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD
, PCI_DEVICE_ID_DUNORD_I3000
, quirk_dunord
);
1020 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1021 * is subtractive decoding (transparent), and does indicate this
1022 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1025 static void __devinit
quirk_transparent_bridge(struct pci_dev
*dev
)
1027 dev
->transparent
= 1;
1029 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82380FB
, quirk_transparent_bridge
);
1030 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA
, 0x605, quirk_transparent_bridge
);
1033 * Common misconfiguration of the MediaGX/Geode PCI master that will
1034 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1035 * datasheets found at http://www.national.com/ds/GX for info on what
1036 * these bits do. <christer@weinigel.se>
1038 static void quirk_mediagx_master(struct pci_dev
*dev
)
1041 pci_read_config_byte(dev
, 0x41, ®
);
1044 dev_info(&dev
->dev
, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg
);
1045 pci_write_config_byte(dev
, 0x41, reg
);
1048 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
1049 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
1052 * Ensure C0 rev restreaming is off. This is normally done by
1053 * the BIOS but in the odd case it is not the results are corruption
1054 * hence the presence of a Linux check
1056 static void quirk_disable_pxb(struct pci_dev
*pdev
)
1060 if (pdev
->revision
!= 0x04) /* Only C0 requires this */
1062 pci_read_config_word(pdev
, 0x40, &config
);
1063 if (config
& (1<<6)) {
1065 pci_write_config_word(pdev
, 0x40, config
);
1066 dev_info(&pdev
->dev
, "C0 revision 450NX. Disabling PCI restreaming\n");
1069 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
1070 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
1072 static void __devinit
quirk_amd_ide_mode(struct pci_dev
*pdev
)
1074 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1077 pci_read_config_byte(pdev
, PCI_CLASS_DEVICE
, &tmp
);
1079 pci_read_config_byte(pdev
, 0x40, &tmp
);
1080 pci_write_config_byte(pdev
, 0x40, tmp
|1);
1081 pci_write_config_byte(pdev
, 0x9, 1);
1082 pci_write_config_byte(pdev
, 0xa, 6);
1083 pci_write_config_byte(pdev
, 0x40, tmp
);
1085 pdev
->class = PCI_CLASS_STORAGE_SATA_AHCI
;
1086 dev_info(&pdev
->dev
, "set SATA to AHCI mode\n");
1089 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
1090 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
1091 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
1092 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
1093 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE
, quirk_amd_ide_mode
);
1094 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE
, quirk_amd_ide_mode
);
1097 * Serverworks CSB5 IDE does not fully support native mode
1099 static void __devinit
quirk_svwks_csb5ide(struct pci_dev
*pdev
)
1102 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1106 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
1107 /* PCI layer will sort out resources */
1110 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
, quirk_svwks_csb5ide
);
1113 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1115 static void __init
quirk_ide_samemode(struct pci_dev
*pdev
)
1119 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1121 if (((prog
& 1) && !(prog
& 4)) || ((prog
& 4) && !(prog
& 1))) {
1122 dev_info(&pdev
->dev
, "IDE mode mismatch; forcing legacy mode\n");
1125 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
1128 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_10
, quirk_ide_samemode
);
1131 * Some ATA devices break if put into D3
1134 static void __devinit
quirk_no_ata_d3(struct pci_dev
*pdev
)
1136 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1137 if ((pdev
->class >> 8) == PCI_CLASS_STORAGE_IDE
)
1138 pdev
->dev_flags
|= PCI_DEV_FLAGS_NO_D3
;
1140 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_ANY_ID
, quirk_no_ata_d3
);
1141 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
, quirk_no_ata_d3
);
1142 /* ALi loses some register settings that we cannot then restore */
1143 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL
, PCI_ANY_ID
, quirk_no_ata_d3
);
1144 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1145 occur when mode detecting */
1146 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
, quirk_no_ata_d3
);
1148 /* This was originally an Alpha specific thing, but it really fits here.
1149 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1151 static void __init
quirk_eisa_bridge(struct pci_dev
*dev
)
1153 dev
->class = PCI_CLASS_BRIDGE_EISA
<< 8;
1155 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82375
, quirk_eisa_bridge
);
1159 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1160 * is not activated. The myth is that Asus said that they do not want the
1161 * users to be irritated by just another PCI Device in the Win98 device
1162 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1163 * package 2.7.0 for details)
1165 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1166 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1167 * becomes necessary to do this tweak in two steps -- the chosen trigger
1168 * is either the Host bridge (preferred) or on-board VGA controller.
1170 * Note that we used to unhide the SMBus that way on Toshiba laptops
1171 * (Satellite A40 and Tecra M2) but then found that the thermal management
1172 * was done by SMM code, which could cause unsynchronized concurrent
1173 * accesses to the SMBus registers, with potentially bad effects. Thus you
1174 * should be very careful when adding new entries: if SMM is accessing the
1175 * Intel SMBus, this is a very good reason to leave it hidden.
1177 * Likewise, many recent laptops use ACPI for thermal management. If the
1178 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1179 * natively, and keeping the SMBus hidden is the right thing to do. If you
1180 * are about to add an entry in the table below, please first disassemble
1181 * the DSDT and double-check that there is no code accessing the SMBus.
1183 static int asus_hides_smbus
;
1185 static void __init
asus_hides_smbus_hostbridge(struct pci_dev
*dev
)
1187 if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1188 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845_HB
)
1189 switch(dev
->subsystem_device
) {
1190 case 0x8025: /* P4B-LX */
1191 case 0x8070: /* P4B */
1192 case 0x8088: /* P4B533 */
1193 case 0x1626: /* L3C notebook */
1194 asus_hides_smbus
= 1;
1196 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
)
1197 switch(dev
->subsystem_device
) {
1198 case 0x80b1: /* P4GE-V */
1199 case 0x80b2: /* P4PE */
1200 case 0x8093: /* P4B533-V */
1201 asus_hides_smbus
= 1;
1203 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82850_HB
)
1204 switch(dev
->subsystem_device
) {
1205 case 0x8030: /* P4T533 */
1206 asus_hides_smbus
= 1;
1208 else if (dev
->device
== PCI_DEVICE_ID_INTEL_7205_0
)
1209 switch (dev
->subsystem_device
) {
1210 case 0x8070: /* P4G8X Deluxe */
1211 asus_hides_smbus
= 1;
1213 else if (dev
->device
== PCI_DEVICE_ID_INTEL_E7501_MCH
)
1214 switch (dev
->subsystem_device
) {
1215 case 0x80c9: /* PU-DLS */
1216 asus_hides_smbus
= 1;
1218 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
1219 switch (dev
->subsystem_device
) {
1220 case 0x1751: /* M2N notebook */
1221 case 0x1821: /* M5N notebook */
1222 case 0x1897: /* A6L notebook */
1223 asus_hides_smbus
= 1;
1225 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1226 switch (dev
->subsystem_device
) {
1227 case 0x184b: /* W1N notebook */
1228 case 0x186a: /* M6Ne notebook */
1229 asus_hides_smbus
= 1;
1231 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1232 switch (dev
->subsystem_device
) {
1233 case 0x80f2: /* P4P800-X */
1234 asus_hides_smbus
= 1;
1236 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82915GM_HB
)
1237 switch (dev
->subsystem_device
) {
1238 case 0x1882: /* M6V notebook */
1239 case 0x1977: /* A6VA notebook */
1240 asus_hides_smbus
= 1;
1242 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_HP
)) {
1243 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1244 switch(dev
->subsystem_device
) {
1245 case 0x088C: /* HP Compaq nc8000 */
1246 case 0x0890: /* HP Compaq nc6000 */
1247 asus_hides_smbus
= 1;
1249 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1250 switch (dev
->subsystem_device
) {
1251 case 0x12bc: /* HP D330L */
1252 case 0x12bd: /* HP D530 */
1253 case 0x006a: /* HP Compaq nx9500 */
1254 asus_hides_smbus
= 1;
1256 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82875_HB
)
1257 switch (dev
->subsystem_device
) {
1258 case 0x12bf: /* HP xw4100 */
1259 asus_hides_smbus
= 1;
1261 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_SAMSUNG
)) {
1262 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1263 switch(dev
->subsystem_device
) {
1264 case 0xC00C: /* Samsung P35 notebook */
1265 asus_hides_smbus
= 1;
1267 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
)) {
1268 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1269 switch(dev
->subsystem_device
) {
1270 case 0x0058: /* Compaq Evo N620c */
1271 asus_hides_smbus
= 1;
1273 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82810_IG3
)
1274 switch(dev
->subsystem_device
) {
1275 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1276 /* Motherboard doesn't have Host bridge
1277 * subvendor/subdevice IDs, therefore checking
1278 * its on-board VGA controller */
1279 asus_hides_smbus
= 1;
1281 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82801DB_2
)
1282 switch(dev
->subsystem_device
) {
1283 case 0x00b8: /* Compaq Evo D510 CMT */
1284 case 0x00b9: /* Compaq Evo D510 SFF */
1285 case 0x00ba: /* Compaq Evo D510 USDT */
1286 /* Motherboard doesn't have Host bridge
1287 * subvendor/subdevice IDs and on-board VGA
1288 * controller is disabled if an AGP card is
1289 * inserted, therefore checking USB UHCI
1291 asus_hides_smbus
= 1;
1293 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82815_CGC
)
1294 switch (dev
->subsystem_device
) {
1295 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1296 /* Motherboard doesn't have host bridge
1297 * subvendor/subdevice IDs, therefore checking
1298 * its on-board VGA controller */
1299 asus_hides_smbus
= 1;
1303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845_HB
, asus_hides_smbus_hostbridge
);
1304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845G_HB
, asus_hides_smbus_hostbridge
);
1305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82850_HB
, asus_hides_smbus_hostbridge
);
1306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
, asus_hides_smbus_hostbridge
);
1307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82875_HB
, asus_hides_smbus_hostbridge
);
1308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_7205_0
, asus_hides_smbus_hostbridge
);
1309 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7501_MCH
, asus_hides_smbus_hostbridge
);
1310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855PM_HB
, asus_hides_smbus_hostbridge
);
1311 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855GM_HB
, asus_hides_smbus_hostbridge
);
1312 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82915GM_HB
, asus_hides_smbus_hostbridge
);
1314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82810_IG3
, asus_hides_smbus_hostbridge
);
1315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_2
, asus_hides_smbus_hostbridge
);
1316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82815_CGC
, asus_hides_smbus_hostbridge
);
1318 static void asus_hides_smbus_lpc(struct pci_dev
*dev
)
1322 if (likely(!asus_hides_smbus
))
1325 pci_read_config_word(dev
, 0xF2, &val
);
1327 pci_write_config_word(dev
, 0xF2, val
& (~0x8));
1328 pci_read_config_word(dev
, 0xF2, &val
);
1330 dev_info(&dev
->dev
, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val
);
1332 dev_info(&dev
->dev
, "Enabled i801 SMBus device\n");
1335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1342 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1343 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1344 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1345 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1346 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1347 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1348 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1350 /* It appears we just have one such device. If not, we have a warning */
1351 static void __iomem
*asus_rcba_base
;
1352 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev
*dev
)
1356 if (likely(!asus_hides_smbus
))
1358 WARN_ON(asus_rcba_base
);
1360 pci_read_config_dword(dev
, 0xF0, &rcba
);
1361 /* use bits 31:14, 16 kB aligned */
1362 asus_rcba_base
= ioremap_nocache(rcba
& 0xFFFFC000, 0x4000);
1363 if (asus_rcba_base
== NULL
)
1367 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev
*dev
)
1371 if (likely(!asus_hides_smbus
|| !asus_rcba_base
))
1373 /* read the Function Disable register, dword mode only */
1374 val
= readl(asus_rcba_base
+ 0x3418);
1375 writel(val
& 0xFFFFFFF7, asus_rcba_base
+ 0x3418); /* enable the SMBus device */
1378 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev
*dev
)
1380 if (likely(!asus_hides_smbus
|| !asus_rcba_base
))
1382 iounmap(asus_rcba_base
);
1383 asus_rcba_base
= NULL
;
1384 dev_info(&dev
->dev
, "Enabled ICH6/i801 SMBus device\n");
1387 static void asus_hides_smbus_lpc_ich6(struct pci_dev
*dev
)
1389 asus_hides_smbus_lpc_ich6_suspend(dev
);
1390 asus_hides_smbus_lpc_ich6_resume_early(dev
);
1391 asus_hides_smbus_lpc_ich6_resume(dev
);
1393 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6
);
1394 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_suspend
);
1395 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_resume
);
1396 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_resume_early
);
1399 * SiS 96x south bridge: BIOS typically hides SMBus device...
1401 static void quirk_sis_96x_smbus(struct pci_dev
*dev
)
1404 pci_read_config_byte(dev
, 0x77, &val
);
1406 dev_info(&dev
->dev
, "Enabling SiS 96x SMBus\n");
1407 pci_write_config_byte(dev
, 0x77, val
& ~0x10);
1410 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1411 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1412 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1413 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1414 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1415 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1416 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1417 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1420 * ... This is further complicated by the fact that some SiS96x south
1421 * bridges pretend to be 85C503/5513 instead. In that case see if we
1422 * spotted a compatible north bridge to make sure.
1423 * (pci_find_device doesn't work yet)
1425 * We can also enable the sis96x bit in the discovery register..
1427 #define SIS_DETECT_REGISTER 0x40
1429 static void quirk_sis_503(struct pci_dev
*dev
)
1434 pci_read_config_byte(dev
, SIS_DETECT_REGISTER
, ®
);
1435 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
| (1 << 6));
1436 pci_read_config_word(dev
, PCI_DEVICE_ID
, &devid
);
1437 if (((devid
& 0xfff0) != 0x0960) && (devid
!= 0x0018)) {
1438 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
);
1443 * Ok, it now shows up as a 96x.. run the 96x quirk by
1444 * hand in case it has already been processed.
1445 * (depends on link order, which is apparently not guaranteed)
1447 dev
->device
= devid
;
1448 quirk_sis_96x_smbus(dev
);
1450 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1451 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1455 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1456 * and MC97 modem controller are disabled when a second PCI soundcard is
1457 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1460 static void asus_hides_ac97_lpc(struct pci_dev
*dev
)
1463 int asus_hides_ac97
= 0;
1465 if (likely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1466 if (dev
->device
== PCI_DEVICE_ID_VIA_8237
)
1467 asus_hides_ac97
= 1;
1470 if (!asus_hides_ac97
)
1473 pci_read_config_byte(dev
, 0x50, &val
);
1475 pci_write_config_byte(dev
, 0x50, val
& (~0xc0));
1476 pci_read_config_byte(dev
, 0x50, &val
);
1478 dev_info(&dev
->dev
, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val
);
1480 dev_info(&dev
->dev
, "Enabled onboard AC97/MC97 devices\n");
1483 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1484 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1486 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1489 * If we are using libata we can drive this chip properly but must
1490 * do this early on to make the additional device appear during
1493 static void quirk_jmicron_ata(struct pci_dev
*pdev
)
1495 u32 conf1
, conf5
, class;
1498 /* Only poke fn 0 */
1499 if (PCI_FUNC(pdev
->devfn
))
1502 pci_read_config_dword(pdev
, 0x40, &conf1
);
1503 pci_read_config_dword(pdev
, 0x80, &conf5
);
1505 conf1
&= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1506 conf5
&= ~(1 << 24); /* Clear bit 24 */
1508 switch (pdev
->device
) {
1509 case PCI_DEVICE_ID_JMICRON_JMB360
: /* SATA single port */
1510 case PCI_DEVICE_ID_JMICRON_JMB362
: /* SATA dual ports */
1511 /* The controller should be in single function ahci mode */
1512 conf1
|= 0x0002A100; /* Set 8, 13, 15, 17 */
1515 case PCI_DEVICE_ID_JMICRON_JMB365
:
1516 case PCI_DEVICE_ID_JMICRON_JMB366
:
1517 /* Redirect IDE second PATA port to the right spot */
1520 case PCI_DEVICE_ID_JMICRON_JMB361
:
1521 case PCI_DEVICE_ID_JMICRON_JMB363
:
1522 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1523 /* Set the class codes correctly and then direct IDE 0 */
1524 conf1
|= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1527 case PCI_DEVICE_ID_JMICRON_JMB368
:
1528 /* The controller should be in single function IDE mode */
1529 conf1
|= 0x00C00000; /* Set 22, 23 */
1533 pci_write_config_dword(pdev
, 0x40, conf1
);
1534 pci_write_config_dword(pdev
, 0x80, conf5
);
1536 /* Update pdev accordingly */
1537 pci_read_config_byte(pdev
, PCI_HEADER_TYPE
, &hdr
);
1538 pdev
->hdr_type
= hdr
& 0x7f;
1539 pdev
->multifunction
= !!(hdr
& 0x80);
1541 pci_read_config_dword(pdev
, PCI_CLASS_REVISION
, &class);
1542 pdev
->class = class >> 8;
1544 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1545 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1546 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB362
, quirk_jmicron_ata
);
1547 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1548 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1549 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1550 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1551 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1552 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1553 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB362
, quirk_jmicron_ata
);
1554 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1555 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1556 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1557 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1561 #ifdef CONFIG_X86_IO_APIC
1562 static void __init
quirk_alder_ioapic(struct pci_dev
*pdev
)
1566 if ((pdev
->class >> 8) != 0xff00)
1569 /* the first BAR is the location of the IO APIC...we must
1570 * not touch this (and it's already covered by the fixmap), so
1571 * forcibly insert it into the resource tree */
1572 if (pci_resource_start(pdev
, 0) && pci_resource_len(pdev
, 0))
1573 insert_resource(&iomem_resource
, &pdev
->resource
[0]);
1575 /* The next five BARs all seem to be rubbish, so just clean
1577 for (i
=1; i
< 6; i
++) {
1578 memset(&pdev
->resource
[i
], 0, sizeof(pdev
->resource
[i
]));
1582 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EESSC
, quirk_alder_ioapic
);
1585 static void __devinit
quirk_pcie_mch(struct pci_dev
*pdev
)
1590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7520_MCH
, quirk_pcie_mch
);
1591 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7320_MCH
, quirk_pcie_mch
);
1592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7525_MCH
, quirk_pcie_mch
);
1596 * It's possible for the MSI to get corrupted if shpc and acpi
1597 * are used together on certain PXH-based systems.
1599 static void __devinit
quirk_pcie_pxh(struct pci_dev
*dev
)
1603 dev_warn(&dev
->dev
, "PXH quirk detected; SHPC device MSI disabled\n");
1605 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_0
, quirk_pcie_pxh
);
1606 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_1
, quirk_pcie_pxh
);
1607 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_pcie_pxh
);
1608 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_pcie_pxh
);
1609 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_pcie_pxh
);
1612 * Some Intel PCI Express chipsets have trouble with downstream
1613 * device power management.
1615 static void quirk_intel_pcie_pm(struct pci_dev
* dev
)
1617 pci_pm_d3_delay
= 120;
1621 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e2, quirk_intel_pcie_pm
);
1622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e3, quirk_intel_pcie_pm
);
1623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e4, quirk_intel_pcie_pm
);
1624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e5, quirk_intel_pcie_pm
);
1625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e6, quirk_intel_pcie_pm
);
1626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e7, quirk_intel_pcie_pm
);
1627 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f7, quirk_intel_pcie_pm
);
1628 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f8, quirk_intel_pcie_pm
);
1629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f9, quirk_intel_pcie_pm
);
1630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25fa, quirk_intel_pcie_pm
);
1631 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2601, quirk_intel_pcie_pm
);
1632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2602, quirk_intel_pcie_pm
);
1633 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2603, quirk_intel_pcie_pm
);
1634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2604, quirk_intel_pcie_pm
);
1635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2605, quirk_intel_pcie_pm
);
1636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2606, quirk_intel_pcie_pm
);
1637 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2607, quirk_intel_pcie_pm
);
1638 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2608, quirk_intel_pcie_pm
);
1639 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2609, quirk_intel_pcie_pm
);
1640 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260a, quirk_intel_pcie_pm
);
1641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260b, quirk_intel_pcie_pm
);
1643 #ifdef CONFIG_X86_IO_APIC
1645 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1646 * remap the original interrupt in the linux kernel to the boot interrupt, so
1647 * that a PCI device's interrupt handler is installed on the boot interrupt
1650 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev
*dev
)
1652 if (noioapicquirk
|| noioapicreroute
)
1655 dev
->irq_reroute_variant
= INTEL_IRQ_REROUTE_VARIANT
;
1656 dev_info(&dev
->dev
, "rerouting interrupts for [%04x:%04x]\n",
1657 dev
->vendor
, dev
->device
);
1659 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_0
, quirk_reroute_to_boot_interrupts_intel
);
1660 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_1
, quirk_reroute_to_boot_interrupts_intel
);
1661 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_0
, quirk_reroute_to_boot_interrupts_intel
);
1662 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_reroute_to_boot_interrupts_intel
);
1663 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_reroute_to_boot_interrupts_intel
);
1664 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_reroute_to_boot_interrupts_intel
);
1665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_0
, quirk_reroute_to_boot_interrupts_intel
);
1666 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_1
, quirk_reroute_to_boot_interrupts_intel
);
1667 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_0
, quirk_reroute_to_boot_interrupts_intel
);
1668 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_1
, quirk_reroute_to_boot_interrupts_intel
);
1669 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_0
, quirk_reroute_to_boot_interrupts_intel
);
1670 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_reroute_to_boot_interrupts_intel
);
1671 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_reroute_to_boot_interrupts_intel
);
1672 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_reroute_to_boot_interrupts_intel
);
1673 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_0
, quirk_reroute_to_boot_interrupts_intel
);
1674 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_1
, quirk_reroute_to_boot_interrupts_intel
);
1677 * On some chipsets we can disable the generation of legacy INTx boot
1682 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1683 * 300641-004US, section 5.7.3.
1685 #define INTEL_6300_IOAPIC_ABAR 0x40
1686 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1688 static void quirk_disable_intel_boot_interrupt(struct pci_dev
*dev
)
1690 u16 pci_config_word
;
1695 pci_read_config_word(dev
, INTEL_6300_IOAPIC_ABAR
, &pci_config_word
);
1696 pci_config_word
|= INTEL_6300_DISABLE_BOOT_IRQ
;
1697 pci_write_config_word(dev
, INTEL_6300_IOAPIC_ABAR
, pci_config_word
);
1699 dev_info(&dev
->dev
, "disabled boot interrupts on device [%04x:%04x]\n",
1700 dev
->vendor
, dev
->device
);
1702 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_10
, quirk_disable_intel_boot_interrupt
);
1703 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_10
, quirk_disable_intel_boot_interrupt
);
1706 * disable boot interrupts on HT-1000
1708 #define BC_HT1000_FEATURE_REG 0x64
1709 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1710 #define BC_HT1000_MAP_IDX 0xC00
1711 #define BC_HT1000_MAP_DATA 0xC01
1713 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev
*dev
)
1715 u32 pci_config_dword
;
1721 pci_read_config_dword(dev
, BC_HT1000_FEATURE_REG
, &pci_config_dword
);
1722 pci_write_config_dword(dev
, BC_HT1000_FEATURE_REG
, pci_config_dword
|
1723 BC_HT1000_PIC_REGS_ENABLE
);
1725 for (irq
= 0x10; irq
< 0x10 + 32; irq
++) {
1726 outb(irq
, BC_HT1000_MAP_IDX
);
1727 outb(0x00, BC_HT1000_MAP_DATA
);
1730 pci_write_config_dword(dev
, BC_HT1000_FEATURE_REG
, pci_config_dword
);
1732 dev_info(&dev
->dev
, "disabled boot interrupts on device [%04x:%04x]\n",
1733 dev
->vendor
, dev
->device
);
1735 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000SB
, quirk_disable_broadcom_boot_interrupt
);
1736 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000SB
, quirk_disable_broadcom_boot_interrupt
);
1739 * disable boot interrupts on AMD and ATI chipsets
1742 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1743 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1744 * (due to an erratum).
1746 #define AMD_813X_MISC 0x40
1747 #define AMD_813X_NOIOAMODE (1<<0)
1748 #define AMD_813X_REV_B1 0x12
1749 #define AMD_813X_REV_B2 0x13
1751 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev
*dev
)
1753 u32 pci_config_dword
;
1757 if ((dev
->revision
== AMD_813X_REV_B1
) ||
1758 (dev
->revision
== AMD_813X_REV_B2
))
1761 pci_read_config_dword(dev
, AMD_813X_MISC
, &pci_config_dword
);
1762 pci_config_dword
&= ~AMD_813X_NOIOAMODE
;
1763 pci_write_config_dword(dev
, AMD_813X_MISC
, pci_config_dword
);
1765 dev_info(&dev
->dev
, "disabled boot interrupts on device [%04x:%04x]\n",
1766 dev
->vendor
, dev
->device
);
1768 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
1769 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
1770 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
1771 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
1773 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1775 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev
*dev
)
1777 u16 pci_config_word
;
1782 pci_read_config_word(dev
, AMD_8111_PCI_IRQ_ROUTING
, &pci_config_word
);
1783 if (!pci_config_word
) {
1784 dev_info(&dev
->dev
, "boot interrupts on device [%04x:%04x] "
1785 "already disabled\n", dev
->vendor
, dev
->device
);
1788 pci_write_config_word(dev
, AMD_8111_PCI_IRQ_ROUTING
, 0);
1789 dev_info(&dev
->dev
, "disabled boot interrupts on device [%04x:%04x]\n",
1790 dev
->vendor
, dev
->device
);
1792 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8111_SMBUS
, quirk_disable_amd_8111_boot_interrupt
);
1793 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8111_SMBUS
, quirk_disable_amd_8111_boot_interrupt
);
1794 #endif /* CONFIG_X86_IO_APIC */
1797 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1798 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1799 * Re-allocate the region if needed...
1801 static void __init
quirk_tc86c001_ide(struct pci_dev
*dev
)
1803 struct resource
*r
= &dev
->resource
[0];
1805 if (r
->start
& 0x8) {
1810 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2
,
1811 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE
,
1812 quirk_tc86c001_ide
);
1814 static void __devinit
quirk_netmos(struct pci_dev
*dev
)
1816 unsigned int num_parallel
= (dev
->subsystem_device
& 0xf0) >> 4;
1817 unsigned int num_serial
= dev
->subsystem_device
& 0xf;
1820 * These Netmos parts are multiport serial devices with optional
1821 * parallel ports. Even when parallel ports are present, they
1822 * are identified as class SERIAL, which means the serial driver
1823 * will claim them. To prevent this, mark them as class OTHER.
1824 * These combo devices should be claimed by parport_serial.
1826 * The subdevice ID is of the form 0x00PS, where <P> is the number
1827 * of parallel ports and <S> is the number of serial ports.
1829 switch (dev
->device
) {
1830 case PCI_DEVICE_ID_NETMOS_9835
:
1831 /* Well, this rule doesn't hold for the following 9835 device */
1832 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_IBM
&&
1833 dev
->subsystem_device
== 0x0299)
1835 case PCI_DEVICE_ID_NETMOS_9735
:
1836 case PCI_DEVICE_ID_NETMOS_9745
:
1837 case PCI_DEVICE_ID_NETMOS_9845
:
1838 case PCI_DEVICE_ID_NETMOS_9855
:
1839 if ((dev
->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL
&&
1841 dev_info(&dev
->dev
, "Netmos %04x (%u parallel, "
1842 "%u serial); changing class SERIAL to OTHER "
1843 "(use parport_serial)\n",
1844 dev
->device
, num_parallel
, num_serial
);
1845 dev
->class = (PCI_CLASS_COMMUNICATION_OTHER
<< 8) |
1846 (dev
->class & 0xff);
1850 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS
, PCI_ANY_ID
, quirk_netmos
);
1852 static void __devinit
quirk_e100_interrupt(struct pci_dev
*dev
)
1859 switch (dev
->device
) {
1860 /* PCI IDs taken from drivers/net/e100.c */
1862 case 0x1030 ... 0x1034:
1863 case 0x1038 ... 0x103E:
1864 case 0x1050 ... 0x1057:
1866 case 0x1064 ... 0x106B:
1867 case 0x1091 ... 0x1095:
1880 * Some firmware hands off the e100 with interrupts enabled,
1881 * which can cause a flood of interrupts if packets are
1882 * received before the driver attaches to the device. So
1883 * disable all e100 interrupts here. The driver will
1884 * re-enable them when it's ready.
1886 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1888 if (!(command
& PCI_COMMAND_MEMORY
) || !pci_resource_start(dev
, 0))
1892 * Check that the device is in the D0 power state. If it's not,
1893 * there is no point to look any further.
1895 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1897 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &pmcsr
);
1898 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) != PCI_D0
)
1902 /* Convert from PCI bus to resource space. */
1903 csr
= ioremap(pci_resource_start(dev
, 0), 8);
1905 dev_warn(&dev
->dev
, "Can't map e100 registers\n");
1909 cmd_hi
= readb(csr
+ 3);
1911 dev_warn(&dev
->dev
, "Firmware left e100 interrupts enabled; "
1918 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, quirk_e100_interrupt
);
1921 * The 82575 and 82598 may experience data corruption issues when transitioning
1922 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1924 static void __devinit
quirk_disable_aspm_l0s(struct pci_dev
*dev
)
1926 dev_info(&dev
->dev
, "Disabling L0s\n");
1927 pci_disable_link_state(dev
, PCIE_LINK_STATE_L0S
);
1929 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10a7, quirk_disable_aspm_l0s
);
1930 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10a9, quirk_disable_aspm_l0s
);
1931 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10b6, quirk_disable_aspm_l0s
);
1932 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c6, quirk_disable_aspm_l0s
);
1933 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c7, quirk_disable_aspm_l0s
);
1934 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c8, quirk_disable_aspm_l0s
);
1935 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10d6, quirk_disable_aspm_l0s
);
1936 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10db, quirk_disable_aspm_l0s
);
1937 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10dd, quirk_disable_aspm_l0s
);
1938 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10e1, quirk_disable_aspm_l0s
);
1939 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10ec, quirk_disable_aspm_l0s
);
1940 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10f1, quirk_disable_aspm_l0s
);
1941 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10f4, quirk_disable_aspm_l0s
);
1942 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1508, quirk_disable_aspm_l0s
);
1944 static void __devinit
fixup_rev1_53c810(struct pci_dev
* dev
)
1946 /* rev 1 ncr53c810 chips don't set the class at all which means
1947 * they don't get their resources remapped. Fix that here.
1950 if (dev
->class == PCI_CLASS_NOT_DEFINED
) {
1951 dev_info(&dev
->dev
, "NCR 53c810 rev 1 detected; setting PCI class\n");
1952 dev
->class = PCI_CLASS_STORAGE_SCSI
;
1955 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR
, PCI_DEVICE_ID_NCR_53C810
, fixup_rev1_53c810
);
1957 /* Enable 1k I/O space granularity on the Intel P64H2 */
1958 static void __devinit
quirk_p64h2_1k_io(struct pci_dev
*dev
)
1961 u8 io_base_lo
, io_limit_lo
;
1962 unsigned long base
, limit
;
1963 struct resource
*res
= dev
->resource
+ PCI_BRIDGE_RESOURCES
;
1965 pci_read_config_word(dev
, 0x40, &en1k
);
1968 dev_info(&dev
->dev
, "Enable I/O Space to 1KB granularity\n");
1970 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
1971 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
1972 base
= (io_base_lo
& (PCI_IO_RANGE_MASK
| 0x0c)) << 8;
1973 limit
= (io_limit_lo
& (PCI_IO_RANGE_MASK
| 0x0c)) << 8;
1975 if (base
<= limit
) {
1977 res
->end
= limit
+ 0x3ff;
1981 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x1460, quirk_p64h2_1k_io
);
1983 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1984 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1985 * in drivers/pci/setup-bus.c
1987 static void __devinit
quirk_p64h2_1k_io_fix_iobl(struct pci_dev
*dev
)
1989 u16 en1k
, iobl_adr
, iobl_adr_1k
;
1990 struct resource
*res
= dev
->resource
+ PCI_BRIDGE_RESOURCES
;
1992 pci_read_config_word(dev
, 0x40, &en1k
);
1995 pci_read_config_word(dev
, PCI_IO_BASE
, &iobl_adr
);
1997 iobl_adr_1k
= iobl_adr
| (res
->start
>> 8) | (res
->end
& 0xfc00);
1999 if (iobl_adr
!= iobl_adr_1k
) {
2000 dev_info(&dev
->dev
, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
2001 iobl_adr
,iobl_adr_1k
);
2002 pci_write_config_word(dev
, PCI_IO_BASE
, iobl_adr_1k
);
2006 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1460, quirk_p64h2_1k_io_fix_iobl
);
2008 /* Under some circumstances, AER is not linked with extended capabilities.
2009 * Force it to be linked by setting the corresponding control bit in the
2012 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev
*dev
)
2015 if (pci_read_config_byte(dev
, 0xf41, &b
) == 0) {
2017 pci_write_config_byte(dev
, 0xf41, b
| 0x20);
2019 "Linking AER extended capability\n");
2023 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2024 quirk_nvidia_ck804_pcie_aer_ext_cap
);
2025 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2026 quirk_nvidia_ck804_pcie_aer_ext_cap
);
2028 static void __devinit
quirk_via_cx700_pci_parking_caching(struct pci_dev
*dev
)
2031 * Disable PCI Bus Parking and PCI Master read caching on CX700
2032 * which causes unspecified timing errors with a VT6212L on the PCI
2033 * bus leading to USB2.0 packet loss. The defaults are that these
2034 * features are turned off but some BIOSes turn them on.
2038 if (pci_read_config_byte(dev
, 0x76, &b
) == 0) {
2040 /* Turn off PCI Bus Parking */
2041 pci_write_config_byte(dev
, 0x76, b
^ 0x40);
2044 "Disabling VIA CX700 PCI parking\n");
2048 if (pci_read_config_byte(dev
, 0x72, &b
) == 0) {
2050 /* Turn off PCI Master read caching */
2051 pci_write_config_byte(dev
, 0x72, 0x0);
2053 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2054 pci_write_config_byte(dev
, 0x75, 0x1);
2056 /* Disable "Read FIFO Timer" */
2057 pci_write_config_byte(dev
, 0x77, 0x0);
2060 "Disabling VIA CX700 PCI caching\n");
2064 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA
, 0x324e, quirk_via_cx700_pci_parking_caching
);
2067 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2068 * VPD end tag will hang the device. This problem was initially
2069 * observed when a vpd entry was created in sysfs
2070 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2071 * will dump 32k of data. Reading a full 32k will cause an access
2072 * beyond the VPD end tag causing the device to hang. Once the device
2073 * is hung, the bnx2 driver will not be able to reset the device.
2074 * We believe that it is legal to read beyond the end tag and
2075 * therefore the solution is to limit the read/write length.
2077 static void __devinit
quirk_brcm_570x_limit_vpd(struct pci_dev
*dev
)
2080 * Only disable the VPD capability for 5706, 5706S, 5708,
2081 * 5708S and 5709 rev. A
2083 if ((dev
->device
== PCI_DEVICE_ID_NX2_5706
) ||
2084 (dev
->device
== PCI_DEVICE_ID_NX2_5706S
) ||
2085 (dev
->device
== PCI_DEVICE_ID_NX2_5708
) ||
2086 (dev
->device
== PCI_DEVICE_ID_NX2_5708S
) ||
2087 ((dev
->device
== PCI_DEVICE_ID_NX2_5709
) &&
2088 (dev
->revision
& 0xf0) == 0x0)) {
2090 dev
->vpd
->len
= 0x80;
2094 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2095 PCI_DEVICE_ID_NX2_5706
,
2096 quirk_brcm_570x_limit_vpd
);
2097 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2098 PCI_DEVICE_ID_NX2_5706S
,
2099 quirk_brcm_570x_limit_vpd
);
2100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2101 PCI_DEVICE_ID_NX2_5708
,
2102 quirk_brcm_570x_limit_vpd
);
2103 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2104 PCI_DEVICE_ID_NX2_5708S
,
2105 quirk_brcm_570x_limit_vpd
);
2106 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2107 PCI_DEVICE_ID_NX2_5709
,
2108 quirk_brcm_570x_limit_vpd
);
2109 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2110 PCI_DEVICE_ID_NX2_5709S
,
2111 quirk_brcm_570x_limit_vpd
);
2113 /* Originally in EDAC sources for i82875P:
2114 * Intel tells BIOS developers to hide device 6 which
2115 * configures the overflow device access containing
2116 * the DRBs - this is where we expose device 6.
2117 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2119 static void __devinit
quirk_unhide_mch_dev6(struct pci_dev
*dev
)
2123 if (pci_read_config_byte(dev
, 0xF4, ®
) == 0 && !(reg
& 0x02)) {
2124 dev_info(&dev
->dev
, "Enabling MCH 'Overflow' Device\n");
2125 pci_write_config_byte(dev
, 0xF4, reg
| 0x02);
2129 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
,
2130 quirk_unhide_mch_dev6
);
2131 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82875_HB
,
2132 quirk_unhide_mch_dev6
);
2135 #ifdef CONFIG_PCI_MSI
2136 /* Some chipsets do not support MSI. We cannot easily rely on setting
2137 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2138 * some other busses controlled by the chipset even if Linux is not
2139 * aware of it. Instead of setting the flag on all busses in the
2140 * machine, simply disable MSI globally.
2142 static void __init
quirk_disable_all_msi(struct pci_dev
*dev
)
2145 dev_warn(&dev
->dev
, "MSI quirk detected; MSI disabled\n");
2147 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE
, quirk_disable_all_msi
);
2148 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS400_200
, quirk_disable_all_msi
);
2149 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS480
, quirk_disable_all_msi
);
2150 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3336
, quirk_disable_all_msi
);
2151 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3351
, quirk_disable_all_msi
);
2152 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3364
, quirk_disable_all_msi
);
2154 /* Disable MSI on chipsets that are known to not support it */
2155 static void __devinit
quirk_disable_msi(struct pci_dev
*dev
)
2157 if (dev
->subordinate
) {
2158 dev_warn(&dev
->dev
, "MSI quirk detected; "
2159 "subordinate MSI disabled\n");
2160 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_msi
);
2164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, 0xa238, quirk_disable_msi
);
2165 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x5a3f, quirk_disable_msi
);
2167 /* Go through the list of Hypertransport capabilities and
2168 * return 1 if a HT MSI capability is found and enabled */
2169 static int __devinit
msi_ht_cap_enabled(struct pci_dev
*dev
)
2173 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2174 while (pos
&& ttl
--) {
2177 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2180 dev_info(&dev
->dev
, "Found %s HT MSI Mapping\n",
2181 flags
& HT_MSI_FLAGS_ENABLE
?
2182 "enabled" : "disabled");
2183 return (flags
& HT_MSI_FLAGS_ENABLE
) != 0;
2186 pos
= pci_find_next_ht_capability(dev
, pos
,
2187 HT_CAPTYPE_MSI_MAPPING
);
2192 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2193 static void __devinit
quirk_msi_ht_cap(struct pci_dev
*dev
)
2195 if (dev
->subordinate
&& !msi_ht_cap_enabled(dev
)) {
2196 dev_warn(&dev
->dev
, "MSI quirk detected; "
2197 "subordinate MSI disabled\n");
2198 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE
,
2204 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2205 * MSI are supported if the MSI capability set in any of these mappings.
2207 static void __devinit
quirk_nvidia_ck804_msi_ht_cap(struct pci_dev
*dev
)
2209 struct pci_dev
*pdev
;
2211 if (!dev
->subordinate
)
2214 /* check HT MSI cap on this chipset and the root one.
2215 * a single one having MSI is enough to be sure that MSI are supported.
2217 pdev
= pci_get_slot(dev
->bus
, 0);
2220 if (!msi_ht_cap_enabled(dev
) && !msi_ht_cap_enabled(pdev
)) {
2221 dev_warn(&dev
->dev
, "MSI quirk detected; "
2222 "subordinate MSI disabled\n");
2223 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2228 quirk_nvidia_ck804_msi_ht_cap
);
2230 /* Force enable MSI mapping capability on HT bridges */
2231 static void __devinit
ht_enable_msi_mapping(struct pci_dev
*dev
)
2235 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2236 while (pos
&& ttl
--) {
2239 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2241 dev_info(&dev
->dev
, "Enabling HT MSI Mapping\n");
2243 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2244 flags
| HT_MSI_FLAGS_ENABLE
);
2246 pos
= pci_find_next_ht_capability(dev
, pos
,
2247 HT_CAPTYPE_MSI_MAPPING
);
2250 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS
,
2251 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB
,
2252 ht_enable_msi_mapping
);
2254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
,
2255 ht_enable_msi_mapping
);
2257 /* The P5N32-SLI motherboards from Asus have a problem with msi
2258 * for the MCP55 NIC. It is not yet determined whether the msi problem
2259 * also affects other devices. As for now, turn off msi for this device.
2261 static void __devinit
nvenet_msi_disable(struct pci_dev
*dev
)
2263 if (dmi_name_in_vendors("P5N32-SLI PREMIUM") ||
2264 dmi_name_in_vendors("P5N32-E SLI")) {
2266 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2270 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2271 PCI_DEVICE_ID_NVIDIA_NVENET_15
,
2272 nvenet_msi_disable
);
2274 static int __devinit
ht_check_msi_mapping(struct pci_dev
*dev
)
2279 /* check if there is HT MSI cap or enabled on this device */
2280 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2281 while (pos
&& ttl
--) {
2286 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2288 if (flags
& HT_MSI_FLAGS_ENABLE
) {
2295 pos
= pci_find_next_ht_capability(dev
, pos
,
2296 HT_CAPTYPE_MSI_MAPPING
);
2302 static int __devinit
host_bridge_with_leaf(struct pci_dev
*host_bridge
)
2304 struct pci_dev
*dev
;
2309 dev_no
= host_bridge
->devfn
>> 3;
2310 for (i
= dev_no
+ 1; i
< 0x20; i
++) {
2311 dev
= pci_get_slot(host_bridge
->bus
, PCI_DEVFN(i
, 0));
2315 /* found next host bridge ?*/
2316 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_SLAVE
);
2322 if (ht_check_msi_mapping(dev
)) {
2333 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2334 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2336 static int __devinit
is_end_of_ht_chain(struct pci_dev
*dev
)
2342 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_SLAVE
);
2347 pci_read_config_word(dev
, pos
+ PCI_CAP_FLAGS
, &flags
);
2349 ctrl_off
= ((flags
>> 10) & 1) ?
2350 PCI_HT_CAP_SLAVE_CTRL0
: PCI_HT_CAP_SLAVE_CTRL1
;
2351 pci_read_config_word(dev
, pos
+ ctrl_off
, &ctrl
);
2353 if (ctrl
& (1 << 6))
2360 static void __devinit
nv_ht_enable_msi_mapping(struct pci_dev
*dev
)
2362 struct pci_dev
*host_bridge
;
2367 dev_no
= dev
->devfn
>> 3;
2368 for (i
= dev_no
; i
>= 0; i
--) {
2369 host_bridge
= pci_get_slot(dev
->bus
, PCI_DEVFN(i
, 0));
2373 pos
= pci_find_ht_capability(host_bridge
, HT_CAPTYPE_SLAVE
);
2378 pci_dev_put(host_bridge
);
2384 /* don't enable end_device/host_bridge with leaf directly here */
2385 if (host_bridge
== dev
&& is_end_of_ht_chain(host_bridge
) &&
2386 host_bridge_with_leaf(host_bridge
))
2389 /* root did that ! */
2390 if (msi_ht_cap_enabled(host_bridge
))
2393 ht_enable_msi_mapping(dev
);
2396 pci_dev_put(host_bridge
);
2399 static void __devinit
ht_disable_msi_mapping(struct pci_dev
*dev
)
2403 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2404 while (pos
&& ttl
--) {
2407 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2409 dev_info(&dev
->dev
, "Disabling HT MSI Mapping\n");
2411 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2412 flags
& ~HT_MSI_FLAGS_ENABLE
);
2414 pos
= pci_find_next_ht_capability(dev
, pos
,
2415 HT_CAPTYPE_MSI_MAPPING
);
2419 static void __devinit
__nv_msi_ht_cap_quirk(struct pci_dev
*dev
, int all
)
2421 struct pci_dev
*host_bridge
;
2425 /* check if there is HT MSI cap or enabled on this device */
2426 found
= ht_check_msi_mapping(dev
);
2433 * HT MSI mapping should be disabled on devices that are below
2434 * a non-Hypertransport host bridge. Locate the host bridge...
2436 host_bridge
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2437 if (host_bridge
== NULL
) {
2439 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2443 pos
= pci_find_ht_capability(host_bridge
, HT_CAPTYPE_SLAVE
);
2445 /* Host bridge is to HT */
2447 /* it is not enabled, try to enable it */
2449 ht_enable_msi_mapping(dev
);
2451 nv_ht_enable_msi_mapping(dev
);
2456 /* HT MSI is not enabled */
2460 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2461 ht_disable_msi_mapping(dev
);
2464 static void __devinit
nv_msi_ht_cap_quirk_all(struct pci_dev
*dev
)
2466 return __nv_msi_ht_cap_quirk(dev
, 1);
2469 static void __devinit
nv_msi_ht_cap_quirk_leaf(struct pci_dev
*dev
)
2471 return __nv_msi_ht_cap_quirk(dev
, 0);
2474 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_leaf
);
2475 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_leaf
);
2477 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_all
);
2478 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_all
);
2480 static void __devinit
quirk_msi_intx_disable_bug(struct pci_dev
*dev
)
2482 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
2484 static void __devinit
quirk_msi_intx_disable_ati_bug(struct pci_dev
*dev
)
2488 /* SB700 MSI issue will be fixed at HW level from revision A21,
2489 * we need check PCI REVISION ID of SMBus controller to get SB700
2492 p
= pci_get_device(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
2497 if ((p
->revision
< 0x3B) && (p
->revision
>= 0x30))
2498 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
2501 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2502 PCI_DEVICE_ID_TIGON3_5780
,
2503 quirk_msi_intx_disable_bug
);
2504 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2505 PCI_DEVICE_ID_TIGON3_5780S
,
2506 quirk_msi_intx_disable_bug
);
2507 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2508 PCI_DEVICE_ID_TIGON3_5714
,
2509 quirk_msi_intx_disable_bug
);
2510 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2511 PCI_DEVICE_ID_TIGON3_5714S
,
2512 quirk_msi_intx_disable_bug
);
2513 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2514 PCI_DEVICE_ID_TIGON3_5715
,
2515 quirk_msi_intx_disable_bug
);
2516 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2517 PCI_DEVICE_ID_TIGON3_5715S
,
2518 quirk_msi_intx_disable_bug
);
2520 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4390,
2521 quirk_msi_intx_disable_ati_bug
);
2522 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4391,
2523 quirk_msi_intx_disable_ati_bug
);
2524 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4392,
2525 quirk_msi_intx_disable_ati_bug
);
2526 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4393,
2527 quirk_msi_intx_disable_ati_bug
);
2528 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4394,
2529 quirk_msi_intx_disable_ati_bug
);
2531 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4373,
2532 quirk_msi_intx_disable_bug
);
2533 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4374,
2534 quirk_msi_intx_disable_bug
);
2535 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4375,
2536 quirk_msi_intx_disable_bug
);
2538 #endif /* CONFIG_PCI_MSI */
2540 static void pci_do_fixups(struct pci_dev
*dev
, struct pci_fixup
*f
,
2541 struct pci_fixup
*end
)
2544 if ((f
->vendor
== dev
->vendor
|| f
->vendor
== (u16
) PCI_ANY_ID
) &&
2545 (f
->device
== dev
->device
|| f
->device
== (u16
) PCI_ANY_ID
)) {
2546 dev_dbg(&dev
->dev
, "calling %pF\n", f
->hook
);
2553 extern struct pci_fixup __start_pci_fixups_early
[];
2554 extern struct pci_fixup __end_pci_fixups_early
[];
2555 extern struct pci_fixup __start_pci_fixups_header
[];
2556 extern struct pci_fixup __end_pci_fixups_header
[];
2557 extern struct pci_fixup __start_pci_fixups_final
[];
2558 extern struct pci_fixup __end_pci_fixups_final
[];
2559 extern struct pci_fixup __start_pci_fixups_enable
[];
2560 extern struct pci_fixup __end_pci_fixups_enable
[];
2561 extern struct pci_fixup __start_pci_fixups_resume
[];
2562 extern struct pci_fixup __end_pci_fixups_resume
[];
2563 extern struct pci_fixup __start_pci_fixups_resume_early
[];
2564 extern struct pci_fixup __end_pci_fixups_resume_early
[];
2565 extern struct pci_fixup __start_pci_fixups_suspend
[];
2566 extern struct pci_fixup __end_pci_fixups_suspend
[];
2568 #if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
2569 #define VTUNCERRMSK_REG 0x1ac
2570 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2572 * This is a quirk for masking vt-d spec defined errors to platform error
2573 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2574 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2575 * on the RAS config settings of the platform) when a vt-d fault happens.
2576 * The resulting SMI caused the system to hang.
2578 * VT-d spec related errors are already handled by the VT-d OS code, so no
2579 * need to report the same error through other channels.
2581 static void vtd_mask_spec_errors(struct pci_dev
*dev
)
2585 pci_read_config_dword(dev
, VTUNCERRMSK_REG
, &word
);
2586 pci_write_config_dword(dev
, VTUNCERRMSK_REG
, word
| VTD_MSK_SPEC_ERRORS
);
2588 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x342e, vtd_mask_spec_errors
);
2589 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x3c28, vtd_mask_spec_errors
);
2592 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
)
2594 struct pci_fixup
*start
, *end
;
2597 case pci_fixup_early
:
2598 start
= __start_pci_fixups_early
;
2599 end
= __end_pci_fixups_early
;
2602 case pci_fixup_header
:
2603 start
= __start_pci_fixups_header
;
2604 end
= __end_pci_fixups_header
;
2607 case pci_fixup_final
:
2608 start
= __start_pci_fixups_final
;
2609 end
= __end_pci_fixups_final
;
2612 case pci_fixup_enable
:
2613 start
= __start_pci_fixups_enable
;
2614 end
= __end_pci_fixups_enable
;
2617 case pci_fixup_resume
:
2618 start
= __start_pci_fixups_resume
;
2619 end
= __end_pci_fixups_resume
;
2622 case pci_fixup_resume_early
:
2623 start
= __start_pci_fixups_resume_early
;
2624 end
= __end_pci_fixups_resume_early
;
2627 case pci_fixup_suspend
:
2628 start
= __start_pci_fixups_suspend
;
2629 end
= __end_pci_fixups_suspend
;
2633 /* stupid compiler warning, you would think with an enum... */
2636 pci_do_fixups(dev
, start
, end
);
2639 static int __init
pci_apply_final_quirks(void)
2641 struct pci_dev
*dev
= NULL
;
2645 if (pci_cache_line_size
)
2646 printk(KERN_DEBUG
"PCI: CLS %u bytes\n",
2647 pci_cache_line_size
<< 2);
2649 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
2650 pci_fixup_device(pci_fixup_final
, dev
);
2652 * If arch hasn't set it explicitly yet, use the CLS
2653 * value shared by all PCI devices. If there's a
2654 * mismatch, fall back to the default value.
2656 if (!pci_cache_line_size
) {
2657 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &tmp
);
2660 if (!tmp
|| cls
== tmp
)
2663 printk(KERN_DEBUG
"PCI: CLS mismatch (%u != %u), "
2664 "using %u bytes\n", cls
<< 2, tmp
<< 2,
2665 pci_dfl_cache_line_size
<< 2);
2666 pci_cache_line_size
= pci_dfl_cache_line_size
;
2669 if (!pci_cache_line_size
) {
2670 printk(KERN_DEBUG
"PCI: CLS %u bytes, default %u\n",
2671 cls
<< 2, pci_dfl_cache_line_size
<< 2);
2672 pci_cache_line_size
= cls
? cls
: pci_dfl_cache_line_size
;
2678 fs_initcall_sync(pci_apply_final_quirks
);
2681 * Followings are device-specific reset methods which can be used to
2682 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
2685 static int reset_intel_generic_dev(struct pci_dev
*dev
, int probe
)
2689 /* only implement PCI_CLASS_SERIAL_USB at present */
2690 if (dev
->class == PCI_CLASS_SERIAL_USB
) {
2691 pos
= pci_find_capability(dev
, PCI_CAP_ID_VNDR
);
2698 pci_write_config_byte(dev
, pos
+ 0x4, 1);
2707 static int reset_intel_82599_sfp_virtfn(struct pci_dev
*dev
, int probe
)
2711 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2718 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
,
2719 PCI_EXP_DEVCTL_BCR_FLR
);
2725 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
2727 static const struct pci_dev_reset_methods pci_dev_reset_methods
[] = {
2728 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82599_SFP_VF
,
2729 reset_intel_82599_sfp_virtfn
},
2730 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
,
2731 reset_intel_generic_dev
},
2735 int pci_dev_specific_reset(struct pci_dev
*dev
, int probe
)
2737 const struct pci_dev_reset_methods
*i
;
2739 for (i
= pci_dev_reset_methods
; i
->reset
; i
++) {
2740 if ((i
->vendor
== dev
->vendor
||
2741 i
->vendor
== (u16
)PCI_ANY_ID
) &&
2742 (i
->device
== dev
->device
||
2743 i
->device
== (u16
)PCI_ANY_ID
))
2744 return i
->reset(dev
, probe
);
2751 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
) {}
2752 int pci_dev_specific_reset(struct pci_dev
*dev
, int probe
) { return -ENOTTY
; }
2754 EXPORT_SYMBOL(pci_fixup_device
);