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ring-buffer: Fix advance of reader in rb_buffer_peek()
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / gianfar.c
blobd8b264956ab9c878ea55f4243113e4b3b69c4b0a
1 /*
2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
10 * Maintainer: Kumar Gala
11 *
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
27 *
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
77 #include <linux/mm.h>
78 #include <linux/of_platform.h>
79 #include <linux/ip.h>
80 #include <linux/tcp.h>
81 #include <linux/udp.h>
82 #include <linux/in.h>
83
84 #include <asm/io.h>
85 #include <asm/irq.h>
86 #include <asm/uaccess.h>
87 #include <linux/module.h>
88 #include <linux/dma-mapping.h>
89 #include <linux/crc32.h>
90 #include <linux/mii.h>
91 #include <linux/phy.h>
92 #include <linux/phy_fixed.h>
93 #include <linux/of.h>
94
95 #include "gianfar.h"
96 #include "fsl_pq_mdio.h"
97
98 #define TX_TIMEOUT (1*HZ)
99 #undef BRIEF_GFAR_ERRORS
100 #undef VERBOSE_GFAR_ERRORS
101
102 const char gfar_driver_name[] = "Gianfar Ethernet";
103 const char gfar_driver_version[] = "1.3";
104
105 static int gfar_enet_open(struct net_device *dev);
106 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
107 static void gfar_reset_task(struct work_struct *work);
108 static void gfar_timeout(struct net_device *dev);
109 static int gfar_close(struct net_device *dev);
110 struct sk_buff *gfar_new_skb(struct net_device *dev);
111 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
112 struct sk_buff *skb);
113 static int gfar_set_mac_address(struct net_device *dev);
114 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
115 static irqreturn_t gfar_error(int irq, void *dev_id);
116 static irqreturn_t gfar_transmit(int irq, void *dev_id);
117 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
118 static void adjust_link(struct net_device *dev);
119 static void init_registers(struct net_device *dev);
120 static int init_phy(struct net_device *dev);
121 static int gfar_probe(struct of_device *ofdev,
122 const struct of_device_id *match);
123 static int gfar_remove(struct of_device *ofdev);
124 static void free_skb_resources(struct gfar_private *priv);
125 static void gfar_set_multi(struct net_device *dev);
126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
127 static void gfar_configure_serdes(struct net_device *dev);
128 static int gfar_poll(struct napi_struct *napi, int budget);
129 #ifdef CONFIG_NET_POLL_CONTROLLER
130 static void gfar_netpoll(struct net_device *dev);
131 #endif
132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
133 static int gfar_clean_tx_ring(struct net_device *dev);
134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
135 int amount_pull);
136 static void gfar_vlan_rx_register(struct net_device *netdev,
137 struct vlan_group *grp);
138 void gfar_halt(struct net_device *dev);
139 static void gfar_halt_nodisable(struct net_device *dev);
140 void gfar_start(struct net_device *dev);
141 static void gfar_clear_exact_match(struct net_device *dev);
142 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
143 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
144
145 MODULE_AUTHOR("Freescale Semiconductor, Inc");
146 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
147 MODULE_LICENSE("GPL");
148
149 static const struct net_device_ops gfar_netdev_ops = {
150 .ndo_open = gfar_enet_open,
151 .ndo_start_xmit = gfar_start_xmit,
152 .ndo_stop = gfar_close,
153 .ndo_change_mtu = gfar_change_mtu,
154 .ndo_set_multicast_list = gfar_set_multi,
155 .ndo_tx_timeout = gfar_timeout,
156 .ndo_do_ioctl = gfar_ioctl,
157 .ndo_vlan_rx_register = gfar_vlan_rx_register,
158 .ndo_set_mac_address = eth_mac_addr,
159 .ndo_validate_addr = eth_validate_addr,
160 #ifdef CONFIG_NET_POLL_CONTROLLER
161 .ndo_poll_controller = gfar_netpoll,
162 #endif
163 };
164
165 /* Returns 1 if incoming frames use an FCB */
166 static inline int gfar_uses_fcb(struct gfar_private *priv)
167 {
168 return priv->vlgrp || priv->rx_csum_enable;
169 }
170
171 static int gfar_of_init(struct net_device *dev)
172 {
173 struct device_node *phy, *mdio;
174 const unsigned int *id;
175 const char *model;
176 const char *ctype;
177 const void *mac_addr;
178 const phandle *ph;
179 u64 addr, size;
180 int err = 0;
181 struct gfar_private *priv = netdev_priv(dev);
182 struct device_node *np = priv->node;
183 char bus_name[MII_BUS_ID_SIZE];
184 const u32 *stash;
185 const u32 *stash_len;
186 const u32 *stash_idx;
187
188 if (!np || !of_device_is_available(np))
189 return -ENODEV;
190
191 /* get a pointer to the register memory */
192 addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
193 priv->regs = ioremap(addr, size);
194
195 if (priv->regs == NULL)
196 return -ENOMEM;
197
198 priv->interruptTransmit = irq_of_parse_and_map(np, 0);
199
200 model = of_get_property(np, "model", NULL);
201
202 /* If we aren't the FEC we have multiple interrupts */
203 if (model && strcasecmp(model, "FEC")) {
204 priv->interruptReceive = irq_of_parse_and_map(np, 1);
205
206 priv->interruptError = irq_of_parse_and_map(np, 2);
207
208 if (priv->interruptTransmit < 0 ||
209 priv->interruptReceive < 0 ||
210 priv->interruptError < 0) {
211 err = -EINVAL;
212 goto err_out;
213 }
214 }
215
216 stash = of_get_property(np, "bd-stash", NULL);
217
218 if(stash) {
219 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
220 priv->bd_stash_en = 1;
221 }
222
223 stash_len = of_get_property(np, "rx-stash-len", NULL);
224
225 if (stash_len)
226 priv->rx_stash_size = *stash_len;
227
228 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
229
230 if (stash_idx)
231 priv->rx_stash_index = *stash_idx;
232
233 if (stash_len || stash_idx)
234 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
235
236 mac_addr = of_get_mac_address(np);
237 if (mac_addr)
238 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
239
240 if (model && !strcasecmp(model, "TSEC"))
241 priv->device_flags =
242 FSL_GIANFAR_DEV_HAS_GIGABIT |
243 FSL_GIANFAR_DEV_HAS_COALESCE |
244 FSL_GIANFAR_DEV_HAS_RMON |
245 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
246 if (model && !strcasecmp(model, "eTSEC"))
247 priv->device_flags =
248 FSL_GIANFAR_DEV_HAS_GIGABIT |
249 FSL_GIANFAR_DEV_HAS_COALESCE |
250 FSL_GIANFAR_DEV_HAS_RMON |
251 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
252 FSL_GIANFAR_DEV_HAS_PADDING |
253 FSL_GIANFAR_DEV_HAS_CSUM |
254 FSL_GIANFAR_DEV_HAS_VLAN |
255 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
256 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
257
258 ctype = of_get_property(np, "phy-connection-type", NULL);
259
260 /* We only care about rgmii-id. The rest are autodetected */
261 if (ctype && !strcmp(ctype, "rgmii-id"))
262 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
263 else
264 priv->interface = PHY_INTERFACE_MODE_MII;
265
266 if (of_get_property(np, "fsl,magic-packet", NULL))
267 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
268
269 ph = of_get_property(np, "phy-handle", NULL);
270 if (ph == NULL) {
271 u32 *fixed_link;
272
273 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
274 if (!fixed_link) {
275 err = -ENODEV;
276 goto err_out;
277 }
278
279 snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id),
280 PHY_ID_FMT, "0", fixed_link[0]);
281 } else {
282 phy = of_find_node_by_phandle(*ph);
283
284 if (phy == NULL) {
285 err = -ENODEV;
286 goto err_out;
287 }
288
289 mdio = of_get_parent(phy);
290
291 id = of_get_property(phy, "reg", NULL);
292
293 of_node_put(phy);
294
295 fsl_pq_mdio_bus_name(bus_name, mdio);
296 of_node_put(mdio);
297 snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id), "%s:%02x",
298 bus_name, *id);
299 }
300
301 /* Find the TBI PHY. If it's not there, we don't support SGMII */
302 ph = of_get_property(np, "tbi-handle", NULL);
303 if (ph) {
304 struct device_node *tbi = of_find_node_by_phandle(*ph);
305 struct of_device *ofdev;
306 struct mii_bus *bus;
307
308 if (!tbi)
309 return 0;
310
311 mdio = of_get_parent(tbi);
312 if (!mdio)
313 return 0;
314
315 ofdev = of_find_device_by_node(mdio);
316
317 of_node_put(mdio);
318
319 id = of_get_property(tbi, "reg", NULL);
320 if (!id)
321 return 0;
322
323 of_node_put(tbi);
324
325 bus = dev_get_drvdata(&ofdev->dev);
326
327 priv->tbiphy = bus->phy_map[*id];
328 }
329
330 return 0;
331
332 err_out:
333 iounmap(priv->regs);
334 return err;
335 }
336
337 /* Ioctl MII Interface */
338 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
339 {
340 struct gfar_private *priv = netdev_priv(dev);
341
342 if (!netif_running(dev))
343 return -EINVAL;
344
345 if (!priv->phydev)
346 return -ENODEV;
347
348 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
349 }
350
351 /* Set up the ethernet device structure, private data,
352 * and anything else we need before we start */
353 static int gfar_probe(struct of_device *ofdev,
354 const struct of_device_id *match)
355 {
356 u32 tempval;
357 struct net_device *dev = NULL;
358 struct gfar_private *priv = NULL;
359 DECLARE_MAC_BUF(mac);
360 int err = 0;
361 int len_devname;
362
363 /* Create an ethernet device instance */
364 dev = alloc_etherdev(sizeof (*priv));
365
366 if (NULL == dev)
367 return -ENOMEM;
368
369 priv = netdev_priv(dev);
370 priv->ndev = dev;
371 priv->ofdev = ofdev;
372 priv->node = ofdev->node;
373 SET_NETDEV_DEV(dev, &ofdev->dev);
374
375 err = gfar_of_init(dev);
376
377 if (err)
378 goto regs_fail;
379
380 spin_lock_init(&priv->txlock);
381 spin_lock_init(&priv->rxlock);
382 spin_lock_init(&priv->bflock);
383 INIT_WORK(&priv->reset_task, gfar_reset_task);
384
385 dev_set_drvdata(&ofdev->dev, priv);
386
387 /* Stop the DMA engine now, in case it was running before */
388 /* (The firmware could have used it, and left it running). */
389 gfar_halt(dev);
390
391 /* Reset MAC layer */
392 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
393
394 /* We need to delay at least 3 TX clocks */
395 udelay(2);
396
397 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
398 gfar_write(&priv->regs->maccfg1, tempval);
399
400 /* Initialize MACCFG2. */
401 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
402
403 /* Initialize ECNTRL */
404 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
405
406 /* Set the dev->base_addr to the gfar reg region */
407 dev->base_addr = (unsigned long) (priv->regs);
408
409 SET_NETDEV_DEV(dev, &ofdev->dev);
410
411 /* Fill in the dev structure */
412 dev->watchdog_timeo = TX_TIMEOUT;
413 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
414 dev->mtu = 1500;
415
416 dev->netdev_ops = &gfar_netdev_ops;
417 dev->ethtool_ops = &gfar_ethtool_ops;
418
419 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
420 priv->rx_csum_enable = 1;
421 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
422 } else
423 priv->rx_csum_enable = 0;
424
425 priv->vlgrp = NULL;
426
427 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
428 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
429
430 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
431 priv->extended_hash = 1;
432 priv->hash_width = 9;
433
434 priv->hash_regs[0] = &priv->regs->igaddr0;
435 priv->hash_regs[1] = &priv->regs->igaddr1;
436 priv->hash_regs[2] = &priv->regs->igaddr2;
437 priv->hash_regs[3] = &priv->regs->igaddr3;
438 priv->hash_regs[4] = &priv->regs->igaddr4;
439 priv->hash_regs[5] = &priv->regs->igaddr5;
440 priv->hash_regs[6] = &priv->regs->igaddr6;
441 priv->hash_regs[7] = &priv->regs->igaddr7;
442 priv->hash_regs[8] = &priv->regs->gaddr0;
443 priv->hash_regs[9] = &priv->regs->gaddr1;
444 priv->hash_regs[10] = &priv->regs->gaddr2;
445 priv->hash_regs[11] = &priv->regs->gaddr3;
446 priv->hash_regs[12] = &priv->regs->gaddr4;
447 priv->hash_regs[13] = &priv->regs->gaddr5;
448 priv->hash_regs[14] = &priv->regs->gaddr6;
449 priv->hash_regs[15] = &priv->regs->gaddr7;
450
451 } else {
452 priv->extended_hash = 0;
453 priv->hash_width = 8;
454
455 priv->hash_regs[0] = &priv->regs->gaddr0;
456 priv->hash_regs[1] = &priv->regs->gaddr1;
457 priv->hash_regs[2] = &priv->regs->gaddr2;
458 priv->hash_regs[3] = &priv->regs->gaddr3;
459 priv->hash_regs[4] = &priv->regs->gaddr4;
460 priv->hash_regs[5] = &priv->regs->gaddr5;
461 priv->hash_regs[6] = &priv->regs->gaddr6;
462 priv->hash_regs[7] = &priv->regs->gaddr7;
463 }
464
465 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
466 priv->padding = DEFAULT_PADDING;
467 else
468 priv->padding = 0;
469
470 if (dev->features & NETIF_F_IP_CSUM)
471 dev->hard_header_len += GMAC_FCB_LEN;
472
473 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
474 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
475 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
476 priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
477
478 priv->txcoalescing = DEFAULT_TX_COALESCE;
479 priv->txic = DEFAULT_TXIC;
480 priv->rxcoalescing = DEFAULT_RX_COALESCE;
481 priv->rxic = DEFAULT_RXIC;
482
483 /* Enable most messages by default */
484 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
485
486 /* Carrier starts down, phylib will bring it up */
487 netif_carrier_off(dev);
488
489 err = register_netdev(dev);
490
491 if (err) {
492 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
493 dev->name);
494 goto register_fail;
495 }
496
497 device_init_wakeup(&dev->dev,
498 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
499
500 /* fill out IRQ number and name fields */
501 len_devname = strlen(dev->name);
502 strncpy(&priv->int_name_tx[0], dev->name, len_devname);
503 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
504 strncpy(&priv->int_name_tx[len_devname],
505 "_tx", sizeof("_tx") + 1);
506
507 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
508 strncpy(&priv->int_name_rx[len_devname],
509 "_rx", sizeof("_rx") + 1);
510
511 strncpy(&priv->int_name_er[0], dev->name, len_devname);
512 strncpy(&priv->int_name_er[len_devname],
513 "_er", sizeof("_er") + 1);
514 } else
515 priv->int_name_tx[len_devname] = '\0';
516
517 /* Create all the sysfs files */
518 gfar_init_sysfs(dev);
519
520 /* Print out the device info */
521 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
522
523 /* Even more device info helps when determining which kernel */
524 /* provided which set of benchmarks. */
525 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
526 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
527 dev->name, priv->rx_ring_size, priv->tx_ring_size);
528
529 return 0;
530
531 register_fail:
532 iounmap(priv->regs);
533 regs_fail:
534 free_netdev(dev);
535 return err;
536 }
537
538 static int gfar_remove(struct of_device *ofdev)
539 {
540 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
541
542 dev_set_drvdata(&ofdev->dev, NULL);
543
544 iounmap(priv->regs);
545 free_netdev(priv->ndev);
546
547 return 0;
548 }
549
550 #ifdef CONFIG_PM
551 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
552 {
553 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
554 struct net_device *dev = priv->ndev;
555 unsigned long flags;
556 u32 tempval;
557
558 int magic_packet = priv->wol_en &&
559 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
560
561 netif_device_detach(dev);
562
563 if (netif_running(dev)) {
564 spin_lock_irqsave(&priv->txlock, flags);
565 spin_lock(&priv->rxlock);
566
567 gfar_halt_nodisable(dev);
568
569 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
570 tempval = gfar_read(&priv->regs->maccfg1);
571
572 tempval &= ~MACCFG1_TX_EN;
573
574 if (!magic_packet)
575 tempval &= ~MACCFG1_RX_EN;
576
577 gfar_write(&priv->regs->maccfg1, tempval);
578
579 spin_unlock(&priv->rxlock);
580 spin_unlock_irqrestore(&priv->txlock, flags);
581
582 napi_disable(&priv->napi);
583
584 if (magic_packet) {
585 /* Enable interrupt on Magic Packet */
586 gfar_write(&priv->regs->imask, IMASK_MAG);
587
588 /* Enable Magic Packet mode */
589 tempval = gfar_read(&priv->regs->maccfg2);
590 tempval |= MACCFG2_MPEN;
591 gfar_write(&priv->regs->maccfg2, tempval);
592 } else {
593 phy_stop(priv->phydev);
594 }
595 }
596
597 return 0;
598 }
599
600 static int gfar_resume(struct of_device *ofdev)
601 {
602 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
603 struct net_device *dev = priv->ndev;
604 unsigned long flags;
605 u32 tempval;
606 int magic_packet = priv->wol_en &&
607 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
608
609 if (!netif_running(dev)) {
610 netif_device_attach(dev);
611 return 0;
612 }
613
614 if (!magic_packet && priv->phydev)
615 phy_start(priv->phydev);
616
617 /* Disable Magic Packet mode, in case something
618 * else woke us up.
619 */
620
621 spin_lock_irqsave(&priv->txlock, flags);
622 spin_lock(&priv->rxlock);
623
624 tempval = gfar_read(&priv->regs->maccfg2);
625 tempval &= ~MACCFG2_MPEN;
626 gfar_write(&priv->regs->maccfg2, tempval);
627
628 gfar_start(dev);
629
630 spin_unlock(&priv->rxlock);
631 spin_unlock_irqrestore(&priv->txlock, flags);
632
633 netif_device_attach(dev);
634
635 napi_enable(&priv->napi);
636
637 return 0;
638 }
639 #else
640 #define gfar_suspend NULL
641 #define gfar_resume NULL
642 #endif
643
644 /* Reads the controller's registers to determine what interface
645 * connects it to the PHY.
646 */
647 static phy_interface_t gfar_get_interface(struct net_device *dev)
648 {
649 struct gfar_private *priv = netdev_priv(dev);
650 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
651
652 if (ecntrl & ECNTRL_SGMII_MODE)
653 return PHY_INTERFACE_MODE_SGMII;
654
655 if (ecntrl & ECNTRL_TBI_MODE) {
656 if (ecntrl & ECNTRL_REDUCED_MODE)
657 return PHY_INTERFACE_MODE_RTBI;
658 else
659 return PHY_INTERFACE_MODE_TBI;
660 }
661
662 if (ecntrl & ECNTRL_REDUCED_MODE) {
663 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
664 return PHY_INTERFACE_MODE_RMII;
665 else {
666 phy_interface_t interface = priv->interface;
667
668 /*
669 * This isn't autodetected right now, so it must
670 * be set by the device tree or platform code.
671 */
672 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
673 return PHY_INTERFACE_MODE_RGMII_ID;
674
675 return PHY_INTERFACE_MODE_RGMII;
676 }
677 }
678
679 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
680 return PHY_INTERFACE_MODE_GMII;
681
682 return PHY_INTERFACE_MODE_MII;
683 }
684
685
686 /* Initializes driver's PHY state, and attaches to the PHY.
687 * Returns 0 on success.
688 */
689 static int init_phy(struct net_device *dev)
690 {
691 struct gfar_private *priv = netdev_priv(dev);
692 uint gigabit_support =
693 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
694 SUPPORTED_1000baseT_Full : 0;
695 struct phy_device *phydev;
696 phy_interface_t interface;
697
698 priv->oldlink = 0;
699 priv->oldspeed = 0;
700 priv->oldduplex = -1;
701
702 interface = gfar_get_interface(dev);
703
704 phydev = phy_connect(dev, priv->phy_bus_id, &adjust_link, 0, interface);
705
706 if (interface == PHY_INTERFACE_MODE_SGMII)
707 gfar_configure_serdes(dev);
708
709 if (IS_ERR(phydev)) {
710 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
711 return PTR_ERR(phydev);
712 }
713
714 /* Remove any features not supported by the controller */
715 phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
716 phydev->advertising = phydev->supported;
717
718 priv->phydev = phydev;
719
720 return 0;
721 }
722
723 /*
724 * Initialize TBI PHY interface for communicating with the
725 * SERDES lynx PHY on the chip. We communicate with this PHY
726 * through the MDIO bus on each controller, treating it as a
727 * "normal" PHY at the address found in the TBIPA register. We assume
728 * that the TBIPA register is valid. Either the MDIO bus code will set
729 * it to a value that doesn't conflict with other PHYs on the bus, or the
730 * value doesn't matter, as there are no other PHYs on the bus.
731 */
732 static void gfar_configure_serdes(struct net_device *dev)
733 {
734 struct gfar_private *priv = netdev_priv(dev);
735
736 if (!priv->tbiphy) {
737 printk(KERN_WARNING "SGMII mode requires that the device "
738 "tree specify a tbi-handle\n");
739 return;
740 }
741
742 /*
743 * If the link is already up, we must already be ok, and don't need to
744 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
745 * everything for us? Resetting it takes the link down and requires
746 * several seconds for it to come back.
747 */
748 if (phy_read(priv->tbiphy, MII_BMSR) & BMSR_LSTATUS)
749 return;
750
751 /* Single clk mode, mii mode off(for serdes communication) */
752 phy_write(priv->tbiphy, MII_TBICON, TBICON_CLK_SELECT);
753
754 phy_write(priv->tbiphy, MII_ADVERTISE,
755 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
756 ADVERTISE_1000XPSE_ASYM);
757
758 phy_write(priv->tbiphy, MII_BMCR, BMCR_ANENABLE |
759 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
760 }
761
762 static void init_registers(struct net_device *dev)
763 {
764 struct gfar_private *priv = netdev_priv(dev);
765
766 /* Clear IEVENT */
767 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
768
769 /* Initialize IMASK */
770 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
771
772 /* Init hash registers to zero */
773 gfar_write(&priv->regs->igaddr0, 0);
774 gfar_write(&priv->regs->igaddr1, 0);
775 gfar_write(&priv->regs->igaddr2, 0);
776 gfar_write(&priv->regs->igaddr3, 0);
777 gfar_write(&priv->regs->igaddr4, 0);
778 gfar_write(&priv->regs->igaddr5, 0);
779 gfar_write(&priv->regs->igaddr6, 0);
780 gfar_write(&priv->regs->igaddr7, 0);
781
782 gfar_write(&priv->regs->gaddr0, 0);
783 gfar_write(&priv->regs->gaddr1, 0);
784 gfar_write(&priv->regs->gaddr2, 0);
785 gfar_write(&priv->regs->gaddr3, 0);
786 gfar_write(&priv->regs->gaddr4, 0);
787 gfar_write(&priv->regs->gaddr5, 0);
788 gfar_write(&priv->regs->gaddr6, 0);
789 gfar_write(&priv->regs->gaddr7, 0);
790
791 /* Zero out the rmon mib registers if it has them */
792 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
793 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
794
795 /* Mask off the CAM interrupts */
796 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
797 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
798 }
799
800 /* Initialize the max receive buffer length */
801 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
802
803 /* Initialize the Minimum Frame Length Register */
804 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
805 }
806
807
808 /* Halt the receive and transmit queues */
809 static void gfar_halt_nodisable(struct net_device *dev)
810 {
811 struct gfar_private *priv = netdev_priv(dev);
812 struct gfar __iomem *regs = priv->regs;
813 u32 tempval;
814
815 /* Mask all interrupts */
816 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
817
818 /* Clear all interrupts */
819 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
820
821 /* Stop the DMA, and wait for it to stop */
822 tempval = gfar_read(&priv->regs->dmactrl);
823 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
824 != (DMACTRL_GRS | DMACTRL_GTS)) {
825 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
826 gfar_write(&priv->regs->dmactrl, tempval);
827
828 while (!(gfar_read(&priv->regs->ievent) &
829 (IEVENT_GRSC | IEVENT_GTSC)))
830 cpu_relax();
831 }
832 }
833
834 /* Halt the receive and transmit queues */
835 void gfar_halt(struct net_device *dev)
836 {
837 struct gfar_private *priv = netdev_priv(dev);
838 struct gfar __iomem *regs = priv->regs;
839 u32 tempval;
840
841 gfar_halt_nodisable(dev);
842
843 /* Disable Rx and Tx */
844 tempval = gfar_read(&regs->maccfg1);
845 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
846 gfar_write(&regs->maccfg1, tempval);
847 }
848
849 void stop_gfar(struct net_device *dev)
850 {
851 struct gfar_private *priv = netdev_priv(dev);
852 struct gfar __iomem *regs = priv->regs;
853 unsigned long flags;
854
855 phy_stop(priv->phydev);
856
857 /* Lock it down */
858 spin_lock_irqsave(&priv->txlock, flags);
859 spin_lock(&priv->rxlock);
860
861 gfar_halt(dev);
862
863 spin_unlock(&priv->rxlock);
864 spin_unlock_irqrestore(&priv->txlock, flags);
865
866 /* Free the IRQs */
867 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
868 free_irq(priv->interruptError, dev);
869 free_irq(priv->interruptTransmit, dev);
870 free_irq(priv->interruptReceive, dev);
871 } else {
872 free_irq(priv->interruptTransmit, dev);
873 }
874
875 free_skb_resources(priv);
876
877 dma_free_coherent(&priv->ofdev->dev,
878 sizeof(struct txbd8)*priv->tx_ring_size
879 + sizeof(struct rxbd8)*priv->rx_ring_size,
880 priv->tx_bd_base,
881 gfar_read(&regs->tbase0));
882 }
883
884 /* If there are any tx skbs or rx skbs still around, free them.
885 * Then free tx_skbuff and rx_skbuff */
886 static void free_skb_resources(struct gfar_private *priv)
887 {
888 struct rxbd8 *rxbdp;
889 struct txbd8 *txbdp;
890 int i, j;
891
892 /* Go through all the buffer descriptors and free their data buffers */
893 txbdp = priv->tx_bd_base;
894
895 for (i = 0; i < priv->tx_ring_size; i++) {
896 if (!priv->tx_skbuff[i])
897 continue;
898
899 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
900 txbdp->length, DMA_TO_DEVICE);
901 txbdp->lstatus = 0;
902 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
903 txbdp++;
904 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
905 txbdp->length, DMA_TO_DEVICE);
906 }
907 txbdp++;
908 dev_kfree_skb_any(priv->tx_skbuff[i]);
909 priv->tx_skbuff[i] = NULL;
910 }
911
912 kfree(priv->tx_skbuff);
913
914 rxbdp = priv->rx_bd_base;
915
916 /* rx_skbuff is not guaranteed to be allocated, so only
917 * free it and its contents if it is allocated */
918 if(priv->rx_skbuff != NULL) {
919 for (i = 0; i < priv->rx_ring_size; i++) {
920 if (priv->rx_skbuff[i]) {
921 dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr,
922 priv->rx_buffer_size,
923 DMA_FROM_DEVICE);
924
925 dev_kfree_skb_any(priv->rx_skbuff[i]);
926 priv->rx_skbuff[i] = NULL;
927 }
928
929 rxbdp->lstatus = 0;
930 rxbdp->bufPtr = 0;
931
932 rxbdp++;
933 }
934
935 kfree(priv->rx_skbuff);
936 }
937 }
938
939 void gfar_start(struct net_device *dev)
940 {
941 struct gfar_private *priv = netdev_priv(dev);
942 struct gfar __iomem *regs = priv->regs;
943 u32 tempval;
944
945 /* Enable Rx and Tx in MACCFG1 */
946 tempval = gfar_read(&regs->maccfg1);
947 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
948 gfar_write(&regs->maccfg1, tempval);
949
950 /* Initialize DMACTRL to have WWR and WOP */
951 tempval = gfar_read(&priv->regs->dmactrl);
952 tempval |= DMACTRL_INIT_SETTINGS;
953 gfar_write(&priv->regs->dmactrl, tempval);
954
955 /* Make sure we aren't stopped */
956 tempval = gfar_read(&priv->regs->dmactrl);
957 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
958 gfar_write(&priv->regs->dmactrl, tempval);
959
960 /* Clear THLT/RHLT, so that the DMA starts polling now */
961 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
962 gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
963
964 /* Unmask the interrupts we look for */
965 gfar_write(&regs->imask, IMASK_DEFAULT);
966
967 dev->trans_start = jiffies;
968 }
969
970 /* Bring the controller up and running */
971 int startup_gfar(struct net_device *dev)
972 {
973 struct txbd8 *txbdp;
974 struct rxbd8 *rxbdp;
975 dma_addr_t addr = 0;
976 unsigned long vaddr;
977 int i;
978 struct gfar_private *priv = netdev_priv(dev);
979 struct gfar __iomem *regs = priv->regs;
980 int err = 0;
981 u32 rctrl = 0;
982 u32 attrs = 0;
983
984 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
985
986 /* Allocate memory for the buffer descriptors */
987 vaddr = (unsigned long) dma_alloc_coherent(&priv->ofdev->dev,
988 sizeof (struct txbd8) * priv->tx_ring_size +
989 sizeof (struct rxbd8) * priv->rx_ring_size,
990 &addr, GFP_KERNEL);
991
992 if (vaddr == 0) {
993 if (netif_msg_ifup(priv))
994 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
995 dev->name);
996 return -ENOMEM;
997 }
998
999 priv->tx_bd_base = (struct txbd8 *) vaddr;
1000
1001 /* enet DMA only understands physical addresses */
1002 gfar_write(&regs->tbase0, addr);
1003
1004 /* Start the rx descriptor ring where the tx ring leaves off */
1005 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
1006 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
1007 priv->rx_bd_base = (struct rxbd8 *) vaddr;
1008 gfar_write(&regs->rbase0, addr);
1009
1010 /* Setup the skbuff rings */
1011 priv->tx_skbuff =
1012 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
1013 priv->tx_ring_size, GFP_KERNEL);
1014
1015 if (NULL == priv->tx_skbuff) {
1016 if (netif_msg_ifup(priv))
1017 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
1018 dev->name);
1019 err = -ENOMEM;
1020 goto tx_skb_fail;
1021 }
1022
1023 for (i = 0; i < priv->tx_ring_size; i++)
1024 priv->tx_skbuff[i] = NULL;
1025
1026 priv->rx_skbuff =
1027 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
1028 priv->rx_ring_size, GFP_KERNEL);
1029
1030 if (NULL == priv->rx_skbuff) {
1031 if (netif_msg_ifup(priv))
1032 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
1033 dev->name);
1034 err = -ENOMEM;
1035 goto rx_skb_fail;
1036 }
1037
1038 for (i = 0; i < priv->rx_ring_size; i++)
1039 priv->rx_skbuff[i] = NULL;
1040
1041 /* Initialize some variables in our dev structure */
1042 priv->num_txbdfree = priv->tx_ring_size;
1043 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
1044 priv->cur_rx = priv->rx_bd_base;
1045 priv->skb_curtx = priv->skb_dirtytx = 0;
1046 priv->skb_currx = 0;
1047
1048 /* Initialize Transmit Descriptor Ring */
1049 txbdp = priv->tx_bd_base;
1050 for (i = 0; i < priv->tx_ring_size; i++) {
1051 txbdp->lstatus = 0;
1052 txbdp->bufPtr = 0;
1053 txbdp++;
1054 }
1055
1056 /* Set the last descriptor in the ring to indicate wrap */
1057 txbdp--;
1058 txbdp->status |= TXBD_WRAP;
1059
1060 rxbdp = priv->rx_bd_base;
1061 for (i = 0; i < priv->rx_ring_size; i++) {
1062 struct sk_buff *skb;
1063
1064 skb = gfar_new_skb(dev);
1065
1066 if (!skb) {
1067 printk(KERN_ERR "%s: Can't allocate RX buffers\n",
1068 dev->name);
1069
1070 goto err_rxalloc_fail;
1071 }
1072
1073 priv->rx_skbuff[i] = skb;
1074
1075 gfar_new_rxbdp(dev, rxbdp, skb);
1076
1077 rxbdp++;
1078 }
1079
1080 /* Set the last descriptor in the ring to wrap */
1081 rxbdp--;
1082 rxbdp->status |= RXBD_WRAP;
1083
1084 /* If the device has multiple interrupts, register for
1085 * them. Otherwise, only register for the one */
1086 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1087 /* Install our interrupt handlers for Error,
1088 * Transmit, and Receive */
1089 if (request_irq(priv->interruptError, gfar_error,
1090 0, priv->int_name_er, dev) < 0) {
1091 if (netif_msg_intr(priv))
1092 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1093 dev->name, priv->interruptError);
1094
1095 err = -1;
1096 goto err_irq_fail;
1097 }
1098
1099 if (request_irq(priv->interruptTransmit, gfar_transmit,
1100 0, priv->int_name_tx, dev) < 0) {
1101 if (netif_msg_intr(priv))
1102 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1103 dev->name, priv->interruptTransmit);
1104
1105 err = -1;
1106
1107 goto tx_irq_fail;
1108 }
1109
1110 if (request_irq(priv->interruptReceive, gfar_receive,
1111 0, priv->int_name_rx, dev) < 0) {
1112 if (netif_msg_intr(priv))
1113 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1114 dev->name, priv->interruptReceive);
1115
1116 err = -1;
1117 goto rx_irq_fail;
1118 }
1119 } else {
1120 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1121 0, priv->int_name_tx, dev) < 0) {
1122 if (netif_msg_intr(priv))
1123 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1124 dev->name, priv->interruptTransmit);
1125
1126 err = -1;
1127 goto err_irq_fail;
1128 }
1129 }
1130
1131 phy_start(priv->phydev);
1132
1133 /* Configure the coalescing support */
1134 gfar_write(&regs->txic, 0);
1135 if (priv->txcoalescing)
1136 gfar_write(&regs->txic, priv->txic);
1137
1138 gfar_write(&regs->rxic, 0);
1139 if (priv->rxcoalescing)
1140 gfar_write(&regs->rxic, priv->rxic);
1141
1142 if (priv->rx_csum_enable)
1143 rctrl |= RCTRL_CHECKSUMMING;
1144
1145 if (priv->extended_hash) {
1146 rctrl |= RCTRL_EXTHASH;
1147
1148 gfar_clear_exact_match(dev);
1149 rctrl |= RCTRL_EMEN;
1150 }
1151
1152 if (priv->padding) {
1153 rctrl &= ~RCTRL_PAL_MASK;
1154 rctrl |= RCTRL_PADDING(priv->padding);
1155 }
1156
1157 /* Init rctrl based on our settings */
1158 gfar_write(&priv->regs->rctrl, rctrl);
1159
1160 if (dev->features & NETIF_F_IP_CSUM)
1161 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1162
1163 /* Set the extraction length and index */
1164 attrs = ATTRELI_EL(priv->rx_stash_size) |
1165 ATTRELI_EI(priv->rx_stash_index);
1166
1167 gfar_write(&priv->regs->attreli, attrs);
1168
1169 /* Start with defaults, and add stashing or locking
1170 * depending on the approprate variables */
1171 attrs = ATTR_INIT_SETTINGS;
1172
1173 if (priv->bd_stash_en)
1174 attrs |= ATTR_BDSTASH;
1175
1176 if (priv->rx_stash_size != 0)
1177 attrs |= ATTR_BUFSTASH;
1178
1179 gfar_write(&priv->regs->attr, attrs);
1180
1181 gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1182 gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1183 gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1184
1185 /* Start the controller */
1186 gfar_start(dev);
1187
1188 return 0;
1189
1190 rx_irq_fail:
1191 free_irq(priv->interruptTransmit, dev);
1192 tx_irq_fail:
1193 free_irq(priv->interruptError, dev);
1194 err_irq_fail:
1195 err_rxalloc_fail:
1196 rx_skb_fail:
1197 free_skb_resources(priv);
1198 tx_skb_fail:
1199 dma_free_coherent(&priv->ofdev->dev,
1200 sizeof(struct txbd8)*priv->tx_ring_size
1201 + sizeof(struct rxbd8)*priv->rx_ring_size,
1202 priv->tx_bd_base,
1203 gfar_read(&regs->tbase0));
1204
1205 return err;
1206 }
1207
1208 /* Called when something needs to use the ethernet device */
1209 /* Returns 0 for success. */
1210 static int gfar_enet_open(struct net_device *dev)
1211 {
1212 struct gfar_private *priv = netdev_priv(dev);
1213 int err;
1214
1215 napi_enable(&priv->napi);
1216
1217 skb_queue_head_init(&priv->rx_recycle);
1218
1219 /* Initialize a bunch of registers */
1220 init_registers(dev);
1221
1222 gfar_set_mac_address(dev);
1223
1224 err = init_phy(dev);
1225
1226 if(err) {
1227 napi_disable(&priv->napi);
1228 return err;
1229 }
1230
1231 err = startup_gfar(dev);
1232 if (err) {
1233 napi_disable(&priv->napi);
1234 return err;
1235 }
1236
1237 netif_start_queue(dev);
1238
1239 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1240
1241 return err;
1242 }
1243
1244 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1245 {
1246 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1247 cacheable_memzero(fcb, GMAC_FCB_LEN);
1248
1249 return fcb;
1250 }
1251
1252 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1253 {
1254 u8 flags = 0;
1255
1256 /* If we're here, it's a IP packet with a TCP or UDP
1257 * payload. We set it to checksum, using a pseudo-header
1258 * we provide
1259 */
1260 flags = TXFCB_DEFAULT;
1261
1262 /* Tell the controller what the protocol is */
1263 /* And provide the already calculated phcs */
1264 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1265 flags |= TXFCB_UDP;
1266 fcb->phcs = udp_hdr(skb)->check;
1267 } else
1268 fcb->phcs = tcp_hdr(skb)->check;
1269
1270 /* l3os is the distance between the start of the
1271 * frame (skb->data) and the start of the IP hdr.
1272 * l4os is the distance between the start of the
1273 * l3 hdr and the l4 hdr */
1274 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1275 fcb->l4os = skb_network_header_len(skb);
1276
1277 fcb->flags = flags;
1278 }
1279
1280 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1281 {
1282 fcb->flags |= TXFCB_VLN;
1283 fcb->vlctl = vlan_tx_tag_get(skb);
1284 }
1285
1286 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1287 struct txbd8 *base, int ring_size)
1288 {
1289 struct txbd8 *new_bd = bdp + stride;
1290
1291 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1292 }
1293
1294 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1295 int ring_size)
1296 {
1297 return skip_txbd(bdp, 1, base, ring_size);
1298 }
1299
1300 /* This is called by the kernel when a frame is ready for transmission. */
1301 /* It is pointed to by the dev->hard_start_xmit function pointer */
1302 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1303 {
1304 struct gfar_private *priv = netdev_priv(dev);
1305 struct txfcb *fcb = NULL;
1306 struct txbd8 *txbdp, *txbdp_start, *base;
1307 u32 lstatus;
1308 int i;
1309 u32 bufaddr;
1310 unsigned long flags;
1311 unsigned int nr_frags, length;
1312
1313 base = priv->tx_bd_base;
1314
1315 /* make space for additional header when fcb is needed */
1316 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1317 (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1318 (skb_headroom(skb) < GMAC_FCB_LEN)) {
1319 struct sk_buff *skb_new;
1320
1321 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1322 if (!skb_new) {
1323 dev->stats.tx_errors++;
1324 kfree_skb(skb);
1325 return NETDEV_TX_OK;
1326 }
1327 kfree_skb(skb);
1328 skb = skb_new;
1329 }
1330
1331 /* total number of fragments in the SKB */
1332 nr_frags = skb_shinfo(skb)->nr_frags;
1333
1334 spin_lock_irqsave(&priv->txlock, flags);
1335
1336 /* check if there is space to queue this packet */
1337 if ((nr_frags+1) > priv->num_txbdfree) {
1338 /* no space, stop the queue */
1339 netif_stop_queue(dev);
1340 dev->stats.tx_fifo_errors++;
1341 spin_unlock_irqrestore(&priv->txlock, flags);
1342 return NETDEV_TX_BUSY;
1343 }
1344
1345 /* Update transmit stats */
1346 dev->stats.tx_bytes += skb->len;
1347
1348 txbdp = txbdp_start = priv->cur_tx;
1349
1350 if (nr_frags == 0) {
1351 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1352 } else {
1353 /* Place the fragment addresses and lengths into the TxBDs */
1354 for (i = 0; i < nr_frags; i++) {
1355 /* Point at the next BD, wrapping as needed */
1356 txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1357
1358 length = skb_shinfo(skb)->frags[i].size;
1359
1360 lstatus = txbdp->lstatus | length |
1361 BD_LFLAG(TXBD_READY);
1362
1363 /* Handle the last BD specially */
1364 if (i == nr_frags - 1)
1365 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1366
1367 bufaddr = dma_map_page(&priv->ofdev->dev,
1368 skb_shinfo(skb)->frags[i].page,
1369 skb_shinfo(skb)->frags[i].page_offset,
1370 length,
1371 DMA_TO_DEVICE);
1372
1373 /* set the TxBD length and buffer pointer */
1374 txbdp->bufPtr = bufaddr;
1375 txbdp->lstatus = lstatus;
1376 }
1377
1378 lstatus = txbdp_start->lstatus;
1379 }
1380
1381 /* Set up checksumming */
1382 if (CHECKSUM_PARTIAL == skb->ip_summed) {
1383 fcb = gfar_add_fcb(skb);
1384 lstatus |= BD_LFLAG(TXBD_TOE);
1385 gfar_tx_checksum(skb, fcb);
1386 }
1387
1388 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1389 if (unlikely(NULL == fcb)) {
1390 fcb = gfar_add_fcb(skb);
1391 lstatus |= BD_LFLAG(TXBD_TOE);
1392 }
1393
1394 gfar_tx_vlan(skb, fcb);
1395 }
1396
1397 /* setup the TxBD length and buffer pointer for the first BD */
1398 priv->tx_skbuff[priv->skb_curtx] = skb;
1399 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1400 skb_headlen(skb), DMA_TO_DEVICE);
1401
1402 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1403
1404 /*
1405 * The powerpc-specific eieio() is used, as wmb() has too strong
1406 * semantics (it requires synchronization between cacheable and
1407 * uncacheable mappings, which eieio doesn't provide and which we
1408 * don't need), thus requiring a more expensive sync instruction. At
1409 * some point, the set of architecture-independent barrier functions
1410 * should be expanded to include weaker barriers.
1411 */
1412 eieio();
1413
1414 txbdp_start->lstatus = lstatus;
1415
1416 /* Update the current skb pointer to the next entry we will use
1417 * (wrapping if necessary) */
1418 priv->skb_curtx = (priv->skb_curtx + 1) &
1419 TX_RING_MOD_MASK(priv->tx_ring_size);
1420
1421 priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1422
1423 /* reduce TxBD free count */
1424 priv->num_txbdfree -= (nr_frags + 1);
1425
1426 dev->trans_start = jiffies;
1427
1428 /* If the next BD still needs to be cleaned up, then the bds
1429 are full. We need to tell the kernel to stop sending us stuff. */
1430 if (!priv->num_txbdfree) {
1431 netif_stop_queue(dev);
1432
1433 dev->stats.tx_fifo_errors++;
1434 }
1435
1436 /* Tell the DMA to go go go */
1437 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1438
1439 /* Unlock priv */
1440 spin_unlock_irqrestore(&priv->txlock, flags);
1441
1442 return NETDEV_TX_OK;
1443 }
1444
1445 /* Stops the kernel queue, and halts the controller */
1446 static int gfar_close(struct net_device *dev)
1447 {
1448 struct gfar_private *priv = netdev_priv(dev);
1449
1450 napi_disable(&priv->napi);
1451
1452 skb_queue_purge(&priv->rx_recycle);
1453 cancel_work_sync(&priv->reset_task);
1454 stop_gfar(dev);
1455
1456 /* Disconnect from the PHY */
1457 phy_disconnect(priv->phydev);
1458 priv->phydev = NULL;
1459
1460 netif_stop_queue(dev);
1461
1462 return 0;
1463 }
1464
1465 /* Changes the mac address if the controller is not running. */
1466 static int gfar_set_mac_address(struct net_device *dev)
1467 {
1468 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1469
1470 return 0;
1471 }
1472
1473
1474 /* Enables and disables VLAN insertion/extraction */
1475 static void gfar_vlan_rx_register(struct net_device *dev,
1476 struct vlan_group *grp)
1477 {
1478 struct gfar_private *priv = netdev_priv(dev);
1479 unsigned long flags;
1480 u32 tempval;
1481
1482 spin_lock_irqsave(&priv->rxlock, flags);
1483
1484 priv->vlgrp = grp;
1485
1486 if (grp) {
1487 /* Enable VLAN tag insertion */
1488 tempval = gfar_read(&priv->regs->tctrl);
1489 tempval |= TCTRL_VLINS;
1490
1491 gfar_write(&priv->regs->tctrl, tempval);
1492
1493 /* Enable VLAN tag extraction */
1494 tempval = gfar_read(&priv->regs->rctrl);
1495 tempval |= RCTRL_VLEX;
1496 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1497 gfar_write(&priv->regs->rctrl, tempval);
1498 } else {
1499 /* Disable VLAN tag insertion */
1500 tempval = gfar_read(&priv->regs->tctrl);
1501 tempval &= ~TCTRL_VLINS;
1502 gfar_write(&priv->regs->tctrl, tempval);
1503
1504 /* Disable VLAN tag extraction */
1505 tempval = gfar_read(&priv->regs->rctrl);
1506 tempval &= ~RCTRL_VLEX;
1507 /* If parse is no longer required, then disable parser */
1508 if (tempval & RCTRL_REQ_PARSER)
1509 tempval |= RCTRL_PRSDEP_INIT;
1510 else
1511 tempval &= ~RCTRL_PRSDEP_INIT;
1512 gfar_write(&priv->regs->rctrl, tempval);
1513 }
1514
1515 gfar_change_mtu(dev, dev->mtu);
1516
1517 spin_unlock_irqrestore(&priv->rxlock, flags);
1518 }
1519
1520 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1521 {
1522 int tempsize, tempval;
1523 struct gfar_private *priv = netdev_priv(dev);
1524 int oldsize = priv->rx_buffer_size;
1525 int frame_size = new_mtu + ETH_HLEN;
1526
1527 if (priv->vlgrp)
1528 frame_size += VLAN_HLEN;
1529
1530 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1531 if (netif_msg_drv(priv))
1532 printk(KERN_ERR "%s: Invalid MTU setting\n",
1533 dev->name);
1534 return -EINVAL;
1535 }
1536
1537 if (gfar_uses_fcb(priv))
1538 frame_size += GMAC_FCB_LEN;
1539
1540 frame_size += priv->padding;
1541
1542 tempsize =
1543 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1544 INCREMENTAL_BUFFER_SIZE;
1545
1546 /* Only stop and start the controller if it isn't already
1547 * stopped, and we changed something */
1548 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1549 stop_gfar(dev);
1550
1551 priv->rx_buffer_size = tempsize;
1552
1553 dev->mtu = new_mtu;
1554
1555 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1556 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1557
1558 /* If the mtu is larger than the max size for standard
1559 * ethernet frames (ie, a jumbo frame), then set maccfg2
1560 * to allow huge frames, and to check the length */
1561 tempval = gfar_read(&priv->regs->maccfg2);
1562
1563 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1564 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1565 else
1566 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1567
1568 gfar_write(&priv->regs->maccfg2, tempval);
1569
1570 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1571 startup_gfar(dev);
1572
1573 return 0;
1574 }
1575
1576 /* gfar_reset_task gets scheduled when a packet has not been
1577 * transmitted after a set amount of time.
1578 * For now, assume that clearing out all the structures, and
1579 * starting over will fix the problem.
1580 */
1581 static void gfar_reset_task(struct work_struct *work)
1582 {
1583 struct gfar_private *priv = container_of(work, struct gfar_private,
1584 reset_task);
1585 struct net_device *dev = priv->ndev;
1586
1587 if (dev->flags & IFF_UP) {
1588 netif_stop_queue(dev);
1589 stop_gfar(dev);
1590 startup_gfar(dev);
1591 netif_start_queue(dev);
1592 }
1593
1594 netif_tx_schedule_all(dev);
1595 }
1596
1597 static void gfar_timeout(struct net_device *dev)
1598 {
1599 struct gfar_private *priv = netdev_priv(dev);
1600
1601 dev->stats.tx_errors++;
1602 schedule_work(&priv->reset_task);
1603 }
1604
1605 /* Interrupt Handler for Transmit complete */
1606 static int gfar_clean_tx_ring(struct net_device *dev)
1607 {
1608 struct gfar_private *priv = netdev_priv(dev);
1609 struct txbd8 *bdp;
1610 struct txbd8 *lbdp = NULL;
1611 struct txbd8 *base = priv->tx_bd_base;
1612 struct sk_buff *skb;
1613 int skb_dirtytx;
1614 int tx_ring_size = priv->tx_ring_size;
1615 int frags = 0;
1616 int i;
1617 int howmany = 0;
1618 u32 lstatus;
1619
1620 bdp = priv->dirty_tx;
1621 skb_dirtytx = priv->skb_dirtytx;
1622
1623 while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1624 frags = skb_shinfo(skb)->nr_frags;
1625 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1626
1627 lstatus = lbdp->lstatus;
1628
1629 /* Only clean completed frames */
1630 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1631 (lstatus & BD_LENGTH_MASK))
1632 break;
1633
1634 dma_unmap_single(&priv->ofdev->dev,
1635 bdp->bufPtr,
1636 bdp->length,
1637 DMA_TO_DEVICE);
1638
1639 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1640 bdp = next_txbd(bdp, base, tx_ring_size);
1641
1642 for (i = 0; i < frags; i++) {
1643 dma_unmap_page(&priv->ofdev->dev,
1644 bdp->bufPtr,
1645 bdp->length,
1646 DMA_TO_DEVICE);
1647 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1648 bdp = next_txbd(bdp, base, tx_ring_size);
1649 }
1650
1651 /*
1652 * If there's room in the queue (limit it to rx_buffer_size)
1653 * we add this skb back into the pool, if it's the right size
1654 */
1655 if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size &&
1656 skb_recycle_check(skb, priv->rx_buffer_size +
1657 RXBUF_ALIGNMENT))
1658 __skb_queue_head(&priv->rx_recycle, skb);
1659 else
1660 dev_kfree_skb_any(skb);
1661
1662 priv->tx_skbuff[skb_dirtytx] = NULL;
1663
1664 skb_dirtytx = (skb_dirtytx + 1) &
1665 TX_RING_MOD_MASK(tx_ring_size);
1666
1667 howmany++;
1668 priv->num_txbdfree += frags + 1;
1669 }
1670
1671 /* If we freed a buffer, we can restart transmission, if necessary */
1672 if (netif_queue_stopped(dev) && priv->num_txbdfree)
1673 netif_wake_queue(dev);
1674
1675 /* Update dirty indicators */
1676 priv->skb_dirtytx = skb_dirtytx;
1677 priv->dirty_tx = bdp;
1678
1679 dev->stats.tx_packets += howmany;
1680
1681 return howmany;
1682 }
1683
1684 static void gfar_schedule_cleanup(struct net_device *dev)
1685 {
1686 struct gfar_private *priv = netdev_priv(dev);
1687 unsigned long flags;
1688
1689 spin_lock_irqsave(&priv->txlock, flags);
1690 spin_lock(&priv->rxlock);
1691
1692 if (napi_schedule_prep(&priv->napi)) {
1693 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1694 __napi_schedule(&priv->napi);
1695 } else {
1696 /*
1697 * Clear IEVENT, so interrupts aren't called again
1698 * because of the packets that have already arrived.
1699 */
1700 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1701 }
1702
1703 spin_unlock(&priv->rxlock);
1704 spin_unlock_irqrestore(&priv->txlock, flags);
1705 }
1706
1707 /* Interrupt Handler for Transmit complete */
1708 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1709 {
1710 gfar_schedule_cleanup((struct net_device *)dev_id);
1711 return IRQ_HANDLED;
1712 }
1713
1714 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1715 struct sk_buff *skb)
1716 {
1717 struct gfar_private *priv = netdev_priv(dev);
1718 u32 lstatus;
1719
1720 bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1721 priv->rx_buffer_size, DMA_FROM_DEVICE);
1722
1723 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1724
1725 if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1726 lstatus |= BD_LFLAG(RXBD_WRAP);
1727
1728 eieio();
1729
1730 bdp->lstatus = lstatus;
1731 }
1732
1733
1734 struct sk_buff * gfar_new_skb(struct net_device *dev)
1735 {
1736 unsigned int alignamount;
1737 struct gfar_private *priv = netdev_priv(dev);
1738 struct sk_buff *skb = NULL;
1739
1740 skb = __skb_dequeue(&priv->rx_recycle);
1741 if (!skb)
1742 skb = netdev_alloc_skb(dev,
1743 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1744
1745 if (!skb)
1746 return NULL;
1747
1748 alignamount = RXBUF_ALIGNMENT -
1749 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1750
1751 /* We need the data buffer to be aligned properly. We will reserve
1752 * as many bytes as needed to align the data properly
1753 */
1754 skb_reserve(skb, alignamount);
1755
1756 return skb;
1757 }
1758
1759 static inline void count_errors(unsigned short status, struct net_device *dev)
1760 {
1761 struct gfar_private *priv = netdev_priv(dev);
1762 struct net_device_stats *stats = &dev->stats;
1763 struct gfar_extra_stats *estats = &priv->extra_stats;
1764
1765 /* If the packet was truncated, none of the other errors
1766 * matter */
1767 if (status & RXBD_TRUNCATED) {
1768 stats->rx_length_errors++;
1769
1770 estats->rx_trunc++;
1771
1772 return;
1773 }
1774 /* Count the errors, if there were any */
1775 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1776 stats->rx_length_errors++;
1777
1778 if (status & RXBD_LARGE)
1779 estats->rx_large++;
1780 else
1781 estats->rx_short++;
1782 }
1783 if (status & RXBD_NONOCTET) {
1784 stats->rx_frame_errors++;
1785 estats->rx_nonoctet++;
1786 }
1787 if (status & RXBD_CRCERR) {
1788 estats->rx_crcerr++;
1789 stats->rx_crc_errors++;
1790 }
1791 if (status & RXBD_OVERRUN) {
1792 estats->rx_overrun++;
1793 stats->rx_crc_errors++;
1794 }
1795 }
1796
1797 irqreturn_t gfar_receive(int irq, void *dev_id)
1798 {
1799 gfar_schedule_cleanup((struct net_device *)dev_id);
1800 return IRQ_HANDLED;
1801 }
1802
1803 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1804 {
1805 /* If valid headers were found, and valid sums
1806 * were verified, then we tell the kernel that no
1807 * checksumming is necessary. Otherwise, it is */
1808 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1809 skb->ip_summed = CHECKSUM_UNNECESSARY;
1810 else
1811 skb->ip_summed = CHECKSUM_NONE;
1812 }
1813
1814
1815 /* gfar_process_frame() -- handle one incoming packet if skb
1816 * isn't NULL. */
1817 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1818 int amount_pull)
1819 {
1820 struct gfar_private *priv = netdev_priv(dev);
1821 struct rxfcb *fcb = NULL;
1822
1823 int ret;
1824
1825 /* fcb is at the beginning if exists */
1826 fcb = (struct rxfcb *)skb->data;
1827
1828 /* Remove the FCB from the skb */
1829 /* Remove the padded bytes, if there are any */
1830 if (amount_pull)
1831 skb_pull(skb, amount_pull);
1832
1833 if (priv->rx_csum_enable)
1834 gfar_rx_checksum(skb, fcb);
1835
1836 /* Tell the skb what kind of packet this is */
1837 skb->protocol = eth_type_trans(skb, dev);
1838
1839 /* Send the packet up the stack */
1840 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1841 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1842 else
1843 ret = netif_receive_skb(skb);
1844
1845 if (NET_RX_DROP == ret)
1846 priv->extra_stats.kernel_dropped++;
1847
1848 return 0;
1849 }
1850
1851 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1852 * until the budget/quota has been reached. Returns the number
1853 * of frames handled
1854 */
1855 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1856 {
1857 struct rxbd8 *bdp, *base;
1858 struct sk_buff *skb;
1859 int pkt_len;
1860 int amount_pull;
1861 int howmany = 0;
1862 struct gfar_private *priv = netdev_priv(dev);
1863
1864 /* Get the first full descriptor */
1865 bdp = priv->cur_rx;
1866 base = priv->rx_bd_base;
1867
1868 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1869 priv->padding;
1870
1871 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1872 struct sk_buff *newskb;
1873 rmb();
1874
1875 /* Add another skb for the future */
1876 newskb = gfar_new_skb(dev);
1877
1878 skb = priv->rx_skbuff[priv->skb_currx];
1879
1880 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
1881 priv->rx_buffer_size, DMA_FROM_DEVICE);
1882
1883 /* We drop the frame if we failed to allocate a new buffer */
1884 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1885 bdp->status & RXBD_ERR)) {
1886 count_errors(bdp->status, dev);
1887
1888 if (unlikely(!newskb))
1889 newskb = skb;
1890 else if (skb) {
1891 /*
1892 * We need to reset ->data to what it
1893 * was before gfar_new_skb() re-aligned
1894 * it to an RXBUF_ALIGNMENT boundary
1895 * before we put the skb back on the
1896 * recycle list.
1897 */
1898 skb->data = skb->head + NET_SKB_PAD;
1899 __skb_queue_head(&priv->rx_recycle, skb);
1900 }
1901 } else {
1902 /* Increment the number of packets */
1903 dev->stats.rx_packets++;
1904 howmany++;
1905
1906 if (likely(skb)) {
1907 pkt_len = bdp->length - ETH_FCS_LEN;
1908 /* Remove the FCS from the packet length */
1909 skb_put(skb, pkt_len);
1910 dev->stats.rx_bytes += pkt_len;
1911
1912 if (in_irq() || irqs_disabled())
1913 printk("Interrupt problem!\n");
1914 gfar_process_frame(dev, skb, amount_pull);
1915
1916 } else {
1917 if (netif_msg_rx_err(priv))
1918 printk(KERN_WARNING
1919 "%s: Missing skb!\n", dev->name);
1920 dev->stats.rx_dropped++;
1921 priv->extra_stats.rx_skbmissing++;
1922 }
1923
1924 }
1925
1926 priv->rx_skbuff[priv->skb_currx] = newskb;
1927
1928 /* Setup the new bdp */
1929 gfar_new_rxbdp(dev, bdp, newskb);
1930
1931 /* Update to the next pointer */
1932 bdp = next_bd(bdp, base, priv->rx_ring_size);
1933
1934 /* update to point at the next skb */
1935 priv->skb_currx =
1936 (priv->skb_currx + 1) &
1937 RX_RING_MOD_MASK(priv->rx_ring_size);
1938 }
1939
1940 /* Update the current rxbd pointer to be the next one */
1941 priv->cur_rx = bdp;
1942
1943 return howmany;
1944 }
1945
1946 static int gfar_poll(struct napi_struct *napi, int budget)
1947 {
1948 struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1949 struct net_device *dev = priv->ndev;
1950 int tx_cleaned = 0;
1951 int rx_cleaned = 0;
1952 unsigned long flags;
1953
1954 /* Clear IEVENT, so interrupts aren't called again
1955 * because of the packets that have already arrived */
1956 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1957
1958 /* If we fail to get the lock, don't bother with the TX BDs */
1959 if (spin_trylock_irqsave(&priv->txlock, flags)) {
1960 tx_cleaned = gfar_clean_tx_ring(dev);
1961 spin_unlock_irqrestore(&priv->txlock, flags);
1962 }
1963
1964 rx_cleaned = gfar_clean_rx_ring(dev, budget);
1965
1966 if (tx_cleaned)
1967 return budget;
1968
1969 if (rx_cleaned < budget) {
1970 napi_complete(napi);
1971
1972 /* Clear the halt bit in RSTAT */
1973 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1974
1975 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1976
1977 /* If we are coalescing interrupts, update the timer */
1978 /* Otherwise, clear it */
1979 if (likely(priv->rxcoalescing)) {
1980 gfar_write(&priv->regs->rxic, 0);
1981 gfar_write(&priv->regs->rxic, priv->rxic);
1982 }
1983 if (likely(priv->txcoalescing)) {
1984 gfar_write(&priv->regs->txic, 0);
1985 gfar_write(&priv->regs->txic, priv->txic);
1986 }
1987 }
1988
1989 return rx_cleaned;
1990 }
1991
1992 #ifdef CONFIG_NET_POLL_CONTROLLER
1993 /*
1994 * Polling 'interrupt' - used by things like netconsole to send skbs
1995 * without having to re-enable interrupts. It's not called while
1996 * the interrupt routine is executing.
1997 */
1998 static void gfar_netpoll(struct net_device *dev)
1999 {
2000 struct gfar_private *priv = netdev_priv(dev);
2001
2002 /* If the device has multiple interrupts, run tx/rx */
2003 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2004 disable_irq(priv->interruptTransmit);
2005 disable_irq(priv->interruptReceive);
2006 disable_irq(priv->interruptError);
2007 gfar_interrupt(priv->interruptTransmit, dev);
2008 enable_irq(priv->interruptError);
2009 enable_irq(priv->interruptReceive);
2010 enable_irq(priv->interruptTransmit);
2011 } else {
2012 disable_irq(priv->interruptTransmit);
2013 gfar_interrupt(priv->interruptTransmit, dev);
2014 enable_irq(priv->interruptTransmit);
2015 }
2016 }
2017 #endif
2018
2019 /* The interrupt handler for devices with one interrupt */
2020 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
2021 {
2022 struct net_device *dev = dev_id;
2023 struct gfar_private *priv = netdev_priv(dev);
2024
2025 /* Save ievent for future reference */
2026 u32 events = gfar_read(&priv->regs->ievent);
2027
2028 /* Check for reception */
2029 if (events & IEVENT_RX_MASK)
2030 gfar_receive(irq, dev_id);
2031
2032 /* Check for transmit completion */
2033 if (events & IEVENT_TX_MASK)
2034 gfar_transmit(irq, dev_id);
2035
2036 /* Check for errors */
2037 if (events & IEVENT_ERR_MASK)
2038 gfar_error(irq, dev_id);
2039
2040 return IRQ_HANDLED;
2041 }
2042
2043 /* Called every time the controller might need to be made
2044 * aware of new link state. The PHY code conveys this
2045 * information through variables in the phydev structure, and this
2046 * function converts those variables into the appropriate
2047 * register values, and can bring down the device if needed.
2048 */
2049 static void adjust_link(struct net_device *dev)
2050 {
2051 struct gfar_private *priv = netdev_priv(dev);
2052 struct gfar __iomem *regs = priv->regs;
2053 unsigned long flags;
2054 struct phy_device *phydev = priv->phydev;
2055 int new_state = 0;
2056
2057 spin_lock_irqsave(&priv->txlock, flags);
2058 if (phydev->link) {
2059 u32 tempval = gfar_read(&regs->maccfg2);
2060 u32 ecntrl = gfar_read(&regs->ecntrl);
2061
2062 /* Now we make sure that we can be in full duplex mode.
2063 * If not, we operate in half-duplex mode. */
2064 if (phydev->duplex != priv->oldduplex) {
2065 new_state = 1;
2066 if (!(phydev->duplex))
2067 tempval &= ~(MACCFG2_FULL_DUPLEX);
2068 else
2069 tempval |= MACCFG2_FULL_DUPLEX;
2070
2071 priv->oldduplex = phydev->duplex;
2072 }
2073
2074 if (phydev->speed != priv->oldspeed) {
2075 new_state = 1;
2076 switch (phydev->speed) {
2077 case 1000:
2078 tempval =
2079 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2080
2081 ecntrl &= ~(ECNTRL_R100);
2082 break;
2083 case 100:
2084 case 10:
2085 tempval =
2086 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2087
2088 /* Reduced mode distinguishes
2089 * between 10 and 100 */
2090 if (phydev->speed == SPEED_100)
2091 ecntrl |= ECNTRL_R100;
2092 else
2093 ecntrl &= ~(ECNTRL_R100);
2094 break;
2095 default:
2096 if (netif_msg_link(priv))
2097 printk(KERN_WARNING
2098 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2099 dev->name, phydev->speed);
2100 break;
2101 }
2102
2103 priv->oldspeed = phydev->speed;
2104 }
2105
2106 gfar_write(&regs->maccfg2, tempval);
2107 gfar_write(&regs->ecntrl, ecntrl);
2108
2109 if (!priv->oldlink) {
2110 new_state = 1;
2111 priv->oldlink = 1;
2112 }
2113 } else if (priv->oldlink) {
2114 new_state = 1;
2115 priv->oldlink = 0;
2116 priv->oldspeed = 0;
2117 priv->oldduplex = -1;
2118 }
2119
2120 if (new_state && netif_msg_link(priv))
2121 phy_print_status(phydev);
2122
2123 spin_unlock_irqrestore(&priv->txlock, flags);
2124 }
2125
2126 /* Update the hash table based on the current list of multicast
2127 * addresses we subscribe to. Also, change the promiscuity of
2128 * the device based on the flags (this function is called
2129 * whenever dev->flags is changed */
2130 static void gfar_set_multi(struct net_device *dev)
2131 {
2132 struct dev_mc_list *mc_ptr;
2133 struct gfar_private *priv = netdev_priv(dev);
2134 struct gfar __iomem *regs = priv->regs;
2135 u32 tempval;
2136
2137 if(dev->flags & IFF_PROMISC) {
2138 /* Set RCTRL to PROM */
2139 tempval = gfar_read(&regs->rctrl);
2140 tempval |= RCTRL_PROM;
2141 gfar_write(&regs->rctrl, tempval);
2142 } else {
2143 /* Set RCTRL to not PROM */
2144 tempval = gfar_read(&regs->rctrl);
2145 tempval &= ~(RCTRL_PROM);
2146 gfar_write(&regs->rctrl, tempval);
2147 }
2148
2149 if(dev->flags & IFF_ALLMULTI) {
2150 /* Set the hash to rx all multicast frames */
2151 gfar_write(&regs->igaddr0, 0xffffffff);
2152 gfar_write(&regs->igaddr1, 0xffffffff);
2153 gfar_write(&regs->igaddr2, 0xffffffff);
2154 gfar_write(&regs->igaddr3, 0xffffffff);
2155 gfar_write(&regs->igaddr4, 0xffffffff);
2156 gfar_write(&regs->igaddr5, 0xffffffff);
2157 gfar_write(&regs->igaddr6, 0xffffffff);
2158 gfar_write(&regs->igaddr7, 0xffffffff);
2159 gfar_write(&regs->gaddr0, 0xffffffff);
2160 gfar_write(&regs->gaddr1, 0xffffffff);
2161 gfar_write(&regs->gaddr2, 0xffffffff);
2162 gfar_write(&regs->gaddr3, 0xffffffff);
2163 gfar_write(&regs->gaddr4, 0xffffffff);
2164 gfar_write(&regs->gaddr5, 0xffffffff);
2165 gfar_write(&regs->gaddr6, 0xffffffff);
2166 gfar_write(&regs->gaddr7, 0xffffffff);
2167 } else {
2168 int em_num;
2169 int idx;
2170
2171 /* zero out the hash */
2172 gfar_write(&regs->igaddr0, 0x0);
2173 gfar_write(&regs->igaddr1, 0x0);
2174 gfar_write(&regs->igaddr2, 0x0);
2175 gfar_write(&regs->igaddr3, 0x0);
2176 gfar_write(&regs->igaddr4, 0x0);
2177 gfar_write(&regs->igaddr5, 0x0);
2178 gfar_write(&regs->igaddr6, 0x0);
2179 gfar_write(&regs->igaddr7, 0x0);
2180 gfar_write(&regs->gaddr0, 0x0);
2181 gfar_write(&regs->gaddr1, 0x0);
2182 gfar_write(&regs->gaddr2, 0x0);
2183 gfar_write(&regs->gaddr3, 0x0);
2184 gfar_write(&regs->gaddr4, 0x0);
2185 gfar_write(&regs->gaddr5, 0x0);
2186 gfar_write(&regs->gaddr6, 0x0);
2187 gfar_write(&regs->gaddr7, 0x0);
2188
2189 /* If we have extended hash tables, we need to
2190 * clear the exact match registers to prepare for
2191 * setting them */
2192 if (priv->extended_hash) {
2193 em_num = GFAR_EM_NUM + 1;
2194 gfar_clear_exact_match(dev);
2195 idx = 1;
2196 } else {
2197 idx = 0;
2198 em_num = 0;
2199 }
2200
2201 if(dev->mc_count == 0)
2202 return;
2203
2204 /* Parse the list, and set the appropriate bits */
2205 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2206 if (idx < em_num) {
2207 gfar_set_mac_for_addr(dev, idx,
2208 mc_ptr->dmi_addr);
2209 idx++;
2210 } else
2211 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2212 }
2213 }
2214
2215 return;
2216 }
2217
2218
2219 /* Clears each of the exact match registers to zero, so they
2220 * don't interfere with normal reception */
2221 static void gfar_clear_exact_match(struct net_device *dev)
2222 {
2223 int idx;
2224 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2225
2226 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2227 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2228 }
2229
2230 /* Set the appropriate hash bit for the given addr */
2231 /* The algorithm works like so:
2232 * 1) Take the Destination Address (ie the multicast address), and
2233 * do a CRC on it (little endian), and reverse the bits of the
2234 * result.
2235 * 2) Use the 8 most significant bits as a hash into a 256-entry
2236 * table. The table is controlled through 8 32-bit registers:
2237 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2238 * gaddr7. This means that the 3 most significant bits in the
2239 * hash index which gaddr register to use, and the 5 other bits
2240 * indicate which bit (assuming an IBM numbering scheme, which
2241 * for PowerPC (tm) is usually the case) in the register holds
2242 * the entry. */
2243 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2244 {
2245 u32 tempval;
2246 struct gfar_private *priv = netdev_priv(dev);
2247 u32 result = ether_crc(MAC_ADDR_LEN, addr);
2248 int width = priv->hash_width;
2249 u8 whichbit = (result >> (32 - width)) & 0x1f;
2250 u8 whichreg = result >> (32 - width + 5);
2251 u32 value = (1 << (31-whichbit));
2252
2253 tempval = gfar_read(priv->hash_regs[whichreg]);
2254 tempval |= value;
2255 gfar_write(priv->hash_regs[whichreg], tempval);
2256
2257 return;
2258 }
2259
2260
2261 /* There are multiple MAC Address register pairs on some controllers
2262 * This function sets the numth pair to a given address
2263 */
2264 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2265 {
2266 struct gfar_private *priv = netdev_priv(dev);
2267 int idx;
2268 char tmpbuf[MAC_ADDR_LEN];
2269 u32 tempval;
2270 u32 __iomem *macptr = &priv->regs->macstnaddr1;
2271
2272 macptr += num*2;
2273
2274 /* Now copy it into the mac registers backwards, cuz */
2275 /* little endian is silly */
2276 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2277 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2278
2279 gfar_write(macptr, *((u32 *) (tmpbuf)));
2280
2281 tempval = *((u32 *) (tmpbuf + 4));
2282
2283 gfar_write(macptr+1, tempval);
2284 }
2285
2286 /* GFAR error interrupt handler */
2287 static irqreturn_t gfar_error(int irq, void *dev_id)
2288 {
2289 struct net_device *dev = dev_id;
2290 struct gfar_private *priv = netdev_priv(dev);
2291
2292 /* Save ievent for future reference */
2293 u32 events = gfar_read(&priv->regs->ievent);
2294
2295 /* Clear IEVENT */
2296 gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2297
2298 /* Magic Packet is not an error. */
2299 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2300 (events & IEVENT_MAG))
2301 events &= ~IEVENT_MAG;
2302
2303 /* Hmm... */
2304 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2305 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2306 dev->name, events, gfar_read(&priv->regs->imask));
2307
2308 /* Update the error counters */
2309 if (events & IEVENT_TXE) {
2310 dev->stats.tx_errors++;
2311
2312 if (events & IEVENT_LC)
2313 dev->stats.tx_window_errors++;
2314 if (events & IEVENT_CRL)
2315 dev->stats.tx_aborted_errors++;
2316 if (events & IEVENT_XFUN) {
2317 if (netif_msg_tx_err(priv))
2318 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2319 "packet dropped.\n", dev->name);
2320 dev->stats.tx_dropped++;
2321 priv->extra_stats.tx_underrun++;
2322
2323 /* Reactivate the Tx Queues */
2324 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2325 }
2326 if (netif_msg_tx_err(priv))
2327 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2328 }
2329 if (events & IEVENT_BSY) {
2330 dev->stats.rx_errors++;
2331 priv->extra_stats.rx_bsy++;
2332
2333 gfar_receive(irq, dev_id);
2334
2335 if (netif_msg_rx_err(priv))
2336 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2337 dev->name, gfar_read(&priv->regs->rstat));
2338 }
2339 if (events & IEVENT_BABR) {
2340 dev->stats.rx_errors++;
2341 priv->extra_stats.rx_babr++;
2342
2343 if (netif_msg_rx_err(priv))
2344 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2345 }
2346 if (events & IEVENT_EBERR) {
2347 priv->extra_stats.eberr++;
2348 if (netif_msg_rx_err(priv))
2349 printk(KERN_DEBUG "%s: bus error\n", dev->name);
2350 }
2351 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2352 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2353
2354 if (events & IEVENT_BABT) {
2355 priv->extra_stats.tx_babt++;
2356 if (netif_msg_tx_err(priv))
2357 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2358 }
2359 return IRQ_HANDLED;
2360 }
2361
2362 /* work with hotplug and coldplug */
2363 MODULE_ALIAS("platform:fsl-gianfar");
2364
2365 static struct of_device_id gfar_match[] =
2366 {
2367 {
2368 .type = "network",
2369 .compatible = "gianfar",
2370 },
2371 {},
2372 };
2373
2374 /* Structure for a device driver */
2375 static struct of_platform_driver gfar_driver = {
2376 .name = "fsl-gianfar",
2377 .match_table = gfar_match,
2378
2379 .probe = gfar_probe,
2380 .remove = gfar_remove,
2381 .suspend = gfar_suspend,
2382 .resume = gfar_resume,
2383 };
2384
2385 static int __init gfar_init(void)
2386 {
2387 return of_register_platform_driver(&gfar_driver);
2388 }
2389
2390 static void __exit gfar_exit(void)
2391 {
2392 of_unregister_platform_driver(&gfar_driver);
2393 }
2394
2395 module_init(gfar_init);
2396 module_exit(gfar_exit);
2397
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree