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ring-buffer: Fix advance of reader in rb_buffer_peek()
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / 8139too.c
blobd35cf5b5b6fff3761ea1416d06c11858cf3bad5c
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.28"
94
95
96 #include <linux/module.h>
97 #include <linux/kernel.h>
98 #include <linux/compiler.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/netdevice.h>
102 #include <linux/etherdevice.h>
103 #include <linux/rtnetlink.h>
104 #include <linux/delay.h>
105 #include <linux/ethtool.h>
106 #include <linux/mii.h>
107 #include <linux/completion.h>
108 #include <linux/crc32.h>
109 #include <linux/io.h>
110 #include <linux/uaccess.h>
111 #include <asm/irq.h>
112
113 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
114 #define PFX DRV_NAME ": "
115
116 /* Default Message level */
117 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
118 NETIF_MSG_PROBE | \
119 NETIF_MSG_LINK)
120
121
122 /* define to 1, 2 or 3 to enable copious debugging info */
123 #define RTL8139_DEBUG 0
124
125 /* define to 1 to disable lightweight runtime debugging checks */
126 #undef RTL8139_NDEBUG
127
128
129 #if RTL8139_DEBUG
130 /* note: prints function name for you */
131 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
132 #else
133 # define DPRINTK(fmt, args...)
134 #endif
135
136 #ifdef RTL8139_NDEBUG
137 # define assert(expr) do {} while (0)
138 #else
139 # define assert(expr) \
140 if(unlikely(!(expr))) { \
141 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
142 #expr, __FILE__, __func__, __LINE__); \
143 }
144 #endif
145
146
147 /* A few user-configurable values. */
148 /* media options */
149 #define MAX_UNITS 8
150 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
151 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
152
153 /* Whether to use MMIO or PIO. Default to MMIO. */
154 #ifdef CONFIG_8139TOO_PIO
155 static int use_io = 1;
156 #else
157 static int use_io = 0;
158 #endif
159
160 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
161 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
162 static int multicast_filter_limit = 32;
163
164 /* bitmapped message enable number */
165 static int debug = -1;
166
167 /*
168 * Receive ring size
169 * Warning: 64K ring has hardware issues and may lock up.
170 */
171 #if defined(CONFIG_SH_DREAMCAST)
172 #define RX_BUF_IDX 0 /* 8K ring */
173 #else
174 #define RX_BUF_IDX 2 /* 32K ring */
175 #endif
176 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
177 #define RX_BUF_PAD 16
178 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
179
180 #if RX_BUF_LEN == 65536
181 #define RX_BUF_TOT_LEN RX_BUF_LEN
182 #else
183 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
184 #endif
185
186 /* Number of Tx descriptor registers. */
187 #define NUM_TX_DESC 4
188
189 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
190 #define MAX_ETH_FRAME_SIZE 1536
191
192 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
193 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
194 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
195
196 /* PCI Tuning Parameters
197 Threshold is bytes transferred to chip before transmission starts. */
198 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
199
200 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
201 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
202 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
204 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
205
206 /* Operational parameters that usually are not changed. */
207 /* Time in jiffies before concluding the transmitter is hung. */
208 #define TX_TIMEOUT (6*HZ)
209
210
211 enum {
212 HAS_MII_XCVR = 0x010000,
213 HAS_CHIP_XCVR = 0x020000,
214 HAS_LNK_CHNG = 0x040000,
215 };
216
217 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
218 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
219 #define RTL_MIN_IO_SIZE 0x80
220 #define RTL8139B_IO_SIZE 256
221
222 #define RTL8129_CAPS HAS_MII_XCVR
223 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
224
225 typedef enum {
226 RTL8139 = 0,
227 RTL8129,
228 } board_t;
229
230
231 /* indexed by board_t, above */
232 static const struct {
233 const char *name;
234 u32 hw_flags;
235 } board_info[] __devinitdata = {
236 { "RealTek RTL8139", RTL8139_CAPS },
237 { "RealTek RTL8129", RTL8129_CAPS },
238 };
239
240
241 static struct pci_device_id rtl8139_pci_tbl[] = {
242 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261
262 #ifdef CONFIG_SH_SECUREEDGE5410
263 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
264 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
265 #endif
266 #ifdef CONFIG_8139TOO_8129
267 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
268 #endif
269
270 /* some crazy cards report invalid vendor ids like
271 * 0x0001 here. The other ids are valid and constant,
272 * so we simply don't match on the main vendor id.
273 */
274 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
276 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
277
278 {0,}
279 };
280 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
281
282 static struct {
283 const char str[ETH_GSTRING_LEN];
284 } ethtool_stats_keys[] = {
285 { "early_rx" },
286 { "tx_buf_mapped" },
287 { "tx_timeouts" },
288 { "rx_lost_in_ring" },
289 };
290
291 /* The rest of these values should never change. */
292
293 /* Symbolic offsets to registers. */
294 enum RTL8139_registers {
295 MAC0 = 0, /* Ethernet hardware address. */
296 MAR0 = 8, /* Multicast filter. */
297 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
298 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
299 RxBuf = 0x30,
300 ChipCmd = 0x37,
301 RxBufPtr = 0x38,
302 RxBufAddr = 0x3A,
303 IntrMask = 0x3C,
304 IntrStatus = 0x3E,
305 TxConfig = 0x40,
306 RxConfig = 0x44,
307 Timer = 0x48, /* A general-purpose counter. */
308 RxMissed = 0x4C, /* 24 bits valid, write clears. */
309 Cfg9346 = 0x50,
310 Config0 = 0x51,
311 Config1 = 0x52,
312 TimerInt = 0x54,
313 MediaStatus = 0x58,
314 Config3 = 0x59,
315 Config4 = 0x5A, /* absent on RTL-8139A */
316 HltClk = 0x5B,
317 MultiIntr = 0x5C,
318 TxSummary = 0x60,
319 BasicModeCtrl = 0x62,
320 BasicModeStatus = 0x64,
321 NWayAdvert = 0x66,
322 NWayLPAR = 0x68,
323 NWayExpansion = 0x6A,
324 /* Undocumented registers, but required for proper operation. */
325 FIFOTMS = 0x70, /* FIFO Control and test. */
326 CSCR = 0x74, /* Chip Status and Configuration Register. */
327 PARA78 = 0x78,
328 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */
329 PARA7c = 0x7c, /* Magic transceiver parameter register. */
330 Config5 = 0xD8, /* absent on RTL-8139A */
331 };
332
333 enum ClearBitMasks {
334 MultiIntrClear = 0xF000,
335 ChipCmdClear = 0xE2,
336 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
337 };
338
339 enum ChipCmdBits {
340 CmdReset = 0x10,
341 CmdRxEnb = 0x08,
342 CmdTxEnb = 0x04,
343 RxBufEmpty = 0x01,
344 };
345
346 /* Interrupt register bits, using my own meaningful names. */
347 enum IntrStatusBits {
348 PCIErr = 0x8000,
349 PCSTimeout = 0x4000,
350 RxFIFOOver = 0x40,
351 RxUnderrun = 0x20,
352 RxOverflow = 0x10,
353 TxErr = 0x08,
354 TxOK = 0x04,
355 RxErr = 0x02,
356 RxOK = 0x01,
357
358 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
359 };
360
361 enum TxStatusBits {
362 TxHostOwns = 0x2000,
363 TxUnderrun = 0x4000,
364 TxStatOK = 0x8000,
365 TxOutOfWindow = 0x20000000,
366 TxAborted = 0x40000000,
367 TxCarrierLost = 0x80000000,
368 };
369 enum RxStatusBits {
370 RxMulticast = 0x8000,
371 RxPhysical = 0x4000,
372 RxBroadcast = 0x2000,
373 RxBadSymbol = 0x0020,
374 RxRunt = 0x0010,
375 RxTooLong = 0x0008,
376 RxCRCErr = 0x0004,
377 RxBadAlign = 0x0002,
378 RxStatusOK = 0x0001,
379 };
380
381 /* Bits in RxConfig. */
382 enum rx_mode_bits {
383 AcceptErr = 0x20,
384 AcceptRunt = 0x10,
385 AcceptBroadcast = 0x08,
386 AcceptMulticast = 0x04,
387 AcceptMyPhys = 0x02,
388 AcceptAllPhys = 0x01,
389 };
390
391 /* Bits in TxConfig. */
392 enum tx_config_bits {
393 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
394 TxIFGShift = 24,
395 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
396 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
397 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
398 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
399
400 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
401 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
402 TxClearAbt = (1 << 0), /* Clear abort (WO) */
403 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
404 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
405
406 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
407 };
408
409 /* Bits in Config1 */
410 enum Config1Bits {
411 Cfg1_PM_Enable = 0x01,
412 Cfg1_VPD_Enable = 0x02,
413 Cfg1_PIO = 0x04,
414 Cfg1_MMIO = 0x08,
415 LWAKE = 0x10, /* not on 8139, 8139A */
416 Cfg1_Driver_Load = 0x20,
417 Cfg1_LED0 = 0x40,
418 Cfg1_LED1 = 0x80,
419 SLEEP = (1 << 1), /* only on 8139, 8139A */
420 PWRDN = (1 << 0), /* only on 8139, 8139A */
421 };
422
423 /* Bits in Config3 */
424 enum Config3Bits {
425 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
426 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
427 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
428 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
429 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
430 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
431 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
432 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
433 };
434
435 /* Bits in Config4 */
436 enum Config4Bits {
437 LWPTN = (1 << 2), /* not on 8139, 8139A */
438 };
439
440 /* Bits in Config5 */
441 enum Config5Bits {
442 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
443 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
444 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
445 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
446 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
447 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
448 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
449 };
450
451 enum RxConfigBits {
452 /* rx fifo threshold */
453 RxCfgFIFOShift = 13,
454 RxCfgFIFONone = (7 << RxCfgFIFOShift),
455
456 /* Max DMA burst */
457 RxCfgDMAShift = 8,
458 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
459
460 /* rx ring buffer length */
461 RxCfgRcv8K = 0,
462 RxCfgRcv16K = (1 << 11),
463 RxCfgRcv32K = (1 << 12),
464 RxCfgRcv64K = (1 << 11) | (1 << 12),
465
466 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
467 RxNoWrap = (1 << 7),
468 };
469
470 /* Twister tuning parameters from RealTek.
471 Completely undocumented, but required to tune bad links on some boards. */
472 enum CSCRBits {
473 CSCR_LinkOKBit = 0x0400,
474 CSCR_LinkChangeBit = 0x0800,
475 CSCR_LinkStatusBits = 0x0f000,
476 CSCR_LinkDownOffCmd = 0x003c0,
477 CSCR_LinkDownCmd = 0x0f3c0,
478 };
479
480 enum Cfg9346Bits {
481 Cfg9346_Lock = 0x00,
482 Cfg9346_Unlock = 0xC0,
483 };
484
485 typedef enum {
486 CH_8139 = 0,
487 CH_8139_K,
488 CH_8139A,
489 CH_8139A_G,
490 CH_8139B,
491 CH_8130,
492 CH_8139C,
493 CH_8100,
494 CH_8100B_8139D,
495 CH_8101,
496 } chip_t;
497
498 enum chip_flags {
499 HasHltClk = (1 << 0),
500 HasLWake = (1 << 1),
501 };
502
503 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
504 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
505 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
506
507 /* directly indexed by chip_t, above */
508 static const struct {
509 const char *name;
510 u32 version; /* from RTL8139C/RTL8139D docs */
511 u32 flags;
512 } rtl_chip_info[] = {
513 { "RTL-8139",
514 HW_REVID(1, 0, 0, 0, 0, 0, 0),
515 HasHltClk,
516 },
517
518 { "RTL-8139 rev K",
519 HW_REVID(1, 1, 0, 0, 0, 0, 0),
520 HasHltClk,
521 },
522
523 { "RTL-8139A",
524 HW_REVID(1, 1, 1, 0, 0, 0, 0),
525 HasHltClk, /* XXX undocumented? */
526 },
527
528 { "RTL-8139A rev G",
529 HW_REVID(1, 1, 1, 0, 0, 1, 0),
530 HasHltClk, /* XXX undocumented? */
531 },
532
533 { "RTL-8139B",
534 HW_REVID(1, 1, 1, 1, 0, 0, 0),
535 HasLWake,
536 },
537
538 { "RTL-8130",
539 HW_REVID(1, 1, 1, 1, 1, 0, 0),
540 HasLWake,
541 },
542
543 { "RTL-8139C",
544 HW_REVID(1, 1, 1, 0, 1, 0, 0),
545 HasLWake,
546 },
547
548 { "RTL-8100",
549 HW_REVID(1, 1, 1, 1, 0, 1, 0),
550 HasLWake,
551 },
552
553 { "RTL-8100B/8139D",
554 HW_REVID(1, 1, 1, 0, 1, 0, 1),
555 HasHltClk /* XXX undocumented? */
556 | HasLWake,
557 },
558
559 { "RTL-8101",
560 HW_REVID(1, 1, 1, 0, 1, 1, 1),
561 HasLWake,
562 },
563 };
564
565 struct rtl_extra_stats {
566 unsigned long early_rx;
567 unsigned long tx_buf_mapped;
568 unsigned long tx_timeouts;
569 unsigned long rx_lost_in_ring;
570 };
571
572 struct rtl8139_private {
573 void __iomem *mmio_addr;
574 int drv_flags;
575 struct pci_dev *pci_dev;
576 u32 msg_enable;
577 struct napi_struct napi;
578 struct net_device *dev;
579
580 unsigned char *rx_ring;
581 unsigned int cur_rx; /* RX buf index of next pkt */
582 dma_addr_t rx_ring_dma;
583
584 unsigned int tx_flag;
585 unsigned long cur_tx;
586 unsigned long dirty_tx;
587 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
588 unsigned char *tx_bufs; /* Tx bounce buffer region. */
589 dma_addr_t tx_bufs_dma;
590
591 signed char phys[4]; /* MII device addresses. */
592
593 /* Twister tune state. */
594 char twistie, twist_row, twist_col;
595
596 unsigned int watchdog_fired : 1;
597 unsigned int default_port : 4; /* Last dev->if_port value. */
598 unsigned int have_thread : 1;
599
600 spinlock_t lock;
601 spinlock_t rx_lock;
602
603 chip_t chipset;
604 u32 rx_config;
605 struct rtl_extra_stats xstats;
606
607 struct delayed_work thread;
608
609 struct mii_if_info mii;
610 unsigned int regs_len;
611 unsigned long fifo_copy_timeout;
612 };
613
614 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
615 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
616 MODULE_LICENSE("GPL");
617 MODULE_VERSION(DRV_VERSION);
618
619 module_param(use_io, int, 0);
620 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
621 module_param(multicast_filter_limit, int, 0);
622 module_param_array(media, int, NULL, 0);
623 module_param_array(full_duplex, int, NULL, 0);
624 module_param(debug, int, 0);
625 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
626 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
627 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
628 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
629
630 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
631 static int rtl8139_open (struct net_device *dev);
632 static int mdio_read (struct net_device *dev, int phy_id, int location);
633 static void mdio_write (struct net_device *dev, int phy_id, int location,
634 int val);
635 static void rtl8139_start_thread(struct rtl8139_private *tp);
636 static void rtl8139_tx_timeout (struct net_device *dev);
637 static void rtl8139_init_ring (struct net_device *dev);
638 static int rtl8139_start_xmit (struct sk_buff *skb,
639 struct net_device *dev);
640 #ifdef CONFIG_NET_POLL_CONTROLLER
641 static void rtl8139_poll_controller(struct net_device *dev);
642 #endif
643 static int rtl8139_set_mac_address(struct net_device *dev, void *p);
644 static int rtl8139_poll(struct napi_struct *napi, int budget);
645 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
646 static int rtl8139_close (struct net_device *dev);
647 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
648 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
649 static void rtl8139_set_rx_mode (struct net_device *dev);
650 static void __set_rx_mode (struct net_device *dev);
651 static void rtl8139_hw_start (struct net_device *dev);
652 static void rtl8139_thread (struct work_struct *work);
653 static void rtl8139_tx_timeout_task(struct work_struct *work);
654 static const struct ethtool_ops rtl8139_ethtool_ops;
655
656 /* write MMIO register, with flush */
657 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
658 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
659 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
660 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
661
662 /* write MMIO register */
663 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
664 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
665 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
666
667 /* read MMIO register */
668 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
669 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
670 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
671
672
673 static const u16 rtl8139_intr_mask =
674 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
675 TxErr | TxOK | RxErr | RxOK;
676
677 static const u16 rtl8139_norx_intr_mask =
678 PCIErr | PCSTimeout | RxUnderrun |
679 TxErr | TxOK | RxErr ;
680
681 #if RX_BUF_IDX == 0
682 static const unsigned int rtl8139_rx_config =
683 RxCfgRcv8K | RxNoWrap |
684 (RX_FIFO_THRESH << RxCfgFIFOShift) |
685 (RX_DMA_BURST << RxCfgDMAShift);
686 #elif RX_BUF_IDX == 1
687 static const unsigned int rtl8139_rx_config =
688 RxCfgRcv16K | RxNoWrap |
689 (RX_FIFO_THRESH << RxCfgFIFOShift) |
690 (RX_DMA_BURST << RxCfgDMAShift);
691 #elif RX_BUF_IDX == 2
692 static const unsigned int rtl8139_rx_config =
693 RxCfgRcv32K | RxNoWrap |
694 (RX_FIFO_THRESH << RxCfgFIFOShift) |
695 (RX_DMA_BURST << RxCfgDMAShift);
696 #elif RX_BUF_IDX == 3
697 static const unsigned int rtl8139_rx_config =
698 RxCfgRcv64K |
699 (RX_FIFO_THRESH << RxCfgFIFOShift) |
700 (RX_DMA_BURST << RxCfgDMAShift);
701 #else
702 #error "Invalid configuration for 8139_RXBUF_IDX"
703 #endif
704
705 static const unsigned int rtl8139_tx_config =
706 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
707
708 static void __rtl8139_cleanup_dev (struct net_device *dev)
709 {
710 struct rtl8139_private *tp = netdev_priv(dev);
711 struct pci_dev *pdev;
712
713 assert (dev != NULL);
714 assert (tp->pci_dev != NULL);
715 pdev = tp->pci_dev;
716
717 if (tp->mmio_addr)
718 pci_iounmap (pdev, tp->mmio_addr);
719
720 /* it's ok to call this even if we have no regions to free */
721 pci_release_regions (pdev);
722
723 free_netdev(dev);
724 pci_set_drvdata (pdev, NULL);
725 }
726
727
728 static void rtl8139_chip_reset (void __iomem *ioaddr)
729 {
730 int i;
731
732 /* Soft reset the chip. */
733 RTL_W8 (ChipCmd, CmdReset);
734
735 /* Check that the chip has finished the reset. */
736 for (i = 1000; i > 0; i--) {
737 barrier();
738 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
739 break;
740 udelay (10);
741 }
742 }
743
744
745 static __devinit struct net_device * rtl8139_init_board (struct pci_dev *pdev)
746 {
747 void __iomem *ioaddr;
748 struct net_device *dev;
749 struct rtl8139_private *tp;
750 u8 tmp8;
751 int rc, disable_dev_on_err = 0;
752 unsigned int i;
753 unsigned long pio_start, pio_end, pio_flags, pio_len;
754 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
755 u32 version;
756
757 assert (pdev != NULL);
758
759 /* dev and priv zeroed in alloc_etherdev */
760 dev = alloc_etherdev (sizeof (*tp));
761 if (dev == NULL) {
762 dev_err(&pdev->dev, "Unable to alloc new net device\n");
763 return ERR_PTR(-ENOMEM);
764 }
765 SET_NETDEV_DEV(dev, &pdev->dev);
766
767 tp = netdev_priv(dev);
768 tp->pci_dev = pdev;
769
770 /* enable device (incl. PCI PM wakeup and hotplug setup) */
771 rc = pci_enable_device (pdev);
772 if (rc)
773 goto err_out;
774
775 pio_start = pci_resource_start (pdev, 0);
776 pio_end = pci_resource_end (pdev, 0);
777 pio_flags = pci_resource_flags (pdev, 0);
778 pio_len = pci_resource_len (pdev, 0);
779
780 mmio_start = pci_resource_start (pdev, 1);
781 mmio_end = pci_resource_end (pdev, 1);
782 mmio_flags = pci_resource_flags (pdev, 1);
783 mmio_len = pci_resource_len (pdev, 1);
784
785 /* set this immediately, we need to know before
786 * we talk to the chip directly */
787 DPRINTK("PIO region size == 0x%02X\n", pio_len);
788 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
789
790 retry:
791 if (use_io) {
792 /* make sure PCI base addr 0 is PIO */
793 if (!(pio_flags & IORESOURCE_IO)) {
794 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
795 rc = -ENODEV;
796 goto err_out;
797 }
798 /* check for weird/broken PCI region reporting */
799 if (pio_len < RTL_MIN_IO_SIZE) {
800 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
801 rc = -ENODEV;
802 goto err_out;
803 }
804 } else {
805 /* make sure PCI base addr 1 is MMIO */
806 if (!(mmio_flags & IORESOURCE_MEM)) {
807 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
808 rc = -ENODEV;
809 goto err_out;
810 }
811 if (mmio_len < RTL_MIN_IO_SIZE) {
812 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
813 rc = -ENODEV;
814 goto err_out;
815 }
816 }
817
818 rc = pci_request_regions (pdev, DRV_NAME);
819 if (rc)
820 goto err_out;
821 disable_dev_on_err = 1;
822
823 /* enable PCI bus-mastering */
824 pci_set_master (pdev);
825
826 if (use_io) {
827 ioaddr = pci_iomap(pdev, 0, 0);
828 if (!ioaddr) {
829 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
830 rc = -EIO;
831 goto err_out;
832 }
833 dev->base_addr = pio_start;
834 tp->regs_len = pio_len;
835 } else {
836 /* ioremap MMIO region */
837 ioaddr = pci_iomap(pdev, 1, 0);
838 if (ioaddr == NULL) {
839 dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n");
840 pci_release_regions(pdev);
841 use_io = 1;
842 goto retry;
843 }
844 dev->base_addr = (long) ioaddr;
845 tp->regs_len = mmio_len;
846 }
847 tp->mmio_addr = ioaddr;
848
849 /* Bring old chips out of low-power mode. */
850 RTL_W8 (HltClk, 'R');
851
852 /* check for missing/broken hardware */
853 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
854 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
855 rc = -EIO;
856 goto err_out;
857 }
858
859 /* identify chip attached to board */
860 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
861 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
862 if (version == rtl_chip_info[i].version) {
863 tp->chipset = i;
864 goto match;
865 }
866
867 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
868 dev_printk (KERN_DEBUG, &pdev->dev,
869 "unknown chip version, assuming RTL-8139\n");
870 dev_printk (KERN_DEBUG, &pdev->dev,
871 "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
872 tp->chipset = 0;
873
874 match:
875 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
876 version, i, rtl_chip_info[i].name);
877
878 if (tp->chipset >= CH_8139B) {
879 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
880 DPRINTK("PCI PM wakeup\n");
881 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
882 (tmp8 & LWAKE))
883 new_tmp8 &= ~LWAKE;
884 new_tmp8 |= Cfg1_PM_Enable;
885 if (new_tmp8 != tmp8) {
886 RTL_W8 (Cfg9346, Cfg9346_Unlock);
887 RTL_W8 (Config1, tmp8);
888 RTL_W8 (Cfg9346, Cfg9346_Lock);
889 }
890 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
891 tmp8 = RTL_R8 (Config4);
892 if (tmp8 & LWPTN) {
893 RTL_W8 (Cfg9346, Cfg9346_Unlock);
894 RTL_W8 (Config4, tmp8 & ~LWPTN);
895 RTL_W8 (Cfg9346, Cfg9346_Lock);
896 }
897 }
898 } else {
899 DPRINTK("Old chip wakeup\n");
900 tmp8 = RTL_R8 (Config1);
901 tmp8 &= ~(SLEEP | PWRDN);
902 RTL_W8 (Config1, tmp8);
903 }
904
905 rtl8139_chip_reset (ioaddr);
906
907 return dev;
908
909 err_out:
910 __rtl8139_cleanup_dev (dev);
911 if (disable_dev_on_err)
912 pci_disable_device (pdev);
913 return ERR_PTR(rc);
914 }
915
916 static const struct net_device_ops rtl8139_netdev_ops = {
917 .ndo_open = rtl8139_open,
918 .ndo_stop = rtl8139_close,
919 .ndo_get_stats = rtl8139_get_stats,
920 .ndo_change_mtu = eth_change_mtu,
921 .ndo_validate_addr = eth_validate_addr,
922 .ndo_set_mac_address = rtl8139_set_mac_address,
923 .ndo_start_xmit = rtl8139_start_xmit,
924 .ndo_set_multicast_list = rtl8139_set_rx_mode,
925 .ndo_do_ioctl = netdev_ioctl,
926 .ndo_tx_timeout = rtl8139_tx_timeout,
927 #ifdef CONFIG_NET_POLL_CONTROLLER
928 .ndo_poll_controller = rtl8139_poll_controller,
929 #endif
930 };
931
932 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
933 const struct pci_device_id *ent)
934 {
935 struct net_device *dev = NULL;
936 struct rtl8139_private *tp;
937 int i, addr_len, option;
938 void __iomem *ioaddr;
939 static int board_idx = -1;
940
941 assert (pdev != NULL);
942 assert (ent != NULL);
943
944 board_idx++;
945
946 /* when we're built into the kernel, the driver version message
947 * is only printed if at least one 8139 board has been found
948 */
949 #ifndef MODULE
950 {
951 static int printed_version;
952 if (!printed_version++)
953 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
954 }
955 #endif
956
957 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
958 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
959 dev_info(&pdev->dev,
960 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
961 pdev->vendor, pdev->device, pdev->revision);
962 return -ENODEV;
963 }
964
965 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
966 pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
967 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
968 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
969 printk(KERN_INFO "8139too: OQO Model 2 detected. Forcing PIO\n");
970 use_io = 1;
971 }
972
973 dev = rtl8139_init_board (pdev);
974 if (IS_ERR(dev))
975 return PTR_ERR(dev);
976
977 assert (dev != NULL);
978 tp = netdev_priv(dev);
979 tp->dev = dev;
980
981 ioaddr = tp->mmio_addr;
982 assert (ioaddr != NULL);
983
984 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
985 for (i = 0; i < 3; i++)
986 ((__le16 *) (dev->dev_addr))[i] =
987 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
988 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
989
990 /* The Rtl8139-specific entries in the device structure. */
991 dev->netdev_ops = &rtl8139_netdev_ops;
992 dev->ethtool_ops = &rtl8139_ethtool_ops;
993 dev->watchdog_timeo = TX_TIMEOUT;
994 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
995
996 /* note: the hardware is not capable of sg/csum/highdma, however
997 * through the use of skb_copy_and_csum_dev we enable these
998 * features
999 */
1000 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1001
1002 dev->irq = pdev->irq;
1003
1004 /* tp zeroed and aligned in alloc_etherdev */
1005 tp = netdev_priv(dev);
1006
1007 /* note: tp->chipset set in rtl8139_init_board */
1008 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1009 tp->mmio_addr = ioaddr;
1010 tp->msg_enable =
1011 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1012 spin_lock_init (&tp->lock);
1013 spin_lock_init (&tp->rx_lock);
1014 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1015 tp->mii.dev = dev;
1016 tp->mii.mdio_read = mdio_read;
1017 tp->mii.mdio_write = mdio_write;
1018 tp->mii.phy_id_mask = 0x3f;
1019 tp->mii.reg_num_mask = 0x1f;
1020
1021 /* dev is fully set up and ready to use now */
1022 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1023 i = register_netdev (dev);
1024 if (i) goto err_out;
1025
1026 pci_set_drvdata (pdev, dev);
1027
1028 printk (KERN_INFO "%s: %s at 0x%lx, "
1029 "%pM, IRQ %d\n",
1030 dev->name,
1031 board_info[ent->driver_data].name,
1032 dev->base_addr,
1033 dev->dev_addr,
1034 dev->irq);
1035
1036 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1037 dev->name, rtl_chip_info[tp->chipset].name);
1038
1039 /* Find the connected MII xcvrs.
1040 Doing this in open() would allow detecting external xcvrs later, but
1041 takes too much time. */
1042 #ifdef CONFIG_8139TOO_8129
1043 if (tp->drv_flags & HAS_MII_XCVR) {
1044 int phy, phy_idx = 0;
1045 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1046 int mii_status = mdio_read(dev, phy, 1);
1047 if (mii_status != 0xffff && mii_status != 0x0000) {
1048 u16 advertising = mdio_read(dev, phy, 4);
1049 tp->phys[phy_idx++] = phy;
1050 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1051 "advertising %4.4x.\n",
1052 dev->name, phy, mii_status, advertising);
1053 }
1054 }
1055 if (phy_idx == 0) {
1056 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1057 "transceiver.\n",
1058 dev->name);
1059 tp->phys[0] = 32;
1060 }
1061 } else
1062 #endif
1063 tp->phys[0] = 32;
1064 tp->mii.phy_id = tp->phys[0];
1065
1066 /* The lower four bits are the media type. */
1067 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1068 if (option > 0) {
1069 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1070 tp->default_port = option & 0xFF;
1071 if (tp->default_port)
1072 tp->mii.force_media = 1;
1073 }
1074 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1075 tp->mii.full_duplex = full_duplex[board_idx];
1076 if (tp->mii.full_duplex) {
1077 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1078 /* Changing the MII-advertised media because might prevent
1079 re-connection. */
1080 tp->mii.force_media = 1;
1081 }
1082 if (tp->default_port) {
1083 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1084 (option & 0x20 ? 100 : 10),
1085 (option & 0x10 ? "full" : "half"));
1086 mdio_write(dev, tp->phys[0], 0,
1087 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1088 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1089 }
1090
1091 /* Put the chip into low-power mode. */
1092 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1093 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1094
1095 return 0;
1096
1097 err_out:
1098 __rtl8139_cleanup_dev (dev);
1099 pci_disable_device (pdev);
1100 return i;
1101 }
1102
1103
1104 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1105 {
1106 struct net_device *dev = pci_get_drvdata (pdev);
1107
1108 assert (dev != NULL);
1109
1110 flush_scheduled_work();
1111
1112 unregister_netdev (dev);
1113
1114 __rtl8139_cleanup_dev (dev);
1115 pci_disable_device (pdev);
1116 }
1117
1118
1119 /* Serial EEPROM section. */
1120
1121 /* EEPROM_Ctrl bits. */
1122 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1123 #define EE_CS 0x08 /* EEPROM chip select. */
1124 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1125 #define EE_WRITE_0 0x00
1126 #define EE_WRITE_1 0x02
1127 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1128 #define EE_ENB (0x80 | EE_CS)
1129
1130 /* Delay between EEPROM clock transitions.
1131 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1132 */
1133
1134 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1135
1136 /* The EEPROM commands include the alway-set leading bit. */
1137 #define EE_WRITE_CMD (5)
1138 #define EE_READ_CMD (6)
1139 #define EE_ERASE_CMD (7)
1140
1141 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1142 {
1143 int i;
1144 unsigned retval = 0;
1145 int read_cmd = location | (EE_READ_CMD << addr_len);
1146
1147 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1148 RTL_W8 (Cfg9346, EE_ENB);
1149 eeprom_delay ();
1150
1151 /* Shift the read command bits out. */
1152 for (i = 4 + addr_len; i >= 0; i--) {
1153 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1154 RTL_W8 (Cfg9346, EE_ENB | dataval);
1155 eeprom_delay ();
1156 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1157 eeprom_delay ();
1158 }
1159 RTL_W8 (Cfg9346, EE_ENB);
1160 eeprom_delay ();
1161
1162 for (i = 16; i > 0; i--) {
1163 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1164 eeprom_delay ();
1165 retval =
1166 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1167 0);
1168 RTL_W8 (Cfg9346, EE_ENB);
1169 eeprom_delay ();
1170 }
1171
1172 /* Terminate the EEPROM access. */
1173 RTL_W8 (Cfg9346, ~EE_CS);
1174 eeprom_delay ();
1175
1176 return retval;
1177 }
1178
1179 /* MII serial management: mostly bogus for now. */
1180 /* Read and write the MII management registers using software-generated
1181 serial MDIO protocol.
1182 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1183 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1184 "overclocking" issues. */
1185 #define MDIO_DIR 0x80
1186 #define MDIO_DATA_OUT 0x04
1187 #define MDIO_DATA_IN 0x02
1188 #define MDIO_CLK 0x01
1189 #define MDIO_WRITE0 (MDIO_DIR)
1190 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1191
1192 #define mdio_delay() RTL_R8(Config4)
1193
1194
1195 static const char mii_2_8139_map[8] = {
1196 BasicModeCtrl,
1197 BasicModeStatus,
1198 0,
1199 0,
1200 NWayAdvert,
1201 NWayLPAR,
1202 NWayExpansion,
1203 0
1204 };
1205
1206
1207 #ifdef CONFIG_8139TOO_8129
1208 /* Syncronize the MII management interface by shifting 32 one bits out. */
1209 static void mdio_sync (void __iomem *ioaddr)
1210 {
1211 int i;
1212
1213 for (i = 32; i >= 0; i--) {
1214 RTL_W8 (Config4, MDIO_WRITE1);
1215 mdio_delay ();
1216 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1217 mdio_delay ();
1218 }
1219 }
1220 #endif
1221
1222 static int mdio_read (struct net_device *dev, int phy_id, int location)
1223 {
1224 struct rtl8139_private *tp = netdev_priv(dev);
1225 int retval = 0;
1226 #ifdef CONFIG_8139TOO_8129
1227 void __iomem *ioaddr = tp->mmio_addr;
1228 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1229 int i;
1230 #endif
1231
1232 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1233 void __iomem *ioaddr = tp->mmio_addr;
1234 return location < 8 && mii_2_8139_map[location] ?
1235 RTL_R16 (mii_2_8139_map[location]) : 0;
1236 }
1237
1238 #ifdef CONFIG_8139TOO_8129
1239 mdio_sync (ioaddr);
1240 /* Shift the read command bits out. */
1241 for (i = 15; i >= 0; i--) {
1242 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1243
1244 RTL_W8 (Config4, MDIO_DIR | dataval);
1245 mdio_delay ();
1246 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1247 mdio_delay ();
1248 }
1249
1250 /* Read the two transition, 16 data, and wire-idle bits. */
1251 for (i = 19; i > 0; i--) {
1252 RTL_W8 (Config4, 0);
1253 mdio_delay ();
1254 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1255 RTL_W8 (Config4, MDIO_CLK);
1256 mdio_delay ();
1257 }
1258 #endif
1259
1260 return (retval >> 1) & 0xffff;
1261 }
1262
1263
1264 static void mdio_write (struct net_device *dev, int phy_id, int location,
1265 int value)
1266 {
1267 struct rtl8139_private *tp = netdev_priv(dev);
1268 #ifdef CONFIG_8139TOO_8129
1269 void __iomem *ioaddr = tp->mmio_addr;
1270 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1271 int i;
1272 #endif
1273
1274 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1275 void __iomem *ioaddr = tp->mmio_addr;
1276 if (location == 0) {
1277 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1278 RTL_W16 (BasicModeCtrl, value);
1279 RTL_W8 (Cfg9346, Cfg9346_Lock);
1280 } else if (location < 8 && mii_2_8139_map[location])
1281 RTL_W16 (mii_2_8139_map[location], value);
1282 return;
1283 }
1284
1285 #ifdef CONFIG_8139TOO_8129
1286 mdio_sync (ioaddr);
1287
1288 /* Shift the command bits out. */
1289 for (i = 31; i >= 0; i--) {
1290 int dataval =
1291 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1292 RTL_W8 (Config4, dataval);
1293 mdio_delay ();
1294 RTL_W8 (Config4, dataval | MDIO_CLK);
1295 mdio_delay ();
1296 }
1297 /* Clear out extra bits. */
1298 for (i = 2; i > 0; i--) {
1299 RTL_W8 (Config4, 0);
1300 mdio_delay ();
1301 RTL_W8 (Config4, MDIO_CLK);
1302 mdio_delay ();
1303 }
1304 #endif
1305 }
1306
1307
1308 static int rtl8139_open (struct net_device *dev)
1309 {
1310 struct rtl8139_private *tp = netdev_priv(dev);
1311 int retval;
1312 void __iomem *ioaddr = tp->mmio_addr;
1313
1314 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1315 if (retval)
1316 return retval;
1317
1318 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1319 &tp->tx_bufs_dma, GFP_KERNEL);
1320 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1321 &tp->rx_ring_dma, GFP_KERNEL);
1322 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1323 free_irq(dev->irq, dev);
1324
1325 if (tp->tx_bufs)
1326 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1327 tp->tx_bufs, tp->tx_bufs_dma);
1328 if (tp->rx_ring)
1329 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1330 tp->rx_ring, tp->rx_ring_dma);
1331
1332 return -ENOMEM;
1333
1334 }
1335
1336 napi_enable(&tp->napi);
1337
1338 tp->mii.full_duplex = tp->mii.force_media;
1339 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1340
1341 rtl8139_init_ring (dev);
1342 rtl8139_hw_start (dev);
1343 netif_start_queue (dev);
1344
1345 if (netif_msg_ifup(tp))
1346 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#llx IRQ %d"
1347 " GP Pins %2.2x %s-duplex.\n", dev->name,
1348 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1349 dev->irq, RTL_R8 (MediaStatus),
1350 tp->mii.full_duplex ? "full" : "half");
1351
1352 rtl8139_start_thread(tp);
1353
1354 return 0;
1355 }
1356
1357
1358 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1359 {
1360 struct rtl8139_private *tp = netdev_priv(dev);
1361
1362 if (tp->phys[0] >= 0) {
1363 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1364 }
1365 }
1366
1367 /* Start the hardware at open or resume. */
1368 static void rtl8139_hw_start (struct net_device *dev)
1369 {
1370 struct rtl8139_private *tp = netdev_priv(dev);
1371 void __iomem *ioaddr = tp->mmio_addr;
1372 u32 i;
1373 u8 tmp;
1374
1375 /* Bring old chips out of low-power mode. */
1376 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1377 RTL_W8 (HltClk, 'R');
1378
1379 rtl8139_chip_reset (ioaddr);
1380
1381 /* unlock Config[01234] and BMCR register writes */
1382 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1383 /* Restore our idea of the MAC address. */
1384 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1385 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1386
1387 tp->cur_rx = 0;
1388
1389 /* init Rx ring buffer DMA address */
1390 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1391
1392 /* Must enable Tx/Rx before setting transfer thresholds! */
1393 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1394
1395 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1396 RTL_W32 (RxConfig, tp->rx_config);
1397 RTL_W32 (TxConfig, rtl8139_tx_config);
1398
1399 rtl_check_media (dev, 1);
1400
1401 if (tp->chipset >= CH_8139B) {
1402 /* Disable magic packet scanning, which is enabled
1403 * when PM is enabled in Config1. It can be reenabled
1404 * via ETHTOOL_SWOL if desired. */
1405 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1406 }
1407
1408 DPRINTK("init buffer addresses\n");
1409
1410 /* Lock Config[01234] and BMCR register writes */
1411 RTL_W8 (Cfg9346, Cfg9346_Lock);
1412
1413 /* init Tx buffer DMA addresses */
1414 for (i = 0; i < NUM_TX_DESC; i++)
1415 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1416
1417 RTL_W32 (RxMissed, 0);
1418
1419 rtl8139_set_rx_mode (dev);
1420
1421 /* no early-rx interrupts */
1422 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1423
1424 /* make sure RxTx has started */
1425 tmp = RTL_R8 (ChipCmd);
1426 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1427 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1428
1429 /* Enable all known interrupts by setting the interrupt mask. */
1430 RTL_W16 (IntrMask, rtl8139_intr_mask);
1431 }
1432
1433
1434 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1435 static void rtl8139_init_ring (struct net_device *dev)
1436 {
1437 struct rtl8139_private *tp = netdev_priv(dev);
1438 int i;
1439
1440 tp->cur_rx = 0;
1441 tp->cur_tx = 0;
1442 tp->dirty_tx = 0;
1443
1444 for (i = 0; i < NUM_TX_DESC; i++)
1445 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1446 }
1447
1448
1449 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1450 static int next_tick = 3 * HZ;
1451
1452 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1453 static inline void rtl8139_tune_twister (struct net_device *dev,
1454 struct rtl8139_private *tp) {}
1455 #else
1456 enum TwisterParamVals {
1457 PARA78_default = 0x78fa8388,
1458 PARA7c_default = 0xcb38de43, /* param[0][3] */
1459 PARA7c_xxx = 0xcb38de43,
1460 };
1461
1462 static const unsigned long param[4][4] = {
1463 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1464 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1465 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1466 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1467 };
1468
1469 static void rtl8139_tune_twister (struct net_device *dev,
1470 struct rtl8139_private *tp)
1471 {
1472 int linkcase;
1473 void __iomem *ioaddr = tp->mmio_addr;
1474
1475 /* This is a complicated state machine to configure the "twister" for
1476 impedance/echos based on the cable length.
1477 All of this is magic and undocumented.
1478 */
1479 switch (tp->twistie) {
1480 case 1:
1481 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1482 /* We have link beat, let us tune the twister. */
1483 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1484 tp->twistie = 2; /* Change to state 2. */
1485 next_tick = HZ / 10;
1486 } else {
1487 /* Just put in some reasonable defaults for when beat returns. */
1488 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1489 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1490 RTL_W32 (PARA78, PARA78_default);
1491 RTL_W32 (PARA7c, PARA7c_default);
1492 tp->twistie = 0; /* Bail from future actions. */
1493 }
1494 break;
1495 case 2:
1496 /* Read how long it took to hear the echo. */
1497 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1498 if (linkcase == 0x7000)
1499 tp->twist_row = 3;
1500 else if (linkcase == 0x3000)
1501 tp->twist_row = 2;
1502 else if (linkcase == 0x1000)
1503 tp->twist_row = 1;
1504 else
1505 tp->twist_row = 0;
1506 tp->twist_col = 0;
1507 tp->twistie = 3; /* Change to state 2. */
1508 next_tick = HZ / 10;
1509 break;
1510 case 3:
1511 /* Put out four tuning parameters, one per 100msec. */
1512 if (tp->twist_col == 0)
1513 RTL_W16 (FIFOTMS, 0);
1514 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1515 [(int) tp->twist_col]);
1516 next_tick = HZ / 10;
1517 if (++tp->twist_col >= 4) {
1518 /* For short cables we are done.
1519 For long cables (row == 3) check for mistune. */
1520 tp->twistie =
1521 (tp->twist_row == 3) ? 4 : 0;
1522 }
1523 break;
1524 case 4:
1525 /* Special case for long cables: check for mistune. */
1526 if ((RTL_R16 (CSCR) &
1527 CSCR_LinkStatusBits) == 0x7000) {
1528 tp->twistie = 0;
1529 break;
1530 } else {
1531 RTL_W32 (PARA7c, 0xfb38de03);
1532 tp->twistie = 5;
1533 next_tick = HZ / 10;
1534 }
1535 break;
1536 case 5:
1537 /* Retune for shorter cable (column 2). */
1538 RTL_W32 (FIFOTMS, 0x20);
1539 RTL_W32 (PARA78, PARA78_default);
1540 RTL_W32 (PARA7c, PARA7c_default);
1541 RTL_W32 (FIFOTMS, 0x00);
1542 tp->twist_row = 2;
1543 tp->twist_col = 0;
1544 tp->twistie = 3;
1545 next_tick = HZ / 10;
1546 break;
1547
1548 default:
1549 /* do nothing */
1550 break;
1551 }
1552 }
1553 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1554
1555 static inline void rtl8139_thread_iter (struct net_device *dev,
1556 struct rtl8139_private *tp,
1557 void __iomem *ioaddr)
1558 {
1559 int mii_lpa;
1560
1561 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1562
1563 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1564 int duplex = (mii_lpa & LPA_100FULL)
1565 || (mii_lpa & 0x01C0) == 0x0040;
1566 if (tp->mii.full_duplex != duplex) {
1567 tp->mii.full_duplex = duplex;
1568
1569 if (mii_lpa) {
1570 printk (KERN_INFO
1571 "%s: Setting %s-duplex based on MII #%d link"
1572 " partner ability of %4.4x.\n",
1573 dev->name,
1574 tp->mii.full_duplex ? "full" : "half",
1575 tp->phys[0], mii_lpa);
1576 } else {
1577 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1578 dev->name);
1579 }
1580 #if 0
1581 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1582 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1583 RTL_W8 (Cfg9346, Cfg9346_Lock);
1584 #endif
1585 }
1586 }
1587
1588 next_tick = HZ * 60;
1589
1590 rtl8139_tune_twister (dev, tp);
1591
1592 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1593 dev->name, RTL_R16 (NWayLPAR));
1594 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1595 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1596 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1597 dev->name, RTL_R8 (Config0),
1598 RTL_R8 (Config1));
1599 }
1600
1601 static void rtl8139_thread (struct work_struct *work)
1602 {
1603 struct rtl8139_private *tp =
1604 container_of(work, struct rtl8139_private, thread.work);
1605 struct net_device *dev = tp->mii.dev;
1606 unsigned long thr_delay = next_tick;
1607
1608 rtnl_lock();
1609
1610 if (!netif_running(dev))
1611 goto out_unlock;
1612
1613 if (tp->watchdog_fired) {
1614 tp->watchdog_fired = 0;
1615 rtl8139_tx_timeout_task(work);
1616 } else
1617 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1618
1619 if (tp->have_thread)
1620 schedule_delayed_work(&tp->thread, thr_delay);
1621 out_unlock:
1622 rtnl_unlock ();
1623 }
1624
1625 static void rtl8139_start_thread(struct rtl8139_private *tp)
1626 {
1627 tp->twistie = 0;
1628 if (tp->chipset == CH_8139_K)
1629 tp->twistie = 1;
1630 else if (tp->drv_flags & HAS_LNK_CHNG)
1631 return;
1632
1633 tp->have_thread = 1;
1634 tp->watchdog_fired = 0;
1635
1636 schedule_delayed_work(&tp->thread, next_tick);
1637 }
1638
1639 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1640 {
1641 tp->cur_tx = 0;
1642 tp->dirty_tx = 0;
1643
1644 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1645 }
1646
1647 static void rtl8139_tx_timeout_task (struct work_struct *work)
1648 {
1649 struct rtl8139_private *tp =
1650 container_of(work, struct rtl8139_private, thread.work);
1651 struct net_device *dev = tp->mii.dev;
1652 void __iomem *ioaddr = tp->mmio_addr;
1653 int i;
1654 u8 tmp8;
1655
1656 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1657 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1658 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1659 /* Emit info to figure out what went wrong. */
1660 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1661 dev->name, tp->cur_tx, tp->dirty_tx);
1662 for (i = 0; i < NUM_TX_DESC; i++)
1663 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1664 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1665 i == tp->dirty_tx % NUM_TX_DESC ?
1666 " (queue head)" : "");
1667
1668 tp->xstats.tx_timeouts++;
1669
1670 /* disable Tx ASAP, if not already */
1671 tmp8 = RTL_R8 (ChipCmd);
1672 if (tmp8 & CmdTxEnb)
1673 RTL_W8 (ChipCmd, CmdRxEnb);
1674
1675 spin_lock_bh(&tp->rx_lock);
1676 /* Disable interrupts by clearing the interrupt mask. */
1677 RTL_W16 (IntrMask, 0x0000);
1678
1679 /* Stop a shared interrupt from scavenging while we are. */
1680 spin_lock_irq(&tp->lock);
1681 rtl8139_tx_clear (tp);
1682 spin_unlock_irq(&tp->lock);
1683
1684 /* ...and finally, reset everything */
1685 if (netif_running(dev)) {
1686 rtl8139_hw_start (dev);
1687 netif_wake_queue (dev);
1688 }
1689 spin_unlock_bh(&tp->rx_lock);
1690 }
1691
1692 static void rtl8139_tx_timeout (struct net_device *dev)
1693 {
1694 struct rtl8139_private *tp = netdev_priv(dev);
1695
1696 tp->watchdog_fired = 1;
1697 if (!tp->have_thread) {
1698 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1699 schedule_delayed_work(&tp->thread, next_tick);
1700 }
1701 }
1702
1703 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1704 {
1705 struct rtl8139_private *tp = netdev_priv(dev);
1706 void __iomem *ioaddr = tp->mmio_addr;
1707 unsigned int entry;
1708 unsigned int len = skb->len;
1709 unsigned long flags;
1710
1711 /* Calculate the next Tx descriptor entry. */
1712 entry = tp->cur_tx % NUM_TX_DESC;
1713
1714 /* Note: the chip doesn't have auto-pad! */
1715 if (likely(len < TX_BUF_SIZE)) {
1716 if (len < ETH_ZLEN)
1717 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1718 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1719 dev_kfree_skb(skb);
1720 } else {
1721 dev_kfree_skb(skb);
1722 dev->stats.tx_dropped++;
1723 return 0;
1724 }
1725
1726 spin_lock_irqsave(&tp->lock, flags);
1727 /*
1728 * Writing to TxStatus triggers a DMA transfer of the data
1729 * copied to tp->tx_buf[entry] above. Use a memory barrier
1730 * to make sure that the device sees the updated data.
1731 */
1732 wmb();
1733 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1734 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1735
1736 dev->trans_start = jiffies;
1737
1738 tp->cur_tx++;
1739
1740 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1741 netif_stop_queue (dev);
1742 spin_unlock_irqrestore(&tp->lock, flags);
1743
1744 if (netif_msg_tx_queued(tp))
1745 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1746 dev->name, len, entry);
1747
1748 return 0;
1749 }
1750
1751
1752 static void rtl8139_tx_interrupt (struct net_device *dev,
1753 struct rtl8139_private *tp,
1754 void __iomem *ioaddr)
1755 {
1756 unsigned long dirty_tx, tx_left;
1757
1758 assert (dev != NULL);
1759 assert (ioaddr != NULL);
1760
1761 dirty_tx = tp->dirty_tx;
1762 tx_left = tp->cur_tx - dirty_tx;
1763 while (tx_left > 0) {
1764 int entry = dirty_tx % NUM_TX_DESC;
1765 int txstatus;
1766
1767 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1768
1769 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1770 break; /* It still hasn't been Txed */
1771
1772 /* Note: TxCarrierLost is always asserted at 100mbps. */
1773 if (txstatus & (TxOutOfWindow | TxAborted)) {
1774 /* There was an major error, log it. */
1775 if (netif_msg_tx_err(tp))
1776 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1777 dev->name, txstatus);
1778 dev->stats.tx_errors++;
1779 if (txstatus & TxAborted) {
1780 dev->stats.tx_aborted_errors++;
1781 RTL_W32 (TxConfig, TxClearAbt);
1782 RTL_W16 (IntrStatus, TxErr);
1783 wmb();
1784 }
1785 if (txstatus & TxCarrierLost)
1786 dev->stats.tx_carrier_errors++;
1787 if (txstatus & TxOutOfWindow)
1788 dev->stats.tx_window_errors++;
1789 } else {
1790 if (txstatus & TxUnderrun) {
1791 /* Add 64 to the Tx FIFO threshold. */
1792 if (tp->tx_flag < 0x00300000)
1793 tp->tx_flag += 0x00020000;
1794 dev->stats.tx_fifo_errors++;
1795 }
1796 dev->stats.collisions += (txstatus >> 24) & 15;
1797 dev->stats.tx_bytes += txstatus & 0x7ff;
1798 dev->stats.tx_packets++;
1799 }
1800
1801 dirty_tx++;
1802 tx_left--;
1803 }
1804
1805 #ifndef RTL8139_NDEBUG
1806 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1807 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1808 dev->name, dirty_tx, tp->cur_tx);
1809 dirty_tx += NUM_TX_DESC;
1810 }
1811 #endif /* RTL8139_NDEBUG */
1812
1813 /* only wake the queue if we did work, and the queue is stopped */
1814 if (tp->dirty_tx != dirty_tx) {
1815 tp->dirty_tx = dirty_tx;
1816 mb();
1817 netif_wake_queue (dev);
1818 }
1819 }
1820
1821
1822 /* TODO: clean this up! Rx reset need not be this intensive */
1823 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1824 struct rtl8139_private *tp, void __iomem *ioaddr)
1825 {
1826 u8 tmp8;
1827 #ifdef CONFIG_8139_OLD_RX_RESET
1828 int tmp_work;
1829 #endif
1830
1831 if (netif_msg_rx_err (tp))
1832 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1833 dev->name, rx_status);
1834 dev->stats.rx_errors++;
1835 if (!(rx_status & RxStatusOK)) {
1836 if (rx_status & RxTooLong) {
1837 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1838 dev->name, rx_status);
1839 /* A.C.: The chip hangs here. */
1840 }
1841 if (rx_status & (RxBadSymbol | RxBadAlign))
1842 dev->stats.rx_frame_errors++;
1843 if (rx_status & (RxRunt | RxTooLong))
1844 dev->stats.rx_length_errors++;
1845 if (rx_status & RxCRCErr)
1846 dev->stats.rx_crc_errors++;
1847 } else {
1848 tp->xstats.rx_lost_in_ring++;
1849 }
1850
1851 #ifndef CONFIG_8139_OLD_RX_RESET
1852 tmp8 = RTL_R8 (ChipCmd);
1853 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1854 RTL_W8 (ChipCmd, tmp8);
1855 RTL_W32 (RxConfig, tp->rx_config);
1856 tp->cur_rx = 0;
1857 #else
1858 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1859
1860 /* disable receive */
1861 RTL_W8_F (ChipCmd, CmdTxEnb);
1862 tmp_work = 200;
1863 while (--tmp_work > 0) {
1864 udelay(1);
1865 tmp8 = RTL_R8 (ChipCmd);
1866 if (!(tmp8 & CmdRxEnb))
1867 break;
1868 }
1869 if (tmp_work <= 0)
1870 printk (KERN_WARNING PFX "rx stop wait too long\n");
1871 /* restart receive */
1872 tmp_work = 200;
1873 while (--tmp_work > 0) {
1874 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1875 udelay(1);
1876 tmp8 = RTL_R8 (ChipCmd);
1877 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1878 break;
1879 }
1880 if (tmp_work <= 0)
1881 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1882
1883 /* and reinitialize all rx related registers */
1884 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1885 /* Must enable Tx/Rx before setting transfer thresholds! */
1886 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1887
1888 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1889 RTL_W32 (RxConfig, tp->rx_config);
1890 tp->cur_rx = 0;
1891
1892 DPRINTK("init buffer addresses\n");
1893
1894 /* Lock Config[01234] and BMCR register writes */
1895 RTL_W8 (Cfg9346, Cfg9346_Lock);
1896
1897 /* init Rx ring buffer DMA address */
1898 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1899
1900 /* A.C.: Reset the multicast list. */
1901 __set_rx_mode (dev);
1902 #endif
1903 }
1904
1905 #if RX_BUF_IDX == 3
1906 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1907 u32 offset, unsigned int size)
1908 {
1909 u32 left = RX_BUF_LEN - offset;
1910
1911 if (size > left) {
1912 skb_copy_to_linear_data(skb, ring + offset, left);
1913 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1914 } else
1915 skb_copy_to_linear_data(skb, ring + offset, size);
1916 }
1917 #endif
1918
1919 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1920 {
1921 void __iomem *ioaddr = tp->mmio_addr;
1922 u16 status;
1923
1924 status = RTL_R16 (IntrStatus) & RxAckBits;
1925
1926 /* Clear out errors and receive interrupts */
1927 if (likely(status != 0)) {
1928 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1929 tp->dev->stats.rx_errors++;
1930 if (status & RxFIFOOver)
1931 tp->dev->stats.rx_fifo_errors++;
1932 }
1933 RTL_W16_F (IntrStatus, RxAckBits);
1934 }
1935 }
1936
1937 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1938 int budget)
1939 {
1940 void __iomem *ioaddr = tp->mmio_addr;
1941 int received = 0;
1942 unsigned char *rx_ring = tp->rx_ring;
1943 unsigned int cur_rx = tp->cur_rx;
1944 unsigned int rx_size = 0;
1945
1946 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1947 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1948 RTL_R16 (RxBufAddr),
1949 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1950
1951 while (netif_running(dev) && received < budget
1952 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1953 u32 ring_offset = cur_rx % RX_BUF_LEN;
1954 u32 rx_status;
1955 unsigned int pkt_size;
1956 struct sk_buff *skb;
1957
1958 rmb();
1959
1960 /* read size+status of next frame from DMA ring buffer */
1961 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1962 rx_size = rx_status >> 16;
1963 pkt_size = rx_size - 4;
1964
1965 if (netif_msg_rx_status(tp))
1966 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1967 " cur %4.4x.\n", dev->name, rx_status,
1968 rx_size, cur_rx);
1969 #if RTL8139_DEBUG > 2
1970 {
1971 int i;
1972 DPRINTK ("%s: Frame contents ", dev->name);
1973 for (i = 0; i < 70; i++)
1974 printk (" %2.2x",
1975 rx_ring[ring_offset + i]);
1976 printk (".\n");
1977 }
1978 #endif
1979
1980 /* Packet copy from FIFO still in progress.
1981 * Theoretically, this should never happen
1982 * since EarlyRx is disabled.
1983 */
1984 if (unlikely(rx_size == 0xfff0)) {
1985 if (!tp->fifo_copy_timeout)
1986 tp->fifo_copy_timeout = jiffies + 2;
1987 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1988 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
1989 rx_size = 0;
1990 goto no_early_rx;
1991 }
1992 if (netif_msg_intr(tp)) {
1993 printk(KERN_DEBUG "%s: fifo copy in progress.",
1994 dev->name);
1995 }
1996 tp->xstats.early_rx++;
1997 break;
1998 }
1999
2000 no_early_rx:
2001 tp->fifo_copy_timeout = 0;
2002
2003 /* If Rx err or invalid rx_size/rx_status received
2004 * (which happens if we get lost in the ring),
2005 * Rx process gets reset, so we abort any further
2006 * Rx processing.
2007 */
2008 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2009 (rx_size < 8) ||
2010 (!(rx_status & RxStatusOK)))) {
2011 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2012 received = -1;
2013 goto out;
2014 }
2015
2016 /* Malloc up new buffer, compatible with net-2e. */
2017 /* Omit the four octet CRC from the length. */
2018
2019 skb = netdev_alloc_skb(dev, pkt_size + NET_IP_ALIGN);
2020 if (likely(skb)) {
2021 skb_reserve (skb, NET_IP_ALIGN); /* 16 byte align the IP fields. */
2022 #if RX_BUF_IDX == 3
2023 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2024 #else
2025 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2026 #endif
2027 skb_put (skb, pkt_size);
2028
2029 skb->protocol = eth_type_trans (skb, dev);
2030
2031 dev->stats.rx_bytes += pkt_size;
2032 dev->stats.rx_packets++;
2033
2034 netif_receive_skb (skb);
2035 } else {
2036 if (net_ratelimit())
2037 printk (KERN_WARNING
2038 "%s: Memory squeeze, dropping packet.\n",
2039 dev->name);
2040 dev->stats.rx_dropped++;
2041 }
2042 received++;
2043
2044 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2045 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2046
2047 rtl8139_isr_ack(tp);
2048 }
2049
2050 if (unlikely(!received || rx_size == 0xfff0))
2051 rtl8139_isr_ack(tp);
2052
2053 #if RTL8139_DEBUG > 1
2054 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2055 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2056 RTL_R16 (RxBufAddr),
2057 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2058 #endif
2059
2060 tp->cur_rx = cur_rx;
2061
2062 /*
2063 * The receive buffer should be mostly empty.
2064 * Tell NAPI to reenable the Rx irq.
2065 */
2066 if (tp->fifo_copy_timeout)
2067 received = budget;
2068
2069 out:
2070 return received;
2071 }
2072
2073
2074 static void rtl8139_weird_interrupt (struct net_device *dev,
2075 struct rtl8139_private *tp,
2076 void __iomem *ioaddr,
2077 int status, int link_changed)
2078 {
2079 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2080 dev->name, status);
2081
2082 assert (dev != NULL);
2083 assert (tp != NULL);
2084 assert (ioaddr != NULL);
2085
2086 /* Update the error count. */
2087 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2088 RTL_W32 (RxMissed, 0);
2089
2090 if ((status & RxUnderrun) && link_changed &&
2091 (tp->drv_flags & HAS_LNK_CHNG)) {
2092 rtl_check_media(dev, 0);
2093 status &= ~RxUnderrun;
2094 }
2095
2096 if (status & (RxUnderrun | RxErr))
2097 dev->stats.rx_errors++;
2098
2099 if (status & PCSTimeout)
2100 dev->stats.rx_length_errors++;
2101 if (status & RxUnderrun)
2102 dev->stats.rx_fifo_errors++;
2103 if (status & PCIErr) {
2104 u16 pci_cmd_status;
2105 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2106 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2107
2108 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2109 dev->name, pci_cmd_status);
2110 }
2111 }
2112
2113 static int rtl8139_poll(struct napi_struct *napi, int budget)
2114 {
2115 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2116 struct net_device *dev = tp->dev;
2117 void __iomem *ioaddr = tp->mmio_addr;
2118 int work_done;
2119
2120 spin_lock(&tp->rx_lock);
2121 work_done = 0;
2122 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2123 work_done += rtl8139_rx(dev, tp, budget);
2124
2125 if (work_done < budget) {
2126 unsigned long flags;
2127 /*
2128 * Order is important since data can get interrupted
2129 * again when we think we are done.
2130 */
2131 spin_lock_irqsave(&tp->lock, flags);
2132 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2133 __napi_complete(napi);
2134 spin_unlock_irqrestore(&tp->lock, flags);
2135 }
2136 spin_unlock(&tp->rx_lock);
2137
2138 return work_done;
2139 }
2140
2141 /* The interrupt handler does all of the Rx thread work and cleans up
2142 after the Tx thread. */
2143 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2144 {
2145 struct net_device *dev = (struct net_device *) dev_instance;
2146 struct rtl8139_private *tp = netdev_priv(dev);
2147 void __iomem *ioaddr = tp->mmio_addr;
2148 u16 status, ackstat;
2149 int link_changed = 0; /* avoid bogus "uninit" warning */
2150 int handled = 0;
2151
2152 spin_lock (&tp->lock);
2153 status = RTL_R16 (IntrStatus);
2154
2155 /* shared irq? */
2156 if (unlikely((status & rtl8139_intr_mask) == 0))
2157 goto out;
2158
2159 handled = 1;
2160
2161 /* h/w no longer present (hotplug?) or major error, bail */
2162 if (unlikely(status == 0xFFFF))
2163 goto out;
2164
2165 /* close possible race's with dev_close */
2166 if (unlikely(!netif_running(dev))) {
2167 RTL_W16 (IntrMask, 0);
2168 goto out;
2169 }
2170
2171 /* Acknowledge all of the current interrupt sources ASAP, but
2172 an first get an additional status bit from CSCR. */
2173 if (unlikely(status & RxUnderrun))
2174 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2175
2176 ackstat = status & ~(RxAckBits | TxErr);
2177 if (ackstat)
2178 RTL_W16 (IntrStatus, ackstat);
2179
2180 /* Receive packets are processed by poll routine.
2181 If not running start it now. */
2182 if (status & RxAckBits){
2183 if (napi_schedule_prep(&tp->napi)) {
2184 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2185 __napi_schedule(&tp->napi);
2186 }
2187 }
2188
2189 /* Check uncommon events with one test. */
2190 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2191 rtl8139_weird_interrupt (dev, tp, ioaddr,
2192 status, link_changed);
2193
2194 if (status & (TxOK | TxErr)) {
2195 rtl8139_tx_interrupt (dev, tp, ioaddr);
2196 if (status & TxErr)
2197 RTL_W16 (IntrStatus, TxErr);
2198 }
2199 out:
2200 spin_unlock (&tp->lock);
2201
2202 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2203 dev->name, RTL_R16 (IntrStatus));
2204 return IRQ_RETVAL(handled);
2205 }
2206
2207 #ifdef CONFIG_NET_POLL_CONTROLLER
2208 /*
2209 * Polling receive - used by netconsole and other diagnostic tools
2210 * to allow network i/o with interrupts disabled.
2211 */
2212 static void rtl8139_poll_controller(struct net_device *dev)
2213 {
2214 disable_irq(dev->irq);
2215 rtl8139_interrupt(dev->irq, dev);
2216 enable_irq(dev->irq);
2217 }
2218 #endif
2219
2220 static int rtl8139_set_mac_address(struct net_device *dev, void *p)
2221 {
2222 struct rtl8139_private *tp = netdev_priv(dev);
2223 void __iomem *ioaddr = tp->mmio_addr;
2224 struct sockaddr *addr = p;
2225
2226 if (!is_valid_ether_addr(addr->sa_data))
2227 return -EADDRNOTAVAIL;
2228
2229 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2230
2231 spin_lock_irq(&tp->lock);
2232
2233 RTL_W8_F(Cfg9346, Cfg9346_Unlock);
2234 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
2235 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
2236 RTL_W8_F(Cfg9346, Cfg9346_Lock);
2237
2238 spin_unlock_irq(&tp->lock);
2239
2240 return 0;
2241 }
2242
2243 static int rtl8139_close (struct net_device *dev)
2244 {
2245 struct rtl8139_private *tp = netdev_priv(dev);
2246 void __iomem *ioaddr = tp->mmio_addr;
2247 unsigned long flags;
2248
2249 netif_stop_queue(dev);
2250 napi_disable(&tp->napi);
2251
2252 if (netif_msg_ifdown(tp))
2253 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2254 dev->name, RTL_R16 (IntrStatus));
2255
2256 spin_lock_irqsave (&tp->lock, flags);
2257
2258 /* Stop the chip's Tx and Rx DMA processes. */
2259 RTL_W8 (ChipCmd, 0);
2260
2261 /* Disable interrupts by clearing the interrupt mask. */
2262 RTL_W16 (IntrMask, 0);
2263
2264 /* Update the error counts. */
2265 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2266 RTL_W32 (RxMissed, 0);
2267
2268 spin_unlock_irqrestore (&tp->lock, flags);
2269
2270 free_irq (dev->irq, dev);
2271
2272 rtl8139_tx_clear (tp);
2273
2274 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2275 tp->rx_ring, tp->rx_ring_dma);
2276 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2277 tp->tx_bufs, tp->tx_bufs_dma);
2278 tp->rx_ring = NULL;
2279 tp->tx_bufs = NULL;
2280
2281 /* Green! Put the chip in low-power mode. */
2282 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2283
2284 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2285 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2286
2287 return 0;
2288 }
2289
2290
2291 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2292 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2293 other threads or interrupts aren't messing with the 8139. */
2294 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2295 {
2296 struct rtl8139_private *np = netdev_priv(dev);
2297 void __iomem *ioaddr = np->mmio_addr;
2298
2299 spin_lock_irq(&np->lock);
2300 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2301 u8 cfg3 = RTL_R8 (Config3);
2302 u8 cfg5 = RTL_R8 (Config5);
2303
2304 wol->supported = WAKE_PHY | WAKE_MAGIC
2305 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2306
2307 wol->wolopts = 0;
2308 if (cfg3 & Cfg3_LinkUp)
2309 wol->wolopts |= WAKE_PHY;
2310 if (cfg3 & Cfg3_Magic)
2311 wol->wolopts |= WAKE_MAGIC;
2312 /* (KON)FIXME: See how netdev_set_wol() handles the
2313 following constants. */
2314 if (cfg5 & Cfg5_UWF)
2315 wol->wolopts |= WAKE_UCAST;
2316 if (cfg5 & Cfg5_MWF)
2317 wol->wolopts |= WAKE_MCAST;
2318 if (cfg5 & Cfg5_BWF)
2319 wol->wolopts |= WAKE_BCAST;
2320 }
2321 spin_unlock_irq(&np->lock);
2322 }
2323
2324
2325 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2326 that wol points to kernel memory and other threads or interrupts
2327 aren't messing with the 8139. */
2328 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2329 {
2330 struct rtl8139_private *np = netdev_priv(dev);
2331 void __iomem *ioaddr = np->mmio_addr;
2332 u32 support;
2333 u8 cfg3, cfg5;
2334
2335 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2336 ? (WAKE_PHY | WAKE_MAGIC
2337 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2338 : 0);
2339 if (wol->wolopts & ~support)
2340 return -EINVAL;
2341
2342 spin_lock_irq(&np->lock);
2343 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2344 if (wol->wolopts & WAKE_PHY)
2345 cfg3 |= Cfg3_LinkUp;
2346 if (wol->wolopts & WAKE_MAGIC)
2347 cfg3 |= Cfg3_Magic;
2348 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2349 RTL_W8 (Config3, cfg3);
2350 RTL_W8 (Cfg9346, Cfg9346_Lock);
2351
2352 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2353 /* (KON)FIXME: These are untested. We may have to set the
2354 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2355 documentation. */
2356 if (wol->wolopts & WAKE_UCAST)
2357 cfg5 |= Cfg5_UWF;
2358 if (wol->wolopts & WAKE_MCAST)
2359 cfg5 |= Cfg5_MWF;
2360 if (wol->wolopts & WAKE_BCAST)
2361 cfg5 |= Cfg5_BWF;
2362 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2363 spin_unlock_irq(&np->lock);
2364
2365 return 0;
2366 }
2367
2368 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2369 {
2370 struct rtl8139_private *np = netdev_priv(dev);
2371 strcpy(info->driver, DRV_NAME);
2372 strcpy(info->version, DRV_VERSION);
2373 strcpy(info->bus_info, pci_name(np->pci_dev));
2374 info->regdump_len = np->regs_len;
2375 }
2376
2377 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2378 {
2379 struct rtl8139_private *np = netdev_priv(dev);
2380 spin_lock_irq(&np->lock);
2381 mii_ethtool_gset(&np->mii, cmd);
2382 spin_unlock_irq(&np->lock);
2383 return 0;
2384 }
2385
2386 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2387 {
2388 struct rtl8139_private *np = netdev_priv(dev);
2389 int rc;
2390 spin_lock_irq(&np->lock);
2391 rc = mii_ethtool_sset(&np->mii, cmd);
2392 spin_unlock_irq(&np->lock);
2393 return rc;
2394 }
2395
2396 static int rtl8139_nway_reset(struct net_device *dev)
2397 {
2398 struct rtl8139_private *np = netdev_priv(dev);
2399 return mii_nway_restart(&np->mii);
2400 }
2401
2402 static u32 rtl8139_get_link(struct net_device *dev)
2403 {
2404 struct rtl8139_private *np = netdev_priv(dev);
2405 return mii_link_ok(&np->mii);
2406 }
2407
2408 static u32 rtl8139_get_msglevel(struct net_device *dev)
2409 {
2410 struct rtl8139_private *np = netdev_priv(dev);
2411 return np->msg_enable;
2412 }
2413
2414 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2415 {
2416 struct rtl8139_private *np = netdev_priv(dev);
2417 np->msg_enable = datum;
2418 }
2419
2420 static int rtl8139_get_regs_len(struct net_device *dev)
2421 {
2422 struct rtl8139_private *np;
2423 /* TODO: we are too slack to do reg dumping for pio, for now */
2424 if (use_io)
2425 return 0;
2426 np = netdev_priv(dev);
2427 return np->regs_len;
2428 }
2429
2430 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2431 {
2432 struct rtl8139_private *np;
2433
2434 /* TODO: we are too slack to do reg dumping for pio, for now */
2435 if (use_io)
2436 return;
2437 np = netdev_priv(dev);
2438
2439 regs->version = RTL_REGS_VER;
2440
2441 spin_lock_irq(&np->lock);
2442 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2443 spin_unlock_irq(&np->lock);
2444 }
2445
2446 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2447 {
2448 switch (sset) {
2449 case ETH_SS_STATS:
2450 return RTL_NUM_STATS;
2451 default:
2452 return -EOPNOTSUPP;
2453 }
2454 }
2455
2456 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2457 {
2458 struct rtl8139_private *np = netdev_priv(dev);
2459
2460 data[0] = np->xstats.early_rx;
2461 data[1] = np->xstats.tx_buf_mapped;
2462 data[2] = np->xstats.tx_timeouts;
2463 data[3] = np->xstats.rx_lost_in_ring;
2464 }
2465
2466 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2467 {
2468 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2469 }
2470
2471 static const struct ethtool_ops rtl8139_ethtool_ops = {
2472 .get_drvinfo = rtl8139_get_drvinfo,
2473 .get_settings = rtl8139_get_settings,
2474 .set_settings = rtl8139_set_settings,
2475 .get_regs_len = rtl8139_get_regs_len,
2476 .get_regs = rtl8139_get_regs,
2477 .nway_reset = rtl8139_nway_reset,
2478 .get_link = rtl8139_get_link,
2479 .get_msglevel = rtl8139_get_msglevel,
2480 .set_msglevel = rtl8139_set_msglevel,
2481 .get_wol = rtl8139_get_wol,
2482 .set_wol = rtl8139_set_wol,
2483 .get_strings = rtl8139_get_strings,
2484 .get_sset_count = rtl8139_get_sset_count,
2485 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2486 };
2487
2488 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2489 {
2490 struct rtl8139_private *np = netdev_priv(dev);
2491 int rc;
2492
2493 if (!netif_running(dev))
2494 return -EINVAL;
2495
2496 spin_lock_irq(&np->lock);
2497 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2498 spin_unlock_irq(&np->lock);
2499
2500 return rc;
2501 }
2502
2503
2504 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2505 {
2506 struct rtl8139_private *tp = netdev_priv(dev);
2507 void __iomem *ioaddr = tp->mmio_addr;
2508 unsigned long flags;
2509
2510 if (netif_running(dev)) {
2511 spin_lock_irqsave (&tp->lock, flags);
2512 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2513 RTL_W32 (RxMissed, 0);
2514 spin_unlock_irqrestore (&tp->lock, flags);
2515 }
2516
2517 return &dev->stats;
2518 }
2519
2520 /* Set or clear the multicast filter for this adaptor.
2521 This routine is not state sensitive and need not be SMP locked. */
2522
2523 static void __set_rx_mode (struct net_device *dev)
2524 {
2525 struct rtl8139_private *tp = netdev_priv(dev);
2526 void __iomem *ioaddr = tp->mmio_addr;
2527 u32 mc_filter[2]; /* Multicast hash filter */
2528 int i, rx_mode;
2529 u32 tmp;
2530
2531 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2532 dev->name, dev->flags, RTL_R32 (RxConfig));
2533
2534 /* Note: do not reorder, GCC is clever about common statements. */
2535 if (dev->flags & IFF_PROMISC) {
2536 rx_mode =
2537 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2538 AcceptAllPhys;
2539 mc_filter[1] = mc_filter[0] = 0xffffffff;
2540 } else if ((dev->mc_count > multicast_filter_limit)
2541 || (dev->flags & IFF_ALLMULTI)) {
2542 /* Too many to filter perfectly -- accept all multicasts. */
2543 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2544 mc_filter[1] = mc_filter[0] = 0xffffffff;
2545 } else {
2546 struct dev_mc_list *mclist;
2547 rx_mode = AcceptBroadcast | AcceptMyPhys;
2548 mc_filter[1] = mc_filter[0] = 0;
2549 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2550 i++, mclist = mclist->next) {
2551 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2552
2553 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2554 rx_mode |= AcceptMulticast;
2555 }
2556 }
2557
2558 /* We can safely update without stopping the chip. */
2559 tmp = rtl8139_rx_config | rx_mode;
2560 if (tp->rx_config != tmp) {
2561 RTL_W32_F (RxConfig, tmp);
2562 tp->rx_config = tmp;
2563 }
2564 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2565 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2566 }
2567
2568 static void rtl8139_set_rx_mode (struct net_device *dev)
2569 {
2570 unsigned long flags;
2571 struct rtl8139_private *tp = netdev_priv(dev);
2572
2573 spin_lock_irqsave (&tp->lock, flags);
2574 __set_rx_mode(dev);
2575 spin_unlock_irqrestore (&tp->lock, flags);
2576 }
2577
2578 #ifdef CONFIG_PM
2579
2580 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2581 {
2582 struct net_device *dev = pci_get_drvdata (pdev);
2583 struct rtl8139_private *tp = netdev_priv(dev);
2584 void __iomem *ioaddr = tp->mmio_addr;
2585 unsigned long flags;
2586
2587 pci_save_state (pdev);
2588
2589 if (!netif_running (dev))
2590 return 0;
2591
2592 netif_device_detach (dev);
2593
2594 spin_lock_irqsave (&tp->lock, flags);
2595
2596 /* Disable interrupts, stop Tx and Rx. */
2597 RTL_W16 (IntrMask, 0);
2598 RTL_W8 (ChipCmd, 0);
2599
2600 /* Update the error counts. */
2601 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2602 RTL_W32 (RxMissed, 0);
2603
2604 spin_unlock_irqrestore (&tp->lock, flags);
2605
2606 pci_set_power_state (pdev, PCI_D3hot);
2607
2608 return 0;
2609 }
2610
2611
2612 static int rtl8139_resume (struct pci_dev *pdev)
2613 {
2614 struct net_device *dev = pci_get_drvdata (pdev);
2615
2616 pci_restore_state (pdev);
2617 if (!netif_running (dev))
2618 return 0;
2619 pci_set_power_state (pdev, PCI_D0);
2620 rtl8139_init_ring (dev);
2621 rtl8139_hw_start (dev);
2622 netif_device_attach (dev);
2623 return 0;
2624 }
2625
2626 #endif /* CONFIG_PM */
2627
2628
2629 static struct pci_driver rtl8139_pci_driver = {
2630 .name = DRV_NAME,
2631 .id_table = rtl8139_pci_tbl,
2632 .probe = rtl8139_init_one,
2633 .remove = __devexit_p(rtl8139_remove_one),
2634 #ifdef CONFIG_PM
2635 .suspend = rtl8139_suspend,
2636 .resume = rtl8139_resume,
2637 #endif /* CONFIG_PM */
2638 };
2639
2640
2641 static int __init rtl8139_init_module (void)
2642 {
2643 /* when we're a module, we always print a version message,
2644 * even if no 8139 board is found.
2645 */
2646 #ifdef MODULE
2647 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2648 #endif
2649
2650 return pci_register_driver(&rtl8139_pci_driver);
2651 }
2652
2653
2654 static void __exit rtl8139_cleanup_module (void)
2655 {
2656 pci_unregister_driver (&rtl8139_pci_driver);
2657 }
2658
2659
2660 module_init(rtl8139_init_module);
2661 module_exit(rtl8139_cleanup_module);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree