2 * Copyright (C) 2007 Atmel Corporation.
3 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 #include <linux/module.h>
11 #include <asm/mach/map.h>
13 #include <mach/hardware.h>
15 #include <mach/at91_dbgu.h>
16 #include <mach/at91_pmc.h>
21 struct at91_init_soc __initdata at91_boot_soc
;
23 struct at91_socinfo at91_soc_initdata
;
24 EXPORT_SYMBOL(at91_soc_initdata
);
26 void __init
at91rm9200_set_type(int type
)
28 if (type
== ARCH_REVISON_9200_PQFP
)
29 at91_soc_initdata
.subtype
= AT91_SOC_RM9200_BGA
;
31 at91_soc_initdata
.subtype
= AT91_SOC_RM9200_PQFP
;
34 void __init
at91_init_irq_default(void)
36 at91_init_interrupts(at91_boot_soc
.default_irq_priority
);
39 void __init
at91_init_interrupts(unsigned int *priority
)
41 /* Initialize the AIC interrupt controller */
42 at91_aic_init(priority
);
44 /* Enable GPIO interrupts */
45 at91_gpio_irq_setup();
48 static struct map_desc at91_io_desc __initdata
= {
49 .virtual = AT91_VA_BASE_SYS
,
50 .pfn
= __phys_to_pfn(AT91_BASE_SYS
),
55 #define AT91_DBGU0 0xfffff200
56 #define AT91_DBGU1 0xffffee00
58 static void __init
soc_detect(u32 dbgu_base
)
62 cidr
= __raw_readl(AT91_IO_P2V(dbgu_base
) + AT91_DBGU_CIDR
);
63 socid
= cidr
& ~AT91_CIDR_VERSION
;
66 case ARCH_ID_AT91CAP9
: {
67 #ifdef CONFIG_AT91_PMC_UNIT
68 u32 pmc_ver
= at91_sys_read(AT91_PMC_VER
);
70 if (pmc_ver
== ARCH_REVISION_CAP9_B
)
71 at91_soc_initdata
.subtype
= AT91_SOC_CAP9_REV_B
;
72 else if (pmc_ver
== ARCH_REVISION_CAP9_C
)
73 at91_soc_initdata
.subtype
= AT91_SOC_CAP9_REV_C
;
75 at91_soc_initdata
.type
= AT91_SOC_CAP9
;
76 at91_boot_soc
= at91cap9_soc
;
80 case ARCH_ID_AT91RM9200
:
81 at91_soc_initdata
.type
= AT91_SOC_RM9200
;
82 at91_boot_soc
= at91rm9200_soc
;
85 case ARCH_ID_AT91SAM9260
:
86 at91_soc_initdata
.type
= AT91_SOC_SAM9260
;
87 at91_boot_soc
= at91sam9260_soc
;
90 case ARCH_ID_AT91SAM9261
:
91 at91_soc_initdata
.type
= AT91_SOC_SAM9261
;
92 at91_boot_soc
= at91sam9261_soc
;
95 case ARCH_ID_AT91SAM9263
:
96 at91_soc_initdata
.type
= AT91_SOC_SAM9263
;
97 at91_boot_soc
= at91sam9263_soc
;
100 case ARCH_ID_AT91SAM9G20
:
101 at91_soc_initdata
.type
= AT91_SOC_SAM9G20
;
102 at91_boot_soc
= at91sam9260_soc
;
105 case ARCH_ID_AT91SAM9G45
:
106 at91_soc_initdata
.type
= AT91_SOC_SAM9G45
;
107 if (cidr
== ARCH_ID_AT91SAM9G45ES
)
108 at91_soc_initdata
.subtype
= AT91_SOC_SAM9G45ES
;
109 at91_boot_soc
= at91sam9g45_soc
;
112 case ARCH_ID_AT91SAM9RL64
:
113 at91_soc_initdata
.type
= AT91_SOC_SAM9RL
;
114 at91_boot_soc
= at91sam9rl_soc
;
117 case ARCH_ID_AT91SAM9X5
:
118 at91_soc_initdata
.type
= AT91_SOC_SAM9X5
;
119 at91_boot_soc
= at91sam9x5_soc
;
124 if ((cidr
& ~AT91_CIDR_EXT
) == ARCH_ID_AT91SAM9G10
) {
125 at91_soc_initdata
.type
= AT91_SOC_SAM9G10
;
126 at91_boot_soc
= at91sam9261_soc
;
129 else if ((cidr
& AT91_CIDR_ARCH
) == ARCH_FAMILY_AT91SAM9XE
) {
130 at91_soc_initdata
.type
= AT91_SOC_SAM9260
;
131 at91_soc_initdata
.subtype
= AT91_SOC_SAM9XE
;
132 at91_boot_soc
= at91sam9260_soc
;
135 if (!at91_soc_is_detected())
138 at91_soc_initdata
.cidr
= cidr
;
140 /* sub version of soc */
141 at91_soc_initdata
.exid
= __raw_readl(AT91_IO_P2V(dbgu_base
) + AT91_DBGU_EXID
);
143 if (at91_soc_initdata
.type
== AT91_SOC_SAM9G45
) {
144 switch (at91_soc_initdata
.exid
) {
145 case ARCH_EXID_AT91SAM9M10
:
146 at91_soc_initdata
.subtype
= AT91_SOC_SAM9M10
;
148 case ARCH_EXID_AT91SAM9G46
:
149 at91_soc_initdata
.subtype
= AT91_SOC_SAM9G46
;
151 case ARCH_EXID_AT91SAM9M11
:
152 at91_soc_initdata
.subtype
= AT91_SOC_SAM9M11
;
157 if (at91_soc_initdata
.type
== AT91_SOC_SAM9X5
) {
158 switch (at91_soc_initdata
.exid
) {
159 case ARCH_EXID_AT91SAM9G15
:
160 at91_soc_initdata
.subtype
= AT91_SOC_SAM9G15
;
162 case ARCH_EXID_AT91SAM9G35
:
163 at91_soc_initdata
.subtype
= AT91_SOC_SAM9G35
;
165 case ARCH_EXID_AT91SAM9X35
:
166 at91_soc_initdata
.subtype
= AT91_SOC_SAM9X35
;
168 case ARCH_EXID_AT91SAM9G25
:
169 at91_soc_initdata
.subtype
= AT91_SOC_SAM9G25
;
171 case ARCH_EXID_AT91SAM9X25
:
172 at91_soc_initdata
.subtype
= AT91_SOC_SAM9X25
;
178 static const char *soc_name
[] = {
179 [AT91_SOC_RM9200
] = "at91rm9200",
180 [AT91_SOC_CAP9
] = "at91cap9",
181 [AT91_SOC_SAM9260
] = "at91sam9260",
182 [AT91_SOC_SAM9261
] = "at91sam9261",
183 [AT91_SOC_SAM9263
] = "at91sam9263",
184 [AT91_SOC_SAM9G10
] = "at91sam9g10",
185 [AT91_SOC_SAM9G20
] = "at91sam9g20",
186 [AT91_SOC_SAM9G45
] = "at91sam9g45",
187 [AT91_SOC_SAM9RL
] = "at91sam9rl",
188 [AT91_SOC_SAM9X5
] = "at91sam9x5",
189 [AT91_SOC_NONE
] = "Unknown"
192 const char *at91_get_soc_type(struct at91_socinfo
*c
)
194 return soc_name
[c
->type
];
196 EXPORT_SYMBOL(at91_get_soc_type
);
198 static const char *soc_subtype_name
[] = {
199 [AT91_SOC_RM9200_BGA
] = "at91rm9200 BGA",
200 [AT91_SOC_RM9200_PQFP
] = "at91rm9200 PQFP",
201 [AT91_SOC_CAP9_REV_B
] = "at91cap9 revB",
202 [AT91_SOC_CAP9_REV_C
] = "at91cap9 revC",
203 [AT91_SOC_SAM9XE
] = "at91sam9xe",
204 [AT91_SOC_SAM9G45ES
] = "at91sam9g45es",
205 [AT91_SOC_SAM9M10
] = "at91sam9m10",
206 [AT91_SOC_SAM9G46
] = "at91sam9g46",
207 [AT91_SOC_SAM9M11
] = "at91sam9m11",
208 [AT91_SOC_SAM9G15
] = "at91sam9g15",
209 [AT91_SOC_SAM9G35
] = "at91sam9g35",
210 [AT91_SOC_SAM9X35
] = "at91sam9x35",
211 [AT91_SOC_SAM9G25
] = "at91sam9g25",
212 [AT91_SOC_SAM9X25
] = "at91sam9x25",
213 [AT91_SOC_SUBTYPE_NONE
] = "Unknown"
216 const char *at91_get_soc_subtype(struct at91_socinfo
*c
)
218 return soc_subtype_name
[c
->subtype
];
220 EXPORT_SYMBOL(at91_get_soc_subtype
);
222 void __init
at91_map_io(void)
224 /* Map peripherals */
225 iotable_init(&at91_io_desc
, 1);
227 at91_soc_initdata
.type
= AT91_SOC_NONE
;
228 at91_soc_initdata
.subtype
= AT91_SOC_SUBTYPE_NONE
;
230 soc_detect(AT91_DBGU0
);
231 if (!at91_soc_is_detected())
232 soc_detect(AT91_DBGU1
);
234 if (!at91_soc_is_detected())
235 panic("AT91: Impossible to detect the SOC type");
237 pr_info("AT91: Detected soc type: %s\n",
238 at91_get_soc_type(&at91_soc_initdata
));
239 pr_info("AT91: Detected soc subtype: %s\n",
240 at91_get_soc_subtype(&at91_soc_initdata
));
242 if (!at91_soc_is_enabled())
243 panic("AT91: Soc not enabled");
245 if (at91_boot_soc
.map_io
)
246 at91_boot_soc
.map_io();
249 void __init
at91_initialize(unsigned long main_clock
)
251 /* Init clock subsystem */
252 at91_clock_init(main_clock
);
254 at91_boot_soc
.init();