arch/arm/mach-at91/at91sam9261.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9261.c
   3  *
   4  *  Copyright (C) 2005 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/pm.h>
  15
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <mach/cpu.h>
  20 #include <mach/at91sam9261.h>
  21 #include <mach/at91_pmc.h>
  22 #include <mach/at91_rstc.h>
  23 #include <mach/at91_shdwc.h>
  24
  25 #include "soc.h"
  26 #include "generic.h"
  27 #include "clock.h"
  28
  29 static struct map_desc at91sam9261_sram_desc[] __initdata = {
  30         {
  31                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE,
  32                 .pfn            = __phys_to_pfn(AT91SAM9261_SRAM_BASE),
  33                 .length         = AT91SAM9261_SRAM_SIZE,
  34                 .type           = MT_DEVICE,
  35         },
  36 };
  37
  38 static struct map_desc at91sam9g10_sram_desc[] __initdata = {
  39         {
  40                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9G10_SRAM_SIZE,
  41                 .pfn            = __phys_to_pfn(AT91SAM9G10_SRAM_BASE),
  42                 .length         = AT91SAM9G10_SRAM_SIZE,
  43                 .type           = MT_DEVICE,
  44         },
  45 };
  46
  47 /* --------------------------------------------------------------------
  48  *  Clocks
  49  * -------------------------------------------------------------------- */
  50
  51 /*
  52  * The peripheral clocks.
  53  */
  54 static struct clk pioA_clk = {
  55         .name           = "pioA_clk",
  56         .pmc_mask       = 1 << AT91SAM9261_ID_PIOA,
  57         .type           = CLK_TYPE_PERIPHERAL,
  58 };
  59 static struct clk pioB_clk = {
  60         .name           = "pioB_clk",
  61         .pmc_mask       = 1 << AT91SAM9261_ID_PIOB,
  62         .type           = CLK_TYPE_PERIPHERAL,
  63 };
  64 static struct clk pioC_clk = {
  65         .name           = "pioC_clk",
  66         .pmc_mask       = 1 << AT91SAM9261_ID_PIOC,
  67         .type           = CLK_TYPE_PERIPHERAL,
  68 };
  69 static struct clk usart0_clk = {
  70         .name           = "usart0_clk",
  71         .pmc_mask       = 1 << AT91SAM9261_ID_US0,
  72         .type           = CLK_TYPE_PERIPHERAL,
  73 };
  74 static struct clk usart1_clk = {
  75         .name           = "usart1_clk",
  76         .pmc_mask       = 1 << AT91SAM9261_ID_US1,
  77         .type           = CLK_TYPE_PERIPHERAL,
  78 };
  79 static struct clk usart2_clk = {
  80         .name           = "usart2_clk",
  81         .pmc_mask       = 1 << AT91SAM9261_ID_US2,
  82         .type           = CLK_TYPE_PERIPHERAL,
  83 };
  84 static struct clk mmc_clk = {
  85         .name           = "mci_clk",
  86         .pmc_mask       = 1 << AT91SAM9261_ID_MCI,
  87         .type           = CLK_TYPE_PERIPHERAL,
  88 };
  89 static struct clk udc_clk = {
  90         .name           = "udc_clk",
  91         .pmc_mask       = 1 << AT91SAM9261_ID_UDP,
  92         .type           = CLK_TYPE_PERIPHERAL,
  93 };
  94 static struct clk twi_clk = {
  95         .name           = "twi_clk",
  96         .pmc_mask       = 1 << AT91SAM9261_ID_TWI,
  97         .type           = CLK_TYPE_PERIPHERAL,
  98 };
  99 static struct clk spi0_clk = {
 100         .name           = "spi0_clk",
 101         .pmc_mask       = 1 << AT91SAM9261_ID_SPI0,
 102         .type           = CLK_TYPE_PERIPHERAL,
 103 };
 104 static struct clk spi1_clk = {
 105         .name           = "spi1_clk",
 106         .pmc_mask       = 1 << AT91SAM9261_ID_SPI1,
 107         .type           = CLK_TYPE_PERIPHERAL,
 108 };
 109 static struct clk ssc0_clk = {
 110         .name           = "ssc0_clk",
 111         .pmc_mask       = 1 << AT91SAM9261_ID_SSC0,
 112         .type           = CLK_TYPE_PERIPHERAL,
 113 };
 114 static struct clk ssc1_clk = {
 115         .name           = "ssc1_clk",
 116         .pmc_mask       = 1 << AT91SAM9261_ID_SSC1,
 117         .type           = CLK_TYPE_PERIPHERAL,
 118 };
 119 static struct clk ssc2_clk = {
 120         .name           = "ssc2_clk",
 121         .pmc_mask       = 1 << AT91SAM9261_ID_SSC2,
 122         .type           = CLK_TYPE_PERIPHERAL,
 123 };
 124 static struct clk tc0_clk = {
 125         .name           = "tc0_clk",
 126         .pmc_mask       = 1 << AT91SAM9261_ID_TC0,
 127         .type           = CLK_TYPE_PERIPHERAL,
 128 };
 129 static struct clk tc1_clk = {
 130         .name           = "tc1_clk",
 131         .pmc_mask       = 1 << AT91SAM9261_ID_TC1,
 132         .type           = CLK_TYPE_PERIPHERAL,
 133 };
 134 static struct clk tc2_clk = {
 135         .name           = "tc2_clk",
 136         .pmc_mask       = 1 << AT91SAM9261_ID_TC2,
 137         .type           = CLK_TYPE_PERIPHERAL,
 138 };
 139 static struct clk ohci_clk = {
 140         .name           = "ohci_clk",
 141         .pmc_mask       = 1 << AT91SAM9261_ID_UHP,
 142         .type           = CLK_TYPE_PERIPHERAL,
 143 };
 144 static struct clk lcdc_clk = {
 145         .name           = "lcdc_clk",
 146         .pmc_mask       = 1 << AT91SAM9261_ID_LCDC,
 147         .type           = CLK_TYPE_PERIPHERAL,
 148 };
 149
 150 static struct clk *periph_clocks[] __initdata = {
 151         &pioA_clk,
 152         &pioB_clk,
 153         &pioC_clk,
 154         &usart0_clk,
 155         &usart1_clk,
 156         &usart2_clk,
 157         &mmc_clk,
 158         &udc_clk,
 159         &twi_clk,
 160         &spi0_clk,
 161         &spi1_clk,
 162         &ssc0_clk,
 163         &ssc1_clk,
 164         &ssc2_clk,
 165         &tc0_clk,
 166         &tc1_clk,
 167         &tc2_clk,
 168         &ohci_clk,
 169         &lcdc_clk,
 170         // irq0 .. irq2
 171 };
 172
 173 static struct clk_lookup periph_clocks_lookups[] = {
 174         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 175         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 176         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 177         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 178         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc1_clk),
 179         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 180         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 181         CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
 182 };
 183
 184 static struct clk_lookup usart_clocks_lookups[] = {
 185         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 186         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 187         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 188         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 189 };
 190
 191 /*
 192  * The four programmable clocks.
 193  * You must configure pin multiplexing to bring these signals out.
 194  */
 195 static struct clk pck0 = {
 196         .name           = "pck0",
 197         .pmc_mask       = AT91_PMC_PCK0,
 198         .type           = CLK_TYPE_PROGRAMMABLE,
 199         .id             = 0,
 200 };
 201 static struct clk pck1 = {
 202         .name           = "pck1",
 203         .pmc_mask       = AT91_PMC_PCK1,
 204         .type           = CLK_TYPE_PROGRAMMABLE,
 205         .id             = 1,
 206 };
 207 static struct clk pck2 = {
 208         .name           = "pck2",
 209         .pmc_mask       = AT91_PMC_PCK2,
 210         .type           = CLK_TYPE_PROGRAMMABLE,
 211         .id             = 2,
 212 };
 213 static struct clk pck3 = {
 214         .name           = "pck3",
 215         .pmc_mask       = AT91_PMC_PCK3,
 216         .type           = CLK_TYPE_PROGRAMMABLE,
 217         .id             = 3,
 218 };
 219
 220 /* HClocks */
 221 static struct clk hck0 = {
 222         .name           = "hck0",
 223         .pmc_mask       = AT91_PMC_HCK0,
 224         .type           = CLK_TYPE_SYSTEM,
 225         .id             = 0,
 226 };
 227 static struct clk hck1 = {
 228         .name           = "hck1",
 229         .pmc_mask       = AT91_PMC_HCK1,
 230         .type           = CLK_TYPE_SYSTEM,
 231         .id             = 1,
 232 };
 233
 234 static void __init at91sam9261_register_clocks(void)
 235 {
 236         int i;
 237
 238         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 239                 clk_register(periph_clocks[i]);
 240
 241         clkdev_add_table(periph_clocks_lookups,
 242                          ARRAY_SIZE(periph_clocks_lookups));
 243         clkdev_add_table(usart_clocks_lookups,
 244                          ARRAY_SIZE(usart_clocks_lookups));
 245
 246         clk_register(&pck0);
 247         clk_register(&pck1);
 248         clk_register(&pck2);
 249         clk_register(&pck3);
 250
 251         clk_register(&hck0);
 252         clk_register(&hck1);
 253 }
 254
 255 static struct clk_lookup console_clock_lookup;
 256
 257 void __init at91sam9261_set_console_clock(int id)
 258 {
 259         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 260                 return;
 261
 262         console_clock_lookup.con_id = "usart";
 263         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 264         clkdev_add(&console_clock_lookup);
 265 }
 266
 267 /* --------------------------------------------------------------------
 268  *  GPIO
 269  * -------------------------------------------------------------------- */
 270
 271 static struct at91_gpio_bank at91sam9261_gpio[] = {
 272         {
 273                 .id             = AT91SAM9261_ID_PIOA,
 274                 .offset         = AT91_PIOA,
 275                 .clock          = &pioA_clk,
 276         }, {
 277                 .id             = AT91SAM9261_ID_PIOB,
 278                 .offset         = AT91_PIOB,
 279                 .clock          = &pioB_clk,
 280         }, {
 281                 .id             = AT91SAM9261_ID_PIOC,
 282                 .offset         = AT91_PIOC,
 283                 .clock          = &pioC_clk,
 284         }
 285 };
 286
 287 static void at91sam9261_poweroff(void)
 288 {
 289         at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 290 }
 291
 292
 293 /* --------------------------------------------------------------------
 294  *  AT91SAM9261 processor initialization
 295  * -------------------------------------------------------------------- */
 296
 297 static void __init at91sam9261_map_io(void)
 298 {
 299         if (cpu_is_at91sam9g10())
 300                 iotable_init(at91sam9g10_sram_desc, ARRAY_SIZE(at91sam9g10_sram_desc));
 301         else
 302                 iotable_init(at91sam9261_sram_desc, ARRAY_SIZE(at91sam9261_sram_desc));
 303 }
 304
 305 static void __init at91sam9261_initialize(void)
 306 {
 307         at91_arch_reset = at91sam9_alt_reset;
 308         pm_power_off = at91sam9261_poweroff;
 309         at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
 310                         | (1 << AT91SAM9261_ID_IRQ2);
 311
 312         /* Register the processor-specific clocks */
 313         at91sam9261_register_clocks();
 314
 315         /* Register GPIO subsystem */
 316         at91_gpio_init(at91sam9261_gpio, 3);
 317 }
 318
 319 /* --------------------------------------------------------------------
 320  *  Interrupt initialization
 321  * -------------------------------------------------------------------- */
 322
 323 /*
 324  * The default interrupt priority levels (0 = lowest, 7 = highest).
 325  */
 326 static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
 327         7,      /* Advanced Interrupt Controller */
 328         7,      /* System Peripherals */
 329         1,      /* Parallel IO Controller A */
 330         1,      /* Parallel IO Controller B */
 331         1,      /* Parallel IO Controller C */
 332         0,
 333         5,      /* USART 0 */
 334         5,      /* USART 1 */
 335         5,      /* USART 2 */
 336         0,      /* Multimedia Card Interface */
 337         2,      /* USB Device Port */
 338         6,      /* Two-Wire Interface */
 339         5,      /* Serial Peripheral Interface 0 */
 340         5,      /* Serial Peripheral Interface 1 */
 341         4,      /* Serial Synchronous Controller 0 */
 342         4,      /* Serial Synchronous Controller 1 */
 343         4,      /* Serial Synchronous Controller 2 */
 344         0,      /* Timer Counter 0 */
 345         0,      /* Timer Counter 1 */
 346         0,      /* Timer Counter 2 */
 347         2,      /* USB Host port */
 348         3,      /* LCD Controller */
 349         0,
 350         0,
 351         0,
 352         0,
 353         0,
 354         0,
 355         0,
 356         0,      /* Advanced Interrupt Controller */
 357         0,      /* Advanced Interrupt Controller */
 358         0,      /* Advanced Interrupt Controller */
 359 };
 360
 361 struct at91_init_soc __initdata at91sam9261_soc = {
 362         .map_io = at91sam9261_map_io,
 363         .default_irq_priority = at91sam9261_default_irq_priority,
 364         .init = at91sam9261_initialize,
 365 };