2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
52 static int i915_gem_evict_something(struct drm_device
*dev
, int min_size
);
53 static int i915_gem_evict_from_inactive_list(struct drm_device
*dev
);
54 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
55 struct drm_i915_gem_pwrite
*args
,
56 struct drm_file
*file_priv
);
58 static LIST_HEAD(shrink_list
);
59 static DEFINE_SPINLOCK(shrink_list_lock
);
61 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
64 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
67 (start
& (PAGE_SIZE
- 1)) != 0 ||
68 (end
& (PAGE_SIZE
- 1)) != 0) {
72 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
75 dev
->gtt_total
= (uint32_t) (end
- start
);
81 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
82 struct drm_file
*file_priv
)
84 struct drm_i915_gem_init
*args
= data
;
87 mutex_lock(&dev
->struct_mutex
);
88 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
89 mutex_unlock(&dev
->struct_mutex
);
95 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
96 struct drm_file
*file_priv
)
98 struct drm_i915_gem_get_aperture
*args
= data
;
100 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
103 args
->aper_size
= dev
->gtt_total
;
104 args
->aper_available_size
= (args
->aper_size
-
105 atomic_read(&dev
->pin_memory
));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
116 struct drm_file
*file_priv
)
118 struct drm_i915_gem_create
*args
= data
;
119 struct drm_gem_object
*obj
;
123 args
->size
= roundup(args
->size
, PAGE_SIZE
);
125 /* Allocate the new object */
126 obj
= drm_gem_object_alloc(dev
, args
->size
);
130 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
131 mutex_lock(&dev
->struct_mutex
);
132 drm_gem_object_handle_unreference(obj
);
133 mutex_unlock(&dev
->struct_mutex
);
138 args
->handle
= handle
;
144 fast_shmem_read(struct page
**pages
,
145 loff_t page_base
, int page_offset
,
152 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
155 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
156 kunmap_atomic(vaddr
, KM_USER0
);
164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
166 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
167 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
169 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
170 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
174 slow_shmem_copy(struct page
*dst_page
,
176 struct page
*src_page
,
180 char *dst_vaddr
, *src_vaddr
;
182 dst_vaddr
= kmap_atomic(dst_page
, KM_USER0
);
183 if (dst_vaddr
== NULL
)
186 src_vaddr
= kmap_atomic(src_page
, KM_USER1
);
187 if (src_vaddr
== NULL
) {
188 kunmap_atomic(dst_vaddr
, KM_USER0
);
192 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
194 kunmap_atomic(src_vaddr
, KM_USER1
);
195 kunmap_atomic(dst_vaddr
, KM_USER0
);
201 slow_shmem_bit17_copy(struct page
*gpu_page
,
203 struct page
*cpu_page
,
208 char *gpu_vaddr
, *cpu_vaddr
;
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
213 return slow_shmem_copy(cpu_page
, cpu_offset
,
214 gpu_page
, gpu_offset
, length
);
216 return slow_shmem_copy(gpu_page
, gpu_offset
,
217 cpu_page
, cpu_offset
, length
);
220 gpu_vaddr
= kmap_atomic(gpu_page
, KM_USER0
);
221 if (gpu_vaddr
== NULL
)
224 cpu_vaddr
= kmap_atomic(cpu_page
, KM_USER1
);
225 if (cpu_vaddr
== NULL
) {
226 kunmap_atomic(gpu_vaddr
, KM_USER0
);
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
234 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
235 int this_length
= min(cacheline_end
- gpu_offset
, length
);
236 int swizzled_gpu_offset
= gpu_offset
^ 64;
239 memcpy(cpu_vaddr
+ cpu_offset
,
240 gpu_vaddr
+ swizzled_gpu_offset
,
243 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
244 cpu_vaddr
+ cpu_offset
,
247 cpu_offset
+= this_length
;
248 gpu_offset
+= this_length
;
249 length
-= this_length
;
252 kunmap_atomic(cpu_vaddr
, KM_USER1
);
253 kunmap_atomic(gpu_vaddr
, KM_USER0
);
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
264 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
265 struct drm_i915_gem_pread
*args
,
266 struct drm_file
*file_priv
)
268 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
270 loff_t offset
, page_base
;
271 char __user
*user_data
;
272 int page_offset
, page_length
;
275 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
278 mutex_lock(&dev
->struct_mutex
);
280 ret
= i915_gem_object_get_pages(obj
, 0);
284 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
289 obj_priv
= obj
->driver_private
;
290 offset
= args
->offset
;
293 /* Operation in this page
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
299 page_base
= (offset
& ~(PAGE_SIZE
-1));
300 page_offset
= offset
& (PAGE_SIZE
-1);
301 page_length
= remain
;
302 if ((page_offset
+ remain
) > PAGE_SIZE
)
303 page_length
= PAGE_SIZE
- page_offset
;
305 ret
= fast_shmem_read(obj_priv
->pages
,
306 page_base
, page_offset
,
307 user_data
, page_length
);
311 remain
-= page_length
;
312 user_data
+= page_length
;
313 offset
+= page_length
;
317 i915_gem_object_put_pages(obj
);
319 mutex_unlock(&dev
->struct_mutex
);
325 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
329 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
331 /* If we've insufficient memory to map in the pages, attempt
332 * to make some space by throwing out some old buffers.
334 if (ret
== -ENOMEM
) {
335 struct drm_device
*dev
= obj
->dev
;
337 ret
= i915_gem_evict_something(dev
, obj
->size
);
341 ret
= i915_gem_object_get_pages(obj
, 0);
348 * This is the fallback shmem pread path, which allocates temporary storage
349 * in kernel space to copy_to_user into outside of the struct_mutex, so we
350 * can copy out of the object's backing pages while holding the struct mutex
351 * and not take page faults.
354 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
355 struct drm_i915_gem_pread
*args
,
356 struct drm_file
*file_priv
)
358 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
359 struct mm_struct
*mm
= current
->mm
;
360 struct page
**user_pages
;
362 loff_t offset
, pinned_pages
, i
;
363 loff_t first_data_page
, last_data_page
, num_pages
;
364 int shmem_page_index
, shmem_page_offset
;
365 int data_page_index
, data_page_offset
;
368 uint64_t data_ptr
= args
->data_ptr
;
369 int do_bit17_swizzling
;
373 /* Pin the user pages containing the data. We can't fault while
374 * holding the struct mutex, yet we want to hold it while
375 * dereferencing the user data.
377 first_data_page
= data_ptr
/ PAGE_SIZE
;
378 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
379 num_pages
= last_data_page
- first_data_page
+ 1;
381 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
382 if (user_pages
== NULL
)
385 down_read(&mm
->mmap_sem
);
386 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
387 num_pages
, 1, 0, user_pages
, NULL
);
388 up_read(&mm
->mmap_sem
);
389 if (pinned_pages
< num_pages
) {
391 goto fail_put_user_pages
;
394 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
396 mutex_lock(&dev
->struct_mutex
);
398 ret
= i915_gem_object_get_pages_or_evict(obj
);
402 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
407 obj_priv
= obj
->driver_private
;
408 offset
= args
->offset
;
411 /* Operation in this page
413 * shmem_page_index = page number within shmem file
414 * shmem_page_offset = offset within page in shmem file
415 * data_page_index = page number in get_user_pages return
416 * data_page_offset = offset with data_page_index page.
417 * page_length = bytes to copy for this page
419 shmem_page_index
= offset
/ PAGE_SIZE
;
420 shmem_page_offset
= offset
& ~PAGE_MASK
;
421 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
422 data_page_offset
= data_ptr
& ~PAGE_MASK
;
424 page_length
= remain
;
425 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
426 page_length
= PAGE_SIZE
- shmem_page_offset
;
427 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
428 page_length
= PAGE_SIZE
- data_page_offset
;
430 if (do_bit17_swizzling
) {
431 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
433 user_pages
[data_page_index
],
438 ret
= slow_shmem_copy(user_pages
[data_page_index
],
440 obj_priv
->pages
[shmem_page_index
],
447 remain
-= page_length
;
448 data_ptr
+= page_length
;
449 offset
+= page_length
;
453 i915_gem_object_put_pages(obj
);
455 mutex_unlock(&dev
->struct_mutex
);
457 for (i
= 0; i
< pinned_pages
; i
++) {
458 SetPageDirty(user_pages
[i
]);
459 page_cache_release(user_pages
[i
]);
461 drm_free_large(user_pages
);
467 * Reads data from the object referenced by handle.
469 * On error, the contents of *data are undefined.
472 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
473 struct drm_file
*file_priv
)
475 struct drm_i915_gem_pread
*args
= data
;
476 struct drm_gem_object
*obj
;
477 struct drm_i915_gem_object
*obj_priv
;
480 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
483 obj_priv
= obj
->driver_private
;
485 /* Bounds check source.
487 * XXX: This could use review for overflow issues...
489 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
490 args
->offset
+ args
->size
> obj
->size
) {
495 if (!access_ok(VERIFY_WRITE
,
496 (char __user
*)(uintptr_t)args
->data_ptr
,
502 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
503 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
505 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
507 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
512 drm_gem_object_unreference(obj
);
516 /* This is the fast write path which cannot handle
517 * page faults in the source data
521 fast_user_write(struct io_mapping
*mapping
,
522 loff_t page_base
, int page_offset
,
523 char __user
*user_data
,
527 unsigned long unwritten
;
529 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
530 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
532 io_mapping_unmap_atomic(vaddr_atomic
);
538 /* Here's the write path which can sleep for
543 slow_kernel_write(struct io_mapping
*mapping
,
544 loff_t gtt_base
, int gtt_offset
,
545 struct page
*user_page
, int user_offset
,
548 char *src_vaddr
, *dst_vaddr
;
549 unsigned long unwritten
;
551 dst_vaddr
= io_mapping_map_atomic_wc(mapping
, gtt_base
);
552 src_vaddr
= kmap_atomic(user_page
, KM_USER1
);
553 unwritten
= __copy_from_user_inatomic_nocache(dst_vaddr
+ gtt_offset
,
554 src_vaddr
+ user_offset
,
556 kunmap_atomic(src_vaddr
, KM_USER1
);
557 io_mapping_unmap_atomic(dst_vaddr
);
564 fast_shmem_write(struct page
**pages
,
565 loff_t page_base
, int page_offset
,
570 unsigned long unwritten
;
572 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
575 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
576 kunmap_atomic(vaddr
, KM_USER0
);
584 * This is the fast pwrite path, where we copy the data directly from the
585 * user into the GTT, uncached.
588 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
589 struct drm_i915_gem_pwrite
*args
,
590 struct drm_file
*file_priv
)
592 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
593 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
595 loff_t offset
, page_base
;
596 char __user
*user_data
;
597 int page_offset
, page_length
;
600 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
604 mutex_lock(&dev
->struct_mutex
);
605 ret
= i915_gem_object_pin(obj
, 0);
607 mutex_unlock(&dev
->struct_mutex
);
610 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
614 obj_priv
= obj
->driver_private
;
615 offset
= obj_priv
->gtt_offset
+ args
->offset
;
618 /* Operation in this page
620 * page_base = page offset within aperture
621 * page_offset = offset within page
622 * page_length = bytes to copy for this page
624 page_base
= (offset
& ~(PAGE_SIZE
-1));
625 page_offset
= offset
& (PAGE_SIZE
-1);
626 page_length
= remain
;
627 if ((page_offset
+ remain
) > PAGE_SIZE
)
628 page_length
= PAGE_SIZE
- page_offset
;
630 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
631 page_offset
, user_data
, page_length
);
633 /* If we get a fault while copying data, then (presumably) our
634 * source page isn't available. Return the error and we'll
635 * retry in the slow path.
640 remain
-= page_length
;
641 user_data
+= page_length
;
642 offset
+= page_length
;
646 i915_gem_object_unpin(obj
);
647 mutex_unlock(&dev
->struct_mutex
);
653 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
654 * the memory and maps it using kmap_atomic for copying.
656 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
657 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
660 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
661 struct drm_i915_gem_pwrite
*args
,
662 struct drm_file
*file_priv
)
664 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
665 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
667 loff_t gtt_page_base
, offset
;
668 loff_t first_data_page
, last_data_page
, num_pages
;
669 loff_t pinned_pages
, i
;
670 struct page
**user_pages
;
671 struct mm_struct
*mm
= current
->mm
;
672 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
674 uint64_t data_ptr
= args
->data_ptr
;
678 /* Pin the user pages containing the data. We can't fault while
679 * holding the struct mutex, and all of the pwrite implementations
680 * want to hold it while dereferencing the user data.
682 first_data_page
= data_ptr
/ PAGE_SIZE
;
683 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
684 num_pages
= last_data_page
- first_data_page
+ 1;
686 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
687 if (user_pages
== NULL
)
690 down_read(&mm
->mmap_sem
);
691 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
692 num_pages
, 0, 0, user_pages
, NULL
);
693 up_read(&mm
->mmap_sem
);
694 if (pinned_pages
< num_pages
) {
696 goto out_unpin_pages
;
699 mutex_lock(&dev
->struct_mutex
);
700 ret
= i915_gem_object_pin(obj
, 0);
704 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
706 goto out_unpin_object
;
708 obj_priv
= obj
->driver_private
;
709 offset
= obj_priv
->gtt_offset
+ args
->offset
;
712 /* Operation in this page
714 * gtt_page_base = page offset within aperture
715 * gtt_page_offset = offset within page in aperture
716 * data_page_index = page number in get_user_pages return
717 * data_page_offset = offset with data_page_index page.
718 * page_length = bytes to copy for this page
720 gtt_page_base
= offset
& PAGE_MASK
;
721 gtt_page_offset
= offset
& ~PAGE_MASK
;
722 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
723 data_page_offset
= data_ptr
& ~PAGE_MASK
;
725 page_length
= remain
;
726 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
727 page_length
= PAGE_SIZE
- gtt_page_offset
;
728 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
729 page_length
= PAGE_SIZE
- data_page_offset
;
731 ret
= slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
732 gtt_page_base
, gtt_page_offset
,
733 user_pages
[data_page_index
],
737 /* If we get a fault while copying data, then (presumably) our
738 * source page isn't available. Return the error and we'll
739 * retry in the slow path.
742 goto out_unpin_object
;
744 remain
-= page_length
;
745 offset
+= page_length
;
746 data_ptr
+= page_length
;
750 i915_gem_object_unpin(obj
);
752 mutex_unlock(&dev
->struct_mutex
);
754 for (i
= 0; i
< pinned_pages
; i
++)
755 page_cache_release(user_pages
[i
]);
756 drm_free_large(user_pages
);
762 * This is the fast shmem pwrite path, which attempts to directly
763 * copy_from_user into the kmapped pages backing the object.
766 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
767 struct drm_i915_gem_pwrite
*args
,
768 struct drm_file
*file_priv
)
770 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
772 loff_t offset
, page_base
;
773 char __user
*user_data
;
774 int page_offset
, page_length
;
777 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
780 mutex_lock(&dev
->struct_mutex
);
782 ret
= i915_gem_object_get_pages(obj
, 0);
786 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
790 obj_priv
= obj
->driver_private
;
791 offset
= args
->offset
;
795 /* Operation in this page
797 * page_base = page offset within aperture
798 * page_offset = offset within page
799 * page_length = bytes to copy for this page
801 page_base
= (offset
& ~(PAGE_SIZE
-1));
802 page_offset
= offset
& (PAGE_SIZE
-1);
803 page_length
= remain
;
804 if ((page_offset
+ remain
) > PAGE_SIZE
)
805 page_length
= PAGE_SIZE
- page_offset
;
807 ret
= fast_shmem_write(obj_priv
->pages
,
808 page_base
, page_offset
,
809 user_data
, page_length
);
813 remain
-= page_length
;
814 user_data
+= page_length
;
815 offset
+= page_length
;
819 i915_gem_object_put_pages(obj
);
821 mutex_unlock(&dev
->struct_mutex
);
827 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
828 * the memory and maps it using kmap_atomic for copying.
830 * This avoids taking mmap_sem for faulting on the user's address while the
831 * struct_mutex is held.
834 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
835 struct drm_i915_gem_pwrite
*args
,
836 struct drm_file
*file_priv
)
838 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
839 struct mm_struct
*mm
= current
->mm
;
840 struct page
**user_pages
;
842 loff_t offset
, pinned_pages
, i
;
843 loff_t first_data_page
, last_data_page
, num_pages
;
844 int shmem_page_index
, shmem_page_offset
;
845 int data_page_index
, data_page_offset
;
848 uint64_t data_ptr
= args
->data_ptr
;
849 int do_bit17_swizzling
;
853 /* Pin the user pages containing the data. We can't fault while
854 * holding the struct mutex, and all of the pwrite implementations
855 * want to hold it while dereferencing the user data.
857 first_data_page
= data_ptr
/ PAGE_SIZE
;
858 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
859 num_pages
= last_data_page
- first_data_page
+ 1;
861 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
862 if (user_pages
== NULL
)
865 down_read(&mm
->mmap_sem
);
866 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
867 num_pages
, 0, 0, user_pages
, NULL
);
868 up_read(&mm
->mmap_sem
);
869 if (pinned_pages
< num_pages
) {
871 goto fail_put_user_pages
;
874 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
876 mutex_lock(&dev
->struct_mutex
);
878 ret
= i915_gem_object_get_pages_or_evict(obj
);
882 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
886 obj_priv
= obj
->driver_private
;
887 offset
= args
->offset
;
891 /* Operation in this page
893 * shmem_page_index = page number within shmem file
894 * shmem_page_offset = offset within page in shmem file
895 * data_page_index = page number in get_user_pages return
896 * data_page_offset = offset with data_page_index page.
897 * page_length = bytes to copy for this page
899 shmem_page_index
= offset
/ PAGE_SIZE
;
900 shmem_page_offset
= offset
& ~PAGE_MASK
;
901 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
902 data_page_offset
= data_ptr
& ~PAGE_MASK
;
904 page_length
= remain
;
905 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
906 page_length
= PAGE_SIZE
- shmem_page_offset
;
907 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
908 page_length
= PAGE_SIZE
- data_page_offset
;
910 if (do_bit17_swizzling
) {
911 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
913 user_pages
[data_page_index
],
918 ret
= slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
920 user_pages
[data_page_index
],
927 remain
-= page_length
;
928 data_ptr
+= page_length
;
929 offset
+= page_length
;
933 i915_gem_object_put_pages(obj
);
935 mutex_unlock(&dev
->struct_mutex
);
937 for (i
= 0; i
< pinned_pages
; i
++)
938 page_cache_release(user_pages
[i
]);
939 drm_free_large(user_pages
);
945 * Writes data to the object referenced by handle.
947 * On error, the contents of the buffer that were to be modified are undefined.
950 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
951 struct drm_file
*file_priv
)
953 struct drm_i915_gem_pwrite
*args
= data
;
954 struct drm_gem_object
*obj
;
955 struct drm_i915_gem_object
*obj_priv
;
958 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
961 obj_priv
= obj
->driver_private
;
963 /* Bounds check destination.
965 * XXX: This could use review for overflow issues...
967 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
968 args
->offset
+ args
->size
> obj
->size
) {
973 if (!access_ok(VERIFY_READ
,
974 (char __user
*)(uintptr_t)args
->data_ptr
,
980 /* We can only do the GTT pwrite on untiled buffers, as otherwise
981 * it would end up going through the fenced access, and we'll get
982 * different detiling behavior between reading and writing.
983 * pread/pwrite currently are reading and writing from the CPU
984 * perspective, requiring manual detiling by the client.
986 if (obj_priv
->phys_obj
)
987 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
988 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
989 dev
->gtt_total
!= 0) {
990 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
991 if (ret
== -EFAULT
) {
992 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
995 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
996 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
998 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
999 if (ret
== -EFAULT
) {
1000 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
1007 DRM_INFO("pwrite failed %d\n", ret
);
1011 drm_gem_object_unreference(obj
);
1016 * Called when user space prepares to use an object with the CPU, either
1017 * through the mmap ioctl's mapping or a GTT mapping.
1020 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1021 struct drm_file
*file_priv
)
1023 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1024 struct drm_i915_gem_set_domain
*args
= data
;
1025 struct drm_gem_object
*obj
;
1026 struct drm_i915_gem_object
*obj_priv
;
1027 uint32_t read_domains
= args
->read_domains
;
1028 uint32_t write_domain
= args
->write_domain
;
1031 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1034 /* Only handle setting domains to types used by the CPU. */
1035 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1038 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1041 /* Having something in the write domain implies it's in the read
1042 * domain, and only that read domain. Enforce that in the request.
1044 if (write_domain
!= 0 && read_domains
!= write_domain
)
1047 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1050 obj_priv
= obj
->driver_private
;
1052 mutex_lock(&dev
->struct_mutex
);
1054 intel_mark_busy(dev
, obj
);
1057 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1058 obj
, obj
->size
, read_domains
, write_domain
);
1060 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1061 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1063 /* Update the LRU on the fence for the CPU access that's
1066 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1067 list_move_tail(&obj_priv
->fence_list
,
1068 &dev_priv
->mm
.fence_list
);
1071 /* Silently promote "you're not bound, there was nothing to do"
1072 * to success, since the client was just asking us to
1073 * make sure everything was done.
1078 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1081 drm_gem_object_unreference(obj
);
1082 mutex_unlock(&dev
->struct_mutex
);
1087 * Called when user space has done writes to this buffer
1090 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1091 struct drm_file
*file_priv
)
1093 struct drm_i915_gem_sw_finish
*args
= data
;
1094 struct drm_gem_object
*obj
;
1095 struct drm_i915_gem_object
*obj_priv
;
1098 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1101 mutex_lock(&dev
->struct_mutex
);
1102 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1104 mutex_unlock(&dev
->struct_mutex
);
1109 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1110 __func__
, args
->handle
, obj
, obj
->size
);
1112 obj_priv
= obj
->driver_private
;
1114 /* Pinned buffers may be scanout, so flush the cache */
1115 if (obj_priv
->pin_count
)
1116 i915_gem_object_flush_cpu_write_domain(obj
);
1118 drm_gem_object_unreference(obj
);
1119 mutex_unlock(&dev
->struct_mutex
);
1124 * Maps the contents of an object, returning the address it is mapped
1127 * While the mapping holds a reference on the contents of the object, it doesn't
1128 * imply a ref on the object itself.
1131 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1132 struct drm_file
*file_priv
)
1134 struct drm_i915_gem_mmap
*args
= data
;
1135 struct drm_gem_object
*obj
;
1139 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1142 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1146 offset
= args
->offset
;
1148 down_write(¤t
->mm
->mmap_sem
);
1149 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1150 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1152 up_write(¤t
->mm
->mmap_sem
);
1153 mutex_lock(&dev
->struct_mutex
);
1154 drm_gem_object_unreference(obj
);
1155 mutex_unlock(&dev
->struct_mutex
);
1156 if (IS_ERR((void *)addr
))
1159 args
->addr_ptr
= (uint64_t) addr
;
1165 * i915_gem_fault - fault a page into the GTT
1166 * vma: VMA in question
1169 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1170 * from userspace. The fault handler takes care of binding the object to
1171 * the GTT (if needed), allocating and programming a fence register (again,
1172 * only if needed based on whether the old reg is still valid or the object
1173 * is tiled) and inserting a new PTE into the faulting process.
1175 * Note that the faulting process may involve evicting existing objects
1176 * from the GTT and/or fence registers to make room. So performance may
1177 * suffer if the GTT working set is large or there are few fence registers
1180 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1182 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1183 struct drm_device
*dev
= obj
->dev
;
1184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1185 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1186 pgoff_t page_offset
;
1189 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1191 /* We don't use vmf->pgoff since that has the fake offset */
1192 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1195 /* Now bind it into the GTT if needed */
1196 mutex_lock(&dev
->struct_mutex
);
1197 if (!obj_priv
->gtt_space
) {
1198 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1202 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1204 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1209 /* Need a new fence register? */
1210 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1211 ret
= i915_gem_object_get_fence_reg(obj
);
1216 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1219 /* Finally, remap it using the new GTT offset */
1220 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1222 mutex_unlock(&dev
->struct_mutex
);
1227 return VM_FAULT_NOPAGE
;
1230 return VM_FAULT_OOM
;
1232 return VM_FAULT_SIGBUS
;
1237 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1238 * @obj: obj in question
1240 * GEM memory mapping works by handing back to userspace a fake mmap offset
1241 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1242 * up the object based on the offset and sets up the various memory mapping
1245 * This routine allocates and attaches a fake offset for @obj.
1248 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1250 struct drm_device
*dev
= obj
->dev
;
1251 struct drm_gem_mm
*mm
= dev
->mm_private
;
1252 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1253 struct drm_map_list
*list
;
1254 struct drm_local_map
*map
;
1257 /* Set the object up for mmap'ing */
1258 list
= &obj
->map_list
;
1259 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1264 map
->type
= _DRM_GEM
;
1265 map
->size
= obj
->size
;
1268 /* Get a DRM GEM mmap offset allocated... */
1269 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1270 obj
->size
/ PAGE_SIZE
, 0, 0);
1271 if (!list
->file_offset_node
) {
1272 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1277 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1278 obj
->size
/ PAGE_SIZE
, 0);
1279 if (!list
->file_offset_node
) {
1284 list
->hash
.key
= list
->file_offset_node
->start
;
1285 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1286 DRM_ERROR("failed to add to map hash\n");
1291 /* By now we should be all set, any drm_mmap request on the offset
1292 * below will get to our mmap & fault handler */
1293 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1298 drm_mm_put_block(list
->file_offset_node
);
1306 * i915_gem_release_mmap - remove physical page mappings
1307 * @obj: obj in question
1309 * Preserve the reservation of the mmaping with the DRM core code, but
1310 * relinquish ownership of the pages back to the system.
1312 * It is vital that we remove the page mapping if we have mapped a tiled
1313 * object through the GTT and then lose the fence register due to
1314 * resource pressure. Similarly if the object has been moved out of the
1315 * aperture, than pages mapped into userspace must be revoked. Removing the
1316 * mapping will then trigger a page fault on the next user access, allowing
1317 * fixup by i915_gem_fault().
1320 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1322 struct drm_device
*dev
= obj
->dev
;
1323 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1325 if (dev
->dev_mapping
)
1326 unmap_mapping_range(dev
->dev_mapping
,
1327 obj_priv
->mmap_offset
, obj
->size
, 1);
1331 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1333 struct drm_device
*dev
= obj
->dev
;
1334 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1335 struct drm_gem_mm
*mm
= dev
->mm_private
;
1336 struct drm_map_list
*list
;
1338 list
= &obj
->map_list
;
1339 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1341 if (list
->file_offset_node
) {
1342 drm_mm_put_block(list
->file_offset_node
);
1343 list
->file_offset_node
= NULL
;
1351 obj_priv
->mmap_offset
= 0;
1355 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1356 * @obj: object to check
1358 * Return the required GTT alignment for an object, taking into account
1359 * potential fence register mapping if needed.
1362 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1364 struct drm_device
*dev
= obj
->dev
;
1365 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1369 * Minimum alignment is 4k (GTT page size), but might be greater
1370 * if a fence register is needed for the object.
1372 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1376 * Previous chips need to be aligned to the size of the smallest
1377 * fence register that can contain the object.
1384 for (i
= start
; i
< obj
->size
; i
<<= 1)
1391 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1393 * @data: GTT mapping ioctl data
1394 * @file_priv: GEM object info
1396 * Simply returns the fake offset to userspace so it can mmap it.
1397 * The mmap call will end up in drm_gem_mmap(), which will set things
1398 * up so we can get faults in the handler above.
1400 * The fault handler will take care of binding the object into the GTT
1401 * (since it may have been evicted to make room for something), allocating
1402 * a fence register, and mapping the appropriate aperture address into
1406 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1407 struct drm_file
*file_priv
)
1409 struct drm_i915_gem_mmap_gtt
*args
= data
;
1410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1411 struct drm_gem_object
*obj
;
1412 struct drm_i915_gem_object
*obj_priv
;
1415 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1418 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1422 mutex_lock(&dev
->struct_mutex
);
1424 obj_priv
= obj
->driver_private
;
1426 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1427 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1428 drm_gem_object_unreference(obj
);
1429 mutex_unlock(&dev
->struct_mutex
);
1434 if (!obj_priv
->mmap_offset
) {
1435 ret
= i915_gem_create_mmap_offset(obj
);
1437 drm_gem_object_unreference(obj
);
1438 mutex_unlock(&dev
->struct_mutex
);
1443 args
->offset
= obj_priv
->mmap_offset
;
1446 * Pull it into the GTT so that we have a page list (makes the
1447 * initial fault faster and any subsequent flushing possible).
1449 if (!obj_priv
->agp_mem
) {
1450 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1452 drm_gem_object_unreference(obj
);
1453 mutex_unlock(&dev
->struct_mutex
);
1456 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1459 drm_gem_object_unreference(obj
);
1460 mutex_unlock(&dev
->struct_mutex
);
1466 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1468 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1469 int page_count
= obj
->size
/ PAGE_SIZE
;
1472 BUG_ON(obj_priv
->pages_refcount
== 0);
1473 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1475 if (--obj_priv
->pages_refcount
!= 0)
1478 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1479 i915_gem_object_save_bit_17_swizzle(obj
);
1481 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1482 obj_priv
->dirty
= 0;
1484 for (i
= 0; i
< page_count
; i
++) {
1485 if (obj_priv
->dirty
)
1486 set_page_dirty(obj_priv
->pages
[i
]);
1488 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1489 mark_page_accessed(obj_priv
->pages
[i
]);
1491 page_cache_release(obj_priv
->pages
[i
]);
1493 obj_priv
->dirty
= 0;
1495 drm_free_large(obj_priv
->pages
);
1496 obj_priv
->pages
= NULL
;
1500 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
)
1502 struct drm_device
*dev
= obj
->dev
;
1503 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1504 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1506 /* Add a reference if we're newly entering the active list. */
1507 if (!obj_priv
->active
) {
1508 drm_gem_object_reference(obj
);
1509 obj_priv
->active
= 1;
1511 /* Move from whatever list we were on to the tail of execution. */
1512 spin_lock(&dev_priv
->mm
.active_list_lock
);
1513 list_move_tail(&obj_priv
->list
,
1514 &dev_priv
->mm
.active_list
);
1515 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1516 obj_priv
->last_rendering_seqno
= seqno
;
1520 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1522 struct drm_device
*dev
= obj
->dev
;
1523 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1524 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1526 BUG_ON(!obj_priv
->active
);
1527 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1528 obj_priv
->last_rendering_seqno
= 0;
1531 /* Immediately discard the backing storage */
1533 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1535 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1536 struct inode
*inode
;
1538 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1539 if (inode
->i_op
->truncate
)
1540 inode
->i_op
->truncate (inode
);
1542 obj_priv
->madv
= __I915_MADV_PURGED
;
1546 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1548 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1552 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1554 struct drm_device
*dev
= obj
->dev
;
1555 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1556 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1558 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1559 if (obj_priv
->pin_count
!= 0)
1560 list_del_init(&obj_priv
->list
);
1562 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1564 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1566 obj_priv
->last_rendering_seqno
= 0;
1567 if (obj_priv
->active
) {
1568 obj_priv
->active
= 0;
1569 drm_gem_object_unreference(obj
);
1571 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1575 * Creates a new sequence number, emitting a write of it to the status page
1576 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1578 * Must be called with struct_lock held.
1580 * Returned sequence numbers are nonzero on success.
1583 i915_add_request(struct drm_device
*dev
, struct drm_file
*file_priv
,
1584 uint32_t flush_domains
)
1586 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1587 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1588 struct drm_i915_gem_request
*request
;
1593 if (file_priv
!= NULL
)
1594 i915_file_priv
= file_priv
->driver_priv
;
1596 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1597 if (request
== NULL
)
1600 /* Grab the seqno we're going to make this request be, and bump the
1601 * next (skipping 0 so it can be the reserved no-seqno value).
1603 seqno
= dev_priv
->mm
.next_gem_seqno
;
1604 dev_priv
->mm
.next_gem_seqno
++;
1605 if (dev_priv
->mm
.next_gem_seqno
== 0)
1606 dev_priv
->mm
.next_gem_seqno
++;
1609 OUT_RING(MI_STORE_DWORD_INDEX
);
1610 OUT_RING(I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1613 OUT_RING(MI_USER_INTERRUPT
);
1616 DRM_DEBUG("%d\n", seqno
);
1618 request
->seqno
= seqno
;
1619 request
->emitted_jiffies
= jiffies
;
1620 was_empty
= list_empty(&dev_priv
->mm
.request_list
);
1621 list_add_tail(&request
->list
, &dev_priv
->mm
.request_list
);
1622 if (i915_file_priv
) {
1623 list_add_tail(&request
->client_list
,
1624 &i915_file_priv
->mm
.request_list
);
1626 INIT_LIST_HEAD(&request
->client_list
);
1629 /* Associate any objects on the flushing list matching the write
1630 * domain we're flushing with our flush.
1632 if (flush_domains
!= 0) {
1633 struct drm_i915_gem_object
*obj_priv
, *next
;
1635 list_for_each_entry_safe(obj_priv
, next
,
1636 &dev_priv
->mm
.gpu_write_list
,
1638 struct drm_gem_object
*obj
= obj_priv
->obj
;
1640 if ((obj
->write_domain
& flush_domains
) ==
1641 obj
->write_domain
) {
1642 uint32_t old_write_domain
= obj
->write_domain
;
1644 obj
->write_domain
= 0;
1645 list_del_init(&obj_priv
->gpu_write_list
);
1646 i915_gem_object_move_to_active(obj
, seqno
);
1648 trace_i915_gem_object_change_domain(obj
,
1656 if (!dev_priv
->mm
.suspended
) {
1657 mod_timer(&dev_priv
->hangcheck_timer
, jiffies
+ DRM_I915_HANGCHECK_PERIOD
);
1659 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1665 * Command execution barrier
1667 * Ensures that all commands in the ring are finished
1668 * before signalling the CPU
1671 i915_retire_commands(struct drm_device
*dev
)
1673 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1674 uint32_t cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1675 uint32_t flush_domains
= 0;
1678 /* The sampler always gets flushed on i965 (sigh) */
1680 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1683 OUT_RING(0); /* noop */
1685 return flush_domains
;
1689 * Moves buffers associated only with the given active seqno from the active
1690 * to inactive list, potentially freeing them.
1693 i915_gem_retire_request(struct drm_device
*dev
,
1694 struct drm_i915_gem_request
*request
)
1696 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1698 trace_i915_gem_request_retire(dev
, request
->seqno
);
1700 /* Move any buffers on the active list that are no longer referenced
1701 * by the ringbuffer to the flushing/inactive lists as appropriate.
1703 spin_lock(&dev_priv
->mm
.active_list_lock
);
1704 while (!list_empty(&dev_priv
->mm
.active_list
)) {
1705 struct drm_gem_object
*obj
;
1706 struct drm_i915_gem_object
*obj_priv
;
1708 obj_priv
= list_first_entry(&dev_priv
->mm
.active_list
,
1709 struct drm_i915_gem_object
,
1711 obj
= obj_priv
->obj
;
1713 /* If the seqno being retired doesn't match the oldest in the
1714 * list, then the oldest in the list must still be newer than
1717 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1721 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1722 __func__
, request
->seqno
, obj
);
1725 if (obj
->write_domain
!= 0)
1726 i915_gem_object_move_to_flushing(obj
);
1728 /* Take a reference on the object so it won't be
1729 * freed while the spinlock is held. The list
1730 * protection for this spinlock is safe when breaking
1731 * the lock like this since the next thing we do
1732 * is just get the head of the list again.
1734 drm_gem_object_reference(obj
);
1735 i915_gem_object_move_to_inactive(obj
);
1736 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1737 drm_gem_object_unreference(obj
);
1738 spin_lock(&dev_priv
->mm
.active_list_lock
);
1742 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1746 * Returns true if seq1 is later than seq2.
1749 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1751 return (int32_t)(seq1
- seq2
) >= 0;
1755 i915_get_gem_seqno(struct drm_device
*dev
)
1757 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1759 return READ_HWSP(dev_priv
, I915_GEM_HWS_INDEX
);
1763 * This function clears the request list as sequence numbers are passed.
1766 i915_gem_retire_requests(struct drm_device
*dev
)
1768 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1771 if (!dev_priv
->hw_status_page
|| list_empty(&dev_priv
->mm
.request_list
))
1774 seqno
= i915_get_gem_seqno(dev
);
1776 while (!list_empty(&dev_priv
->mm
.request_list
)) {
1777 struct drm_i915_gem_request
*request
;
1778 uint32_t retiring_seqno
;
1780 request
= list_first_entry(&dev_priv
->mm
.request_list
,
1781 struct drm_i915_gem_request
,
1783 retiring_seqno
= request
->seqno
;
1785 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1786 atomic_read(&dev_priv
->mm
.wedged
)) {
1787 i915_gem_retire_request(dev
, request
);
1789 list_del(&request
->list
);
1790 list_del(&request
->client_list
);
1796 if (unlikely (dev_priv
->trace_irq_seqno
&&
1797 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1798 i915_user_irq_put(dev
);
1799 dev_priv
->trace_irq_seqno
= 0;
1804 i915_gem_retire_work_handler(struct work_struct
*work
)
1806 drm_i915_private_t
*dev_priv
;
1807 struct drm_device
*dev
;
1809 dev_priv
= container_of(work
, drm_i915_private_t
,
1810 mm
.retire_work
.work
);
1811 dev
= dev_priv
->dev
;
1813 mutex_lock(&dev
->struct_mutex
);
1814 i915_gem_retire_requests(dev
);
1815 if (!dev_priv
->mm
.suspended
&&
1816 !list_empty(&dev_priv
->mm
.request_list
))
1817 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1818 mutex_unlock(&dev
->struct_mutex
);
1822 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
, int interruptible
)
1824 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1830 if (atomic_read(&dev_priv
->mm
.wedged
))
1833 if (!i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
)) {
1835 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1837 ier
= I915_READ(IER
);
1839 DRM_ERROR("something (likely vbetool) disabled "
1840 "interrupts, re-enabling\n");
1841 i915_driver_irq_preinstall(dev
);
1842 i915_driver_irq_postinstall(dev
);
1845 trace_i915_gem_request_wait_begin(dev
, seqno
);
1847 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
1848 i915_user_irq_get(dev
);
1850 ret
= wait_event_interruptible(dev_priv
->irq_queue
,
1851 i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
) ||
1852 atomic_read(&dev_priv
->mm
.wedged
));
1854 wait_event(dev_priv
->irq_queue
,
1855 i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
) ||
1856 atomic_read(&dev_priv
->mm
.wedged
));
1858 i915_user_irq_put(dev
);
1859 dev_priv
->mm
.waiting_gem_seqno
= 0;
1861 trace_i915_gem_request_wait_end(dev
, seqno
);
1863 if (atomic_read(&dev_priv
->mm
.wedged
))
1866 if (ret
&& ret
!= -ERESTARTSYS
)
1867 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1868 __func__
, ret
, seqno
, i915_get_gem_seqno(dev
));
1870 /* Directly dispatch request retiring. While we have the work queue
1871 * to handle this, the waiter on a request often wants an associated
1872 * buffer to have made it to the inactive list, and we would need
1873 * a separate wait queue to handle that.
1876 i915_gem_retire_requests(dev
);
1882 * Waits for a sequence number to be signaled, and cleans up the
1883 * request and object lists appropriately for that event.
1886 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
)
1888 return i915_do_wait_request(dev
, seqno
, 1);
1892 * Waits for the ring to finish up to the latest request. Usefull for waiting
1893 * for flip events, e.g for the overlay support. */
1894 int i915_lp_ring_sync(struct drm_device
*dev
)
1899 seqno
= i915_add_request(dev
, NULL
, 0);
1904 ret
= i915_do_wait_request(dev
, seqno
, 0);
1905 BUG_ON(ret
== -ERESTARTSYS
);
1910 i915_gem_flush(struct drm_device
*dev
,
1911 uint32_t invalidate_domains
,
1912 uint32_t flush_domains
)
1914 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1919 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__
,
1920 invalidate_domains
, flush_domains
);
1922 trace_i915_gem_request_flush(dev
, dev_priv
->mm
.next_gem_seqno
,
1923 invalidate_domains
, flush_domains
);
1925 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1926 drm_agp_chipset_flush(dev
);
1928 if ((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) {
1930 * read/write caches:
1932 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1933 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1934 * also flushed at 2d versus 3d pipeline switches.
1938 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1939 * MI_READ_FLUSH is set, and is always flushed on 965.
1941 * I915_GEM_DOMAIN_COMMAND may not exist?
1943 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1944 * invalidated when MI_EXE_FLUSH is set.
1946 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1947 * invalidated with every MI_FLUSH.
1951 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1952 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1953 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1954 * are flushed at any MI_FLUSH.
1957 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1958 if ((invalidate_domains
|flush_domains
) &
1959 I915_GEM_DOMAIN_RENDER
)
1960 cmd
&= ~MI_NO_WRITE_FLUSH
;
1961 if (!IS_I965G(dev
)) {
1963 * On the 965, the sampler cache always gets flushed
1964 * and this bit is reserved.
1966 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
1967 cmd
|= MI_READ_FLUSH
;
1969 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
1970 cmd
|= MI_EXE_FLUSH
;
1973 DRM_INFO("%s: queue flush %08x to ring\n", __func__
, cmd
);
1983 * Ensures that all rendering to the object has completed and the object is
1984 * safe to unbind from the GTT or access from the CPU.
1987 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
1989 struct drm_device
*dev
= obj
->dev
;
1990 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1993 /* This function only exists to support waiting for existing rendering,
1994 * not for emitting required flushes.
1996 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1998 /* If there is rendering queued on the buffer being evicted, wait for
2001 if (obj_priv
->active
) {
2003 DRM_INFO("%s: object %p wait for seqno %08x\n",
2004 __func__
, obj
, obj_priv
->last_rendering_seqno
);
2006 ret
= i915_wait_request(dev
, obj_priv
->last_rendering_seqno
);
2015 * Unbinds an object from the GTT aperture.
2018 i915_gem_object_unbind(struct drm_gem_object
*obj
)
2020 struct drm_device
*dev
= obj
->dev
;
2021 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2025 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
2026 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
2028 if (obj_priv
->gtt_space
== NULL
)
2031 if (obj_priv
->pin_count
!= 0) {
2032 DRM_ERROR("Attempting to unbind pinned buffer\n");
2036 /* blow away mappings if mapped through GTT */
2037 i915_gem_release_mmap(obj
);
2039 /* Move the object to the CPU domain to ensure that
2040 * any possible CPU writes while it's not in the GTT
2041 * are flushed when we go to remap it. This will
2042 * also ensure that all pending GPU writes are finished
2045 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2047 if (ret
!= -ERESTARTSYS
)
2048 DRM_ERROR("set_domain failed: %d\n", ret
);
2052 BUG_ON(obj_priv
->active
);
2054 /* release the fence reg _after_ flushing */
2055 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2056 i915_gem_clear_fence_reg(obj
);
2058 if (obj_priv
->agp_mem
!= NULL
) {
2059 drm_unbind_agp(obj_priv
->agp_mem
);
2060 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2061 obj_priv
->agp_mem
= NULL
;
2064 i915_gem_object_put_pages(obj
);
2065 BUG_ON(obj_priv
->pages_refcount
);
2067 if (obj_priv
->gtt_space
) {
2068 atomic_dec(&dev
->gtt_count
);
2069 atomic_sub(obj
->size
, &dev
->gtt_memory
);
2071 drm_mm_put_block(obj_priv
->gtt_space
);
2072 obj_priv
->gtt_space
= NULL
;
2075 /* Remove ourselves from the LRU list if present. */
2076 if (!list_empty(&obj_priv
->list
))
2077 list_del_init(&obj_priv
->list
);
2079 if (i915_gem_object_is_purgeable(obj_priv
))
2080 i915_gem_object_truncate(obj
);
2082 trace_i915_gem_object_unbind(obj
);
2087 static struct drm_gem_object
*
2088 i915_gem_find_inactive_object(struct drm_device
*dev
, int min_size
)
2090 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2091 struct drm_i915_gem_object
*obj_priv
;
2092 struct drm_gem_object
*best
= NULL
;
2093 struct drm_gem_object
*first
= NULL
;
2095 /* Try to find the smallest clean object */
2096 list_for_each_entry(obj_priv
, &dev_priv
->mm
.inactive_list
, list
) {
2097 struct drm_gem_object
*obj
= obj_priv
->obj
;
2098 if (obj
->size
>= min_size
) {
2099 if ((!obj_priv
->dirty
||
2100 i915_gem_object_is_purgeable(obj_priv
)) &&
2101 (!best
|| obj
->size
< best
->size
)) {
2103 if (best
->size
== min_size
)
2111 return best
? best
: first
;
2115 i915_gem_evict_everything(struct drm_device
*dev
)
2117 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2122 spin_lock(&dev_priv
->mm
.active_list_lock
);
2123 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2124 list_empty(&dev_priv
->mm
.flushing_list
) &&
2125 list_empty(&dev_priv
->mm
.active_list
));
2126 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2131 /* Flush everything (on to the inactive lists) and evict */
2132 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2133 seqno
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
);
2137 ret
= i915_wait_request(dev
, seqno
);
2141 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
2143 ret
= i915_gem_evict_from_inactive_list(dev
);
2147 spin_lock(&dev_priv
->mm
.active_list_lock
);
2148 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2149 list_empty(&dev_priv
->mm
.flushing_list
) &&
2150 list_empty(&dev_priv
->mm
.active_list
));
2151 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2152 BUG_ON(!lists_empty
);
2158 i915_gem_evict_something(struct drm_device
*dev
, int min_size
)
2160 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2161 struct drm_gem_object
*obj
;
2165 i915_gem_retire_requests(dev
);
2167 /* If there's an inactive buffer available now, grab it
2170 obj
= i915_gem_find_inactive_object(dev
, min_size
);
2172 struct drm_i915_gem_object
*obj_priv
;
2175 DRM_INFO("%s: evicting %p\n", __func__
, obj
);
2177 obj_priv
= obj
->driver_private
;
2178 BUG_ON(obj_priv
->pin_count
!= 0);
2179 BUG_ON(obj_priv
->active
);
2181 /* Wait on the rendering and unbind the buffer. */
2182 return i915_gem_object_unbind(obj
);
2185 /* If we didn't get anything, but the ring is still processing
2186 * things, wait for the next to finish and hopefully leave us
2187 * a buffer to evict.
2189 if (!list_empty(&dev_priv
->mm
.request_list
)) {
2190 struct drm_i915_gem_request
*request
;
2192 request
= list_first_entry(&dev_priv
->mm
.request_list
,
2193 struct drm_i915_gem_request
,
2196 ret
= i915_wait_request(dev
, request
->seqno
);
2203 /* If we didn't have anything on the request list but there
2204 * are buffers awaiting a flush, emit one and try again.
2205 * When we wait on it, those buffers waiting for that flush
2206 * will get moved to inactive.
2208 if (!list_empty(&dev_priv
->mm
.flushing_list
)) {
2209 struct drm_i915_gem_object
*obj_priv
;
2211 /* Find an object that we can immediately reuse */
2212 list_for_each_entry(obj_priv
, &dev_priv
->mm
.flushing_list
, list
) {
2213 obj
= obj_priv
->obj
;
2214 if (obj
->size
>= min_size
)
2226 seqno
= i915_add_request(dev
, NULL
, obj
->write_domain
);
2230 ret
= i915_wait_request(dev
, seqno
);
2238 /* If we didn't do any of the above, there's no single buffer
2239 * large enough to swap out for the new one, so just evict
2240 * everything and start again. (This should be rare.)
2242 if (!list_empty (&dev_priv
->mm
.inactive_list
))
2243 return i915_gem_evict_from_inactive_list(dev
);
2245 return i915_gem_evict_everything(dev
);
2250 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2253 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2255 struct address_space
*mapping
;
2256 struct inode
*inode
;
2259 if (obj_priv
->pages_refcount
++ != 0)
2262 /* Get the list of pages out of our struct file. They'll be pinned
2263 * at this point until we release them.
2265 page_count
= obj
->size
/ PAGE_SIZE
;
2266 BUG_ON(obj_priv
->pages
!= NULL
);
2267 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2268 if (obj_priv
->pages
== NULL
) {
2269 obj_priv
->pages_refcount
--;
2273 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2274 mapping
= inode
->i_mapping
;
2275 for (i
= 0; i
< page_count
; i
++) {
2276 page
= read_cache_page_gfp(mapping
, i
,
2284 obj_priv
->pages
[i
] = page
;
2287 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2288 i915_gem_object_do_bit_17_swizzle(obj
);
2294 page_cache_release(obj_priv
->pages
[i
]);
2296 drm_free_large(obj_priv
->pages
);
2297 obj_priv
->pages
= NULL
;
2298 obj_priv
->pages_refcount
--;
2299 return PTR_ERR(page
);
2302 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2304 struct drm_gem_object
*obj
= reg
->obj
;
2305 struct drm_device
*dev
= obj
->dev
;
2306 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2307 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2308 int regnum
= obj_priv
->fence_reg
;
2311 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2313 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2314 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2315 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2316 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2317 val
|= I965_FENCE_REG_VALID
;
2319 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2322 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2324 struct drm_gem_object
*obj
= reg
->obj
;
2325 struct drm_device
*dev
= obj
->dev
;
2326 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2327 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2328 int regnum
= obj_priv
->fence_reg
;
2330 uint32_t fence_reg
, val
;
2333 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2334 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2335 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2336 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2340 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2341 HAS_128_BYTE_Y_TILING(dev
))
2346 /* Note: pitch better be a power of two tile widths */
2347 pitch_val
= obj_priv
->stride
/ tile_width
;
2348 pitch_val
= ffs(pitch_val
) - 1;
2350 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2351 HAS_128_BYTE_Y_TILING(dev
))
2352 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2354 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2356 val
= obj_priv
->gtt_offset
;
2357 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2358 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2359 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2360 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2361 val
|= I830_FENCE_REG_VALID
;
2364 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2366 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2367 I915_WRITE(fence_reg
, val
);
2370 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2372 struct drm_gem_object
*obj
= reg
->obj
;
2373 struct drm_device
*dev
= obj
->dev
;
2374 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2375 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2376 int regnum
= obj_priv
->fence_reg
;
2379 uint32_t fence_size_bits
;
2381 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2382 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2383 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2384 __func__
, obj_priv
->gtt_offset
);
2388 pitch_val
= obj_priv
->stride
/ 128;
2389 pitch_val
= ffs(pitch_val
) - 1;
2390 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2392 val
= obj_priv
->gtt_offset
;
2393 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2394 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2395 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2396 WARN_ON(fence_size_bits
& ~0x00000f00);
2397 val
|= fence_size_bits
;
2398 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2399 val
|= I830_FENCE_REG_VALID
;
2401 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2405 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2406 * @obj: object to map through a fence reg
2408 * When mapping objects through the GTT, userspace wants to be able to write
2409 * to them without having to worry about swizzling if the object is tiled.
2411 * This function walks the fence regs looking for a free one for @obj,
2412 * stealing one if it can't find any.
2414 * It then sets up the reg based on the object's properties: address, pitch
2415 * and tiling format.
2418 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
)
2420 struct drm_device
*dev
= obj
->dev
;
2421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2422 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2423 struct drm_i915_fence_reg
*reg
= NULL
;
2424 struct drm_i915_gem_object
*old_obj_priv
= NULL
;
2427 /* Just update our place in the LRU if our fence is getting used. */
2428 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2429 list_move_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2433 switch (obj_priv
->tiling_mode
) {
2434 case I915_TILING_NONE
:
2435 WARN(1, "allocating a fence for non-tiled object?\n");
2438 if (!obj_priv
->stride
)
2440 WARN((obj_priv
->stride
& (512 - 1)),
2441 "object 0x%08x is X tiled but has non-512B pitch\n",
2442 obj_priv
->gtt_offset
);
2445 if (!obj_priv
->stride
)
2447 WARN((obj_priv
->stride
& (128 - 1)),
2448 "object 0x%08x is Y tiled but has non-128B pitch\n",
2449 obj_priv
->gtt_offset
);
2453 /* First try to find a free reg */
2455 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2456 reg
= &dev_priv
->fence_regs
[i
];
2460 old_obj_priv
= reg
->obj
->driver_private
;
2461 if (!old_obj_priv
->pin_count
)
2465 /* None available, try to steal one or wait for a user to finish */
2466 if (i
== dev_priv
->num_fence_regs
) {
2467 struct drm_gem_object
*old_obj
= NULL
;
2472 list_for_each_entry(old_obj_priv
, &dev_priv
->mm
.fence_list
,
2474 old_obj
= old_obj_priv
->obj
;
2476 if (old_obj_priv
->pin_count
)
2479 /* Take a reference, as otherwise the wait_rendering
2480 * below may cause the object to get freed out from
2483 drm_gem_object_reference(old_obj
);
2485 /* i915 uses fences for GPU access to tiled buffers */
2486 if (IS_I965G(dev
) || !old_obj_priv
->active
)
2489 /* This brings the object to the head of the LRU if it
2490 * had been written to. The only way this should
2491 * result in us waiting longer than the expected
2492 * optimal amount of time is if there was a
2493 * fence-using buffer later that was read-only.
2495 i915_gem_object_flush_gpu_write_domain(old_obj
);
2496 ret
= i915_gem_object_wait_rendering(old_obj
);
2498 drm_gem_object_unreference(old_obj
);
2506 * Zap this virtual mapping so we can set up a fence again
2507 * for this object next time we need it.
2509 i915_gem_release_mmap(old_obj
);
2511 i
= old_obj_priv
->fence_reg
;
2512 reg
= &dev_priv
->fence_regs
[i
];
2514 old_obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2515 list_del_init(&old_obj_priv
->fence_list
);
2517 drm_gem_object_unreference(old_obj
);
2520 obj_priv
->fence_reg
= i
;
2521 list_add_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2526 i965_write_fence_reg(reg
);
2527 else if (IS_I9XX(dev
))
2528 i915_write_fence_reg(reg
);
2530 i830_write_fence_reg(reg
);
2532 trace_i915_gem_object_get_fence(obj
, i
, obj_priv
->tiling_mode
);
2538 * i915_gem_clear_fence_reg - clear out fence register info
2539 * @obj: object to clear
2541 * Zeroes out the fence register itself and clears out the associated
2542 * data structures in dev_priv and obj_priv.
2545 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2547 struct drm_device
*dev
= obj
->dev
;
2548 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2549 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2552 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2556 if (obj_priv
->fence_reg
< 8)
2557 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2559 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
-
2562 I915_WRITE(fence_reg
, 0);
2565 dev_priv
->fence_regs
[obj_priv
->fence_reg
].obj
= NULL
;
2566 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2567 list_del_init(&obj_priv
->fence_list
);
2571 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2572 * to the buffer to finish, and then resets the fence register.
2573 * @obj: tiled object holding a fence register.
2575 * Zeroes out the fence register itself and clears out the associated
2576 * data structures in dev_priv and obj_priv.
2579 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
)
2581 struct drm_device
*dev
= obj
->dev
;
2582 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2584 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2587 /* On the i915, GPU access to tiled buffers is via a fence,
2588 * therefore we must wait for any outstanding access to complete
2589 * before clearing the fence.
2591 if (!IS_I965G(dev
)) {
2594 i915_gem_object_flush_gpu_write_domain(obj
);
2595 i915_gem_object_flush_gtt_write_domain(obj
);
2596 ret
= i915_gem_object_wait_rendering(obj
);
2601 i915_gem_clear_fence_reg (obj
);
2607 * Finds free space in the GTT aperture and binds the object there.
2610 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2612 struct drm_device
*dev
= obj
->dev
;
2613 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2614 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2615 struct drm_mm_node
*free_space
;
2616 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2619 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2620 DRM_ERROR("Attempting to bind a purgeable object\n");
2625 alignment
= i915_gem_get_gtt_alignment(obj
);
2626 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2627 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2631 /* If the object is bigger than the entire aperture, reject it early
2632 * before evicting everything in a vain attempt to find space.
2634 if (obj
->size
> dev
->gtt_total
) {
2635 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2640 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2641 obj
->size
, alignment
, 0);
2642 if (free_space
!= NULL
) {
2643 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2645 if (obj_priv
->gtt_space
!= NULL
) {
2646 obj_priv
->gtt_space
->private = obj
;
2647 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2650 if (obj_priv
->gtt_space
== NULL
) {
2651 /* If the gtt is empty and we're still having trouble
2652 * fitting our object in, we're out of memory.
2655 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2657 ret
= i915_gem_evict_something(dev
, obj
->size
);
2665 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2666 obj
->size
, obj_priv
->gtt_offset
);
2668 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2670 drm_mm_put_block(obj_priv
->gtt_space
);
2671 obj_priv
->gtt_space
= NULL
;
2673 if (ret
== -ENOMEM
) {
2674 /* first try to clear up some space from the GTT */
2675 ret
= i915_gem_evict_something(dev
, obj
->size
);
2677 /* now try to shrink everyone else */
2692 /* Create an AGP memory structure pointing at our pages, and bind it
2695 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2697 obj
->size
>> PAGE_SHIFT
,
2698 obj_priv
->gtt_offset
,
2699 obj_priv
->agp_type
);
2700 if (obj_priv
->agp_mem
== NULL
) {
2701 i915_gem_object_put_pages(obj
);
2702 drm_mm_put_block(obj_priv
->gtt_space
);
2703 obj_priv
->gtt_space
= NULL
;
2705 ret
= i915_gem_evict_something(dev
, obj
->size
);
2711 atomic_inc(&dev
->gtt_count
);
2712 atomic_add(obj
->size
, &dev
->gtt_memory
);
2714 /* Assert that the object is not currently in any GPU domain. As it
2715 * wasn't in the GTT, there shouldn't be any way it could have been in
2718 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2719 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2721 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2727 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2729 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2731 /* If we don't have a page list set up, then we're not pinned
2732 * to GPU, and we can ignore the cache flush because it'll happen
2733 * again at bind time.
2735 if (obj_priv
->pages
== NULL
)
2738 trace_i915_gem_object_clflush(obj
);
2740 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2743 /** Flushes any GPU write domain for the object if it's dirty. */
2745 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
2747 struct drm_device
*dev
= obj
->dev
;
2749 uint32_t old_write_domain
;
2751 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2754 /* Queue the GPU write cache flushing we need. */
2755 old_write_domain
= obj
->write_domain
;
2756 i915_gem_flush(dev
, 0, obj
->write_domain
);
2757 seqno
= i915_add_request(dev
, NULL
, obj
->write_domain
);
2758 BUG_ON(obj
->write_domain
);
2759 i915_gem_object_move_to_active(obj
, seqno
);
2761 trace_i915_gem_object_change_domain(obj
,
2766 /** Flushes the GTT write domain for the object if it's dirty. */
2768 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2770 uint32_t old_write_domain
;
2772 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2775 /* No actual flushing is required for the GTT write domain. Writes
2776 * to it immediately go to main memory as far as we know, so there's
2777 * no chipset flush. It also doesn't land in render cache.
2779 old_write_domain
= obj
->write_domain
;
2780 obj
->write_domain
= 0;
2782 trace_i915_gem_object_change_domain(obj
,
2787 /** Flushes the CPU write domain for the object if it's dirty. */
2789 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2791 struct drm_device
*dev
= obj
->dev
;
2792 uint32_t old_write_domain
;
2794 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2797 i915_gem_clflush_object(obj
);
2798 drm_agp_chipset_flush(dev
);
2799 old_write_domain
= obj
->write_domain
;
2800 obj
->write_domain
= 0;
2802 trace_i915_gem_object_change_domain(obj
,
2808 * Moves a single object to the GTT read, and possibly write domain.
2810 * This function returns when the move is complete, including waiting on
2814 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2816 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2817 uint32_t old_write_domain
, old_read_domains
;
2820 /* Not valid to be called on unbound objects. */
2821 if (obj_priv
->gtt_space
== NULL
)
2824 i915_gem_object_flush_gpu_write_domain(obj
);
2825 /* Wait on any GPU rendering and flushing to occur. */
2826 ret
= i915_gem_object_wait_rendering(obj
);
2830 old_write_domain
= obj
->write_domain
;
2831 old_read_domains
= obj
->read_domains
;
2833 /* If we're writing through the GTT domain, then CPU and GPU caches
2834 * will need to be invalidated at next use.
2837 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2839 i915_gem_object_flush_cpu_write_domain(obj
);
2841 /* It should now be out of any other write domains, and we can update
2842 * the domain values for our changes.
2844 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2845 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2847 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2848 obj_priv
->dirty
= 1;
2851 trace_i915_gem_object_change_domain(obj
,
2859 * Prepare buffer for display plane. Use uninterruptible for possible flush
2860 * wait, as in modesetting process we're not supposed to be interrupted.
2863 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
)
2865 struct drm_device
*dev
= obj
->dev
;
2866 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2867 uint32_t old_write_domain
, old_read_domains
;
2870 /* Not valid to be called on unbound objects. */
2871 if (obj_priv
->gtt_space
== NULL
)
2874 i915_gem_object_flush_gpu_write_domain(obj
);
2876 /* Wait on any GPU rendering and flushing to occur. */
2877 if (obj_priv
->active
) {
2879 DRM_INFO("%s: object %p wait for seqno %08x\n",
2880 __func__
, obj
, obj_priv
->last_rendering_seqno
);
2882 ret
= i915_do_wait_request(dev
, obj_priv
->last_rendering_seqno
, 0);
2887 old_write_domain
= obj
->write_domain
;
2888 old_read_domains
= obj
->read_domains
;
2890 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2892 i915_gem_object_flush_cpu_write_domain(obj
);
2894 /* It should now be out of any other write domains, and we can update
2895 * the domain values for our changes.
2897 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2898 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2899 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2900 obj_priv
->dirty
= 1;
2902 trace_i915_gem_object_change_domain(obj
,
2910 * Moves a single object to the CPU read, and possibly write domain.
2912 * This function returns when the move is complete, including waiting on
2916 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2918 uint32_t old_write_domain
, old_read_domains
;
2921 i915_gem_object_flush_gpu_write_domain(obj
);
2922 /* Wait on any GPU rendering and flushing to occur. */
2923 ret
= i915_gem_object_wait_rendering(obj
);
2927 i915_gem_object_flush_gtt_write_domain(obj
);
2929 /* If we have a partially-valid cache of the object in the CPU,
2930 * finish invalidating it and free the per-page flags.
2932 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2934 old_write_domain
= obj
->write_domain
;
2935 old_read_domains
= obj
->read_domains
;
2937 /* Flush the CPU cache if it's still invalid. */
2938 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2939 i915_gem_clflush_object(obj
);
2941 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2944 /* It should now be out of any other write domains, and we can update
2945 * the domain values for our changes.
2947 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2949 /* If we're writing through the CPU, then the GPU read domains will
2950 * need to be invalidated at next use.
2953 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2954 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2957 trace_i915_gem_object_change_domain(obj
,
2965 * Set the next domain for the specified object. This
2966 * may not actually perform the necessary flushing/invaliding though,
2967 * as that may want to be batched with other set_domain operations
2969 * This is (we hope) the only really tricky part of gem. The goal
2970 * is fairly simple -- track which caches hold bits of the object
2971 * and make sure they remain coherent. A few concrete examples may
2972 * help to explain how it works. For shorthand, we use the notation
2973 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2974 * a pair of read and write domain masks.
2976 * Case 1: the batch buffer
2982 * 5. Unmapped from GTT
2985 * Let's take these a step at a time
2988 * Pages allocated from the kernel may still have
2989 * cache contents, so we set them to (CPU, CPU) always.
2990 * 2. Written by CPU (using pwrite)
2991 * The pwrite function calls set_domain (CPU, CPU) and
2992 * this function does nothing (as nothing changes)
2994 * This function asserts that the object is not
2995 * currently in any GPU-based read or write domains
2997 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2998 * As write_domain is zero, this function adds in the
2999 * current read domains (CPU+COMMAND, 0).
3000 * flush_domains is set to CPU.
3001 * invalidate_domains is set to COMMAND
3002 * clflush is run to get data out of the CPU caches
3003 * then i915_dev_set_domain calls i915_gem_flush to
3004 * emit an MI_FLUSH and drm_agp_chipset_flush
3005 * 5. Unmapped from GTT
3006 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3007 * flush_domains and invalidate_domains end up both zero
3008 * so no flushing/invalidating happens
3012 * Case 2: The shared render buffer
3016 * 3. Read/written by GPU
3017 * 4. set_domain to (CPU,CPU)
3018 * 5. Read/written by CPU
3019 * 6. Read/written by GPU
3022 * Same as last example, (CPU, CPU)
3024 * Nothing changes (assertions find that it is not in the GPU)
3025 * 3. Read/written by GPU
3026 * execbuffer calls set_domain (RENDER, RENDER)
3027 * flush_domains gets CPU
3028 * invalidate_domains gets GPU
3030 * MI_FLUSH and drm_agp_chipset_flush
3031 * 4. set_domain (CPU, CPU)
3032 * flush_domains gets GPU
3033 * invalidate_domains gets CPU
3034 * wait_rendering (obj) to make sure all drawing is complete.
3035 * This will include an MI_FLUSH to get the data from GPU
3037 * clflush (obj) to invalidate the CPU cache
3038 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3039 * 5. Read/written by CPU
3040 * cache lines are loaded and dirtied
3041 * 6. Read written by GPU
3042 * Same as last GPU access
3044 * Case 3: The constant buffer
3049 * 4. Updated (written) by CPU again
3058 * flush_domains = CPU
3059 * invalidate_domains = RENDER
3062 * drm_agp_chipset_flush
3063 * 4. Updated (written) by CPU again
3065 * flush_domains = 0 (no previous write domain)
3066 * invalidate_domains = 0 (no new read domains)
3069 * flush_domains = CPU
3070 * invalidate_domains = RENDER
3073 * drm_agp_chipset_flush
3076 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
3078 struct drm_device
*dev
= obj
->dev
;
3079 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3080 uint32_t invalidate_domains
= 0;
3081 uint32_t flush_domains
= 0;
3082 uint32_t old_read_domains
;
3084 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
3085 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
3087 intel_mark_busy(dev
, obj
);
3090 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3092 obj
->read_domains
, obj
->pending_read_domains
,
3093 obj
->write_domain
, obj
->pending_write_domain
);
3096 * If the object isn't moving to a new write domain,
3097 * let the object stay in multiple read domains
3099 if (obj
->pending_write_domain
== 0)
3100 obj
->pending_read_domains
|= obj
->read_domains
;
3102 obj_priv
->dirty
= 1;
3105 * Flush the current write domain if
3106 * the new read domains don't match. Invalidate
3107 * any read domains which differ from the old
3110 if (obj
->write_domain
&&
3111 obj
->write_domain
!= obj
->pending_read_domains
) {
3112 flush_domains
|= obj
->write_domain
;
3113 invalidate_domains
|=
3114 obj
->pending_read_domains
& ~obj
->write_domain
;
3117 * Invalidate any read caches which may have
3118 * stale data. That is, any new read domains.
3120 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3121 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
3123 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3124 __func__
, flush_domains
, invalidate_domains
);
3126 i915_gem_clflush_object(obj
);
3129 old_read_domains
= obj
->read_domains
;
3131 /* The actual obj->write_domain will be updated with
3132 * pending_write_domain after we emit the accumulated flush for all
3133 * of our domain changes in execbuffers (which clears objects'
3134 * write_domains). So if we have a current write domain that we
3135 * aren't changing, set pending_write_domain to that.
3137 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3138 obj
->pending_write_domain
= obj
->write_domain
;
3139 obj
->read_domains
= obj
->pending_read_domains
;
3141 dev
->invalidate_domains
|= invalidate_domains
;
3142 dev
->flush_domains
|= flush_domains
;
3144 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3146 obj
->read_domains
, obj
->write_domain
,
3147 dev
->invalidate_domains
, dev
->flush_domains
);
3150 trace_i915_gem_object_change_domain(obj
,
3156 * Moves the object from a partially CPU read to a full one.
3158 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3159 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3162 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3164 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3166 if (!obj_priv
->page_cpu_valid
)
3169 /* If we're partially in the CPU read domain, finish moving it in.
3171 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3174 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3175 if (obj_priv
->page_cpu_valid
[i
])
3177 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3181 /* Free the page_cpu_valid mappings which are now stale, whether
3182 * or not we've got I915_GEM_DOMAIN_CPU.
3184 kfree(obj_priv
->page_cpu_valid
);
3185 obj_priv
->page_cpu_valid
= NULL
;
3189 * Set the CPU read domain on a range of the object.
3191 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3192 * not entirely valid. The page_cpu_valid member of the object flags which
3193 * pages have been flushed, and will be respected by
3194 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3195 * of the whole object.
3197 * This function returns when the move is complete, including waiting on
3201 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3202 uint64_t offset
, uint64_t size
)
3204 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3205 uint32_t old_read_domains
;
3208 if (offset
== 0 && size
== obj
->size
)
3209 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3211 i915_gem_object_flush_gpu_write_domain(obj
);
3212 /* Wait on any GPU rendering and flushing to occur. */
3213 ret
= i915_gem_object_wait_rendering(obj
);
3216 i915_gem_object_flush_gtt_write_domain(obj
);
3218 /* If we're already fully in the CPU read domain, we're done. */
3219 if (obj_priv
->page_cpu_valid
== NULL
&&
3220 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3223 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3224 * newly adding I915_GEM_DOMAIN_CPU
3226 if (obj_priv
->page_cpu_valid
== NULL
) {
3227 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3229 if (obj_priv
->page_cpu_valid
== NULL
)
3231 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3232 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3234 /* Flush the cache on any pages that are still invalid from the CPU's
3237 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3239 if (obj_priv
->page_cpu_valid
[i
])
3242 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3244 obj_priv
->page_cpu_valid
[i
] = 1;
3247 /* It should now be out of any other write domains, and we can update
3248 * the domain values for our changes.
3250 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3252 old_read_domains
= obj
->read_domains
;
3253 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3255 trace_i915_gem_object_change_domain(obj
,
3263 * Pin an object to the GTT and evaluate the relocations landing in it.
3266 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3267 struct drm_file
*file_priv
,
3268 struct drm_i915_gem_exec_object
*entry
,
3269 struct drm_i915_gem_relocation_entry
*relocs
)
3271 struct drm_device
*dev
= obj
->dev
;
3272 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3273 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3275 void __iomem
*reloc_page
;
3277 /* Choose the GTT offset for our buffer and put it there. */
3278 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3282 entry
->offset
= obj_priv
->gtt_offset
;
3284 /* Apply the relocations, using the GTT aperture to avoid cache
3285 * flushing requirements.
3287 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3288 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3289 struct drm_gem_object
*target_obj
;
3290 struct drm_i915_gem_object
*target_obj_priv
;
3291 uint32_t reloc_val
, reloc_offset
;
3292 uint32_t __iomem
*reloc_entry
;
3294 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3295 reloc
->target_handle
);
3296 if (target_obj
== NULL
) {
3297 i915_gem_object_unpin(obj
);
3300 target_obj_priv
= target_obj
->driver_private
;
3303 DRM_INFO("%s: obj %p offset %08x target %d "
3304 "read %08x write %08x gtt %08x "
3305 "presumed %08x delta %08x\n",
3308 (int) reloc
->offset
,
3309 (int) reloc
->target_handle
,
3310 (int) reloc
->read_domains
,
3311 (int) reloc
->write_domain
,
3312 (int) target_obj_priv
->gtt_offset
,
3313 (int) reloc
->presumed_offset
,
3317 /* The target buffer should have appeared before us in the
3318 * exec_object list, so it should have a GTT space bound by now.
3320 if (target_obj_priv
->gtt_space
== NULL
) {
3321 DRM_ERROR("No GTT space found for object %d\n",
3322 reloc
->target_handle
);
3323 drm_gem_object_unreference(target_obj
);
3324 i915_gem_object_unpin(obj
);
3328 /* Validate that the target is in a valid r/w GPU domain */
3329 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3330 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3331 DRM_ERROR("reloc with read/write CPU domains: "
3332 "obj %p target %d offset %d "
3333 "read %08x write %08x",
3334 obj
, reloc
->target_handle
,
3335 (int) reloc
->offset
,
3336 reloc
->read_domains
,
3337 reloc
->write_domain
);
3338 drm_gem_object_unreference(target_obj
);
3339 i915_gem_object_unpin(obj
);
3342 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3343 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3344 DRM_ERROR("Write domain conflict: "
3345 "obj %p target %d offset %d "
3346 "new %08x old %08x\n",
3347 obj
, reloc
->target_handle
,
3348 (int) reloc
->offset
,
3349 reloc
->write_domain
,
3350 target_obj
->pending_write_domain
);
3351 drm_gem_object_unreference(target_obj
);
3352 i915_gem_object_unpin(obj
);
3356 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3357 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3359 /* If the relocation already has the right value in it, no
3360 * more work needs to be done.
3362 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3363 drm_gem_object_unreference(target_obj
);
3367 /* Check that the relocation address is valid... */
3368 if (reloc
->offset
> obj
->size
- 4) {
3369 DRM_ERROR("Relocation beyond object bounds: "
3370 "obj %p target %d offset %d size %d.\n",
3371 obj
, reloc
->target_handle
,
3372 (int) reloc
->offset
, (int) obj
->size
);
3373 drm_gem_object_unreference(target_obj
);
3374 i915_gem_object_unpin(obj
);
3377 if (reloc
->offset
& 3) {
3378 DRM_ERROR("Relocation not 4-byte aligned: "
3379 "obj %p target %d offset %d.\n",
3380 obj
, reloc
->target_handle
,
3381 (int) reloc
->offset
);
3382 drm_gem_object_unreference(target_obj
);
3383 i915_gem_object_unpin(obj
);
3387 /* and points to somewhere within the target object. */
3388 if (reloc
->delta
>= target_obj
->size
) {
3389 DRM_ERROR("Relocation beyond target object bounds: "
3390 "obj %p target %d delta %d size %d.\n",
3391 obj
, reloc
->target_handle
,
3392 (int) reloc
->delta
, (int) target_obj
->size
);
3393 drm_gem_object_unreference(target_obj
);
3394 i915_gem_object_unpin(obj
);
3398 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3400 drm_gem_object_unreference(target_obj
);
3401 i915_gem_object_unpin(obj
);
3405 /* Map the page containing the relocation we're going to
3408 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3409 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3412 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3413 (reloc_offset
& (PAGE_SIZE
- 1)));
3414 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3417 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3418 obj
, (unsigned int) reloc
->offset
,
3419 readl(reloc_entry
), reloc_val
);
3421 writel(reloc_val
, reloc_entry
);
3422 io_mapping_unmap_atomic(reloc_page
);
3424 /* The updated presumed offset for this entry will be
3425 * copied back out to the user.
3427 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3429 drm_gem_object_unreference(target_obj
);
3434 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3439 /** Dispatch a batchbuffer to the ring
3442 i915_dispatch_gem_execbuffer(struct drm_device
*dev
,
3443 struct drm_i915_gem_execbuffer
*exec
,
3444 struct drm_clip_rect
*cliprects
,
3445 uint64_t exec_offset
)
3447 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3448 int nbox
= exec
->num_cliprects
;
3450 uint32_t exec_start
, exec_len
;
3453 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3454 exec_len
= (uint32_t) exec
->batch_len
;
3456 trace_i915_gem_request_submit(dev
, dev_priv
->mm
.next_gem_seqno
+ 1);
3458 count
= nbox
? nbox
: 1;
3460 for (i
= 0; i
< count
; i
++) {
3462 int ret
= i915_emit_box(dev
, cliprects
, i
,
3463 exec
->DR1
, exec
->DR4
);
3468 if (IS_I830(dev
) || IS_845G(dev
)) {
3470 OUT_RING(MI_BATCH_BUFFER
);
3471 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3472 OUT_RING(exec_start
+ exec_len
- 4);
3477 if (IS_I965G(dev
)) {
3478 OUT_RING(MI_BATCH_BUFFER_START
|
3480 MI_BATCH_NON_SECURE_I965
);
3481 OUT_RING(exec_start
);
3483 OUT_RING(MI_BATCH_BUFFER_START
|
3485 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3491 /* XXX breadcrumb */
3495 /* Throttle our rendering by waiting until the ring has completed our requests
3496 * emitted over 20 msec ago.
3498 * Note that if we were to use the current jiffies each time around the loop,
3499 * we wouldn't escape the function with any frames outstanding if the time to
3500 * render a frame was over 20ms.
3502 * This should get us reasonable parallelism between CPU and GPU but also
3503 * relatively low latency when blocking on a particular request to finish.
3506 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3508 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3510 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3512 mutex_lock(&dev
->struct_mutex
);
3513 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3514 struct drm_i915_gem_request
*request
;
3516 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3517 struct drm_i915_gem_request
,
3520 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3523 ret
= i915_wait_request(dev
, request
->seqno
);
3527 mutex_unlock(&dev
->struct_mutex
);
3533 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object
*exec_list
,
3534 uint32_t buffer_count
,
3535 struct drm_i915_gem_relocation_entry
**relocs
)
3537 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3541 for (i
= 0; i
< buffer_count
; i
++) {
3542 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3544 reloc_count
+= exec_list
[i
].relocation_count
;
3547 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3548 if (*relocs
== NULL
)
3551 for (i
= 0; i
< buffer_count
; i
++) {
3552 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3554 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3556 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3558 exec_list
[i
].relocation_count
*
3561 drm_free_large(*relocs
);
3566 reloc_index
+= exec_list
[i
].relocation_count
;
3573 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object
*exec_list
,
3574 uint32_t buffer_count
,
3575 struct drm_i915_gem_relocation_entry
*relocs
)
3577 uint32_t reloc_count
= 0, i
;
3580 for (i
= 0; i
< buffer_count
; i
++) {
3581 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3584 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3586 unwritten
= copy_to_user(user_relocs
,
3587 &relocs
[reloc_count
],
3588 exec_list
[i
].relocation_count
*
3596 reloc_count
+= exec_list
[i
].relocation_count
;
3600 drm_free_large(relocs
);
3606 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer
*exec
,
3607 uint64_t exec_offset
)
3609 uint32_t exec_start
, exec_len
;
3611 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3612 exec_len
= (uint32_t) exec
->batch_len
;
3614 if ((exec_start
| exec_len
) & 0x7)
3624 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3625 struct drm_file
*file_priv
)
3627 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3628 struct drm_i915_gem_execbuffer
*args
= data
;
3629 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3630 struct drm_gem_object
**object_list
= NULL
;
3631 struct drm_gem_object
*batch_obj
;
3632 struct drm_i915_gem_object
*obj_priv
;
3633 struct drm_clip_rect
*cliprects
= NULL
;
3634 struct drm_i915_gem_relocation_entry
*relocs
;
3635 int ret
, ret2
, i
, pinned
= 0;
3636 uint64_t exec_offset
;
3637 uint32_t seqno
, flush_domains
, reloc_index
;
3641 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3642 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3645 if (args
->buffer_count
< 1) {
3646 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3649 /* Copy in the exec list from userland */
3650 exec_list
= drm_calloc_large(sizeof(*exec_list
), args
->buffer_count
);
3651 object_list
= drm_calloc_large(sizeof(*object_list
), args
->buffer_count
);
3652 if (exec_list
== NULL
|| object_list
== NULL
) {
3653 DRM_ERROR("Failed to allocate exec or object list "
3655 args
->buffer_count
);
3659 ret
= copy_from_user(exec_list
,
3660 (struct drm_i915_relocation_entry __user
*)
3661 (uintptr_t) args
->buffers_ptr
,
3662 sizeof(*exec_list
) * args
->buffer_count
);
3664 DRM_ERROR("copy %d exec entries failed %d\n",
3665 args
->buffer_count
, ret
);
3669 if (args
->num_cliprects
!= 0) {
3670 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3672 if (cliprects
== NULL
)
3675 ret
= copy_from_user(cliprects
,
3676 (struct drm_clip_rect __user
*)
3677 (uintptr_t) args
->cliprects_ptr
,
3678 sizeof(*cliprects
) * args
->num_cliprects
);
3680 DRM_ERROR("copy %d cliprects failed: %d\n",
3681 args
->num_cliprects
, ret
);
3687 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3692 mutex_lock(&dev
->struct_mutex
);
3694 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3696 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3697 DRM_ERROR("Execbuf while wedged\n");
3698 mutex_unlock(&dev
->struct_mutex
);
3703 if (dev_priv
->mm
.suspended
) {
3704 DRM_ERROR("Execbuf while VT-switched.\n");
3705 mutex_unlock(&dev
->struct_mutex
);
3710 /* Look up object handles */
3711 for (i
= 0; i
< args
->buffer_count
; i
++) {
3712 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3713 exec_list
[i
].handle
);
3714 if (object_list
[i
] == NULL
) {
3715 DRM_ERROR("Invalid object handle %d at index %d\n",
3716 exec_list
[i
].handle
, i
);
3721 obj_priv
= object_list
[i
]->driver_private
;
3722 if (obj_priv
->in_execbuffer
) {
3723 DRM_ERROR("Object %p appears more than once in object list\n",
3728 obj_priv
->in_execbuffer
= true;
3731 /* Pin and relocate */
3732 for (pin_tries
= 0; ; pin_tries
++) {
3736 for (i
= 0; i
< args
->buffer_count
; i
++) {
3737 object_list
[i
]->pending_read_domains
= 0;
3738 object_list
[i
]->pending_write_domain
= 0;
3739 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3742 &relocs
[reloc_index
]);
3746 reloc_index
+= exec_list
[i
].relocation_count
;
3752 /* error other than GTT full, or we've already tried again */
3753 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3754 if (ret
!= -ERESTARTSYS
) {
3755 unsigned long long total_size
= 0;
3756 for (i
= 0; i
< args
->buffer_count
; i
++)
3757 total_size
+= object_list
[i
]->size
;
3758 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3759 pinned
+1, args
->buffer_count
,
3761 DRM_ERROR("%d objects [%d pinned], "
3762 "%d object bytes [%d pinned], "
3763 "%d/%d gtt bytes\n",
3764 atomic_read(&dev
->object_count
),
3765 atomic_read(&dev
->pin_count
),
3766 atomic_read(&dev
->object_memory
),
3767 atomic_read(&dev
->pin_memory
),
3768 atomic_read(&dev
->gtt_memory
),
3774 /* unpin all of our buffers */
3775 for (i
= 0; i
< pinned
; i
++)
3776 i915_gem_object_unpin(object_list
[i
]);
3779 /* evict everyone we can from the aperture */
3780 ret
= i915_gem_evict_everything(dev
);
3781 if (ret
&& ret
!= -ENOSPC
)
3785 /* Set the pending read domains for the batch buffer to COMMAND */
3786 batch_obj
= object_list
[args
->buffer_count
-1];
3787 if (batch_obj
->pending_write_domain
) {
3788 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3792 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3794 /* Sanity check the batch buffer, prior to moving objects */
3795 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3796 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3798 DRM_ERROR("execbuf with invalid offset/length\n");
3802 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3804 /* Zero the global flush/invalidate flags. These
3805 * will be modified as new domains are computed
3808 dev
->invalidate_domains
= 0;
3809 dev
->flush_domains
= 0;
3811 for (i
= 0; i
< args
->buffer_count
; i
++) {
3812 struct drm_gem_object
*obj
= object_list
[i
];
3814 /* Compute new gpu domains and update invalidate/flush */
3815 i915_gem_object_set_to_gpu_domain(obj
);
3818 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3820 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3822 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3824 dev
->invalidate_domains
,
3825 dev
->flush_domains
);
3828 dev
->invalidate_domains
,
3829 dev
->flush_domains
);
3830 if (dev
->flush_domains
& I915_GEM_GPU_DOMAINS
)
3831 (void)i915_add_request(dev
, file_priv
,
3832 dev
->flush_domains
);
3835 for (i
= 0; i
< args
->buffer_count
; i
++) {
3836 struct drm_gem_object
*obj
= object_list
[i
];
3837 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3838 uint32_t old_write_domain
= obj
->write_domain
;
3840 obj
->write_domain
= obj
->pending_write_domain
;
3841 if (obj
->write_domain
)
3842 list_move_tail(&obj_priv
->gpu_write_list
,
3843 &dev_priv
->mm
.gpu_write_list
);
3845 list_del_init(&obj_priv
->gpu_write_list
);
3847 trace_i915_gem_object_change_domain(obj
,
3852 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3855 for (i
= 0; i
< args
->buffer_count
; i
++) {
3856 i915_gem_object_check_coherency(object_list
[i
],
3857 exec_list
[i
].handle
);
3862 i915_gem_dump_object(batch_obj
,
3868 /* Exec the batchbuffer */
3869 ret
= i915_dispatch_gem_execbuffer(dev
, args
, cliprects
, exec_offset
);
3871 DRM_ERROR("dispatch failed %d\n", ret
);
3876 * Ensure that the commands in the batch buffer are
3877 * finished before the interrupt fires
3879 flush_domains
= i915_retire_commands(dev
);
3881 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3884 * Get a seqno representing the execution of the current buffer,
3885 * which we can wait on. We would like to mitigate these interrupts,
3886 * likely by only creating seqnos occasionally (so that we have
3887 * *some* interrupts representing completion of buffers that we can
3888 * wait on when trying to clear up gtt space).
3890 seqno
= i915_add_request(dev
, file_priv
, flush_domains
);
3892 for (i
= 0; i
< args
->buffer_count
; i
++) {
3893 struct drm_gem_object
*obj
= object_list
[i
];
3895 i915_gem_object_move_to_active(obj
, seqno
);
3897 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
3901 i915_dump_lru(dev
, __func__
);
3904 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3907 for (i
= 0; i
< pinned
; i
++)
3908 i915_gem_object_unpin(object_list
[i
]);
3910 for (i
= 0; i
< args
->buffer_count
; i
++) {
3911 if (object_list
[i
]) {
3912 obj_priv
= object_list
[i
]->driver_private
;
3913 obj_priv
->in_execbuffer
= false;
3915 drm_gem_object_unreference(object_list
[i
]);
3918 mutex_unlock(&dev
->struct_mutex
);
3921 /* Copy the new buffer offsets back to the user's exec list. */
3922 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3923 (uintptr_t) args
->buffers_ptr
,
3925 sizeof(*exec_list
) * args
->buffer_count
);
3928 DRM_ERROR("failed to copy %d exec entries "
3929 "back to user (%d)\n",
3930 args
->buffer_count
, ret
);
3934 /* Copy the updated relocations out regardless of current error
3935 * state. Failure to update the relocs would mean that the next
3936 * time userland calls execbuf, it would do so with presumed offset
3937 * state that didn't match the actual object state.
3939 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
3942 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
3949 drm_free_large(object_list
);
3950 drm_free_large(exec_list
);
3957 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
3959 struct drm_device
*dev
= obj
->dev
;
3960 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3963 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3965 if (obj_priv
->gtt_space
!= NULL
) {
3967 alignment
= i915_gem_get_gtt_alignment(obj
);
3968 if (obj_priv
->gtt_offset
& (alignment
- 1)) {
3969 ret
= i915_gem_object_unbind(obj
);
3975 if (obj_priv
->gtt_space
== NULL
) {
3976 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
3981 * Pre-965 chips need a fence register set up in order to
3982 * properly handle tiled surfaces.
3984 if (!IS_I965G(dev
) && obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
3985 ret
= i915_gem_object_get_fence_reg(obj
);
3987 if (ret
!= -EBUSY
&& ret
!= -ERESTARTSYS
)
3988 DRM_ERROR("Failure to install fence: %d\n",
3993 obj_priv
->pin_count
++;
3995 /* If the object is not active and not pending a flush,
3996 * remove it from the inactive list
3998 if (obj_priv
->pin_count
== 1) {
3999 atomic_inc(&dev
->pin_count
);
4000 atomic_add(obj
->size
, &dev
->pin_memory
);
4001 if (!obj_priv
->active
&&
4002 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0 &&
4003 !list_empty(&obj_priv
->list
))
4004 list_del_init(&obj_priv
->list
);
4006 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4012 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4014 struct drm_device
*dev
= obj
->dev
;
4015 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4016 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4018 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4019 obj_priv
->pin_count
--;
4020 BUG_ON(obj_priv
->pin_count
< 0);
4021 BUG_ON(obj_priv
->gtt_space
== NULL
);
4023 /* If the object is no longer pinned, and is
4024 * neither active nor being flushed, then stick it on
4027 if (obj_priv
->pin_count
== 0) {
4028 if (!obj_priv
->active
&&
4029 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4030 list_move_tail(&obj_priv
->list
,
4031 &dev_priv
->mm
.inactive_list
);
4032 atomic_dec(&dev
->pin_count
);
4033 atomic_sub(obj
->size
, &dev
->pin_memory
);
4035 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4039 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4040 struct drm_file
*file_priv
)
4042 struct drm_i915_gem_pin
*args
= data
;
4043 struct drm_gem_object
*obj
;
4044 struct drm_i915_gem_object
*obj_priv
;
4047 mutex_lock(&dev
->struct_mutex
);
4049 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4051 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4053 mutex_unlock(&dev
->struct_mutex
);
4056 obj_priv
= obj
->driver_private
;
4058 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4059 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4060 drm_gem_object_unreference(obj
);
4061 mutex_unlock(&dev
->struct_mutex
);
4065 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4066 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4068 drm_gem_object_unreference(obj
);
4069 mutex_unlock(&dev
->struct_mutex
);
4073 obj_priv
->user_pin_count
++;
4074 obj_priv
->pin_filp
= file_priv
;
4075 if (obj_priv
->user_pin_count
== 1) {
4076 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4078 drm_gem_object_unreference(obj
);
4079 mutex_unlock(&dev
->struct_mutex
);
4084 /* XXX - flush the CPU caches for pinned objects
4085 * as the X server doesn't manage domains yet
4087 i915_gem_object_flush_cpu_write_domain(obj
);
4088 args
->offset
= obj_priv
->gtt_offset
;
4089 drm_gem_object_unreference(obj
);
4090 mutex_unlock(&dev
->struct_mutex
);
4096 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4097 struct drm_file
*file_priv
)
4099 struct drm_i915_gem_pin
*args
= data
;
4100 struct drm_gem_object
*obj
;
4101 struct drm_i915_gem_object
*obj_priv
;
4103 mutex_lock(&dev
->struct_mutex
);
4105 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4107 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4109 mutex_unlock(&dev
->struct_mutex
);
4113 obj_priv
= obj
->driver_private
;
4114 if (obj_priv
->pin_filp
!= file_priv
) {
4115 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4117 drm_gem_object_unreference(obj
);
4118 mutex_unlock(&dev
->struct_mutex
);
4121 obj_priv
->user_pin_count
--;
4122 if (obj_priv
->user_pin_count
== 0) {
4123 obj_priv
->pin_filp
= NULL
;
4124 i915_gem_object_unpin(obj
);
4127 drm_gem_object_unreference(obj
);
4128 mutex_unlock(&dev
->struct_mutex
);
4133 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4134 struct drm_file
*file_priv
)
4136 struct drm_i915_gem_busy
*args
= data
;
4137 struct drm_gem_object
*obj
;
4138 struct drm_i915_gem_object
*obj_priv
;
4140 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4142 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4147 mutex_lock(&dev
->struct_mutex
);
4148 /* Update the active list for the hardware's current position.
4149 * Otherwise this only updates on a delayed timer or when irqs are
4150 * actually unmasked, and our working set ends up being larger than
4153 i915_gem_retire_requests(dev
);
4155 obj_priv
= obj
->driver_private
;
4156 /* Don't count being on the flushing list against the object being
4157 * done. Otherwise, a buffer left on the flushing list but not getting
4158 * flushed (because nobody's flushing that domain) won't ever return
4159 * unbusy and get reused by libdrm's bo cache. The other expected
4160 * consumer of this interface, OpenGL's occlusion queries, also specs
4161 * that the objects get unbusy "eventually" without any interference.
4163 args
->busy
= obj_priv
->active
&& obj_priv
->last_rendering_seqno
!= 0;
4165 drm_gem_object_unreference(obj
);
4166 mutex_unlock(&dev
->struct_mutex
);
4171 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4172 struct drm_file
*file_priv
)
4174 return i915_gem_ring_throttle(dev
, file_priv
);
4178 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4179 struct drm_file
*file_priv
)
4181 struct drm_i915_gem_madvise
*args
= data
;
4182 struct drm_gem_object
*obj
;
4183 struct drm_i915_gem_object
*obj_priv
;
4185 switch (args
->madv
) {
4186 case I915_MADV_DONTNEED
:
4187 case I915_MADV_WILLNEED
:
4193 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4195 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4200 mutex_lock(&dev
->struct_mutex
);
4201 obj_priv
= obj
->driver_private
;
4203 if (obj_priv
->pin_count
) {
4204 drm_gem_object_unreference(obj
);
4205 mutex_unlock(&dev
->struct_mutex
);
4207 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4211 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4212 obj_priv
->madv
= args
->madv
;
4214 /* if the object is no longer bound, discard its backing storage */
4215 if (i915_gem_object_is_purgeable(obj_priv
) &&
4216 obj_priv
->gtt_space
== NULL
)
4217 i915_gem_object_truncate(obj
);
4219 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4221 drm_gem_object_unreference(obj
);
4222 mutex_unlock(&dev
->struct_mutex
);
4227 int i915_gem_init_object(struct drm_gem_object
*obj
)
4229 struct drm_i915_gem_object
*obj_priv
;
4231 obj_priv
= kzalloc(sizeof(*obj_priv
), GFP_KERNEL
);
4232 if (obj_priv
== NULL
)
4236 * We've just allocated pages from the kernel,
4237 * so they've just been written by the CPU with
4238 * zeros. They'll need to be clflushed before we
4239 * use them with the GPU.
4241 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
4242 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
4244 obj_priv
->agp_type
= AGP_USER_MEMORY
;
4246 obj
->driver_private
= obj_priv
;
4247 obj_priv
->obj
= obj
;
4248 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
4249 INIT_LIST_HEAD(&obj_priv
->list
);
4250 INIT_LIST_HEAD(&obj_priv
->gpu_write_list
);
4251 INIT_LIST_HEAD(&obj_priv
->fence_list
);
4252 obj_priv
->madv
= I915_MADV_WILLNEED
;
4254 trace_i915_gem_object_create(obj
);
4259 void i915_gem_free_object(struct drm_gem_object
*obj
)
4261 struct drm_device
*dev
= obj
->dev
;
4262 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4264 trace_i915_gem_object_destroy(obj
);
4266 while (obj_priv
->pin_count
> 0)
4267 i915_gem_object_unpin(obj
);
4269 if (obj_priv
->phys_obj
)
4270 i915_gem_detach_phys_object(dev
, obj
);
4272 i915_gem_object_unbind(obj
);
4274 if (obj_priv
->mmap_offset
)
4275 i915_gem_free_mmap_offset(obj
);
4277 kfree(obj_priv
->page_cpu_valid
);
4278 kfree(obj_priv
->bit_17
);
4279 kfree(obj
->driver_private
);
4282 /** Unbinds all inactive objects. */
4284 i915_gem_evict_from_inactive_list(struct drm_device
*dev
)
4286 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4288 while (!list_empty(&dev_priv
->mm
.inactive_list
)) {
4289 struct drm_gem_object
*obj
;
4292 obj
= list_first_entry(&dev_priv
->mm
.inactive_list
,
4293 struct drm_i915_gem_object
,
4296 ret
= i915_gem_object_unbind(obj
);
4298 DRM_ERROR("Error unbinding object: %d\n", ret
);
4307 i915_gem_idle(struct drm_device
*dev
)
4309 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4310 uint32_t seqno
, cur_seqno
, last_seqno
;
4313 mutex_lock(&dev
->struct_mutex
);
4315 if (dev_priv
->mm
.suspended
|| dev_priv
->ring
.ring_obj
== NULL
) {
4316 mutex_unlock(&dev
->struct_mutex
);
4320 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4321 * We need to replace this with a semaphore, or something.
4323 dev_priv
->mm
.suspended
= 1;
4324 del_timer(&dev_priv
->hangcheck_timer
);
4326 /* Cancel the retire work handler, wait for it to finish if running
4328 mutex_unlock(&dev
->struct_mutex
);
4329 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4330 mutex_lock(&dev
->struct_mutex
);
4332 i915_kernel_lost_context(dev
);
4334 /* Flush the GPU along with all non-CPU write domains
4336 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
4337 seqno
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
);
4340 mutex_unlock(&dev
->struct_mutex
);
4344 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
4348 cur_seqno
= i915_get_gem_seqno(dev
);
4349 if (i915_seqno_passed(cur_seqno
, seqno
))
4351 if (last_seqno
== cur_seqno
) {
4352 if (stuck
++ > 100) {
4353 DRM_ERROR("hardware wedged\n");
4354 atomic_set(&dev_priv
->mm
.wedged
, 1);
4355 DRM_WAKEUP(&dev_priv
->irq_queue
);
4360 last_seqno
= cur_seqno
;
4362 dev_priv
->mm
.waiting_gem_seqno
= 0;
4364 i915_gem_retire_requests(dev
);
4366 spin_lock(&dev_priv
->mm
.active_list_lock
);
4367 if (!atomic_read(&dev_priv
->mm
.wedged
)) {
4368 /* Active and flushing should now be empty as we've
4369 * waited for a sequence higher than any pending execbuffer
4371 WARN_ON(!list_empty(&dev_priv
->mm
.active_list
));
4372 WARN_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4373 /* Request should now be empty as we've also waited
4374 * for the last request in the list
4376 WARN_ON(!list_empty(&dev_priv
->mm
.request_list
));
4379 /* Empty the active and flushing lists to inactive. If there's
4380 * anything left at this point, it means that we're wedged and
4381 * nothing good's going to happen by leaving them there. So strip
4382 * the GPU domains and just stuff them onto inactive.
4384 while (!list_empty(&dev_priv
->mm
.active_list
)) {
4385 struct drm_gem_object
*obj
;
4386 uint32_t old_write_domain
;
4388 obj
= list_first_entry(&dev_priv
->mm
.active_list
,
4389 struct drm_i915_gem_object
,
4391 old_write_domain
= obj
->write_domain
;
4392 obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
4393 i915_gem_object_move_to_inactive(obj
);
4395 trace_i915_gem_object_change_domain(obj
,
4399 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4401 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
4402 struct drm_gem_object
*obj
;
4403 uint32_t old_write_domain
;
4405 obj
= list_first_entry(&dev_priv
->mm
.flushing_list
,
4406 struct drm_i915_gem_object
,
4408 old_write_domain
= obj
->write_domain
;
4409 obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
4410 i915_gem_object_move_to_inactive(obj
);
4412 trace_i915_gem_object_change_domain(obj
,
4418 /* Move all inactive buffers out of the GTT. */
4419 ret
= i915_gem_evict_from_inactive_list(dev
);
4420 WARN_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4422 mutex_unlock(&dev
->struct_mutex
);
4426 i915_gem_cleanup_ringbuffer(dev
);
4427 mutex_unlock(&dev
->struct_mutex
);
4433 i915_gem_init_hws(struct drm_device
*dev
)
4435 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4436 struct drm_gem_object
*obj
;
4437 struct drm_i915_gem_object
*obj_priv
;
4440 /* If we need a physical address for the status page, it's already
4441 * initialized at driver load time.
4443 if (!I915_NEED_GFX_HWS(dev
))
4446 obj
= drm_gem_object_alloc(dev
, 4096);
4448 DRM_ERROR("Failed to allocate status page\n");
4451 obj_priv
= obj
->driver_private
;
4452 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4454 ret
= i915_gem_object_pin(obj
, 4096);
4456 drm_gem_object_unreference(obj
);
4460 dev_priv
->status_gfx_addr
= obj_priv
->gtt_offset
;
4462 dev_priv
->hw_status_page
= kmap(obj_priv
->pages
[0]);
4463 if (dev_priv
->hw_status_page
== NULL
) {
4464 DRM_ERROR("Failed to map status page.\n");
4465 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4466 i915_gem_object_unpin(obj
);
4467 drm_gem_object_unreference(obj
);
4470 dev_priv
->hws_obj
= obj
;
4471 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
4472 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
4473 I915_READ(HWS_PGA
); /* posting read */
4474 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv
->status_gfx_addr
);
4480 i915_gem_cleanup_hws(struct drm_device
*dev
)
4482 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4483 struct drm_gem_object
*obj
;
4484 struct drm_i915_gem_object
*obj_priv
;
4486 if (dev_priv
->hws_obj
== NULL
)
4489 obj
= dev_priv
->hws_obj
;
4490 obj_priv
= obj
->driver_private
;
4492 kunmap(obj_priv
->pages
[0]);
4493 i915_gem_object_unpin(obj
);
4494 drm_gem_object_unreference(obj
);
4495 dev_priv
->hws_obj
= NULL
;
4497 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4498 dev_priv
->hw_status_page
= NULL
;
4500 /* Write high address into HWS_PGA when disabling. */
4501 I915_WRITE(HWS_PGA
, 0x1ffff000);
4505 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4507 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4508 struct drm_gem_object
*obj
;
4509 struct drm_i915_gem_object
*obj_priv
;
4510 drm_i915_ring_buffer_t
*ring
= &dev_priv
->ring
;
4514 ret
= i915_gem_init_hws(dev
);
4518 obj
= drm_gem_object_alloc(dev
, 128 * 1024);
4520 DRM_ERROR("Failed to allocate ringbuffer\n");
4521 i915_gem_cleanup_hws(dev
);
4524 obj_priv
= obj
->driver_private
;
4526 ret
= i915_gem_object_pin(obj
, 4096);
4528 drm_gem_object_unreference(obj
);
4529 i915_gem_cleanup_hws(dev
);
4533 /* Set up the kernel mapping for the ring. */
4534 ring
->Size
= obj
->size
;
4536 ring
->map
.offset
= dev
->agp
->base
+ obj_priv
->gtt_offset
;
4537 ring
->map
.size
= obj
->size
;
4539 ring
->map
.flags
= 0;
4542 drm_core_ioremap_wc(&ring
->map
, dev
);
4543 if (ring
->map
.handle
== NULL
) {
4544 DRM_ERROR("Failed to map ringbuffer.\n");
4545 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4546 i915_gem_object_unpin(obj
);
4547 drm_gem_object_unreference(obj
);
4548 i915_gem_cleanup_hws(dev
);
4551 ring
->ring_obj
= obj
;
4552 ring
->virtual_start
= ring
->map
.handle
;
4554 /* Stop the ring if it's running. */
4555 I915_WRITE(PRB0_CTL
, 0);
4556 I915_WRITE(PRB0_TAIL
, 0);
4557 I915_WRITE(PRB0_HEAD
, 0);
4559 /* Initialize the ring. */
4560 I915_WRITE(PRB0_START
, obj_priv
->gtt_offset
);
4561 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4563 /* G45 ring initialization fails to reset head to zero */
4565 DRM_ERROR("Ring head not reset to zero "
4566 "ctl %08x head %08x tail %08x start %08x\n",
4567 I915_READ(PRB0_CTL
),
4568 I915_READ(PRB0_HEAD
),
4569 I915_READ(PRB0_TAIL
),
4570 I915_READ(PRB0_START
));
4571 I915_WRITE(PRB0_HEAD
, 0);
4573 DRM_ERROR("Ring head forced to zero "
4574 "ctl %08x head %08x tail %08x start %08x\n",
4575 I915_READ(PRB0_CTL
),
4576 I915_READ(PRB0_HEAD
),
4577 I915_READ(PRB0_TAIL
),
4578 I915_READ(PRB0_START
));
4581 I915_WRITE(PRB0_CTL
,
4582 ((obj
->size
- 4096) & RING_NR_PAGES
) |
4586 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4588 /* If the head is still not zero, the ring is dead */
4590 DRM_ERROR("Ring initialization failed "
4591 "ctl %08x head %08x tail %08x start %08x\n",
4592 I915_READ(PRB0_CTL
),
4593 I915_READ(PRB0_HEAD
),
4594 I915_READ(PRB0_TAIL
),
4595 I915_READ(PRB0_START
));
4599 /* Update our cache of the ring state */
4600 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4601 i915_kernel_lost_context(dev
);
4603 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4604 ring
->tail
= I915_READ(PRB0_TAIL
) & TAIL_ADDR
;
4605 ring
->space
= ring
->head
- (ring
->tail
+ 8);
4606 if (ring
->space
< 0)
4607 ring
->space
+= ring
->Size
;
4614 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4616 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4618 if (dev_priv
->ring
.ring_obj
== NULL
)
4621 drm_core_ioremapfree(&dev_priv
->ring
.map
, dev
);
4623 i915_gem_object_unpin(dev_priv
->ring
.ring_obj
);
4624 drm_gem_object_unreference(dev_priv
->ring
.ring_obj
);
4625 dev_priv
->ring
.ring_obj
= NULL
;
4626 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4628 i915_gem_cleanup_hws(dev
);
4632 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4633 struct drm_file
*file_priv
)
4635 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4638 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4641 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4642 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4643 atomic_set(&dev_priv
->mm
.wedged
, 0);
4646 mutex_lock(&dev
->struct_mutex
);
4647 dev_priv
->mm
.suspended
= 0;
4649 ret
= i915_gem_init_ringbuffer(dev
);
4651 mutex_unlock(&dev
->struct_mutex
);
4655 spin_lock(&dev_priv
->mm
.active_list_lock
);
4656 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4657 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4659 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4660 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4661 BUG_ON(!list_empty(&dev_priv
->mm
.request_list
));
4662 mutex_unlock(&dev
->struct_mutex
);
4664 drm_irq_install(dev
);
4670 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4671 struct drm_file
*file_priv
)
4673 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4676 drm_irq_uninstall(dev
);
4677 return i915_gem_idle(dev
);
4681 i915_gem_lastclose(struct drm_device
*dev
)
4685 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4688 ret
= i915_gem_idle(dev
);
4690 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4694 i915_gem_load(struct drm_device
*dev
)
4697 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4699 spin_lock_init(&dev_priv
->mm
.active_list_lock
);
4700 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4701 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4702 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4703 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4704 INIT_LIST_HEAD(&dev_priv
->mm
.request_list
);
4705 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4706 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4707 i915_gem_retire_work_handler
);
4708 dev_priv
->mm
.next_gem_seqno
= 1;
4710 spin_lock(&shrink_list_lock
);
4711 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4712 spin_unlock(&shrink_list_lock
);
4714 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4715 if (IS_I915G(dev
) || IS_I915GM(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
4716 u32 tmp
= I915_READ(MI_ARB_STATE
);
4717 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4718 /* arb state is a masked write, so set bit + bit in mask */
4719 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4720 I915_WRITE(MI_ARB_STATE
, tmp
);
4724 /* Old X drivers will take 0-2 for front, back, depth buffers */
4725 dev_priv
->fence_reg_start
= 3;
4727 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4728 dev_priv
->num_fence_regs
= 16;
4730 dev_priv
->num_fence_regs
= 8;
4732 /* Initialize fence registers to zero */
4733 if (IS_I965G(dev
)) {
4734 for (i
= 0; i
< 16; i
++)
4735 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4737 for (i
= 0; i
< 8; i
++)
4738 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4739 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4740 for (i
= 0; i
< 8; i
++)
4741 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4744 i915_gem_detect_bit_6_swizzle(dev
);
4748 * Create a physically contiguous memory object for this object
4749 * e.g. for cursor + overlay regs
4751 int i915_gem_init_phys_object(struct drm_device
*dev
,
4754 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4755 struct drm_i915_gem_phys_object
*phys_obj
;
4758 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4761 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4767 phys_obj
->handle
= drm_pci_alloc(dev
, size
, 0);
4768 if (!phys_obj
->handle
) {
4773 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4776 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4784 void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4786 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4787 struct drm_i915_gem_phys_object
*phys_obj
;
4789 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4792 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4793 if (phys_obj
->cur_obj
) {
4794 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4798 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4800 drm_pci_free(dev
, phys_obj
->handle
);
4802 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4805 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4809 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4810 i915_gem_free_phys_object(dev
, i
);
4813 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4814 struct drm_gem_object
*obj
)
4816 struct drm_i915_gem_object
*obj_priv
;
4821 obj_priv
= obj
->driver_private
;
4822 if (!obj_priv
->phys_obj
)
4825 ret
= i915_gem_object_get_pages(obj
, 0);
4829 page_count
= obj
->size
/ PAGE_SIZE
;
4831 for (i
= 0; i
< page_count
; i
++) {
4832 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4833 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4835 memcpy(dst
, src
, PAGE_SIZE
);
4836 kunmap_atomic(dst
, KM_USER0
);
4838 drm_clflush_pages(obj_priv
->pages
, page_count
);
4839 drm_agp_chipset_flush(dev
);
4841 i915_gem_object_put_pages(obj
);
4843 obj_priv
->phys_obj
->cur_obj
= NULL
;
4844 obj_priv
->phys_obj
= NULL
;
4848 i915_gem_attach_phys_object(struct drm_device
*dev
,
4849 struct drm_gem_object
*obj
, int id
)
4851 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4852 struct drm_i915_gem_object
*obj_priv
;
4857 if (id
> I915_MAX_PHYS_OBJECT
)
4860 obj_priv
= obj
->driver_private
;
4862 if (obj_priv
->phys_obj
) {
4863 if (obj_priv
->phys_obj
->id
== id
)
4865 i915_gem_detach_phys_object(dev
, obj
);
4869 /* create a new object */
4870 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4871 ret
= i915_gem_init_phys_object(dev
, id
,
4874 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4879 /* bind to the object */
4880 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4881 obj_priv
->phys_obj
->cur_obj
= obj
;
4883 ret
= i915_gem_object_get_pages(obj
, 0);
4885 DRM_ERROR("failed to get page list\n");
4889 page_count
= obj
->size
/ PAGE_SIZE
;
4891 for (i
= 0; i
< page_count
; i
++) {
4892 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4893 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4895 memcpy(dst
, src
, PAGE_SIZE
);
4896 kunmap_atomic(src
, KM_USER0
);
4899 i915_gem_object_put_pages(obj
);
4907 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4908 struct drm_i915_gem_pwrite
*args
,
4909 struct drm_file
*file_priv
)
4911 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4914 char __user
*user_data
;
4916 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4917 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4919 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4920 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4924 drm_agp_chipset_flush(dev
);
4928 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
4930 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
4932 /* Clean up our request list when the client is going away, so that
4933 * later retire_requests won't dereference our soon-to-be-gone
4936 mutex_lock(&dev
->struct_mutex
);
4937 while (!list_empty(&i915_file_priv
->mm
.request_list
))
4938 list_del_init(i915_file_priv
->mm
.request_list
.next
);
4939 mutex_unlock(&dev
->struct_mutex
);
4943 i915_gem_shrink(int nr_to_scan
, gfp_t gfp_mask
)
4945 drm_i915_private_t
*dev_priv
, *next_dev
;
4946 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4948 int would_deadlock
= 1;
4950 /* "fast-path" to count number of available objects */
4951 if (nr_to_scan
== 0) {
4952 spin_lock(&shrink_list_lock
);
4953 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4954 struct drm_device
*dev
= dev_priv
->dev
;
4956 if (mutex_trylock(&dev
->struct_mutex
)) {
4957 list_for_each_entry(obj_priv
,
4958 &dev_priv
->mm
.inactive_list
,
4961 mutex_unlock(&dev
->struct_mutex
);
4964 spin_unlock(&shrink_list_lock
);
4966 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4969 spin_lock(&shrink_list_lock
);
4971 /* first scan for clean buffers */
4972 list_for_each_entry_safe(dev_priv
, next_dev
,
4973 &shrink_list
, mm
.shrink_list
) {
4974 struct drm_device
*dev
= dev_priv
->dev
;
4976 if (! mutex_trylock(&dev
->struct_mutex
))
4979 spin_unlock(&shrink_list_lock
);
4981 i915_gem_retire_requests(dev
);
4983 list_for_each_entry_safe(obj_priv
, next_obj
,
4984 &dev_priv
->mm
.inactive_list
,
4986 if (i915_gem_object_is_purgeable(obj_priv
)) {
4987 i915_gem_object_unbind(obj_priv
->obj
);
4988 if (--nr_to_scan
<= 0)
4993 spin_lock(&shrink_list_lock
);
4994 mutex_unlock(&dev
->struct_mutex
);
4998 if (nr_to_scan
<= 0)
5002 /* second pass, evict/count anything still on the inactive list */
5003 list_for_each_entry_safe(dev_priv
, next_dev
,
5004 &shrink_list
, mm
.shrink_list
) {
5005 struct drm_device
*dev
= dev_priv
->dev
;
5007 if (! mutex_trylock(&dev
->struct_mutex
))
5010 spin_unlock(&shrink_list_lock
);
5012 list_for_each_entry_safe(obj_priv
, next_obj
,
5013 &dev_priv
->mm
.inactive_list
,
5015 if (nr_to_scan
> 0) {
5016 i915_gem_object_unbind(obj_priv
->obj
);
5022 spin_lock(&shrink_list_lock
);
5023 mutex_unlock(&dev
->struct_mutex
);
5028 spin_unlock(&shrink_list_lock
);
5033 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5038 static struct shrinker shrinker
= {
5039 .shrink
= i915_gem_shrink
,
5040 .seeks
= DEFAULT_SEEKS
,
5044 i915_gem_shrinker_init(void)
5046 register_shrinker(&shrinker
);
5050 i915_gem_shrinker_exit(void)
5052 unregister_shrinker(&shrinker
);