2 * V4L2 Driver for i.MX27/i.MX25 camera host
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/slab.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/errno.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
24 #include <linux/moduleparam.h>
25 #include <linux/time.h>
26 #include <linux/version.h>
27 #include <linux/device.h>
28 #include <linux/platform_device.h>
29 #include <linux/mutex.h>
30 #include <linux/clk.h>
32 #include <media/v4l2-common.h>
33 #include <media/v4l2-dev.h>
34 #include <media/videobuf-dma-contig.h>
35 #include <media/soc_camera.h>
36 #include <media/soc_mediabus.h>
38 #include <linux/videodev2.h>
40 #include <mach/mx2_cam.h>
41 #ifdef CONFIG_MACH_MX27
42 #include <mach/dma-mx1-mx2.h>
44 #include <mach/hardware.h>
48 #define MX2_CAM_DRV_NAME "mx2-camera"
49 #define MX2_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
50 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
53 #define CSICR1_RESET_VAL 0x40000800
54 #define CSICR2_RESET_VAL 0x0
55 #define CSICR3_RESET_VAL 0x0
57 /* csi control reg 1 */
58 #define CSICR1_SWAP16_EN (1 << 31)
59 #define CSICR1_EXT_VSYNC (1 << 30)
60 #define CSICR1_EOF_INTEN (1 << 29)
61 #define CSICR1_PRP_IF_EN (1 << 28)
62 #define CSICR1_CCIR_MODE (1 << 27)
63 #define CSICR1_COF_INTEN (1 << 26)
64 #define CSICR1_SF_OR_INTEN (1 << 25)
65 #define CSICR1_RF_OR_INTEN (1 << 24)
66 #define CSICR1_STATFF_LEVEL (3 << 22)
67 #define CSICR1_STATFF_INTEN (1 << 21)
68 #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */
69 #define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */
70 #define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */
71 #define CSICR1_RXFF_INTEN (1 << 18)
72 #define CSICR1_SOF_POL (1 << 17)
73 #define CSICR1_SOF_INTEN (1 << 16)
74 #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
75 #define CSICR1_HSYNC_POL (1 << 11)
76 #define CSICR1_CCIR_EN (1 << 10)
77 #define CSICR1_MCLKEN (1 << 9)
78 #define CSICR1_FCC (1 << 8)
79 #define CSICR1_PACK_DIR (1 << 7)
80 #define CSICR1_CLR_STATFIFO (1 << 6)
81 #define CSICR1_CLR_RXFIFO (1 << 5)
82 #define CSICR1_GCLK_MODE (1 << 4)
83 #define CSICR1_INV_DATA (1 << 3)
84 #define CSICR1_INV_PCLK (1 << 2)
85 #define CSICR1_REDGE (1 << 1)
87 #define SHIFT_STATFF_LEVEL 22
88 #define SHIFT_RXFF_LEVEL 19
89 #define SHIFT_MCLKDIV 12
92 #define CSICR3_FRMCNT (0xFFFF << 16)
93 #define CSICR3_FRMCNT_RST (1 << 15)
94 #define CSICR3_DMA_REFLASH_RFF (1 << 14)
95 #define CSICR3_DMA_REFLASH_SFF (1 << 13)
96 #define CSICR3_DMA_REQ_EN_RFF (1 << 12)
97 #define CSICR3_DMA_REQ_EN_SFF (1 << 11)
98 #define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */
99 #define CSICR3_CSI_SUP (1 << 3)
100 #define CSICR3_ZERO_PACK_EN (1 << 2)
101 #define CSICR3_ECC_INT_EN (1 << 1)
102 #define CSICR3_ECC_AUTO_EN (1 << 0)
104 #define SHIFT_FRMCNT 16
107 #define CSISR_SFF_OR_INT (1 << 25)
108 #define CSISR_RFF_OR_INT (1 << 24)
109 #define CSISR_STATFF_INT (1 << 21)
110 #define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */
111 #define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */
112 #define CSISR_RXFF_INT (1 << 18)
113 #define CSISR_EOF_INT (1 << 17)
114 #define CSISR_SOF_INT (1 << 16)
115 #define CSISR_F2_INT (1 << 15)
116 #define CSISR_F1_INT (1 << 14)
117 #define CSISR_COF_INT (1 << 13)
118 #define CSISR_ECC_INT (1 << 1)
119 #define CSISR_DRDY (1 << 0)
123 #define CSISR (cpu_is_mx27() ? 0x08 : 0x18)
124 #define CSISTATFIFO 0x0c
125 #define CSIRFIFO 0x10
126 #define CSIRXCNT 0x14
127 #define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08)
128 #define CSIDMASA_STATFIFO 0x20
129 #define CSIDMATA_STATFIFO 0x24
130 #define CSIDMASA_FB1 0x28
131 #define CSIDMASA_FB2 0x2c
132 #define CSIFBUF_PARA 0x30
133 #define CSIIMAG_PARA 0x34
136 #define PRP_CNTL 0x00
137 #define PRP_INTR_CNTL 0x04
138 #define PRP_INTRSTATUS 0x08
139 #define PRP_SOURCE_Y_PTR 0x0c
140 #define PRP_SOURCE_CB_PTR 0x10
141 #define PRP_SOURCE_CR_PTR 0x14
142 #define PRP_DEST_RGB1_PTR 0x18
143 #define PRP_DEST_RGB2_PTR 0x1c
144 #define PRP_DEST_Y_PTR 0x20
145 #define PRP_DEST_CB_PTR 0x24
146 #define PRP_DEST_CR_PTR 0x28
147 #define PRP_SRC_FRAME_SIZE 0x2c
148 #define PRP_DEST_CH1_LINE_STRIDE 0x30
149 #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
150 #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
151 #define PRP_CH1_OUT_IMAGE_SIZE 0x3c
152 #define PRP_CH2_OUT_IMAGE_SIZE 0x40
153 #define PRP_SRC_LINE_STRIDE 0x44
154 #define PRP_CSC_COEF_012 0x48
155 #define PRP_CSC_COEF_345 0x4c
156 #define PRP_CSC_COEF_678 0x50
157 #define PRP_CH1_RZ_HORI_COEF1 0x54
158 #define PRP_CH1_RZ_HORI_COEF2 0x58
159 #define PRP_CH1_RZ_HORI_VALID 0x5c
160 #define PRP_CH1_RZ_VERT_COEF1 0x60
161 #define PRP_CH1_RZ_VERT_COEF2 0x64
162 #define PRP_CH1_RZ_VERT_VALID 0x68
163 #define PRP_CH2_RZ_HORI_COEF1 0x6c
164 #define PRP_CH2_RZ_HORI_COEF2 0x70
165 #define PRP_CH2_RZ_HORI_VALID 0x74
166 #define PRP_CH2_RZ_VERT_COEF1 0x78
167 #define PRP_CH2_RZ_VERT_COEF2 0x7c
168 #define PRP_CH2_RZ_VERT_VALID 0x80
170 #define PRP_CNTL_CH1EN (1 << 0)
171 #define PRP_CNTL_CH2EN (1 << 1)
172 #define PRP_CNTL_CSIEN (1 << 2)
173 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
174 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
175 #define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
176 #define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
177 #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
178 #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
179 #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
180 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
181 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
182 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
183 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
184 #define PRP_CNTL_CH1_LEN (1 << 9)
185 #define PRP_CNTL_CH2_LEN (1 << 10)
186 #define PRP_CNTL_SKIP_FRAME (1 << 11)
187 #define PRP_CNTL_SWRST (1 << 12)
188 #define PRP_CNTL_CLKEN (1 << 13)
189 #define PRP_CNTL_WEN (1 << 14)
190 #define PRP_CNTL_CH1BYP (1 << 15)
191 #define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
192 #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
193 #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
194 #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
195 #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
196 #define PRP_CNTL_CH2B1EN (1 << 29)
197 #define PRP_CNTL_CH2B2EN (1 << 30)
198 #define PRP_CNTL_CH2FEN (1 << 31)
200 /* IRQ Enable and status register */
201 #define PRP_INTR_RDERR (1 << 0)
202 #define PRP_INTR_CH1WERR (1 << 1)
203 #define PRP_INTR_CH2WERR (1 << 2)
204 #define PRP_INTR_CH1FC (1 << 3)
205 #define PRP_INTR_CH2FC (1 << 5)
206 #define PRP_INTR_LBOVF (1 << 7)
207 #define PRP_INTR_CH2OVF (1 << 8)
209 #define mx27_camera_emma(pcdev) (cpu_is_mx27() && pcdev->use_emma)
211 #define MAX_VIDEO_MEM 16
213 struct mx2_camera_dev
{
215 struct soc_camera_host soc_host
;
216 struct soc_camera_device
*icd
;
217 struct clk
*clk_csi
, *clk_emma
;
219 unsigned int irq_csi
, irq_emma
;
220 void __iomem
*base_csi
, *base_emma
;
221 unsigned long base_dma
;
223 struct mx2_camera_platform_data
*pdata
;
224 struct resource
*res_csi
, *res_emma
;
225 unsigned long platform_flags
;
227 struct list_head capture
;
228 struct list_head active_bufs
;
233 struct mx2_buffer
*active
;
234 struct mx2_buffer
*fb1_active
;
235 struct mx2_buffer
*fb2_active
;
241 void *discard_buffer
;
242 dma_addr_t discard_buffer_dma
;
246 /* buffer for one video frame */
248 /* common v4l buffer stuff -- must be first */
249 struct videobuf_buffer vb
;
251 enum v4l2_mbus_pixelcode code
;
256 static void mx2_camera_deactivate(struct mx2_camera_dev
*pcdev
)
260 clk_disable(pcdev
->clk_csi
);
261 writel(0, pcdev
->base_csi
+ CSICR1
);
262 if (mx27_camera_emma(pcdev
)) {
263 writel(0, pcdev
->base_emma
+ PRP_CNTL
);
264 } else if (cpu_is_mx25()) {
265 spin_lock_irqsave(&pcdev
->lock
, flags
);
266 pcdev
->fb1_active
= NULL
;
267 pcdev
->fb2_active
= NULL
;
268 writel(0, pcdev
->base_csi
+ CSIDMASA_FB1
);
269 writel(0, pcdev
->base_csi
+ CSIDMASA_FB2
);
270 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
275 * The following two functions absolutely depend on the fact, that
276 * there can be only one camera on mx2 camera sensor interface
278 static int mx2_camera_add_device(struct soc_camera_device
*icd
)
280 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
281 struct mx2_camera_dev
*pcdev
= ici
->priv
;
288 ret
= clk_enable(pcdev
->clk_csi
);
292 csicr1
= CSICR1_MCLKEN
;
294 if (mx27_camera_emma(pcdev
)) {
295 csicr1
|= CSICR1_PRP_IF_EN
| CSICR1_FCC
|
296 CSICR1_RXFF_LEVEL(0);
297 } else if (cpu_is_mx27())
298 csicr1
|= CSICR1_SOF_INTEN
| CSICR1_RXFF_LEVEL(2);
300 pcdev
->csicr1
= csicr1
;
301 writel(pcdev
->csicr1
, pcdev
->base_csi
+ CSICR1
);
305 dev_info(icd
->dev
.parent
, "Camera driver attached to camera %d\n",
311 static void mx2_camera_remove_device(struct soc_camera_device
*icd
)
313 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
314 struct mx2_camera_dev
*pcdev
= ici
->priv
;
316 BUG_ON(icd
!= pcdev
->icd
);
318 dev_info(icd
->dev
.parent
, "Camera driver detached from camera %d\n",
321 mx2_camera_deactivate(pcdev
);
323 if (pcdev
->discard_buffer
) {
324 dma_free_coherent(ici
->v4l2_dev
.dev
, pcdev
->discard_size
,
325 pcdev
->discard_buffer
,
326 pcdev
->discard_buffer_dma
);
327 pcdev
->discard_buffer
= NULL
;
333 #ifdef CONFIG_MACH_MX27
334 static void mx27_camera_dma_enable(struct mx2_camera_dev
*pcdev
)
338 imx_dma_enable(pcdev
->dma
);
340 tmp
= readl(pcdev
->base_csi
+ CSICR1
);
341 tmp
|= CSICR1_RF_OR_INTEN
;
342 writel(tmp
, pcdev
->base_csi
+ CSICR1
);
345 static irqreturn_t
mx27_camera_irq(int irq_csi
, void *data
)
347 struct mx2_camera_dev
*pcdev
= data
;
348 u32 status
= readl(pcdev
->base_csi
+ CSISR
);
350 if (status
& CSISR_SOF_INT
&& pcdev
->active
) {
353 tmp
= readl(pcdev
->base_csi
+ CSICR1
);
354 writel(tmp
| CSICR1_CLR_RXFIFO
, pcdev
->base_csi
+ CSICR1
);
355 mx27_camera_dma_enable(pcdev
);
358 writel(CSISR_SOF_INT
| CSISR_RFF_OR_INT
, pcdev
->base_csi
+ CSISR
);
363 static irqreturn_t
mx27_camera_irq(int irq_csi
, void *data
)
367 #endif /* CONFIG_MACH_MX27 */
369 static void mx25_camera_frame_done(struct mx2_camera_dev
*pcdev
, int fb
,
372 struct videobuf_buffer
*vb
;
373 struct mx2_buffer
*buf
;
374 struct mx2_buffer
**fb_active
= fb
== 1 ? &pcdev
->fb1_active
:
376 u32 fb_reg
= fb
== 1 ? CSIDMASA_FB1
: CSIDMASA_FB2
;
379 spin_lock_irqsave(&pcdev
->lock
, flags
);
381 if (*fb_active
== NULL
)
384 vb
= &(*fb_active
)->vb
;
385 dev_dbg(pcdev
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
386 vb
, vb
->baddr
, vb
->bsize
);
389 do_gettimeofday(&vb
->ts
);
394 if (list_empty(&pcdev
->capture
)) {
396 writel(0, pcdev
->base_csi
+ fb_reg
);
398 buf
= list_entry(pcdev
->capture
.next
, struct mx2_buffer
,
401 list_del(&vb
->queue
);
402 vb
->state
= VIDEOBUF_ACTIVE
;
403 writel(videobuf_to_dma_contig(vb
), pcdev
->base_csi
+ fb_reg
);
409 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
412 static irqreturn_t
mx25_camera_irq(int irq_csi
, void *data
)
414 struct mx2_camera_dev
*pcdev
= data
;
415 u32 status
= readl(pcdev
->base_csi
+ CSISR
);
417 if (status
& CSISR_DMA_TSF_FB1_INT
)
418 mx25_camera_frame_done(pcdev
, 1, VIDEOBUF_DONE
);
419 else if (status
& CSISR_DMA_TSF_FB2_INT
)
420 mx25_camera_frame_done(pcdev
, 2, VIDEOBUF_DONE
);
422 /* FIXME: handle CSISR_RFF_OR_INT */
424 writel(status
, pcdev
->base_csi
+ CSISR
);
430 * Videobuf operations
432 static int mx2_videobuf_setup(struct videobuf_queue
*vq
, unsigned int *count
,
435 struct soc_camera_device
*icd
= vq
->priv_data
;
436 int bytes_per_line
= soc_mbus_bytes_per_line(icd
->user_width
,
437 icd
->current_fmt
->host_fmt
);
439 dev_dbg(&icd
->dev
, "count=%d, size=%d\n", *count
, *size
);
441 if (bytes_per_line
< 0)
442 return bytes_per_line
;
444 *size
= bytes_per_line
* icd
->user_height
;
448 if (*size
* *count
> MAX_VIDEO_MEM
* 1024 * 1024)
449 *count
= (MAX_VIDEO_MEM
* 1024 * 1024) / *size
;
454 static void free_buffer(struct videobuf_queue
*vq
, struct mx2_buffer
*buf
)
456 struct soc_camera_device
*icd
= vq
->priv_data
;
457 struct videobuf_buffer
*vb
= &buf
->vb
;
459 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
460 vb
, vb
->baddr
, vb
->bsize
);
463 * This waits until this buffer is out of danger, i.e., until it is no
464 * longer in state VIDEOBUF_QUEUED or VIDEOBUF_ACTIVE
466 videobuf_waiton(vq
, vb
, 0, 0);
468 videobuf_dma_contig_free(vq
, vb
);
469 dev_dbg(&icd
->dev
, "%s freed\n", __func__
);
471 vb
->state
= VIDEOBUF_NEEDS_INIT
;
474 static int mx2_videobuf_prepare(struct videobuf_queue
*vq
,
475 struct videobuf_buffer
*vb
, enum v4l2_field field
)
477 struct soc_camera_device
*icd
= vq
->priv_data
;
478 struct mx2_buffer
*buf
= container_of(vb
, struct mx2_buffer
, vb
);
479 int bytes_per_line
= soc_mbus_bytes_per_line(icd
->user_width
,
480 icd
->current_fmt
->host_fmt
);
483 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
484 vb
, vb
->baddr
, vb
->bsize
);
486 if (bytes_per_line
< 0)
487 return bytes_per_line
;
491 * This can be useful if you want to see if we actually fill
492 * the buffer with something
494 memset((void *)vb
->baddr
, 0xaa, vb
->bsize
);
497 if (buf
->code
!= icd
->current_fmt
->code
||
498 vb
->width
!= icd
->user_width
||
499 vb
->height
!= icd
->user_height
||
500 vb
->field
!= field
) {
501 buf
->code
= icd
->current_fmt
->code
;
502 vb
->width
= icd
->user_width
;
503 vb
->height
= icd
->user_height
;
505 vb
->state
= VIDEOBUF_NEEDS_INIT
;
508 vb
->size
= bytes_per_line
* vb
->height
;
509 if (vb
->baddr
&& vb
->bsize
< vb
->size
) {
514 if (vb
->state
== VIDEOBUF_NEEDS_INIT
) {
515 ret
= videobuf_iolock(vq
, vb
, NULL
);
519 vb
->state
= VIDEOBUF_PREPARED
;
525 free_buffer(vq
, buf
);
530 static void mx2_videobuf_queue(struct videobuf_queue
*vq
,
531 struct videobuf_buffer
*vb
)
533 struct soc_camera_device
*icd
= vq
->priv_data
;
534 struct soc_camera_host
*ici
=
535 to_soc_camera_host(icd
->dev
.parent
);
536 struct mx2_camera_dev
*pcdev
= ici
->priv
;
537 struct mx2_buffer
*buf
= container_of(vb
, struct mx2_buffer
, vb
);
540 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
541 vb
, vb
->baddr
, vb
->bsize
);
543 spin_lock_irqsave(&pcdev
->lock
, flags
);
545 vb
->state
= VIDEOBUF_QUEUED
;
546 list_add_tail(&vb
->queue
, &pcdev
->capture
);
548 if (mx27_camera_emma(pcdev
)) {
550 #ifdef CONFIG_MACH_MX27
551 } else if (cpu_is_mx27()) {
554 if (pcdev
->active
== NULL
) {
555 ret
= imx_dma_setup_single(pcdev
->dma
,
556 videobuf_to_dma_contig(vb
), vb
->size
,
557 (u32
)pcdev
->base_dma
+ 0x10,
560 vb
->state
= VIDEOBUF_ERROR
;
565 vb
->state
= VIDEOBUF_ACTIVE
;
569 } else { /* cpu_is_mx25() */
570 u32 csicr3
, dma_inten
= 0;
572 if (pcdev
->fb1_active
== NULL
) {
573 writel(videobuf_to_dma_contig(vb
),
574 pcdev
->base_csi
+ CSIDMASA_FB1
);
575 pcdev
->fb1_active
= buf
;
576 dma_inten
= CSICR1_FB1_DMA_INTEN
;
577 } else if (pcdev
->fb2_active
== NULL
) {
578 writel(videobuf_to_dma_contig(vb
),
579 pcdev
->base_csi
+ CSIDMASA_FB2
);
580 pcdev
->fb2_active
= buf
;
581 dma_inten
= CSICR1_FB2_DMA_INTEN
;
585 list_del(&vb
->queue
);
586 vb
->state
= VIDEOBUF_ACTIVE
;
588 csicr3
= readl(pcdev
->base_csi
+ CSICR3
);
591 writel(csicr3
| CSICR3_DMA_REFLASH_RFF
,
592 pcdev
->base_csi
+ CSICR3
);
594 /* clear & enable interrupts */
595 writel(dma_inten
, pcdev
->base_csi
+ CSISR
);
596 pcdev
->csicr1
|= dma_inten
;
597 writel(pcdev
->csicr1
, pcdev
->base_csi
+ CSICR1
);
600 csicr3
|= CSICR3_DMA_REQ_EN_RFF
| CSICR3_RXFF_LEVEL(1);
601 writel(csicr3
, pcdev
->base_csi
+ CSICR3
);
606 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
609 static void mx2_videobuf_release(struct videobuf_queue
*vq
,
610 struct videobuf_buffer
*vb
)
612 struct soc_camera_device
*icd
= vq
->priv_data
;
613 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
614 struct mx2_camera_dev
*pcdev
= ici
->priv
;
615 struct mx2_buffer
*buf
= container_of(vb
, struct mx2_buffer
, vb
);
619 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
620 vb
, vb
->baddr
, vb
->bsize
);
623 case VIDEOBUF_ACTIVE
:
624 dev_info(&icd
->dev
, "%s (active)\n", __func__
);
626 case VIDEOBUF_QUEUED
:
627 dev_info(&icd
->dev
, "%s (queued)\n", __func__
);
629 case VIDEOBUF_PREPARED
:
630 dev_info(&icd
->dev
, "%s (prepared)\n", __func__
);
633 dev_info(&icd
->dev
, "%s (unknown) %d\n", __func__
,
640 * Terminate only queued but inactive buffers. Active buffers are
641 * released when they become inactive after videobuf_waiton().
643 * FIXME: implement forced termination of active buffers for mx27 and
644 * mx27 eMMA, so that the user won't get stuck in an uninterruptible
645 * state. This requires a specific handling for each of the these DMA
648 spin_lock_irqsave(&pcdev
->lock
, flags
);
649 if (vb
->state
== VIDEOBUF_QUEUED
) {
650 list_del(&vb
->queue
);
651 vb
->state
= VIDEOBUF_ERROR
;
652 } else if (cpu_is_mx25() && vb
->state
== VIDEOBUF_ACTIVE
) {
653 if (pcdev
->fb1_active
== buf
) {
654 pcdev
->csicr1
&= ~CSICR1_FB1_DMA_INTEN
;
655 writel(0, pcdev
->base_csi
+ CSIDMASA_FB1
);
656 pcdev
->fb1_active
= NULL
;
657 } else if (pcdev
->fb2_active
== buf
) {
658 pcdev
->csicr1
&= ~CSICR1_FB2_DMA_INTEN
;
659 writel(0, pcdev
->base_csi
+ CSIDMASA_FB2
);
660 pcdev
->fb2_active
= NULL
;
662 writel(pcdev
->csicr1
, pcdev
->base_csi
+ CSICR1
);
663 vb
->state
= VIDEOBUF_ERROR
;
665 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
667 free_buffer(vq
, buf
);
670 static struct videobuf_queue_ops mx2_videobuf_ops
= {
671 .buf_setup
= mx2_videobuf_setup
,
672 .buf_prepare
= mx2_videobuf_prepare
,
673 .buf_queue
= mx2_videobuf_queue
,
674 .buf_release
= mx2_videobuf_release
,
677 static void mx2_camera_init_videobuf(struct videobuf_queue
*q
,
678 struct soc_camera_device
*icd
)
680 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
681 struct mx2_camera_dev
*pcdev
= ici
->priv
;
683 videobuf_queue_dma_contig_init(q
, &mx2_videobuf_ops
, pcdev
->dev
,
684 &pcdev
->lock
, V4L2_BUF_TYPE_VIDEO_CAPTURE
,
685 V4L2_FIELD_NONE
, sizeof(struct mx2_buffer
), icd
);
688 #define MX2_BUS_FLAGS (SOCAM_DATAWIDTH_8 | \
690 SOCAM_VSYNC_ACTIVE_HIGH | \
691 SOCAM_VSYNC_ACTIVE_LOW | \
692 SOCAM_HSYNC_ACTIVE_HIGH | \
693 SOCAM_HSYNC_ACTIVE_LOW | \
694 SOCAM_PCLK_SAMPLE_RISING | \
695 SOCAM_PCLK_SAMPLE_FALLING | \
696 SOCAM_DATA_ACTIVE_HIGH | \
697 SOCAM_DATA_ACTIVE_LOW)
699 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev
*pcdev
)
704 cntl
= readl(pcdev
->base_emma
+ PRP_CNTL
);
705 writel(PRP_CNTL_SWRST
, pcdev
->base_emma
+ PRP_CNTL
);
706 while (count
++ < 100) {
707 if (!(readl(pcdev
->base_emma
+ PRP_CNTL
) & PRP_CNTL_SWRST
))
716 static void mx27_camera_emma_buf_init(struct soc_camera_device
*icd
,
719 struct soc_camera_host
*ici
=
720 to_soc_camera_host(icd
->dev
.parent
);
721 struct mx2_camera_dev
*pcdev
= ici
->priv
;
723 writel(pcdev
->discard_buffer_dma
,
724 pcdev
->base_emma
+ PRP_DEST_RGB1_PTR
);
725 writel(pcdev
->discard_buffer_dma
,
726 pcdev
->base_emma
+ PRP_DEST_RGB2_PTR
);
729 * We only use the EMMA engine to get rid of the broken
730 * DMA Engine. No color space consversion at the moment.
731 * We set the incomming and outgoing pixelformat to an
732 * 16 Bit wide format and adjust the bytesperline
733 * accordingly. With this configuration the inputdata
734 * will not be changed by the emma and could be any type
735 * of 16 Bit Pixelformat.
737 writel(PRP_CNTL_CH1EN
|
739 PRP_CNTL_DATA_IN_RGB16
|
740 PRP_CNTL_CH1_OUT_RGB16
|
743 PRP_CNTL_CH1_TSKIP(0) |
744 PRP_CNTL_IN_TSKIP(0),
745 pcdev
->base_emma
+ PRP_CNTL
);
747 writel(((bytesperline
>> 1) << 16) | icd
->user_height
,
748 pcdev
->base_emma
+ PRP_SRC_FRAME_SIZE
);
749 writel(((bytesperline
>> 1) << 16) | icd
->user_height
,
750 pcdev
->base_emma
+ PRP_CH1_OUT_IMAGE_SIZE
);
752 pcdev
->base_emma
+ PRP_DEST_CH1_LINE_STRIDE
);
753 writel(0x2ca00565, /* RGB565 */
754 pcdev
->base_emma
+ PRP_SRC_PIXEL_FORMAT_CNTL
);
755 writel(0x2ca00565, /* RGB565 */
756 pcdev
->base_emma
+ PRP_CH1_PIXEL_FORMAT_CNTL
);
758 /* Enable interrupts */
759 writel(PRP_INTR_RDERR
|
766 pcdev
->base_emma
+ PRP_INTR_CNTL
);
769 static int mx2_camera_set_bus_param(struct soc_camera_device
*icd
,
772 struct soc_camera_host
*ici
=
773 to_soc_camera_host(icd
->dev
.parent
);
774 struct mx2_camera_dev
*pcdev
= ici
->priv
;
775 unsigned long camera_flags
, common_flags
;
778 u32 csicr1
= pcdev
->csicr1
;
780 camera_flags
= icd
->ops
->query_bus_param(icd
);
782 common_flags
= soc_camera_bus_param_compatible(camera_flags
,
787 if ((common_flags
& SOCAM_HSYNC_ACTIVE_HIGH
) &&
788 (common_flags
& SOCAM_HSYNC_ACTIVE_LOW
)) {
789 if (pcdev
->platform_flags
& MX2_CAMERA_HSYNC_HIGH
)
790 common_flags
&= ~SOCAM_HSYNC_ACTIVE_LOW
;
792 common_flags
&= ~SOCAM_HSYNC_ACTIVE_HIGH
;
795 if ((common_flags
& SOCAM_PCLK_SAMPLE_RISING
) &&
796 (common_flags
& SOCAM_PCLK_SAMPLE_FALLING
)) {
797 if (pcdev
->platform_flags
& MX2_CAMERA_PCLK_SAMPLE_RISING
)
798 common_flags
&= ~SOCAM_PCLK_SAMPLE_FALLING
;
800 common_flags
&= ~SOCAM_PCLK_SAMPLE_RISING
;
803 ret
= icd
->ops
->set_bus_param(icd
, common_flags
);
807 if (common_flags
& SOCAM_PCLK_SAMPLE_RISING
)
808 csicr1
|= CSICR1_REDGE
;
809 if (common_flags
& SOCAM_PCLK_SAMPLE_FALLING
)
810 csicr1
|= CSICR1_INV_PCLK
;
811 if (common_flags
& SOCAM_VSYNC_ACTIVE_HIGH
)
812 csicr1
|= CSICR1_SOF_POL
;
813 if (common_flags
& SOCAM_HSYNC_ACTIVE_HIGH
)
814 csicr1
|= CSICR1_HSYNC_POL
;
815 if (pcdev
->platform_flags
& MX2_CAMERA_SWAP16
)
816 csicr1
|= CSICR1_SWAP16_EN
;
817 if (pcdev
->platform_flags
& MX2_CAMERA_EXT_VSYNC
)
818 csicr1
|= CSICR1_EXT_VSYNC
;
819 if (pcdev
->platform_flags
& MX2_CAMERA_CCIR
)
820 csicr1
|= CSICR1_CCIR_EN
;
821 if (pcdev
->platform_flags
& MX2_CAMERA_CCIR_INTERLACE
)
822 csicr1
|= CSICR1_CCIR_MODE
;
823 if (pcdev
->platform_flags
& MX2_CAMERA_GATED_CLOCK
)
824 csicr1
|= CSICR1_GCLK_MODE
;
825 if (pcdev
->platform_flags
& MX2_CAMERA_INV_DATA
)
826 csicr1
|= CSICR1_INV_DATA
;
827 if (pcdev
->platform_flags
& MX2_CAMERA_PACK_DIR_MSB
)
828 csicr1
|= CSICR1_PACK_DIR
;
830 pcdev
->csicr1
= csicr1
;
832 bytesperline
= soc_mbus_bytes_per_line(icd
->user_width
,
833 icd
->current_fmt
->host_fmt
);
834 if (bytesperline
< 0)
837 if (mx27_camera_emma(pcdev
)) {
838 ret
= mx27_camera_emma_prp_reset(pcdev
);
842 if (pcdev
->discard_buffer
)
843 dma_free_coherent(ici
->v4l2_dev
.dev
,
844 pcdev
->discard_size
, pcdev
->discard_buffer
,
845 pcdev
->discard_buffer_dma
);
848 * I didn't manage to properly enable/disable the prp
849 * on a per frame basis during running transfers,
850 * thus we allocate a buffer here and use it to
851 * discard frames when no buffer is available.
852 * Feel free to work on this ;)
854 pcdev
->discard_size
= icd
->user_height
* bytesperline
;
855 pcdev
->discard_buffer
= dma_alloc_coherent(ici
->v4l2_dev
.dev
,
856 pcdev
->discard_size
, &pcdev
->discard_buffer_dma
,
858 if (!pcdev
->discard_buffer
)
861 mx27_camera_emma_buf_init(icd
, bytesperline
);
862 } else if (cpu_is_mx25()) {
863 writel((bytesperline
* icd
->user_height
) >> 2,
864 pcdev
->base_csi
+ CSIRXCNT
);
865 writel((bytesperline
<< 16) | icd
->user_height
,
866 pcdev
->base_csi
+ CSIIMAG_PARA
);
869 writel(pcdev
->csicr1
, pcdev
->base_csi
+ CSICR1
);
874 static int mx2_camera_set_crop(struct soc_camera_device
*icd
,
877 struct v4l2_rect
*rect
= &a
->c
;
878 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
879 struct v4l2_mbus_framefmt mf
;
882 soc_camera_limit_side(&rect
->left
, &rect
->width
, 0, 2, 4096);
883 soc_camera_limit_side(&rect
->top
, &rect
->height
, 0, 2, 4096);
885 ret
= v4l2_subdev_call(sd
, video
, s_crop
, a
);
889 /* The capture device might have changed its output */
890 ret
= v4l2_subdev_call(sd
, video
, g_mbus_fmt
, &mf
);
894 dev_dbg(icd
->dev
.parent
, "Sensor cropped %dx%d\n",
895 mf
.width
, mf
.height
);
897 icd
->user_width
= mf
.width
;
898 icd
->user_height
= mf
.height
;
903 static int mx2_camera_set_fmt(struct soc_camera_device
*icd
,
904 struct v4l2_format
*f
)
906 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
907 struct mx2_camera_dev
*pcdev
= ici
->priv
;
908 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
909 const struct soc_camera_format_xlate
*xlate
;
910 struct v4l2_pix_format
*pix
= &f
->fmt
.pix
;
911 struct v4l2_mbus_framefmt mf
;
914 xlate
= soc_camera_xlate_by_fourcc(icd
, pix
->pixelformat
);
916 dev_warn(icd
->dev
.parent
, "Format %x not found\n",
921 mf
.width
= pix
->width
;
922 mf
.height
= pix
->height
;
923 mf
.field
= pix
->field
;
924 mf
.colorspace
= pix
->colorspace
;
925 mf
.code
= xlate
->code
;
927 ret
= v4l2_subdev_call(sd
, video
, s_mbus_fmt
, &mf
);
928 if (ret
< 0 && ret
!= -ENOIOCTLCMD
)
931 if (mf
.code
!= xlate
->code
)
934 pix
->width
= mf
.width
;
935 pix
->height
= mf
.height
;
936 pix
->field
= mf
.field
;
937 pix
->colorspace
= mf
.colorspace
;
938 icd
->current_fmt
= xlate
;
943 static int mx2_camera_try_fmt(struct soc_camera_device
*icd
,
944 struct v4l2_format
*f
)
946 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
947 struct mx2_camera_dev
*pcdev
= ici
->priv
;
948 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
949 const struct soc_camera_format_xlate
*xlate
;
950 struct v4l2_pix_format
*pix
= &f
->fmt
.pix
;
951 struct v4l2_mbus_framefmt mf
;
952 __u32 pixfmt
= pix
->pixelformat
;
953 unsigned int width_limit
;
956 xlate
= soc_camera_xlate_by_fourcc(icd
, pixfmt
);
957 if (pixfmt
&& !xlate
) {
958 dev_warn(icd
->dev
.parent
, "Format %x not found\n", pixfmt
);
962 /* FIXME: implement MX27 limits */
964 /* limit to MX25 hardware capabilities */
966 if (xlate
->host_fmt
->bits_per_sample
<= 8)
967 width_limit
= 0xffff * 4;
969 width_limit
= 0xffff * 2;
970 /* CSIIMAG_PARA limit */
971 if (pix
->width
> width_limit
)
972 pix
->width
= width_limit
;
973 if (pix
->height
> 0xffff)
974 pix
->height
= 0xffff;
976 pix
->bytesperline
= soc_mbus_bytes_per_line(pix
->width
,
978 if (pix
->bytesperline
< 0)
979 return pix
->bytesperline
;
980 pix
->sizeimage
= pix
->height
* pix
->bytesperline
;
981 if (pix
->sizeimage
> (4 * 0x3ffff)) { /* CSIRXCNT limit */
982 dev_warn(icd
->dev
.parent
,
983 "Image size (%u) above limit\n",
989 /* limit to sensor capabilities */
990 mf
.width
= pix
->width
;
991 mf
.height
= pix
->height
;
992 mf
.field
= pix
->field
;
993 mf
.colorspace
= pix
->colorspace
;
994 mf
.code
= xlate
->code
;
996 ret
= v4l2_subdev_call(sd
, video
, try_mbus_fmt
, &mf
);
1000 if (mf
.field
== V4L2_FIELD_ANY
)
1001 mf
.field
= V4L2_FIELD_NONE
;
1002 if (mf
.field
!= V4L2_FIELD_NONE
) {
1003 dev_err(icd
->dev
.parent
, "Field type %d unsupported.\n",
1008 pix
->width
= mf
.width
;
1009 pix
->height
= mf
.height
;
1010 pix
->field
= mf
.field
;
1011 pix
->colorspace
= mf
.colorspace
;
1016 static int mx2_camera_querycap(struct soc_camera_host
*ici
,
1017 struct v4l2_capability
*cap
)
1019 /* cap->name is set by the friendly caller:-> */
1020 strlcpy(cap
->card
, MX2_CAM_DRIVER_DESCRIPTION
, sizeof(cap
->card
));
1021 cap
->version
= MX2_CAM_VERSION_CODE
;
1022 cap
->capabilities
= V4L2_CAP_VIDEO_CAPTURE
| V4L2_CAP_STREAMING
;
1027 static int mx2_camera_reqbufs(struct soc_camera_file
*icf
,
1028 struct v4l2_requestbuffers
*p
)
1032 for (i
= 0; i
< p
->count
; i
++) {
1033 struct mx2_buffer
*buf
= container_of(icf
->vb_vidq
.bufs
[i
],
1034 struct mx2_buffer
, vb
);
1035 INIT_LIST_HEAD(&buf
->vb
.queue
);
1041 #ifdef CONFIG_MACH_MX27
1042 static void mx27_camera_frame_done(struct mx2_camera_dev
*pcdev
, int state
)
1044 struct videobuf_buffer
*vb
;
1045 struct mx2_buffer
*buf
;
1046 unsigned long flags
;
1049 spin_lock_irqsave(&pcdev
->lock
, flags
);
1051 if (!pcdev
->active
) {
1052 dev_err(pcdev
->dev
, "%s called with no active buffer!\n",
1057 vb
= &pcdev
->active
->vb
;
1058 buf
= container_of(vb
, struct mx2_buffer
, vb
);
1059 WARN_ON(list_empty(&vb
->queue
));
1060 dev_dbg(pcdev
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
1061 vb
, vb
->baddr
, vb
->bsize
);
1063 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
1064 list_del_init(&vb
->queue
);
1066 do_gettimeofday(&vb
->ts
);
1071 if (list_empty(&pcdev
->capture
)) {
1072 pcdev
->active
= NULL
;
1076 pcdev
->active
= list_entry(pcdev
->capture
.next
,
1077 struct mx2_buffer
, vb
.queue
);
1079 vb
= &pcdev
->active
->vb
;
1080 vb
->state
= VIDEOBUF_ACTIVE
;
1082 ret
= imx_dma_setup_single(pcdev
->dma
, videobuf_to_dma_contig(vb
),
1083 vb
->size
, (u32
)pcdev
->base_dma
+ 0x10, DMA_MODE_READ
);
1086 vb
->state
= VIDEOBUF_ERROR
;
1087 pcdev
->active
= NULL
;
1092 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
1095 static void mx27_camera_dma_err_callback(int channel
, void *data
, int err
)
1097 struct mx2_camera_dev
*pcdev
= data
;
1099 mx27_camera_frame_done(pcdev
, VIDEOBUF_ERROR
);
1102 static void mx27_camera_dma_callback(int channel
, void *data
)
1104 struct mx2_camera_dev
*pcdev
= data
;
1106 mx27_camera_frame_done(pcdev
, VIDEOBUF_DONE
);
1109 #define DMA_REQ_CSI_RX 31 /* FIXME: Add this to a resource */
1111 static int __devinit
mx27_camera_dma_init(struct platform_device
*pdev
,
1112 struct mx2_camera_dev
*pcdev
)
1116 pcdev
->dma
= imx_dma_request_by_prio("CSI RX DMA", DMA_PRIO_HIGH
);
1117 if (pcdev
->dma
< 0) {
1118 dev_err(&pdev
->dev
, "%s failed to request DMA channel\n",
1123 err
= imx_dma_setup_handlers(pcdev
->dma
, mx27_camera_dma_callback
,
1124 mx27_camera_dma_err_callback
, pcdev
);
1126 dev_err(&pdev
->dev
, "%s failed to set DMA callback\n",
1131 err
= imx_dma_config_channel(pcdev
->dma
,
1132 IMX_DMA_MEMSIZE_32
| IMX_DMA_TYPE_FIFO
,
1133 IMX_DMA_MEMSIZE_32
| IMX_DMA_TYPE_LINEAR
,
1136 dev_err(&pdev
->dev
, "%s failed to config DMA channel\n",
1141 imx_dma_config_burstlen(pcdev
->dma
, 64);
1146 imx_dma_free(pcdev
->dma
);
1150 #endif /* CONFIG_MACH_MX27 */
1152 static unsigned int mx2_camera_poll(struct file
*file
, poll_table
*pt
)
1154 struct soc_camera_file
*icf
= file
->private_data
;
1156 return videobuf_poll_stream(file
, &icf
->vb_vidq
, pt
);
1159 static struct soc_camera_host_ops mx2_soc_camera_host_ops
= {
1160 .owner
= THIS_MODULE
,
1161 .add
= mx2_camera_add_device
,
1162 .remove
= mx2_camera_remove_device
,
1163 .set_fmt
= mx2_camera_set_fmt
,
1164 .set_crop
= mx2_camera_set_crop
,
1165 .try_fmt
= mx2_camera_try_fmt
,
1166 .init_videobuf
= mx2_camera_init_videobuf
,
1167 .reqbufs
= mx2_camera_reqbufs
,
1168 .poll
= mx2_camera_poll
,
1169 .querycap
= mx2_camera_querycap
,
1170 .set_bus_param
= mx2_camera_set_bus_param
,
1173 static void mx27_camera_frame_done_emma(struct mx2_camera_dev
*pcdev
,
1174 int bufnum
, int state
)
1176 struct mx2_buffer
*buf
;
1177 struct videobuf_buffer
*vb
;
1180 if (!list_empty(&pcdev
->active_bufs
)) {
1181 buf
= list_entry(pcdev
->active_bufs
.next
,
1182 struct mx2_buffer
, vb
.queue
);
1184 BUG_ON(buf
->bufnum
!= bufnum
);
1188 phys
= videobuf_to_dma_contig(vb
);
1189 if (readl(pcdev
->base_emma
+ PRP_DEST_RGB1_PTR
+ 4 * bufnum
)
1191 dev_err(pcdev
->dev
, "%p != %p\n", phys
,
1192 readl(pcdev
->base_emma
+
1197 dev_dbg(pcdev
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
, vb
,
1198 vb
->baddr
, vb
->bsize
);
1200 list_del(&vb
->queue
);
1202 do_gettimeofday(&vb
->ts
);
1208 if (list_empty(&pcdev
->capture
)) {
1209 writel(pcdev
->discard_buffer_dma
, pcdev
->base_emma
+
1210 PRP_DEST_RGB1_PTR
+ 4 * bufnum
);
1214 buf
= list_entry(pcdev
->capture
.next
,
1215 struct mx2_buffer
, vb
.queue
);
1217 buf
->bufnum
= !bufnum
;
1219 list_move_tail(pcdev
->capture
.next
, &pcdev
->active_bufs
);
1222 vb
->state
= VIDEOBUF_ACTIVE
;
1224 phys
= videobuf_to_dma_contig(vb
);
1225 writel(phys
, pcdev
->base_emma
+ PRP_DEST_RGB1_PTR
+ 4 * bufnum
);
1228 static irqreturn_t
mx27_camera_emma_irq(int irq_emma
, void *data
)
1230 struct mx2_camera_dev
*pcdev
= data
;
1231 unsigned int status
= readl(pcdev
->base_emma
+ PRP_INTRSTATUS
);
1232 struct mx2_buffer
*buf
;
1234 if (status
& (1 << 7)) { /* overflow */
1237 * We only disable channel 1 here since this is the only
1240 * FIXME: the correct DMA overflow handling should be resetting
1241 * the buffer, returning an error frame, and continuing with
1244 cntl
= readl(pcdev
->base_emma
+ PRP_CNTL
);
1245 writel(cntl
& ~PRP_CNTL_CH1EN
, pcdev
->base_emma
+ PRP_CNTL
);
1246 writel(cntl
, pcdev
->base_emma
+ PRP_CNTL
);
1248 if ((status
& (3 << 5)) == (3 << 5)
1249 && !list_empty(&pcdev
->active_bufs
)) {
1251 * Both buffers have triggered, process the one we're expecting
1254 buf
= list_entry(pcdev
->active_bufs
.next
,
1255 struct mx2_buffer
, vb
.queue
);
1256 mx27_camera_frame_done_emma(pcdev
, buf
->bufnum
, VIDEOBUF_DONE
);
1257 status
&= ~(1 << (6 - buf
->bufnum
)); /* mark processed */
1259 if (status
& (1 << 6))
1260 mx27_camera_frame_done_emma(pcdev
, 0, VIDEOBUF_DONE
);
1261 if (status
& (1 << 5))
1262 mx27_camera_frame_done_emma(pcdev
, 1, VIDEOBUF_DONE
);
1264 writel(status
, pcdev
->base_emma
+ PRP_INTRSTATUS
);
1269 static int __devinit
mx27_camera_emma_init(struct mx2_camera_dev
*pcdev
)
1271 struct resource
*res_emma
= pcdev
->res_emma
;
1274 if (!request_mem_region(res_emma
->start
, resource_size(res_emma
),
1275 MX2_CAM_DRV_NAME
)) {
1280 pcdev
->base_emma
= ioremap(res_emma
->start
, resource_size(res_emma
));
1281 if (!pcdev
->base_emma
) {
1286 err
= request_irq(pcdev
->irq_emma
, mx27_camera_emma_irq
, 0,
1287 MX2_CAM_DRV_NAME
, pcdev
);
1289 dev_err(pcdev
->dev
, "Camera EMMA interrupt register failed \n");
1293 pcdev
->clk_emma
= clk_get(NULL
, "emma");
1294 if (IS_ERR(pcdev
->clk_emma
)) {
1295 err
= PTR_ERR(pcdev
->clk_emma
);
1299 clk_enable(pcdev
->clk_emma
);
1301 err
= mx27_camera_emma_prp_reset(pcdev
);
1303 goto exit_clk_emma_put
;
1308 clk_disable(pcdev
->clk_emma
);
1309 clk_put(pcdev
->clk_emma
);
1311 free_irq(pcdev
->irq_emma
, pcdev
);
1313 iounmap(pcdev
->base_emma
);
1315 release_mem_region(res_emma
->start
, resource_size(res_emma
));
1320 static int __devinit
mx2_camera_probe(struct platform_device
*pdev
)
1322 struct mx2_camera_dev
*pcdev
;
1323 struct resource
*res_csi
, *res_emma
;
1324 void __iomem
*base_csi
;
1325 int irq_csi
, irq_emma
;
1326 irq_handler_t mx2_cam_irq_handler
= cpu_is_mx25() ? mx25_camera_irq
1330 dev_dbg(&pdev
->dev
, "initialising\n");
1332 res_csi
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1333 irq_csi
= platform_get_irq(pdev
, 0);
1334 if (res_csi
== NULL
|| irq_csi
< 0) {
1335 dev_err(&pdev
->dev
, "Missing platform resources data\n");
1340 pcdev
= kzalloc(sizeof(*pcdev
), GFP_KERNEL
);
1342 dev_err(&pdev
->dev
, "Could not allocate pcdev\n");
1347 pcdev
->clk_csi
= clk_get(&pdev
->dev
, NULL
);
1348 if (IS_ERR(pcdev
->clk_csi
)) {
1349 err
= PTR_ERR(pcdev
->clk_csi
);
1353 dev_dbg(&pdev
->dev
, "Camera clock frequency: %ld\n",
1354 clk_get_rate(pcdev
->clk_csi
));
1356 /* Initialize DMA */
1357 #ifdef CONFIG_MACH_MX27
1358 if (cpu_is_mx27()) {
1359 err
= mx27_camera_dma_init(pdev
, pcdev
);
1363 #endif /* CONFIG_MACH_MX27 */
1365 pcdev
->res_csi
= res_csi
;
1366 pcdev
->pdata
= pdev
->dev
.platform_data
;
1370 pcdev
->platform_flags
= pcdev
->pdata
->flags
;
1372 rate
= clk_round_rate(pcdev
->clk_csi
, pcdev
->pdata
->clk
* 2);
1377 err
= clk_set_rate(pcdev
->clk_csi
, rate
);
1382 INIT_LIST_HEAD(&pcdev
->capture
);
1383 INIT_LIST_HEAD(&pcdev
->active_bufs
);
1384 spin_lock_init(&pcdev
->lock
);
1387 * Request the regions.
1389 if (!request_mem_region(res_csi
->start
, resource_size(res_csi
),
1390 MX2_CAM_DRV_NAME
)) {
1395 base_csi
= ioremap(res_csi
->start
, resource_size(res_csi
));
1400 pcdev
->irq_csi
= irq_csi
;
1401 pcdev
->base_csi
= base_csi
;
1402 pcdev
->base_dma
= res_csi
->start
;
1403 pcdev
->dev
= &pdev
->dev
;
1405 err
= request_irq(pcdev
->irq_csi
, mx2_cam_irq_handler
, 0,
1406 MX2_CAM_DRV_NAME
, pcdev
);
1408 dev_err(pcdev
->dev
, "Camera interrupt register failed \n");
1412 if (cpu_is_mx27()) {
1414 res_emma
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1415 irq_emma
= platform_get_irq(pdev
, 1);
1417 if (res_emma
&& irq_emma
>= 0) {
1418 dev_info(&pdev
->dev
, "Using EMMA\n");
1419 pcdev
->use_emma
= 1;
1420 pcdev
->res_emma
= res_emma
;
1421 pcdev
->irq_emma
= irq_emma
;
1422 if (mx27_camera_emma_init(pcdev
))
1427 pcdev
->soc_host
.drv_name
= MX2_CAM_DRV_NAME
,
1428 pcdev
->soc_host
.ops
= &mx2_soc_camera_host_ops
,
1429 pcdev
->soc_host
.priv
= pcdev
;
1430 pcdev
->soc_host
.v4l2_dev
.dev
= &pdev
->dev
;
1431 pcdev
->soc_host
.nr
= pdev
->id
;
1432 err
= soc_camera_host_register(&pcdev
->soc_host
);
1434 goto exit_free_emma
;
1436 dev_info(&pdev
->dev
, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1437 clk_get_rate(pcdev
->clk_csi
));
1442 if (mx27_camera_emma(pcdev
)) {
1443 free_irq(pcdev
->irq_emma
, pcdev
);
1444 clk_disable(pcdev
->clk_emma
);
1445 clk_put(pcdev
->clk_emma
);
1446 iounmap(pcdev
->base_emma
);
1447 release_mem_region(res_emma
->start
, resource_size(res_emma
));
1450 free_irq(pcdev
->irq_csi
, pcdev
);
1454 release_mem_region(res_csi
->start
, resource_size(res_csi
));
1456 #ifdef CONFIG_MACH_MX27
1458 imx_dma_free(pcdev
->dma
);
1460 clk_put(pcdev
->clk_csi
);
1461 #endif /* CONFIG_MACH_MX27 */
1468 static int __devexit
mx2_camera_remove(struct platform_device
*pdev
)
1470 struct soc_camera_host
*soc_host
= to_soc_camera_host(&pdev
->dev
);
1471 struct mx2_camera_dev
*pcdev
= container_of(soc_host
,
1472 struct mx2_camera_dev
, soc_host
);
1473 struct resource
*res
;
1475 clk_put(pcdev
->clk_csi
);
1476 #ifdef CONFIG_MACH_MX27
1478 imx_dma_free(pcdev
->dma
);
1479 #endif /* CONFIG_MACH_MX27 */
1480 free_irq(pcdev
->irq_csi
, pcdev
);
1481 if (mx27_camera_emma(pcdev
))
1482 free_irq(pcdev
->irq_emma
, pcdev
);
1484 soc_camera_host_unregister(&pcdev
->soc_host
);
1486 iounmap(pcdev
->base_csi
);
1488 if (mx27_camera_emma(pcdev
)) {
1489 clk_disable(pcdev
->clk_emma
);
1490 clk_put(pcdev
->clk_emma
);
1491 iounmap(pcdev
->base_emma
);
1492 res
= pcdev
->res_emma
;
1493 release_mem_region(res
->start
, resource_size(res
));
1496 res
= pcdev
->res_csi
;
1497 release_mem_region(res
->start
, resource_size(res
));
1501 dev_info(&pdev
->dev
, "MX2 Camera driver unloaded\n");
1506 static struct platform_driver mx2_camera_driver
= {
1508 .name
= MX2_CAM_DRV_NAME
,
1510 .remove
= __devexit_p(mx2_camera_remove
),
1514 static int __init
mx2_camera_init(void)
1516 return platform_driver_probe(&mx2_camera_driver
, &mx2_camera_probe
);
1519 static void __exit
mx2_camera_exit(void)
1521 return platform_driver_unregister(&mx2_camera_driver
);
1524 module_init(mx2_camera_init
);
1525 module_exit(mx2_camera_exit
);
1527 MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
1528 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1529 MODULE_LICENSE("GPL");