1 STMicroelectronics 10/100/1000 Synopsys Ethernet driver
3 Copyright (C) 2007-2010 STMicroelectronics Ltd
4 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
6 This is the driver for the MAC 10/100/1000 on-chip Ethernet controllers
7 (Synopsys IP blocks); it has been fully tested on STLinux platforms.
9 Currently this network device driver is for all STM embedded MAC/GMAC
10 (i.e. 7xxx/5xxx SoCs) and it's known working on other platforms i.e. ARM SPEAr.
12 DWC Ether MAC 10/100/1000 Universal version 3.41a and DWC Ether MAC 10/100
13 Universal version 4.0 have been used for developing the first code
16 Please, for more information also visit: www.stlinux.com
18 1) Kernel Configuration
19 The kernel configuration option is STMMAC_ETH:
20 Device Drivers ---> Network device support ---> Ethernet (1000 Mbit) --->
21 STMicroelectronics 10/100/1000 Ethernet driver (STMMAC_ETH)
23 2) Driver parameters list:
24 debug: message level (0: no output, 16: all);
25 phyaddr: to manually provide the physical address to the PHY device;
26 dma_rxsize: DMA rx ring size;
27 dma_txsize: DMA tx ring size;
28 buf_sz: DMA buffer size;
29 tc: control the HW FIFO threshold;
30 tx_coe: Enable/Disable Tx Checksum Offload engine;
31 watchdog: transmit timeout (in milliseconds);
32 flow_ctrl: Flow control ability [on/off];
33 pause: Flow Control Pause Time;
34 tmrate: timer period (only if timer optimisation is configured).
36 3) Command line options
37 Driver parameters can be also passed in command line by using:
38 stmmaceth=dma_rxsize:128,dma_txsize:512
40 4) Driver information and notes
43 The xmit method is invoked when the kernel needs to transmit a packet; it sets
44 the descriptors in the ring and informs the DMA engine that there is a packet
45 ready to be transmitted.
46 Once the controller has finished transmitting the packet, an interrupt is
47 triggered; So the driver will be able to release the socket buffers.
48 By default, the driver sets the NETIF_F_SG bit in the features field of the
49 net_device structure enabling the scatter/gather feature.
52 When one or more packets are received, an interrupt happens. The interrupts
53 are not queued so the driver has to scan all the descriptors in the ring during
55 This is based on NAPI so the interrupt handler signals only if there is work to be
57 Then the poll method will be scheduled at some future point.
58 The incoming packets are stored, by the DMA, in a list of pre-allocated socket
59 buffers in order to avoid the memcpy (Zero-copy).
61 4.3) Timer-Driver Interrupt
62 Instead of having the device that asynchronously notifies the frame receptions, the
63 driver configures a timer to generate an interrupt at regular intervals.
64 Based on the granularity of the timer, the frames that are received by the device
65 will experience different levels of latency. Some NICs have dedicated timer
66 device to perform this task. STMMAC can use either the RTC device or the TMU
67 channel 2 on STLinux platforms.
68 The timers frequency can be passed to the driver as parameter; when change it,
69 take care of both hardware capability and network stability/performance impact.
70 Several performance tests on STM platforms showed this optimisation allows to spare
71 the CPU while having the maximum throughput.
74 Wake up on Lan feature through Magic and Unicast frames are supported for the GMAC
78 Driver handles both normal and enhanced descriptors. The latter has been only
79 tested on DWC Ether MAC 10/100/1000 Universal version 3.41a and later.
81 STMMAC supports DMA descriptor to operate both in dual buffer (RING)
82 and linked-list(CHAINED) mode. In RING each descriptor points to two
83 data buffer pointers whereas in CHAINED mode they point to only one data
84 buffer pointer. RING mode is the default.
86 In CHAINED mode each descriptor will have pointer to next descriptor in
87 the list, hence creating the explicit chaining in the descriptor itself,
88 whereas such explicit chaining is not possible in RING mode.
91 Ethtool is supported. Driver statistics and internal errors can be taken using:
92 ethtool -S ethX command. It is possible to dump registers etc.
94 4.7) Jumbo and Segmentation Offloading
95 Jumbo frames are supported and tested for the GMAC.
96 The GSO has been also added but it's performed in software.
100 The driver is compatible with PAL to work with PHY and GPHY devices.
102 4.9) Platform information
103 Several driver's information can be passed through the platform
104 These are included in the include/linux/stmmac.h header file
105 and detailed below as well:
107 struct plat_stmmacenet_data {
111 struct stmmac_mdio_bus_data *mdio_bus_data;
119 int force_sf_dma_mode;
120 void (*fix_mac_speed)(void *priv, unsigned int speed);
121 void (*bus_setup)(void __iomem *ioaddr);
122 int (*init)(struct platform_device *pdev);
123 void (*exit)(struct platform_device *pdev);
128 o bus_id: bus identifier.
129 o phy_addr: the physical address can be passed from the platform.
130 If it is set to -1 the driver will automatically
131 detect it at run-time by probing all the 32 addresses.
132 o interface: PHY device's interface.
133 o mdio_bus_data: specific platform fields for the MDIO bus.
134 o pbl: the Programmable Burst Length is maximum number of beats to
135 be transferred in one DMA transaction.
136 GMAC also enables the 4xPBL by default.
137 o clk_csr: CSR Clock range selection.
138 o has_gmac: uses the GMAC core.
139 o enh_desc: if sets the MAC will use the enhanced descriptor structure.
140 o tx_coe: core is able to perform the tx csum in HW.
141 o bugged_jumbo: some HWs are not able to perform the csum in HW for
142 over-sized frames due to limited buffer sizes.
143 Setting this flag the csum will be done in SW on
145 o pmt: core has the embedded power module (optional).
146 o force_sf_dma_mode: force DMA to use the Store and Forward mode
147 instead of the Threshold.
148 o fix_mac_speed: this callback is used for modifying some syscfg registers
149 (on ST SoCs) according to the link speed negotiated by the
151 o bus_setup: perform HW setup of the bus. For example, on some ST platforms
152 this field is used to configure the AMBA bridge to generate more
153 efficient STBus traffic.
154 o init/exit: callbacks used for calling a custom initialisation;
155 this is sometime necessary on some platforms (e.g. ST boxes)
156 where the HW needs to have set some PIO lines or system cfg
158 o custom_cfg: this is a custom configuration that can be passed while
159 initialising the resources.
163 struct stmmac_mdio_bus_data {
165 int (*phy_reset)(void *priv);
166 unsigned int phy_mask;
172 o bus_id: bus identifier;
173 o phy_reset: hook to reset the phy device attached to the bus.
174 o phy_mask: phy mask passed when register the MDIO bus within the driver.
175 o irqs: list of IRQs, one per PHY.
176 o probed_phy_irq: if irqs is NULL, use this for probed PHY.
178 Below an example how the structures above are using on ST platforms.
180 static struct plat_stmmacenet_data stxYYY_ethernet_platform_data = {
184 .fix_mac_speed = stxYYY_ethernet_fix_mac_speed,
186 |-> to write an internal syscfg
187 | on this platform when the
188 | link speed changes from 10 to
190 .init = &stmmac_claim_resource,
192 |-> On ST SoC this calls own "PAD"
193 | manager framework to claim
194 | all the resources necessary
195 | (GPIO ...). The .custom_cfg field
196 | is used to pass a custom config.
199 Below the usage of the stmmac_mdio_bus_data: on this SoC, in fact,
200 there are two MAC cores: one MAC is for MDIO Bus/PHY emulation
201 with fixed_link support.
203 static struct stmmac_mdio_bus_data stmmac1_mdio_bus = {
206 |-> phy device on the bus_id 1
207 .phy_reset = phy_reset;
209 |-> function to provide the phy_reset on this board
213 static struct fixed_phy_status stmmac0_fixed_phy_status = {
219 During the board's device_init we can configure the first
220 MAC for fixed_link by calling:
221 fixed_phy_add(PHY_POLL, 1, &stmmac0_fixed_phy_status));)
222 and the second one, with a real PHY device attached to the bus,
223 by using the stmmac_mdio_bus_data structure (to provide the id, the
224 reset procedure etc).
226 4.10) List of source files:
229 o stmmac_main.c: main network device driver;
230 o stmmac_mdio.c: mdio functions;
231 o stmmac_ethtool.c: ethtool support;
232 o stmmac_timer.[ch]: timer code used for mitigating the driver dma interrupts
233 Only tested on ST40 platforms based.
234 o stmmac.h: private driver structure;
235 o common.h: common definitions and VFTs;
236 o descs.h: descriptor structure definitions;
237 o dwmac1000_core.c: GMAC core functions;
238 o dwmac1000_dma.c: dma functions for the GMAC chip;
239 o dwmac1000.h: specific header file for the GMAC;
240 o dwmac100_core: MAC 100 core and dma code;
241 o dwmac100_dma.c: dma funtions for the MAC chip;
242 o dwmac1000.h: specific header file for the MAC;
243 o dwmac_lib.c: generic DMA functions shared among chips
244 o enh_desc.c: functions for handling enhanced descriptors
245 o norm_desc.c: functions for handling normal descriptors
249 The driver exports many information i.e. internal statistics,
250 debug information, MAC and DMA registers etc.
252 These can be read in several ways depending on the
253 type of the information actually needed.
255 For example a user can be use the ethtool support
256 to get statistics: e.g. using: ethtool -S ethX
257 (that shows the Management counters (MMC) if supported)
258 or sees the MAC/DMA registers: e.g. using: ethtool -d ethX
260 Compiling the Kernel with CONFIG_DEBUG_FS and enabling the
261 STMMAC_DEBUG_FS option the driver will export the following
264 /sys/kernel/debug/stmmaceth/descriptors_status
265 To show the DMA TX/RX descriptor rings
267 Developer can also use the "debug" module parameter to get
268 further debug information.
270 In the end, there are other macros (that cannot be enabled
271 via menuconfig) to turn-on the RX/TX DMA debugging,
272 specific MAC core debug printk etc. Others to enable the
273 debug in the TX and RX processes.
274 All these are only useful during the developing stage
275 and should never enabled inside the code for general usage.
276 In fact, these can generate an huge amount of debug messages.
279 o XGMAC is not supported.
280 o Review the timer optimisation code to use an embedded device that will be
281 available in new chip generations.