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staging: brcm80211: remove nested include statements
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / brcm80211 / brcmsmac / wlc_bmac.c
blobdc41593d956ea7702c03e9d0363d50232efc48a6
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23
24 #include <proto/802.11.h>
25 #include <proto/802.1d.h>
26 #include <osl.h>
27 #include <bcmdefs.h>
28 #include <bcmdevs.h>
29 #include <bcmwifi.h>
30 #include <siutils.h>
31 #include <bcmsrom.h>
32 #include <bcmotp.h>
33 #include <bcmutils.h>
34 #include <wlioctl.h>
35 #include <sbconfig.h>
36 #include <sbchipc.h>
37 #include <pcicfg.h>
38 #include <sbhnddma.h>
39 #include <hnddma.h>
40 #include <hndpmu.h>
41
42 #include "wlc_types.h"
43 #include "sbhndpio.h"
44 #include "d11.h"
45 #include "wlc_cfg.h"
46 #include "wlc_rate.h"
47 #include "wlc_scb.h"
48 #include "wlc_pub.h"
49 #include "wlc_key.h"
50 #include "wlc_phy_shim.h"
51 #include "phy/wlc_phy_hal.h"
52 #include "wlc_channel.h"
53 #include "wlc_bsscfg.h"
54 #include "wlc_mac80211.h"
55 #include "wl_export.h"
56 #include "wl_ucode.h"
57 #include "d11ucode_ext.h"
58 #include "wlc_antsel.h"
59 #include "pcie_core.h"
60 #include "wlc_alloc.h"
61 #include "wl_dbg.h"
62 #include "wlc_bmac.h"
63
64 #define TIMER_INTERVAL_WATCHDOG_BMAC 1000 /* watchdog timer, in unit of ms */
65
66 #define SYNTHPU_DLY_APHY_US 3700 /* a phy synthpu_dly time in us */
67 #define SYNTHPU_DLY_BPHY_US 1050 /* b/g phy synthpu_dly time in us, default */
68 #define SYNTHPU_DLY_NPHY_US 2048 /* n phy REV3 synthpu_dly time in us, default */
69 #define SYNTHPU_DLY_LPPHY_US 300 /* lpphy synthpu_dly time in us */
70
71 #define SYNTHPU_DLY_PHY_US_QT 100 /* QT synthpu_dly time in us */
72
73 #ifndef BMAC_DUP_TO_REMOVE
74 #define WLC_RM_WAIT_TX_SUSPEND 4 /* Wait Tx Suspend */
75
76 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT value */
77
78 #endif /* BMAC_DUP_TO_REMOVE */
79
80 #define DMAREG(wlc_hw, direction, fifonum) \
81 ((direction == DMA_TX) ? \
82 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
83 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
84
85 /*
86 * The following table lists the buffer memory allocated to xmt fifos in HW.
87 * the size is in units of 256bytes(one block), total size is HW dependent
88 * ucode has default fifo partition, sw can overwrite if necessary
89 *
90 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
91 * the twiki is updated before making changes.
92 */
93
94 #define XMTFIFOTBL_STARTREV 20 /* Starting corerev for the fifo size table */
95
96 static u16 xmtfifo_sz[][NFIFO] = {
97 {20, 192, 192, 21, 17, 5}, /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
98 {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
99 {20, 192, 192, 21, 17, 5}, /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
100 {20, 192, 192, 21, 17, 5}, /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
101 {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
102 };
103
104 static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
105 static void wlc_coreinit(struct wlc_info *wlc);
106
107 /* used by wlc_wakeucode_init() */
108 static void wlc_write_inits(struct wlc_hw_info *wlc_hw, const d11init_t *inits);
109 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
110 const uint nbytes);
111 static void wlc_ucode_download(struct wlc_hw_info *wlc);
112 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
113
114 /* used by wlc_dpc() */
115 static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
116 u32 s2);
117 static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
118 static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
119
120 /* used by wlc_down() */
121 static void wlc_flushqueues(struct wlc_info *wlc);
122
123 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
124 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
125 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
126 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw,
127 uint tx_fifo);
128 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo);
129 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo);
130
131 /* Low Level Prototypes */
132 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw);
133 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw);
134 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want);
135 static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
136 u32 sel);
137 static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
138 u16 v, u32 sel);
139 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk);
140 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
141 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
142 static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
143 static bool wlc_validboardtype(struct wlc_hw_info *wlc);
144 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
145 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw);
146 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
147 static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
148 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
149 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool want, mbool flags);
150 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
151 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
152 static u32 wlc_wlintrsoff(struct wlc_info *wlc);
153 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
154 static void wlc_gpio_init(struct wlc_info *wlc);
155 static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
156 int len);
157 static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
158 int len);
159 static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
160 static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
161 static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
162 chanspec_t chanspec);
163 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
164 bool shortslot);
165 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
166 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
167 u8 rate);
168
169 /* === Low Level functions === */
170
171 void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
172 {
173 wlc_hw->shortslot = shortslot;
174
175 if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
176 wlc_suspend_mac_and_wait(wlc_hw->wlc);
177 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
178 wlc_enable_mac(wlc_hw->wlc);
179 }
180 }
181
182 /*
183 * Update the slot timing for standard 11b/g (20us slots)
184 * or shortslot 11g (9us slots)
185 * The PSM needs to be suspended for this call.
186 */
187 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
188 bool shortslot)
189 {
190 struct osl_info *osh;
191 d11regs_t *regs;
192
193 osh = wlc_hw->osh;
194 regs = wlc_hw->regs;
195
196 if (shortslot) {
197 /* 11g short slot: 11a timing */
198 W_REG(osh, &regs->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
199 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
200 } else {
201 /* 11g long slot: 11b timing */
202 W_REG(osh, &regs->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
203 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
204 }
205 }
206
207 static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
208 {
209 /* init microcode host flags */
210 wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
211
212 /* do band-specific ucode IHR, SHM, and SCR inits */
213 if (D11REV_IS(wlc_hw->corerev, 23)) {
214 if (WLCISNPHY(wlc_hw->band)) {
215 wlc_write_inits(wlc_hw, d11n0bsinitvals16);
216 } else {
217 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
218 __func__, wlc_hw->unit, wlc_hw->corerev);
219 }
220 } else {
221 if (D11REV_IS(wlc_hw->corerev, 24)) {
222 if (WLCISLCNPHY(wlc_hw->band)) {
223 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
224 } else
225 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
226 __func__, wlc_hw->unit,
227 wlc_hw->corerev);
228 } else {
229 WL_ERROR("%s: wl%d: unsupported corerev %d\n",
230 __func__, wlc_hw->unit, wlc_hw->corerev);
231 }
232 }
233 }
234
235 /* switch to new band but leave it inactive */
236 static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
237 {
238 struct wlc_hw_info *wlc_hw = wlc->hw;
239 u32 macintmask;
240
241 WL_TRACE("wl%d: wlc_setband_inact\n", wlc_hw->unit);
242
243 ASSERT(bandunit != wlc_hw->band->bandunit);
244 ASSERT(si_iscoreup(wlc_hw->sih));
245 ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
246 0);
247
248 /* disable interrupts */
249 macintmask = wl_intrsoff(wlc->wl);
250
251 /* radio off */
252 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
253
254 ASSERT(wlc_hw->clk);
255
256 wlc_bmac_core_phy_clk(wlc_hw, OFF);
257
258 wlc_setxband(wlc_hw, bandunit);
259
260 return macintmask;
261 }
262
263 /* Process received frames */
264 /*
265 * Return true if more frames need to be processed. false otherwise.
266 * Param 'bound' indicates max. # frames to process before break out.
267 */
268 static bool BCMFASTPATH
269 wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
270 {
271 struct sk_buff *p;
272 struct sk_buff *head = NULL;
273 struct sk_buff *tail = NULL;
274 uint n = 0;
275 uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
276 u32 tsf_h, tsf_l;
277 wlc_d11rxhdr_t *wlc_rxhdr = NULL;
278
279 WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
280 /* gather received frames */
281 while ((p = dma_rx(wlc_hw->di[fifo]))) {
282
283 if (!tail)
284 head = tail = p;
285 else {
286 tail->prev = p;
287 tail = p;
288 }
289
290 /* !give others some time to run! */
291 if (++n >= bound_limit)
292 break;
293 }
294
295 /* get the TSF REG reading */
296 wlc_bmac_read_tsf(wlc_hw, &tsf_l, &tsf_h);
297
298 /* post more rbufs */
299 dma_rxfill(wlc_hw->di[fifo]);
300
301 /* process each frame */
302 while ((p = head) != NULL) {
303 head = head->prev;
304 p->prev = NULL;
305
306 /* record the tsf_l in wlc_rxd11hdr */
307 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
308 wlc_rxhdr->tsf_l = cpu_to_le32(tsf_l);
309
310 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
311 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
312
313 wlc_recv(wlc_hw->wlc, p);
314 }
315
316 return n >= bound_limit;
317 }
318
319 /* second-level interrupt processing
320 * Return true if another dpc needs to be re-scheduled. false otherwise.
321 * Param 'bounded' indicates if applicable loops should be bounded.
322 */
323 bool BCMFASTPATH wlc_dpc(struct wlc_info *wlc, bool bounded)
324 {
325 u32 macintstatus;
326 struct wlc_hw_info *wlc_hw = wlc->hw;
327 d11regs_t *regs = wlc_hw->regs;
328 bool fatal = false;
329
330 if (DEVICEREMOVED(wlc)) {
331 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
332 wl_down(wlc->wl);
333 return false;
334 }
335
336 /* grab and clear the saved software intstatus bits */
337 macintstatus = wlc->macintstatus;
338 wlc->macintstatus = 0;
339
340 WL_TRACE("wl%d: wlc_dpc: macintstatus 0x%x\n",
341 wlc_hw->unit, macintstatus);
342
343 if (macintstatus & MI_PRQ) {
344 /* Process probe request FIFO */
345 ASSERT(0 && "PRQ Interrupt in non-MBSS");
346 }
347
348 /* BCN template is available */
349 /* ZZZ: Use AP_ACTIVE ? */
350 if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub) || wlc->aps_associated)
351 && (macintstatus & MI_BCNTPL)) {
352 wlc_update_beacon(wlc);
353 }
354
355 /* PMQ entry addition */
356 if (macintstatus & MI_PMQ) {
357 }
358
359 /* tx status */
360 if (macintstatus & MI_TFS) {
361 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
362 wlc->macintstatus |= MI_TFS;
363 if (fatal) {
364 WL_ERROR("MI_TFS: fatal\n");
365 goto fatal;
366 }
367 }
368
369 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
370 wlc_tbtt(wlc, regs);
371
372 /* ATIM window end */
373 if (macintstatus & MI_ATIMWINEND) {
374 WL_TRACE("wlc_isr: end of ATIM window\n");
375
376 OR_REG(wlc_hw->osh, &regs->maccommand, wlc->qvalid);
377 wlc->qvalid = 0;
378 }
379
380 /* phy tx error */
381 if (macintstatus & MI_PHYTXERR) {
382 wlc->pub->_cnt->txphyerr++;
383 }
384
385 /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
386 if (macintstatus & MI_DMAINT) {
387 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
388 wlc->macintstatus |= MI_DMAINT;
389 }
390 }
391
392 /* TX FIFO suspend/flush completion */
393 if (macintstatus & MI_TXSTOP) {
394 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
395 /* WL_ERROR("dpc: fifo_suspend_comlete\n"); */
396 }
397 }
398
399 /* noise sample collected */
400 if (macintstatus & MI_BG_NOISE) {
401 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
402 }
403
404 if (macintstatus & MI_GP0) {
405 WL_ERROR("wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n",
406 wlc_hw->unit, wlc_hw->now);
407
408 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
409 __func__, wlc_hw->sih->chip,
410 wlc_hw->sih->chiprev);
411
412 wlc->pub->_cnt->psmwds++;
413
414 /* big hammer */
415 wl_init(wlc->wl);
416 }
417
418 /* gptimer timeout */
419 if (macintstatus & MI_TO) {
420 W_REG(wlc_hw->osh, &regs->gptimer, 0);
421 }
422
423 if (macintstatus & MI_RFDISABLE) {
424 WL_TRACE("wl%d: BMAC Detected a change on the RF Disable Input\n", wlc_hw->unit);
425
426 wlc->pub->_cnt->rfdisable++;
427 wl_rfkill_set_hw_state(wlc->wl);
428 }
429
430 /* send any enq'd tx packets. Just makes sure to jump start tx */
431 if (!pktq_empty(&wlc->active_queue->q))
432 wlc_send_q(wlc, wlc->active_queue);
433
434 ASSERT(wlc_ps_check(wlc));
435
436 /* make sure the bound indication and the implementation are in sync */
437 ASSERT(bounded == true || wlc->macintstatus == 0);
438
439 /* it isn't done and needs to be resched if macintstatus is non-zero */
440 return wlc->macintstatus != 0;
441
442 fatal:
443 wl_init(wlc->wl);
444 return wlc->macintstatus != 0;
445 }
446
447 /* common low-level watchdog code */
448 void wlc_bmac_watchdog(void *arg)
449 {
450 struct wlc_info *wlc = (struct wlc_info *) arg;
451 struct wlc_hw_info *wlc_hw = wlc->hw;
452
453 WL_TRACE("wl%d: wlc_bmac_watchdog\n", wlc_hw->unit);
454
455 if (!wlc_hw->up)
456 return;
457
458 /* increment second count */
459 wlc_hw->now++;
460
461 /* Check for FIFO error interrupts */
462 wlc_bmac_fifoerrors(wlc_hw);
463
464 /* make sure RX dma has buffers */
465 dma_rxfill(wlc->hw->di[RX_FIFO]);
466
467 wlc_phy_watchdog(wlc_hw->band->pi);
468 }
469
470 void
471 wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
472 bool mute, struct txpwr_limits *txpwr)
473 {
474 uint bandunit;
475
476 WL_TRACE("wl%d: wlc_bmac_set_chanspec 0x%x\n",
477 wlc_hw->unit, chanspec);
478
479 wlc_hw->chanspec = chanspec;
480
481 /* Switch bands if necessary */
482 if (NBANDS_HW(wlc_hw) > 1) {
483 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
484 if (wlc_hw->band->bandunit != bandunit) {
485 /* wlc_bmac_setband disables other bandunit,
486 * use light band switch if not up yet
487 */
488 if (wlc_hw->up) {
489 wlc_phy_chanspec_radio_set(wlc_hw->
490 bandstate[bandunit]->
491 pi, chanspec);
492 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
493 } else {
494 wlc_setxband(wlc_hw, bandunit);
495 }
496 }
497 }
498
499 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
500
501 if (!wlc_hw->up) {
502 if (wlc_hw->clk)
503 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
504 chanspec);
505 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
506 } else {
507 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
508 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
509
510 /* Update muting of the channel */
511 wlc_bmac_mute(wlc_hw, mute, 0);
512 }
513 }
514
515 int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
516 {
517 state->machwcap = wlc_hw->machwcap;
518
519 return 0;
520 }
521
522 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
523 {
524 uint i;
525 char name[8];
526 /* ucode host flag 2 needed for pio mode, independent of band and fifo */
527 u16 pio_mhf2 = 0;
528 struct wlc_hw_info *wlc_hw = wlc->hw;
529 uint unit = wlc_hw->unit;
530 wlc_tunables_t *tune = wlc->pub->tunables;
531
532 /* name and offsets for dma_attach */
533 snprintf(name, sizeof(name), "wl%d", unit);
534
535 if (wlc_hw->di[0] == 0) { /* Init FIFOs */
536 uint addrwidth;
537 int dma_attach_err = 0;
538 struct osl_info *osh = wlc_hw->osh;
539
540 /* Find out the DMA addressing capability and let OS know
541 * All the channels within one DMA core have 'common-minimum' same
542 * capability
543 */
544 addrwidth =
545 dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
546
547 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
548 WL_ERROR("wl%d: wlc_attach: alloc_dma_resources failed\n",
549 unit);
550 return false;
551 }
552
553 /*
554 * FIFO 0
555 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
556 * RX: RX_FIFO (RX data packets)
557 */
558 ASSERT(TX_AC_BK_FIFO == 0);
559 ASSERT(RX_FIFO == 0);
560 wlc_hw->di[0] = dma_attach(osh, name, wlc_hw->sih,
561 (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
562 NULL), DMAREG(wlc_hw, DMA_RX, 0),
563 (wme ? tune->ntxd : 0), tune->nrxd,
564 tune->rxbufsz, -1, tune->nrxbufpost,
565 WL_HWRXOFF, &wl_msg_level);
566 dma_attach_err |= (NULL == wlc_hw->di[0]);
567
568 /*
569 * FIFO 1
570 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
571 * (legacy) TX_DATA_FIFO (TX data packets)
572 * RX: UNUSED
573 */
574 ASSERT(TX_AC_BE_FIFO == 1);
575 ASSERT(TX_DATA_FIFO == 1);
576 wlc_hw->di[1] = dma_attach(osh, name, wlc_hw->sih,
577 DMAREG(wlc_hw, DMA_TX, 1), NULL,
578 tune->ntxd, 0, 0, -1, 0, 0,
579 &wl_msg_level);
580 dma_attach_err |= (NULL == wlc_hw->di[1]);
581
582 /*
583 * FIFO 2
584 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
585 * RX: UNUSED
586 */
587 ASSERT(TX_AC_VI_FIFO == 2);
588 wlc_hw->di[2] = dma_attach(osh, name, wlc_hw->sih,
589 DMAREG(wlc_hw, DMA_TX, 2), NULL,
590 tune->ntxd, 0, 0, -1, 0, 0,
591 &wl_msg_level);
592 dma_attach_err |= (NULL == wlc_hw->di[2]);
593 /*
594 * FIFO 3
595 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
596 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
597 */
598 ASSERT(TX_AC_VO_FIFO == 3);
599 ASSERT(TX_CTL_FIFO == 3);
600 wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
601 DMAREG(wlc_hw, DMA_TX, 3),
602 NULL, tune->ntxd, 0, 0, -1,
603 0, 0, &wl_msg_level);
604 dma_attach_err |= (NULL == wlc_hw->di[3]);
605 /* Cleaner to leave this as if with AP defined */
606
607 if (dma_attach_err) {
608 WL_ERROR("wl%d: wlc_attach: dma_attach failed\n", unit);
609 return false;
610 }
611
612 /* get pointer to dma engine tx flow control variable */
613 for (i = 0; i < NFIFO; i++)
614 if (wlc_hw->di[i])
615 wlc_hw->txavail[i] =
616 (uint *) dma_getvar(wlc_hw->di[i],
617 "&txavail");
618 }
619
620 /* initial ucode host flags */
621 wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
622
623 return true;
624 }
625
626 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
627 {
628 uint j;
629
630 for (j = 0; j < NFIFO; j++) {
631 if (wlc_hw->di[j]) {
632 dma_detach(wlc_hw->di[j]);
633 wlc_hw->di[j] = NULL;
634 }
635 }
636 }
637
638 /* low level attach
639 * run backplane attach, init nvram
640 * run phy attach
641 * initialize software state for each core and band
642 * put the whole chip in reset(driver down state), no clock
643 */
644 int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
645 bool piomode, struct osl_info *osh, void *regsva,
646 uint bustype, void *btparam)
647 {
648 struct wlc_hw_info *wlc_hw;
649 d11regs_t *regs;
650 char *macaddr = NULL;
651 char *vars;
652 uint err = 0;
653 uint j;
654 bool wme = false;
655 shared_phy_params_t sha_params;
656
657 WL_TRACE("wl%d: wlc_bmac_attach: vendor 0x%x device 0x%x\n",
658 unit, vendor, device);
659
660 ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF);
661
662 wme = true;
663
664 wlc_hw = wlc->hw;
665 wlc_hw->wlc = wlc;
666 wlc_hw->unit = unit;
667 wlc_hw->osh = osh;
668 wlc_hw->band = wlc_hw->bandstate[0];
669 wlc_hw->_piomode = piomode;
670
671 /* populate struct wlc_hw_info with default values */
672 wlc_bmac_info_init(wlc_hw);
673
674 /*
675 * Do the hardware portion of the attach.
676 * Also initialize software state that depends on the particular hardware
677 * we are running.
678 */
679 wlc_hw->sih = si_attach((uint) device, osh, regsva, bustype, btparam,
680 &wlc_hw->vars, &wlc_hw->vars_size);
681 if (wlc_hw->sih == NULL) {
682 WL_ERROR("wl%d: wlc_bmac_attach: si_attach failed\n", unit);
683 err = 11;
684 goto fail;
685 }
686 vars = wlc_hw->vars;
687
688 /*
689 * Get vendid/devid nvram overwrites, which could be different
690 * than those the BIOS recognizes for devices on PCMCIA_BUS,
691 * SDIO_BUS, and SROMless devices on PCI_BUS.
692 */
693 #ifdef BCMBUSTYPE
694 bustype = BCMBUSTYPE;
695 #endif
696 if (bustype != SI_BUS) {
697 char *var;
698
699 var = getvar(vars, "vendid");
700 if (var) {
701 vendor = (u16) simple_strtoul(var, NULL, 0);
702 WL_ERROR("Overriding vendor id = 0x%x\n", vendor);
703 }
704 var = getvar(vars, "devid");
705 if (var) {
706 u16 devid = (u16) simple_strtoul(var, NULL, 0);
707 if (devid != 0xffff) {
708 device = devid;
709 WL_ERROR("Overriding device id = 0x%x\n",
710 device);
711 }
712 }
713
714 /* verify again the device is supported */
715 if (!wlc_chipmatch(vendor, device)) {
716 WL_ERROR("wl%d: wlc_bmac_attach: Unsupported vendor/device (0x%x/0x%x)\n",
717 unit, vendor, device);
718 err = 12;
719 goto fail;
720 }
721 }
722
723 wlc_hw->vendorid = vendor;
724 wlc_hw->deviceid = device;
725
726 /* set bar0 window to point at D11 core */
727 wlc_hw->regs = (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID, 0);
728 wlc_hw->corerev = si_corerev(wlc_hw->sih);
729
730 regs = wlc_hw->regs;
731
732 wlc->regs = wlc_hw->regs;
733
734 /* validate chip, chiprev and corerev */
735 if (!wlc_isgoodchip(wlc_hw)) {
736 err = 13;
737 goto fail;
738 }
739
740 /* initialize power control registers */
741 si_clkctl_init(wlc_hw->sih);
742
743 /* request fastclock and force fastclock for the rest of attach
744 * bring the d11 core out of reset.
745 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
746 * But it will be called again inside wlc_corereset, after d11 is out of reset.
747 */
748 wlc_clkctl_clk(wlc_hw, CLK_FAST);
749 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
750
751 if (!wlc_bmac_validate_chip_access(wlc_hw)) {
752 WL_ERROR("wl%d: wlc_bmac_attach: validate_chip_access failed\n",
753 unit);
754 err = 14;
755 goto fail;
756 }
757
758 /* get the board rev, used just below */
759 j = getintvar(vars, "boardrev");
760 /* promote srom boardrev of 0xFF to 1 */
761 if (j == BOARDREV_PROMOTABLE)
762 j = BOARDREV_PROMOTED;
763 wlc_hw->boardrev = (u16) j;
764 if (!wlc_validboardtype(wlc_hw)) {
765 WL_ERROR("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n",
766 unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
767 err = 15;
768 goto fail;
769 }
770 wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
771 wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
772 wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
773
774 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
775 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
776
777 if ((wlc_hw->sih->bustype == PCI_BUS)
778 && (si_pci_war16165(wlc_hw->sih)))
779 wlc->war16165 = true;
780
781 /* check device id(srom, nvram etc.) to set bands */
782 if (wlc_hw->deviceid == BCM43224_D11N_ID) {
783 /* Dualband boards */
784 wlc_hw->_nbands = 2;
785 } else
786 wlc_hw->_nbands = 1;
787
788 if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
789 wlc_hw->_nbands = 1;
790
791 /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
792 * init of these values
793 */
794 wlc->vendorid = wlc_hw->vendorid;
795 wlc->deviceid = wlc_hw->deviceid;
796 wlc->pub->sih = wlc_hw->sih;
797 wlc->pub->corerev = wlc_hw->corerev;
798 wlc->pub->sromrev = wlc_hw->sromrev;
799 wlc->pub->boardrev = wlc_hw->boardrev;
800 wlc->pub->boardflags = wlc_hw->boardflags;
801 wlc->pub->boardflags2 = wlc_hw->boardflags2;
802 wlc->pub->_nbands = wlc_hw->_nbands;
803
804 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
805
806 if (wlc_hw->physhim == NULL) {
807 WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_shim_attach failed\n",
808 unit);
809 err = 25;
810 goto fail;
811 }
812
813 /* pass all the parameters to wlc_phy_shared_attach in one struct */
814 sha_params.osh = osh;
815 sha_params.sih = wlc_hw->sih;
816 sha_params.physhim = wlc_hw->physhim;
817 sha_params.unit = unit;
818 sha_params.corerev = wlc_hw->corerev;
819 sha_params.vars = vars;
820 sha_params.vid = wlc_hw->vendorid;
821 sha_params.did = wlc_hw->deviceid;
822 sha_params.chip = wlc_hw->sih->chip;
823 sha_params.chiprev = wlc_hw->sih->chiprev;
824 sha_params.chippkg = wlc_hw->sih->chippkg;
825 sha_params.sromrev = wlc_hw->sromrev;
826 sha_params.boardtype = wlc_hw->sih->boardtype;
827 sha_params.boardrev = wlc_hw->boardrev;
828 sha_params.boardvendor = wlc_hw->sih->boardvendor;
829 sha_params.boardflags = wlc_hw->boardflags;
830 sha_params.boardflags2 = wlc_hw->boardflags2;
831 sha_params.bustype = wlc_hw->sih->bustype;
832 sha_params.buscorerev = wlc_hw->sih->buscorerev;
833
834 /* alloc and save pointer to shared phy state area */
835 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
836 if (!wlc_hw->phy_sh) {
837 err = 16;
838 goto fail;
839 }
840
841 /* initialize software state for each core and band */
842 for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
843 /*
844 * band0 is always 2.4Ghz
845 * band1, if present, is 5Ghz
846 */
847
848 /* So if this is a single band 11a card, use band 1 */
849 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
850 j = BAND_5G_INDEX;
851
852 wlc_setxband(wlc_hw, j);
853
854 wlc_hw->band->bandunit = j;
855 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
856 wlc->band->bandunit = j;
857 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
858 wlc->core->coreidx = si_coreidx(wlc_hw->sih);
859
860 wlc_hw->machwcap = R_REG(wlc_hw->osh, &regs->machwcap);
861 wlc_hw->machwcap_backup = wlc_hw->machwcap;
862
863 /* init tx fifo size */
864 ASSERT((wlc_hw->corerev - XMTFIFOTBL_STARTREV) <
865 ARRAY_SIZE(xmtfifo_sz));
866 wlc_hw->xmtfifo_sz =
867 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
868
869 /* Get a phy for this band */
870 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
871 (void *)regs, wlc_bmac_bandtype(wlc_hw), vars);
872 if (wlc_hw->band->pi == NULL) {
873 WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_attach failed\n",
874 unit);
875 err = 17;
876 goto fail;
877 }
878
879 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
880
881 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
882 &wlc_hw->band->phyrev,
883 &wlc_hw->band->radioid,
884 &wlc_hw->band->radiorev);
885 wlc_hw->band->abgphy_encore =
886 wlc_phy_get_encore(wlc_hw->band->pi);
887 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
888 wlc_hw->band->core_flags =
889 wlc_phy_get_coreflags(wlc_hw->band->pi);
890
891 /* verify good phy_type & supported phy revision */
892 if (WLCISNPHY(wlc_hw->band)) {
893 if (NCONF_HAS(wlc_hw->band->phyrev))
894 goto good_phy;
895 else
896 goto bad_phy;
897 } else if (WLCISLCNPHY(wlc_hw->band)) {
898 if (LCNCONF_HAS(wlc_hw->band->phyrev))
899 goto good_phy;
900 else
901 goto bad_phy;
902 } else {
903 bad_phy:
904 WL_ERROR("wl%d: wlc_bmac_attach: unsupported phy type/rev (%d/%d)\n",
905 unit,
906 wlc_hw->band->phytype, wlc_hw->band->phyrev);
907 err = 18;
908 goto fail;
909 }
910
911 good_phy:
912 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
913 * high level attach. However we can not make that change until all low level access
914 * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
915 * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
916 * low only init when all fns updated.
917 */
918 wlc->band->pi = wlc_hw->band->pi;
919 wlc->band->phytype = wlc_hw->band->phytype;
920 wlc->band->phyrev = wlc_hw->band->phyrev;
921 wlc->band->radioid = wlc_hw->band->radioid;
922 wlc->band->radiorev = wlc_hw->band->radiorev;
923
924 /* default contention windows size limits */
925 wlc_hw->band->CWmin = APHY_CWMIN;
926 wlc_hw->band->CWmax = PHY_CWMAX;
927
928 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
929 err = 19;
930 goto fail;
931 }
932 }
933
934 /* disable core to match driver "down" state */
935 wlc_coredisable(wlc_hw);
936
937 /* Match driver "down" state */
938 if (wlc_hw->sih->bustype == PCI_BUS)
939 si_pci_down(wlc_hw->sih);
940
941 /* register sb interrupt callback functions */
942 si_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
943 (void *)wlc_wlintrsrestore, NULL, wlc);
944
945 /* turn off pll and xtal to match driver "down" state */
946 wlc_bmac_xtal(wlc_hw, OFF);
947
948 /* *********************************************************************
949 * The hardware is in the DOWN state at this point. D11 core
950 * or cores are in reset with clocks off, and the board PLLs
951 * are off if possible.
952 *
953 * Beyond this point, wlc->sbclk == false and chip registers
954 * should not be touched.
955 *********************************************************************
956 */
957
958 /* init etheraddr state variables */
959 macaddr = wlc_get_macaddr(wlc_hw);
960 if (macaddr == NULL) {
961 WL_ERROR("wl%d: wlc_bmac_attach: macaddr not found\n", unit);
962 err = 21;
963 goto fail;
964 }
965 bcm_ether_atoe(macaddr, wlc_hw->etheraddr);
966 if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
967 is_zero_ether_addr(wlc_hw->etheraddr)) {
968 WL_ERROR("wl%d: wlc_bmac_attach: bad macaddr %s\n",
969 unit, macaddr);
970 err = 22;
971 goto fail;
972 }
973
974 WL_TRACE("%s:: deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
975 __func__, wlc_hw->deviceid, wlc_hw->_nbands,
976 wlc_hw->sih->boardtype, macaddr);
977
978 return err;
979
980 fail:
981 WL_ERROR("wl%d: wlc_bmac_attach: failed with err %d\n", unit, err);
982 return err;
983 }
984
985 /*
986 * Initialize wlc_info default values ...
987 * may get overrides later in this function
988 * BMAC_NOTES, move low out and resolve the dangling ones
989 */
990 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
991 {
992 struct wlc_info *wlc = wlc_hw->wlc;
993
994 /* set default sw macintmask value */
995 wlc->defmacintmask = DEF_MACINTMASK;
996
997 /* various 802.11g modes */
998 wlc_hw->shortslot = false;
999
1000 wlc_hw->SFBL = RETRY_SHORT_FB;
1001 wlc_hw->LFBL = RETRY_LONG_FB;
1002
1003 /* default mac retry limits */
1004 wlc_hw->SRL = RETRY_SHORT_DEF;
1005 wlc_hw->LRL = RETRY_LONG_DEF;
1006 wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
1007 }
1008
1009 /*
1010 * low level detach
1011 */
1012 int wlc_bmac_detach(struct wlc_info *wlc)
1013 {
1014 uint i;
1015 wlc_hwband_t *band;
1016 struct wlc_hw_info *wlc_hw = wlc->hw;
1017 int callbacks;
1018
1019 callbacks = 0;
1020
1021 if (wlc_hw->sih) {
1022 /* detach interrupt sync mechanism since interrupt is disabled and per-port
1023 * interrupt object may has been freed. this must be done before sb core switch
1024 */
1025 si_deregister_intr_callback(wlc_hw->sih);
1026
1027 if (wlc_hw->sih->bustype == PCI_BUS)
1028 si_pci_sleep(wlc_hw->sih);
1029 }
1030
1031 wlc_bmac_detach_dmapio(wlc_hw);
1032
1033 band = wlc_hw->band;
1034 for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
1035 if (band->pi) {
1036 /* Detach this band's phy */
1037 wlc_phy_detach(band->pi);
1038 band->pi = NULL;
1039 }
1040 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1041 }
1042
1043 /* Free shared phy state */
1044 wlc_phy_shared_detach(wlc_hw->phy_sh);
1045
1046 wlc_phy_shim_detach(wlc_hw->physhim);
1047
1048 /* free vars */
1049 if (wlc_hw->vars) {
1050 kfree(wlc_hw->vars);
1051 wlc_hw->vars = NULL;
1052 }
1053
1054 if (wlc_hw->sih) {
1055 si_detach(wlc_hw->sih);
1056 wlc_hw->sih = NULL;
1057 }
1058
1059 return callbacks;
1060
1061 }
1062
1063 void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
1064 {
1065 WL_TRACE("wl%d: wlc_bmac_reset\n", wlc_hw->unit);
1066
1067 wlc_hw->wlc->pub->_cnt->reset++;
1068
1069 /* reset the core */
1070 if (!DEVICEREMOVED(wlc_hw->wlc))
1071 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1072
1073 /* purge the dma rings */
1074 wlc_flushqueues(wlc_hw->wlc);
1075
1076 wlc_reset_bmac_done(wlc_hw->wlc);
1077 }
1078
1079 void
1080 wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
1081 bool mute) {
1082 u32 macintmask;
1083 bool fastclk;
1084 struct wlc_info *wlc = wlc_hw->wlc;
1085
1086 WL_TRACE("wl%d: wlc_bmac_init\n", wlc_hw->unit);
1087
1088 /* request FAST clock if not on */
1089 fastclk = wlc_hw->forcefastclk;
1090 if (!fastclk)
1091 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1092
1093 /* disable interrupts */
1094 macintmask = wl_intrsoff(wlc->wl);
1095
1096 /* set up the specified band and chanspec */
1097 wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1098 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1099
1100 /* do one-time phy inits and calibration */
1101 wlc_phy_cal_init(wlc_hw->band->pi);
1102
1103 /* core-specific initialization */
1104 wlc_coreinit(wlc);
1105
1106 /* suspend the tx fifos and mute the phy for preism cac time */
1107 if (mute)
1108 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1109
1110 /* band-specific inits */
1111 wlc_bmac_bsinit(wlc, chanspec);
1112
1113 /* restore macintmask */
1114 wl_intrsrestore(wlc->wl, macintmask);
1115
1116 /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1117 * and wlc_enable_mac() will clear this override bit.
1118 */
1119 mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1120
1121 /*
1122 * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1123 */
1124 wlc_hw->mac_suspend_depth = 1;
1125
1126 /* restore the clk */
1127 if (!fastclk)
1128 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1129 }
1130
1131 int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
1132 {
1133 uint coremask;
1134
1135 WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1136
1137 ASSERT(wlc_hw->wlc->pub->hw_up && wlc_hw->wlc->macintmask == 0);
1138
1139 /*
1140 * Enable pll and xtal, initialize the power control registers,
1141 * and force fastclock for the remainder of wlc_up().
1142 */
1143 wlc_bmac_xtal(wlc_hw, ON);
1144 si_clkctl_init(wlc_hw->sih);
1145 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1146
1147 /*
1148 * Configure pci/pcmcia here instead of in wlc_attach()
1149 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
1150 */
1151 coremask = (1 << wlc_hw->wlc->core->coreidx);
1152
1153 if (wlc_hw->sih->bustype == PCI_BUS)
1154 si_pci_setup(wlc_hw->sih, coremask);
1155
1156 ASSERT(si_coreid(wlc_hw->sih) == D11_CORE_ID);
1157
1158 /*
1159 * Need to read the hwradio status here to cover the case where the system
1160 * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1161 */
1162 if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1163 /* put SB PCI in down state again */
1164 if (wlc_hw->sih->bustype == PCI_BUS)
1165 si_pci_down(wlc_hw->sih);
1166 wlc_bmac_xtal(wlc_hw, OFF);
1167 return BCME_RADIOOFF;
1168 }
1169
1170 if (wlc_hw->sih->bustype == PCI_BUS)
1171 si_pci_up(wlc_hw->sih);
1172
1173 /* reset the d11 core */
1174 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1175
1176 return 0;
1177 }
1178
1179 int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
1180 {
1181 WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1182
1183 wlc_hw->up = true;
1184 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1185
1186 /* FULLY enable dynamic power control and d11 core interrupt */
1187 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1188 ASSERT(wlc_hw->wlc->macintmask == 0);
1189 wl_intrson(wlc_hw->wlc->wl);
1190 return 0;
1191 }
1192
1193 int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
1194 {
1195 bool dev_gone;
1196 uint callbacks = 0;
1197
1198 WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1199
1200 if (!wlc_hw->up)
1201 return callbacks;
1202
1203 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1204
1205 /* disable interrupts */
1206 if (dev_gone)
1207 wlc_hw->wlc->macintmask = 0;
1208 else {
1209 /* now disable interrupts */
1210 wl_intrsoff(wlc_hw->wlc->wl);
1211
1212 /* ensure we're running on the pll clock again */
1213 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1214 }
1215 /* down phy at the last of this stage */
1216 callbacks += wlc_phy_down(wlc_hw->band->pi);
1217
1218 return callbacks;
1219 }
1220
1221 int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
1222 {
1223 uint callbacks = 0;
1224 bool dev_gone;
1225
1226 WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1227
1228 if (!wlc_hw->up)
1229 return callbacks;
1230
1231 wlc_hw->up = false;
1232 wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1233
1234 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1235
1236 if (dev_gone) {
1237 wlc_hw->sbclk = false;
1238 wlc_hw->clk = false;
1239 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1240
1241 /* reclaim any posted packets */
1242 wlc_flushqueues(wlc_hw->wlc);
1243 } else {
1244
1245 /* Reset and disable the core */
1246 if (si_iscoreup(wlc_hw->sih)) {
1247 if (R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) &
1248 MCTL_EN_MAC)
1249 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1250 callbacks += wl_reset(wlc_hw->wlc->wl);
1251 wlc_coredisable(wlc_hw);
1252 }
1253
1254 /* turn off primary xtal and pll */
1255 if (!wlc_hw->noreset) {
1256 if (wlc_hw->sih->bustype == PCI_BUS)
1257 si_pci_down(wlc_hw->sih);
1258 wlc_bmac_xtal(wlc_hw, OFF);
1259 }
1260 }
1261
1262 return callbacks;
1263 }
1264
1265 void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
1266 {
1267 /* delay before first read of ucode state */
1268 udelay(40);
1269
1270 /* wait until ucode is no longer asleep */
1271 SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1272 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1273
1274 ASSERT(wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) != DBGST_ASLEEP);
1275 }
1276
1277 void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
1278 {
1279 memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
1280 }
1281
1282 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
1283 {
1284 return wlc_hw->band->bandtype;
1285 }
1286
1287 /* control chip clock to save power, enable dynamic clock or force fast clock */
1288 static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
1289 {
1290 if (PMUCTL_ENAB(wlc_hw->sih)) {
1291 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1292 * but mac core will still run on ALP(not HT) when it enters powersave mode,
1293 * which means the FCA bit may not be set.
1294 * should wakeup mac if driver wants it to run on HT.
1295 */
1296
1297 if (wlc_hw->clk) {
1298 if (mode == CLK_FAST) {
1299 OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1300 CCS_FORCEHT);
1301
1302 udelay(64);
1303
1304 SPINWAIT(((R_REG
1305 (wlc_hw->osh,
1306 &wlc_hw->regs->
1307 clk_ctl_st) & CCS_HTAVAIL) == 0),
1308 PMU_MAX_TRANSITION_DLY);
1309 ASSERT(R_REG
1310 (wlc_hw->osh,
1311 &wlc_hw->regs->
1312 clk_ctl_st) & CCS_HTAVAIL);
1313 } else {
1314 if ((wlc_hw->sih->pmurev == 0) &&
1315 (R_REG
1316 (wlc_hw->osh,
1317 &wlc_hw->regs->
1318 clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1319 SPINWAIT(((R_REG
1320 (wlc_hw->osh,
1321 &wlc_hw->regs->
1322 clk_ctl_st) & CCS_HTAVAIL)
1323 == 0),
1324 PMU_MAX_TRANSITION_DLY);
1325 AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1326 ~CCS_FORCEHT);
1327 }
1328 }
1329 wlc_hw->forcefastclk = (mode == CLK_FAST);
1330 } else {
1331
1332 /* old chips w/o PMU, force HT through cc,
1333 * then use FCA to verify mac is running fast clock
1334 */
1335
1336 wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
1337
1338 /* check fast clock is available (if core is not in reset) */
1339 if (wlc_hw->forcefastclk && wlc_hw->clk)
1340 ASSERT(si_core_sflags(wlc_hw->sih, 0, 0) & SISF_FCLKA);
1341
1342 /* keep the ucode wake bit on if forcefastclk is on
1343 * since we do not want ucode to put us back to slow clock
1344 * when it dozes for PM mode.
1345 * Code below matches the wake override bit with current forcefastclk state
1346 * Only setting bit in wake_override instead of waking ucode immediately
1347 * since old code (wlc.c 1.4499) had this behavior. Older code set
1348 * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1349 * (protected by an up check) was executed just below.
1350 */
1351 if (wlc_hw->forcefastclk)
1352 mboolset(wlc_hw->wake_override,
1353 WLC_WAKE_OVERRIDE_FORCEFAST);
1354 else
1355 mboolclr(wlc_hw->wake_override,
1356 WLC_WAKE_OVERRIDE_FORCEFAST);
1357 }
1358 }
1359
1360 /* set initial host flags value */
1361 static void
1362 wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1363 {
1364 struct wlc_hw_info *wlc_hw = wlc->hw;
1365
1366 memset(mhfs, 0, MHFMAX * sizeof(u16));
1367
1368 mhfs[MHF2] |= mhf2_init;
1369
1370 /* prohibit use of slowclock on multifunction boards */
1371 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1372 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1373
1374 if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1375 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1376 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1377 }
1378 }
1379
1380 /* set or clear ucode host flag bits
1381 * it has an optimization for no-change write
1382 * it only writes through shared memory when the core has clock;
1383 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1384 *
1385 *
1386 * bands values are: WLC_BAND_AUTO <--- Current band only
1387 * WLC_BAND_5G <--- 5G band only
1388 * WLC_BAND_2G <--- 2G band only
1389 * WLC_BAND_ALL <--- All bands
1390 */
1391 void
1392 wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1393 int bands)
1394 {
1395 u16 save;
1396 u16 addr[MHFMAX] = {
1397 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1398 M_HOST_FLAGS5
1399 };
1400 wlc_hwband_t *band;
1401
1402 ASSERT((val & ~mask) == 0);
1403 ASSERT(idx < MHFMAX);
1404 ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1405
1406 switch (bands) {
1407 /* Current band only or all bands,
1408 * then set the band to current band
1409 */
1410 case WLC_BAND_AUTO:
1411 case WLC_BAND_ALL:
1412 band = wlc_hw->band;
1413 break;
1414 case WLC_BAND_5G:
1415 band = wlc_hw->bandstate[BAND_5G_INDEX];
1416 break;
1417 case WLC_BAND_2G:
1418 band = wlc_hw->bandstate[BAND_2G_INDEX];
1419 break;
1420 default:
1421 ASSERT(0);
1422 band = NULL;
1423 }
1424
1425 if (band) {
1426 save = band->mhfs[idx];
1427 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1428
1429 /* optimization: only write through if changed, and
1430 * changed band is the current band
1431 */
1432 if (wlc_hw->clk && (band->mhfs[idx] != save)
1433 && (band == wlc_hw->band))
1434 wlc_bmac_write_shm(wlc_hw, addr[idx],
1435 (u16) band->mhfs[idx]);
1436 }
1437
1438 if (bands == WLC_BAND_ALL) {
1439 wlc_hw->bandstate[0]->mhfs[idx] =
1440 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1441 wlc_hw->bandstate[1]->mhfs[idx] =
1442 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1443 }
1444 }
1445
1446 u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
1447 {
1448 wlc_hwband_t *band;
1449 ASSERT(idx < MHFMAX);
1450
1451 switch (bands) {
1452 case WLC_BAND_AUTO:
1453 band = wlc_hw->band;
1454 break;
1455 case WLC_BAND_5G:
1456 band = wlc_hw->bandstate[BAND_5G_INDEX];
1457 break;
1458 case WLC_BAND_2G:
1459 band = wlc_hw->bandstate[BAND_2G_INDEX];
1460 break;
1461 default:
1462 ASSERT(0);
1463 band = NULL;
1464 }
1465
1466 if (!band)
1467 return 0;
1468
1469 return band->mhfs[idx];
1470 }
1471
1472 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
1473 {
1474 u8 idx;
1475 u16 addr[] = {
1476 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1477 M_HOST_FLAGS5
1478 };
1479
1480 ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1481
1482 for (idx = 0; idx < MHFMAX; idx++) {
1483 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1484 }
1485 }
1486
1487 /* set the maccontrol register to desired reset state and
1488 * initialize the sw cache of the register
1489 */
1490 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
1491 {
1492 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1493 wlc_hw->maccontrol = 0;
1494 wlc_hw->suspended_fifos = 0;
1495 wlc_hw->wake_override = 0;
1496 wlc_hw->mute_override = 0;
1497 wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1498 }
1499
1500 /* set or clear maccontrol bits */
1501 void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
1502 {
1503 u32 maccontrol;
1504 u32 new_maccontrol;
1505
1506 ASSERT((val & ~mask) == 0);
1507
1508 maccontrol = wlc_hw->maccontrol;
1509 new_maccontrol = (maccontrol & ~mask) | val;
1510
1511 /* if the new maccontrol value is the same as the old, nothing to do */
1512 if (new_maccontrol == maccontrol)
1513 return;
1514
1515 /* something changed, cache the new value */
1516 wlc_hw->maccontrol = new_maccontrol;
1517
1518 /* write the new values with overrides applied */
1519 wlc_mctrl_write(wlc_hw);
1520 }
1521
1522 /* write the software state of maccontrol and overrides to the maccontrol register */
1523 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
1524 {
1525 u32 maccontrol = wlc_hw->maccontrol;
1526
1527 /* OR in the wake bit if overridden */
1528 if (wlc_hw->wake_override)
1529 maccontrol |= MCTL_WAKE;
1530
1531 /* set AP and INFRA bits for mute if needed */
1532 if (wlc_hw->mute_override) {
1533 maccontrol &= ~(MCTL_AP);
1534 maccontrol |= MCTL_INFRA;
1535 }
1536
1537 W_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol, maccontrol);
1538 }
1539
1540 void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
1541 {
1542 ASSERT((wlc_hw->wake_override & override_bit) == 0);
1543
1544 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1545 mboolset(wlc_hw->wake_override, override_bit);
1546 return;
1547 }
1548
1549 mboolset(wlc_hw->wake_override, override_bit);
1550
1551 wlc_mctrl_write(wlc_hw);
1552 wlc_bmac_wait_for_wake(wlc_hw);
1553
1554 return;
1555 }
1556
1557 void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
1558 {
1559 ASSERT(wlc_hw->wake_override & override_bit);
1560
1561 mboolclr(wlc_hw->wake_override, override_bit);
1562
1563 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1564 return;
1565
1566 wlc_mctrl_write(wlc_hw);
1567
1568 return;
1569 }
1570
1571 /* When driver needs ucode to stop beaconing, it has to make sure that
1572 * MCTL_AP is clear and MCTL_INFRA is set
1573 * Mode MCTL_AP MCTL_INFRA
1574 * AP 1 1
1575 * STA 0 1 <--- This will ensure no beacons
1576 * IBSS 0 0
1577 */
1578 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
1579 {
1580 wlc_hw->mute_override = 1;
1581
1582 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1583 * override, then there is no change to write
1584 */
1585 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1586 return;
1587
1588 wlc_mctrl_write(wlc_hw);
1589
1590 return;
1591 }
1592
1593 /* Clear the override on AP and INFRA bits */
1594 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
1595 {
1596 if (wlc_hw->mute_override == 0)
1597 return;
1598
1599 wlc_hw->mute_override = 0;
1600
1601 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1602 * override, then there is no change to write
1603 */
1604 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1605 return;
1606
1607 wlc_mctrl_write(wlc_hw);
1608 }
1609
1610 /*
1611 * Write a MAC address to the rcmta structure
1612 */
1613 void
1614 wlc_bmac_set_rcmta(struct wlc_hw_info *wlc_hw, int idx,
1615 const u8 *addr)
1616 {
1617 d11regs_t *regs = wlc_hw->regs;
1618 volatile u16 *objdata16 = (volatile u16 *)&regs->objdata;
1619 u32 mac_hm;
1620 u16 mac_l;
1621 struct osl_info *osh;
1622
1623 WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
1624
1625 mac_hm =
1626 (addr[3] << 24) | (addr[2] << 16) |
1627 (addr[1] << 8) | addr[0];
1628 mac_l = (addr[5] << 8) | addr[4];
1629
1630 osh = wlc_hw->osh;
1631
1632 W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
1633 (void)R_REG(osh, &regs->objaddr);
1634 W_REG(osh, &regs->objdata, mac_hm);
1635 W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
1636 (void)R_REG(osh, &regs->objaddr);
1637 W_REG(osh, objdata16, mac_l);
1638 }
1639
1640 /*
1641 * Write a MAC address to the given match reg offset in the RXE match engine.
1642 */
1643 void
1644 wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
1645 const u8 *addr)
1646 {
1647 d11regs_t *regs;
1648 u16 mac_l;
1649 u16 mac_m;
1650 u16 mac_h;
1651 struct osl_info *osh;
1652
1653 WL_TRACE("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit);
1654
1655 ASSERT(match_reg_offset < RCM_SIZE);
1656
1657 regs = wlc_hw->regs;
1658 mac_l = addr[0] | (addr[1] << 8);
1659 mac_m = addr[2] | (addr[3] << 8);
1660 mac_h = addr[4] | (addr[5] << 8);
1661
1662 osh = wlc_hw->osh;
1663
1664 /* enter the MAC addr into the RXE match registers */
1665 W_REG(osh, &regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1666 W_REG(osh, &regs->rcm_mat_data, mac_l);
1667 W_REG(osh, &regs->rcm_mat_data, mac_m);
1668 W_REG(osh, &regs->rcm_mat_data, mac_h);
1669
1670 }
1671
1672 void
1673 wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
1674 void *buf)
1675 {
1676 d11regs_t *regs;
1677 u32 word;
1678 bool be_bit;
1679 #ifdef IL_BIGENDIAN
1680 volatile u16 *dptr = NULL;
1681 #endif /* IL_BIGENDIAN */
1682 struct osl_info *osh;
1683
1684 WL_TRACE("wl%d: wlc_bmac_write_template_ram\n", wlc_hw->unit);
1685
1686 regs = wlc_hw->regs;
1687 osh = wlc_hw->osh;
1688
1689 ASSERT(IS_ALIGNED(offset, sizeof(u32)));
1690 ASSERT(IS_ALIGNED(len, sizeof(u32)));
1691 ASSERT((offset & ~0xffff) == 0);
1692
1693 W_REG(osh, &regs->tplatewrptr, offset);
1694
1695 /* if MCTL_BIGEND bit set in mac control register,
1696 * the chip swaps data in fifo, as well as data in
1697 * template ram
1698 */
1699 be_bit = (R_REG(osh, &regs->maccontrol) & MCTL_BIGEND) != 0;
1700
1701 while (len > 0) {
1702 memcpy(&word, buf, sizeof(u32));
1703
1704 if (be_bit)
1705 word = cpu_to_be32(word);
1706 else
1707 word = cpu_to_le32(word);
1708
1709 W_REG(osh, &regs->tplatewrdata, word);
1710
1711 buf = (u8 *) buf + sizeof(u32);
1712 len -= sizeof(u32);
1713 }
1714 }
1715
1716 void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
1717 {
1718 struct osl_info *osh;
1719
1720 osh = wlc_hw->osh;
1721 wlc_hw->band->CWmin = newmin;
1722
1723 W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1724 (void)R_REG(osh, &wlc_hw->regs->objaddr);
1725 W_REG(osh, &wlc_hw->regs->objdata, newmin);
1726 }
1727
1728 void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
1729 {
1730 struct osl_info *osh;
1731
1732 osh = wlc_hw->osh;
1733 wlc_hw->band->CWmax = newmax;
1734
1735 W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1736 (void)R_REG(osh, &wlc_hw->regs->objaddr);
1737 W_REG(osh, &wlc_hw->regs->objdata, newmax);
1738 }
1739
1740 void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
1741 {
1742 bool fastclk;
1743
1744 /* request FAST clock if not on */
1745 fastclk = wlc_hw->forcefastclk;
1746 if (!fastclk)
1747 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1748
1749 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1750
1751 ASSERT(wlc_hw->clk);
1752
1753 wlc_bmac_phy_reset(wlc_hw);
1754 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1755
1756 /* restore the clk */
1757 if (!fastclk)
1758 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1759 }
1760
1761 static void
1762 wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1763 {
1764 d11regs_t *regs = wlc_hw->regs;
1765
1766 wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1767 bcn);
1768 /* write beacon length to SCR */
1769 ASSERT(len < 65536);
1770 wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1771 /* mark beacon0 valid */
1772 OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN0VLD);
1773 }
1774
1775 static void
1776 wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1777 {
1778 d11regs_t *regs = wlc_hw->regs;
1779
1780 wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1781 bcn);
1782 /* write beacon length to SCR */
1783 ASSERT(len < 65536);
1784 wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1785 /* mark beacon1 valid */
1786 OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN1VLD);
1787 }
1788
1789 /* mac is assumed to be suspended at this point */
1790 void
1791 wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
1792 bool both)
1793 {
1794 d11regs_t *regs = wlc_hw->regs;
1795
1796 if (both) {
1797 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1798 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1799 } else {
1800 /* bcn 0 */
1801 if (!(R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN0VLD))
1802 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1803 /* bcn 1 */
1804 else if (!
1805 (R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN1VLD))
1806 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1807 else /* one template should always have been available */
1808 ASSERT(0);
1809 }
1810 }
1811
1812 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
1813 {
1814 u16 v;
1815 struct wlc_info *wlc = wlc_hw->wlc;
1816 /* update SYNTHPU_DLY */
1817
1818 if (WLCISLCNPHY(wlc->band)) {
1819 v = SYNTHPU_DLY_LPPHY_US;
1820 } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1821 v = SYNTHPU_DLY_NPHY_US;
1822 } else {
1823 v = SYNTHPU_DLY_BPHY_US;
1824 }
1825
1826 wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1827 }
1828
1829 /* band-specific init */
1830 static void
1831 WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1832 {
1833 struct wlc_hw_info *wlc_hw = wlc->hw;
1834
1835 WL_TRACE("wl%d: wlc_bmac_bsinit: bandunit %d\n",
1836 wlc_hw->unit, wlc_hw->band->bandunit);
1837
1838 /* sanity check */
1839 if (PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion)) !=
1840 PHY_TYPE_LCNXN)
1841 ASSERT((uint)
1842 PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion))
1843 == wlc_hw->band->phytype);
1844
1845 wlc_ucode_bsinit(wlc_hw);
1846
1847 wlc_phy_init(wlc_hw->band->pi, chanspec);
1848
1849 wlc_ucode_txant_set(wlc_hw);
1850
1851 /* cwmin is band-specific, update hardware with value for current band */
1852 wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1853 wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1854
1855 wlc_bmac_update_slot_timing(wlc_hw,
1856 BAND_5G(wlc_hw->band->
1857 bandtype) ? true : wlc_hw->
1858 shortslot);
1859
1860 /* write phytype and phyvers */
1861 wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1862 wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1863
1864 /* initialize the txphyctl1 rate table since shmem is shared between bands */
1865 wlc_upd_ofdm_pctl1_table(wlc_hw);
1866
1867 wlc_bmac_upd_synthpu(wlc_hw);
1868 }
1869
1870 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
1871 {
1872 WL_TRACE("wl%d: wlc_bmac_core_phy_clk: clk %d\n", wlc_hw->unit, clk);
1873
1874 wlc_hw->phyclk = clk;
1875
1876 if (OFF == clk) { /* clear gmode bit, put phy into reset */
1877
1878 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1879 (SICF_PRST | SICF_FGC));
1880 udelay(1);
1881 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1882 udelay(1);
1883
1884 } else { /* take phy out of reset */
1885
1886 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1887 udelay(1);
1888 si_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1889 udelay(1);
1890
1891 }
1892 }
1893
1894 /* Perform a soft reset of the PHY PLL */
1895 void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
1896 {
1897 WL_TRACE("wl%d: wlc_bmac_core_phypll_reset\n", wlc_hw->unit);
1898
1899 si_corereg(wlc_hw->sih, SI_CC_IDX,
1900 offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1901 udelay(1);
1902 si_corereg(wlc_hw->sih, SI_CC_IDX,
1903 offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1904 udelay(1);
1905 si_corereg(wlc_hw->sih, SI_CC_IDX,
1906 offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1907 udelay(1);
1908 si_corereg(wlc_hw->sih, SI_CC_IDX,
1909 offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1910 udelay(1);
1911 }
1912
1913 /* light way to turn on phy clock without reset for NPHY only
1914 * refer to wlc_bmac_core_phy_clk for full version
1915 */
1916 void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
1917 {
1918 /* support(necessary for NPHY and HYPHY) only */
1919 if (!WLCISNPHY(wlc_hw->band))
1920 return;
1921
1922 if (ON == clk)
1923 si_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1924 else
1925 si_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1926
1927 }
1928
1929 void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
1930 {
1931 if (ON == clk)
1932 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1933 else
1934 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1935 }
1936
1937 void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
1938 {
1939 wlc_phy_t *pih = wlc_hw->band->pi;
1940 u32 phy_bw_clkbits;
1941 bool phy_in_reset = false;
1942
1943 WL_TRACE("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit);
1944
1945 if (pih == NULL)
1946 return;
1947
1948 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1949
1950 /* Specfic reset sequence required for NPHY rev 3 and 4 */
1951 if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1952 NREV_LE(wlc_hw->band->phyrev, 4)) {
1953 /* Set the PHY bandwidth */
1954 si_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
1955
1956 udelay(1);
1957
1958 /* Perform a soft reset of the PHY PLL */
1959 wlc_bmac_core_phypll_reset(wlc_hw);
1960
1961 /* reset the PHY */
1962 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
1963 (SICF_PRST | SICF_PCLKE));
1964 phy_in_reset = true;
1965 } else {
1966
1967 si_core_cflags(wlc_hw->sih,
1968 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1969 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1970 }
1971
1972 udelay(2);
1973 wlc_bmac_core_phy_clk(wlc_hw, ON);
1974
1975 if (pih)
1976 wlc_phy_anacore(pih, ON);
1977 }
1978
1979 /* switch to and initialize new band */
1980 static void
1981 WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
1982 chanspec_t chanspec) {
1983 struct wlc_info *wlc = wlc_hw->wlc;
1984 u32 macintmask;
1985
1986 ASSERT(NBANDS_HW(wlc_hw) > 1);
1987 ASSERT(bandunit != wlc_hw->band->bandunit);
1988
1989 /* Enable the d11 core before accessing it */
1990 if (!si_iscoreup(wlc_hw->sih)) {
1991 si_core_reset(wlc_hw->sih, 0, 0);
1992 ASSERT(si_iscoreup(wlc_hw->sih));
1993 wlc_mctrl_reset(wlc_hw);
1994 }
1995
1996 macintmask = wlc_setband_inact(wlc, bandunit);
1997
1998 if (!wlc_hw->up)
1999 return;
2000
2001 wlc_bmac_core_phy_clk(wlc_hw, ON);
2002
2003 /* band-specific initializations */
2004 wlc_bmac_bsinit(wlc, chanspec);
2005
2006 /*
2007 * If there are any pending software interrupt bits,
2008 * then replace these with a harmless nonzero value
2009 * so wlc_dpc() will re-enable interrupts when done.
2010 */
2011 if (wlc->macintstatus)
2012 wlc->macintstatus = MI_DMAINT;
2013
2014 /* restore macintmask */
2015 wl_intrsrestore(wlc->wl, macintmask);
2016
2017 /* ucode should still be suspended.. */
2018 ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
2019 0);
2020 }
2021
2022 /* low-level band switch utility routine */
2023 void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
2024 {
2025 WL_TRACE("wl%d: wlc_setxband: bandunit %d\n", wlc_hw->unit, bandunit);
2026
2027 wlc_hw->band = wlc_hw->bandstate[bandunit];
2028
2029 /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
2030 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
2031
2032 /* set gmode core flag */
2033 if (wlc_hw->sbclk && !wlc_hw->noreset) {
2034 si_core_cflags(wlc_hw->sih, SICF_GMODE,
2035 ((bandunit == 0) ? SICF_GMODE : 0));
2036 }
2037 }
2038
2039 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
2040 {
2041
2042 /* reject unsupported corerev */
2043 if (!VALID_COREREV(wlc_hw->corerev)) {
2044 WL_ERROR("unsupported core rev %d\n", wlc_hw->corerev);
2045 return false;
2046 }
2047
2048 return true;
2049 }
2050
2051 static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
2052 {
2053 bool goodboard = true;
2054 uint boardrev = wlc_hw->boardrev;
2055
2056 if (boardrev == 0)
2057 goodboard = false;
2058 else if (boardrev > 0xff) {
2059 uint brt = (boardrev & 0xf000) >> 12;
2060 uint b0 = (boardrev & 0xf00) >> 8;
2061 uint b1 = (boardrev & 0xf0) >> 4;
2062 uint b2 = boardrev & 0xf;
2063
2064 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
2065 || (b2 > 9))
2066 goodboard = false;
2067 }
2068
2069 if (wlc_hw->sih->boardvendor != VENDOR_BROADCOM)
2070 return goodboard;
2071
2072 return goodboard;
2073 }
2074
2075 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
2076 {
2077 const char *varname = "macaddr";
2078 char *macaddr;
2079
2080 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
2081 macaddr = getvar(wlc_hw->vars, varname);
2082 if (macaddr != NULL)
2083 return macaddr;
2084
2085 if (NBANDS_HW(wlc_hw) > 1)
2086 varname = "et1macaddr";
2087 else
2088 varname = "il0macaddr";
2089
2090 macaddr = getvar(wlc_hw->vars, varname);
2091 if (macaddr == NULL) {
2092 WL_ERROR("wl%d: wlc_get_macaddr: macaddr getvar(%s) not found\n",
2093 wlc_hw->unit, varname);
2094 }
2095
2096 return macaddr;
2097 }
2098
2099 /*
2100 * Return true if radio is disabled, otherwise false.
2101 * hw radio disable signal is an external pin, users activate it asynchronously
2102 * this function could be called when driver is down and w/o clock
2103 * it operates on different registers depending on corerev and boardflag.
2104 */
2105 bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
2106 {
2107 bool v, clk, xtal;
2108 u32 resetbits = 0, flags = 0;
2109
2110 xtal = wlc_hw->sbclk;
2111 if (!xtal)
2112 wlc_bmac_xtal(wlc_hw, ON);
2113
2114 /* may need to take core out of reset first */
2115 clk = wlc_hw->clk;
2116 if (!clk) {
2117 /*
2118 * mac no longer enables phyclk automatically when driver
2119 * accesses phyreg throughput mac. This can be skipped since
2120 * only mac reg is accessed below
2121 */
2122 flags |= SICF_PCLKE;
2123
2124 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2125 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2126 (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2127 (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2128 wlc_hw->regs =
2129 (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2130 0);
2131 si_core_reset(wlc_hw->sih, flags, resetbits);
2132 wlc_mctrl_reset(wlc_hw);
2133 }
2134
2135 v = ((R_REG(wlc_hw->osh, &wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2136
2137 /* put core back into reset */
2138 if (!clk)
2139 si_core_disable(wlc_hw->sih, 0);
2140
2141 if (!xtal)
2142 wlc_bmac_xtal(wlc_hw, OFF);
2143
2144 return v;
2145 }
2146
2147 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2148 void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
2149 {
2150 if (wlc_hw->wlc->pub->hw_up)
2151 return;
2152
2153 WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
2154
2155 /*
2156 * Enable pll and xtal, initialize the power control registers,
2157 * and force fastclock for the remainder of wlc_up().
2158 */
2159 wlc_bmac_xtal(wlc_hw, ON);
2160 si_clkctl_init(wlc_hw->sih);
2161 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2162
2163 if (wlc_hw->sih->bustype == PCI_BUS) {
2164 si_pci_fixcfg(wlc_hw->sih);
2165
2166 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2167 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2168 (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2169 (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2170 wlc_hw->regs =
2171 (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2172 0);
2173 }
2174
2175 /* Inform phy that a POR reset has occurred so it does a complete phy init */
2176 wlc_phy_por_inform(wlc_hw->band->pi);
2177
2178 wlc_hw->ucode_loaded = false;
2179 wlc_hw->wlc->pub->hw_up = true;
2180
2181 if ((wlc_hw->boardflags & BFL_FEM)
2182 && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2183 if (!
2184 (wlc_hw->boardrev >= 0x1250
2185 && (wlc_hw->boardflags & BFL_FEM_BT)))
2186 si_epa_4313war(wlc_hw->sih);
2187 }
2188 }
2189
2190 static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
2191 {
2192 struct hnddma_pub *di = wlc_hw->di[fifo];
2193 return dma_rxreset(di);
2194 }
2195
2196 /* d11 core reset
2197 * ensure fask clock during reset
2198 * reset dma
2199 * reset d11(out of reset)
2200 * reset phy(out of reset)
2201 * clear software macintstatus for fresh new start
2202 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2203 */
2204 void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
2205 {
2206 d11regs_t *regs;
2207 uint i;
2208 bool fastclk;
2209 u32 resetbits = 0;
2210
2211 if (flags == WLC_USE_COREFLAGS)
2212 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2213
2214 WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
2215
2216 regs = wlc_hw->regs;
2217
2218 /* request FAST clock if not on */
2219 fastclk = wlc_hw->forcefastclk;
2220 if (!fastclk)
2221 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2222
2223 /* reset the dma engines except first time thru */
2224 if (si_iscoreup(wlc_hw->sih)) {
2225 for (i = 0; i < NFIFO; i++)
2226 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2227 WL_ERROR("wl%d: %s: dma_txreset[%d]: cannot stop dma\n",
2228 wlc_hw->unit, __func__, i);
2229 }
2230
2231 if ((wlc_hw->di[RX_FIFO])
2232 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2233 WL_ERROR("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n",
2234 wlc_hw->unit, __func__, RX_FIFO);
2235 }
2236 }
2237 /* if noreset, just stop the psm and return */
2238 if (wlc_hw->noreset) {
2239 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2240 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2241 return;
2242 }
2243
2244 /*
2245 * mac no longer enables phyclk automatically when driver accesses
2246 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2247 * band->pi is invalid. need to enable PHY CLK
2248 */
2249 flags |= SICF_PCLKE;
2250
2251 /* reset the core
2252 * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2253 * is cleared by the core_reset. have to re-request it.
2254 * This adds some delay and we can optimize it by also requesting fastclk through
2255 * chipcommon during this period if necessary. But that has to work coordinate
2256 * with other driver like mips/arm since they may touch chipcommon as well.
2257 */
2258 wlc_hw->clk = false;
2259 si_core_reset(wlc_hw->sih, flags, resetbits);
2260 wlc_hw->clk = true;
2261 if (wlc_hw->band && wlc_hw->band->pi)
2262 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2263
2264 wlc_mctrl_reset(wlc_hw);
2265
2266 if (PMUCTL_ENAB(wlc_hw->sih))
2267 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2268
2269 wlc_bmac_phy_reset(wlc_hw);
2270
2271 /* turn on PHY_PLL */
2272 wlc_bmac_core_phypll_ctl(wlc_hw, true);
2273
2274 /* clear sw intstatus */
2275 wlc_hw->wlc->macintstatus = 0;
2276
2277 /* restore the clk setting */
2278 if (!fastclk)
2279 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2280 }
2281
2282 /* txfifo sizes needs to be modified(increased) since the newer cores
2283 * have more memory.
2284 */
2285 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
2286 {
2287 d11regs_t *regs = wlc_hw->regs;
2288 u16 fifo_nu;
2289 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2290 u16 txfifo_def, txfifo_def1;
2291 u16 txfifo_cmd;
2292 struct osl_info *osh;
2293
2294 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2295 txfifo_startblk = TXFIFO_START_BLK;
2296
2297 osh = wlc_hw->osh;
2298
2299 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2300 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2301
2302 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2303 txfifo_def = (txfifo_startblk & 0xff) |
2304 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2305 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2306 ((((txfifo_endblk -
2307 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2308 txfifo_cmd =
2309 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2310
2311 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2312 W_REG(osh, &regs->xmtfifodef, txfifo_def);
2313 W_REG(osh, &regs->xmtfifodef1, txfifo_def1);
2314
2315 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2316
2317 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2318 }
2319 /*
2320 * need to propagate to shm location to be in sync since ucode/hw won't
2321 * do this
2322 */
2323 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2324 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2325 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2326 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2327 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2328 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2329 xmtfifo_sz[TX_AC_BK_FIFO]));
2330 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2331 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2332 xmtfifo_sz[TX_BCMC_FIFO]));
2333 }
2334
2335 /* d11 core init
2336 * reset PSM
2337 * download ucode/PCM
2338 * let ucode run to suspended
2339 * download ucode inits
2340 * config other core registers
2341 * init dma
2342 */
2343 static void wlc_coreinit(struct wlc_info *wlc)
2344 {
2345 struct wlc_hw_info *wlc_hw = wlc->hw;
2346 d11regs_t *regs;
2347 u32 sflags;
2348 uint bcnint_us;
2349 uint i = 0;
2350 bool fifosz_fixup = false;
2351 struct osl_info *osh;
2352 int err = 0;
2353 u16 buf[NFIFO];
2354
2355 regs = wlc_hw->regs;
2356 osh = wlc_hw->osh;
2357
2358 WL_TRACE("wl%d: wlc_coreinit\n", wlc_hw->unit);
2359
2360 /* reset PSM */
2361 wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2362
2363 wlc_ucode_download(wlc_hw);
2364 /*
2365 * FIFOSZ fixup. driver wants to controls the fifo allocation.
2366 */
2367 fifosz_fixup = true;
2368
2369 /* let the PSM run to the suspended state, set mode to BSS STA */
2370 W_REG(osh, &regs->macintstatus, -1);
2371 wlc_bmac_mctrl(wlc_hw, ~0,
2372 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2373
2374 /* wait for ucode to self-suspend after auto-init */
2375 SPINWAIT(((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0),
2376 1000 * 1000);
2377 if ((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0)
2378 WL_ERROR("wl%d: wlc_coreinit: ucode did not self-suspend!\n",
2379 wlc_hw->unit);
2380
2381 wlc_gpio_init(wlc);
2382
2383 sflags = si_core_sflags(wlc_hw->sih, 0, 0);
2384
2385 if (D11REV_IS(wlc_hw->corerev, 23)) {
2386 if (WLCISNPHY(wlc_hw->band))
2387 wlc_write_inits(wlc_hw, d11n0initvals16);
2388 else
2389 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2390 __func__, wlc_hw->unit, wlc_hw->corerev);
2391 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2392 if (WLCISLCNPHY(wlc_hw->band)) {
2393 wlc_write_inits(wlc_hw, d11lcn0initvals24);
2394 } else {
2395 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2396 __func__, wlc_hw->unit, wlc_hw->corerev);
2397 }
2398 } else {
2399 WL_ERROR("%s: wl%d: unsupported corerev %d\n",
2400 __func__, wlc_hw->unit, wlc_hw->corerev);
2401 }
2402
2403 /* For old ucode, txfifo sizes needs to be modified(increased) */
2404 if (fifosz_fixup == true) {
2405 wlc_corerev_fifofixup(wlc_hw);
2406 }
2407
2408 /* check txfifo allocations match between ucode and driver */
2409 buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2410 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2411 i = TX_AC_BE_FIFO;
2412 err = -1;
2413 }
2414 buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2415 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2416 i = TX_AC_VI_FIFO;
2417 err = -1;
2418 }
2419 buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2420 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2421 buf[TX_AC_BK_FIFO] &= 0xff;
2422 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2423 i = TX_AC_BK_FIFO;
2424 err = -1;
2425 }
2426 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2427 i = TX_AC_VO_FIFO;
2428 err = -1;
2429 }
2430 buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2431 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2432 buf[TX_BCMC_FIFO] &= 0xff;
2433 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2434 i = TX_BCMC_FIFO;
2435 err = -1;
2436 }
2437 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2438 i = TX_ATIM_FIFO;
2439 err = -1;
2440 }
2441 if (err != 0) {
2442 WL_ERROR("wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n",
2443 buf[i], wlc_hw->xmtfifo_sz[i], i);
2444 ASSERT(0);
2445 }
2446
2447 /* make sure we can still talk to the mac */
2448 ASSERT(R_REG(osh, &regs->maccontrol) != 0xffffffff);
2449
2450 /* band-specific inits done by wlc_bsinit() */
2451
2452 /* Set up frame burst size and antenna swap threshold init values */
2453 wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2454 wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2455
2456 /* enable one rx interrupt per received frame */
2457 W_REG(osh, &regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2458
2459 /* set the station mode (BSS STA) */
2460 wlc_bmac_mctrl(wlc_hw,
2461 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2462 (MCTL_INFRA | MCTL_DISCARD_PMQ));
2463
2464 /* set up Beacon interval */
2465 bcnint_us = 0x8000 << 10;
2466 W_REG(osh, &regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2467 W_REG(osh, &regs->tsf_cfpstart, bcnint_us);
2468 W_REG(osh, &regs->macintstatus, MI_GP1);
2469
2470 /* write interrupt mask */
2471 W_REG(osh, &regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2472
2473 /* allow the MAC to control the PHY clock (dynamic on/off) */
2474 wlc_bmac_macphyclk_set(wlc_hw, ON);
2475
2476 /* program dynamic clock control fast powerup delay register */
2477 wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
2478 W_REG(osh, &regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2479
2480 /* tell the ucode the corerev */
2481 wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2482
2483 /* tell the ucode MAC capabilities */
2484 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2485 (u16) (wlc_hw->machwcap & 0xffff));
2486 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2487 (u16) ((wlc_hw->
2488 machwcap >> 16) & 0xffff));
2489
2490 /* write retry limits to SCR, this done after PSM init */
2491 W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2492 (void)R_REG(osh, &regs->objaddr);
2493 W_REG(osh, &regs->objdata, wlc_hw->SRL);
2494 W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2495 (void)R_REG(osh, &regs->objaddr);
2496 W_REG(osh, &regs->objdata, wlc_hw->LRL);
2497
2498 /* write rate fallback retry limits */
2499 wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2500 wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2501
2502 AND_REG(osh, &regs->ifs_ctl, 0x0FFF);
2503 W_REG(osh, &regs->ifs_aifsn, EDCF_AIFSN_MIN);
2504
2505 /* dma initializations */
2506 wlc->txpend16165war = 0;
2507
2508 /* init the tx dma engines */
2509 for (i = 0; i < NFIFO; i++) {
2510 if (wlc_hw->di[i])
2511 dma_txinit(wlc_hw->di[i]);
2512 }
2513
2514 /* init the rx dma engine(s) and post receive buffers */
2515 dma_rxinit(wlc_hw->di[RX_FIFO]);
2516 dma_rxfill(wlc_hw->di[RX_FIFO]);
2517 }
2518
2519 /* This function is used for changing the tsf frac register
2520 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2521 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2522 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2523 * HTPHY Formula is 2^26/freq(MHz) e.g.
2524 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2525 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2526 * For spuron: 123MHz -> 2^26/123 = 545600.5
2527 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2528 * For spur off: 120MHz -> 2^26/120 = 559240.5
2529 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2530 */
2531
2532 void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
2533 {
2534 d11regs_t *regs;
2535 struct osl_info *osh;
2536 regs = wlc_hw->regs;
2537 osh = wlc_hw->osh;
2538
2539 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2540 (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2541 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2542 W_REG(osh, &regs->tsf_clk_frac_l, 0x2082);
2543 W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2544 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2545 W_REG(osh, &regs->tsf_clk_frac_l, 0x5341);
2546 W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2547 } else { /* 120Mhz */
2548 W_REG(osh, &regs->tsf_clk_frac_l, 0x8889);
2549 W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2550 }
2551 } else if (WLCISLCNPHY(wlc_hw->band)) {
2552 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2553 W_REG(osh, &regs->tsf_clk_frac_l, 0x7CE0);
2554 W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2555 } else { /* 80Mhz */
2556 W_REG(osh, &regs->tsf_clk_frac_l, 0xCCCD);
2557 W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2558 }
2559 }
2560 }
2561
2562 /* Initialize GPIOs that are controlled by D11 core */
2563 static void wlc_gpio_init(struct wlc_info *wlc)
2564 {
2565 struct wlc_hw_info *wlc_hw = wlc->hw;
2566 d11regs_t *regs;
2567 u32 gc, gm;
2568 struct osl_info *osh;
2569
2570 regs = wlc_hw->regs;
2571 osh = wlc_hw->osh;
2572
2573 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2574 wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2575
2576 /*
2577 * Common GPIO setup:
2578 * G0 = LED 0 = WLAN Activity
2579 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2580 * G2 = LED 2 = WLAN 5 GHz Radio State
2581 * G4 = radio disable input (HI enabled, LO disabled)
2582 */
2583
2584 gc = gm = 0;
2585
2586 /* Allocate GPIOs for mimo antenna diversity feature */
2587 if (WLANTSEL_ENAB(wlc)) {
2588 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2589 /* Enable antenna diversity, use 2x3 mode */
2590 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2591 MHF3_ANTSEL_EN, WLC_BAND_ALL);
2592 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2593 MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2594
2595 /* init superswitch control */
2596 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2597
2598 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2599 ASSERT((gm & BOARD_GPIO_12) == 0);
2600 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2601 /* The board itself is powered by these GPIOs (when not sending pattern)
2602 * So set them high
2603 */
2604 OR_REG(osh, &regs->psm_gpio_oe,
2605 (BOARD_GPIO_12 | BOARD_GPIO_13));
2606 OR_REG(osh, &regs->psm_gpio_out,
2607 (BOARD_GPIO_12 | BOARD_GPIO_13));
2608
2609 /* Enable antenna diversity, use 2x4 mode */
2610 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2611 MHF3_ANTSEL_EN, WLC_BAND_ALL);
2612 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2613 WLC_BAND_ALL);
2614
2615 /* Configure the desired clock to be 4Mhz */
2616 wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2617 ANTSEL_CLKDIV_4MHZ);
2618 }
2619 }
2620 /* gpio 9 controls the PA. ucode is responsible for wiggling out and oe */
2621 if (wlc_hw->boardflags & BFL_PACTRL)
2622 gm |= gc |= BOARD_GPIO_PACTRL;
2623
2624 /* apply to gpiocontrol register */
2625 si_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2626 }
2627
2628 static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
2629 {
2630 struct wlc_info *wlc;
2631 wlc = wlc_hw->wlc;
2632
2633 if (wlc_hw->ucode_loaded)
2634 return;
2635
2636 if (D11REV_IS(wlc_hw->corerev, 23)) {
2637 if (WLCISNPHY(wlc_hw->band)) {
2638 wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2639 bcm43xx_16_mimosz);
2640 wlc_hw->ucode_loaded = true;
2641 } else
2642 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2643 __func__, wlc_hw->unit, wlc_hw->corerev);
2644 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2645 if (WLCISLCNPHY(wlc_hw->band)) {
2646 wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2647 bcm43xx_24_lcnsz);
2648 wlc_hw->ucode_loaded = true;
2649 } else {
2650 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2651 __func__, wlc_hw->unit, wlc_hw->corerev);
2652 }
2653 }
2654 }
2655
2656 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
2657 const uint nbytes) {
2658 struct osl_info *osh;
2659 d11regs_t *regs = wlc_hw->regs;
2660 uint i;
2661 uint count;
2662
2663 osh = wlc_hw->osh;
2664
2665 WL_TRACE("wl%d: wlc_ucode_write\n", wlc_hw->unit);
2666
2667 ASSERT(IS_ALIGNED(nbytes, sizeof(u32)));
2668
2669 count = (nbytes / sizeof(u32));
2670
2671 W_REG(osh, &regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2672 (void)R_REG(osh, &regs->objaddr);
2673 for (i = 0; i < count; i++)
2674 W_REG(osh, &regs->objdata, ucode[i]);
2675 }
2676
2677 static void wlc_write_inits(struct wlc_hw_info *wlc_hw, const d11init_t *inits)
2678 {
2679 int i;
2680 struct osl_info *osh;
2681 volatile u8 *base;
2682
2683 WL_TRACE("wl%d: wlc_write_inits\n", wlc_hw->unit);
2684
2685 osh = wlc_hw->osh;
2686 base = (volatile u8 *)wlc_hw->regs;
2687
2688 for (i = 0; inits[i].addr != 0xffff; i++) {
2689 ASSERT((inits[i].size == 2) || (inits[i].size == 4));
2690
2691 if (inits[i].size == 2)
2692 W_REG(osh, (u16 *)(base + inits[i].addr),
2693 inits[i].value);
2694 else if (inits[i].size == 4)
2695 W_REG(osh, (u32 *)(base + inits[i].addr),
2696 inits[i].value);
2697 }
2698 }
2699
2700 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
2701 {
2702 u16 phyctl;
2703 u16 phytxant = wlc_hw->bmac_phytxant;
2704 u16 mask = PHY_TXC_ANT_MASK;
2705
2706 /* set the Probe Response frame phy control word */
2707 phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2708 phyctl = (phyctl & ~mask) | phytxant;
2709 wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2710
2711 /* set the Response (ACK/CTS) frame phy control word */
2712 phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2713 phyctl = (phyctl & ~mask) | phytxant;
2714 wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2715 }
2716
2717 void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
2718 {
2719 /* update sw state */
2720 wlc_hw->bmac_phytxant = phytxant;
2721
2722 /* push to ucode if up */
2723 if (!wlc_hw->up)
2724 return;
2725 wlc_ucode_txant_set(wlc_hw);
2726
2727 }
2728
2729 u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
2730 {
2731 return (u16) wlc_hw->wlc->stf->txant;
2732 }
2733
2734 void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
2735 {
2736 wlc_hw->antsel_type = antsel_type;
2737
2738 /* Update the antsel type for phy module to use */
2739 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2740 }
2741
2742 void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
2743 {
2744 bool fatal = false;
2745 uint unit;
2746 uint intstatus, idx;
2747 d11regs_t *regs = wlc_hw->regs;
2748
2749 unit = wlc_hw->unit;
2750
2751 for (idx = 0; idx < NFIFO; idx++) {
2752 /* read intstatus register and ignore any non-error bits */
2753 intstatus =
2754 R_REG(wlc_hw->osh,
2755 &regs->intctrlregs[idx].intstatus) & I_ERRORS;
2756 if (!intstatus)
2757 continue;
2758
2759 WL_TRACE("wl%d: wlc_bmac_fifoerrors: intstatus%d 0x%x\n",
2760 unit, idx, intstatus);
2761
2762 if (intstatus & I_RO) {
2763 WL_ERROR("wl%d: fifo %d: receive fifo overflow\n",
2764 unit, idx);
2765 wlc_hw->wlc->pub->_cnt->rxoflo++;
2766 fatal = true;
2767 }
2768
2769 if (intstatus & I_PC) {
2770 WL_ERROR("wl%d: fifo %d: descriptor error\n",
2771 unit, idx);
2772 wlc_hw->wlc->pub->_cnt->dmade++;
2773 fatal = true;
2774 }
2775
2776 if (intstatus & I_PD) {
2777 WL_ERROR("wl%d: fifo %d: data error\n", unit, idx);
2778 wlc_hw->wlc->pub->_cnt->dmada++;
2779 fatal = true;
2780 }
2781
2782 if (intstatus & I_DE) {
2783 WL_ERROR("wl%d: fifo %d: descriptor protocol error\n",
2784 unit, idx);
2785 wlc_hw->wlc->pub->_cnt->dmape++;
2786 fatal = true;
2787 }
2788
2789 if (intstatus & I_RU) {
2790 WL_ERROR("wl%d: fifo %d: receive descriptor underflow\n",
2791 idx, unit);
2792 wlc_hw->wlc->pub->_cnt->rxuflo[idx]++;
2793 }
2794
2795 if (intstatus & I_XU) {
2796 WL_ERROR("wl%d: fifo %d: transmit fifo underflow\n",
2797 idx, unit);
2798 wlc_hw->wlc->pub->_cnt->txuflo++;
2799 fatal = true;
2800 }
2801
2802 if (fatal) {
2803 wlc_fatal_error(wlc_hw->wlc); /* big hammer */
2804 break;
2805 } else
2806 W_REG(wlc_hw->osh, &regs->intctrlregs[idx].intstatus,
2807 intstatus);
2808 }
2809 }
2810
2811 void wlc_intrson(struct wlc_info *wlc)
2812 {
2813 struct wlc_hw_info *wlc_hw = wlc->hw;
2814 ASSERT(wlc->defmacintmask);
2815 wlc->macintmask = wlc->defmacintmask;
2816 W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2817 }
2818
2819 /* callback for siutils.c, which has only wlc handler, no wl
2820 * they both check up, not only because there is no need to off/restore d11 interrupt
2821 * but also because per-port code may require sync with valid interrupt.
2822 */
2823
2824 static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2825 {
2826 if (!wlc->hw->up)
2827 return 0;
2828
2829 return wl_intrsoff(wlc->wl);
2830 }
2831
2832 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2833 {
2834 if (!wlc->hw->up)
2835 return;
2836
2837 wl_intrsrestore(wlc->wl, macintmask);
2838 }
2839
2840 u32 wlc_intrsoff(struct wlc_info *wlc)
2841 {
2842 struct wlc_hw_info *wlc_hw = wlc->hw;
2843 u32 macintmask;
2844
2845 if (!wlc_hw->clk)
2846 return 0;
2847
2848 macintmask = wlc->macintmask; /* isr can still happen */
2849
2850 W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, 0);
2851 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->macintmask); /* sync readback */
2852 udelay(1); /* ensure int line is no longer driven */
2853 wlc->macintmask = 0;
2854
2855 /* return previous macintmask; resolve race between us and our isr */
2856 return wlc->macintstatus ? 0 : macintmask;
2857 }
2858
2859 void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
2860 {
2861 struct wlc_hw_info *wlc_hw = wlc->hw;
2862 if (!wlc_hw->clk)
2863 return;
2864
2865 wlc->macintmask = macintmask;
2866 W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2867 }
2868
2869 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
2870 {
2871 u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2872
2873 if (on) {
2874 /* suspend tx fifos */
2875 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2876 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2877 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2878 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2879
2880 /* zero the address match register so we do not send ACKs */
2881 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2882 null_ether_addr);
2883 } else {
2884 /* resume tx fifos */
2885 if (!wlc_hw->wlc->tx_suspended) {
2886 wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2887 }
2888 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2889 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2890 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2891
2892 /* Restore address */
2893 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2894 wlc_hw->etheraddr);
2895 }
2896
2897 wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
2898
2899 if (on)
2900 wlc_ucode_mute_override_set(wlc_hw);
2901 else
2902 wlc_ucode_mute_override_clear(wlc_hw);
2903 }
2904
2905 int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
2906 {
2907 if (fifo >= NFIFO)
2908 return BCME_RANGE;
2909
2910 *blocks = wlc_hw->xmtfifo_sz[fifo];
2911
2912 return 0;
2913 }
2914
2915 /* wlc_bmac_tx_fifo_suspended:
2916 * Check the MAC's tx suspend status for a tx fifo.
2917 *
2918 * When the MAC acknowledges a tx suspend, it indicates that no more
2919 * packets will be transmitted out the radio. This is independent of
2920 * DMA channel suspension---the DMA may have finished suspending, or may still
2921 * be pulling data into a tx fifo, by the time the MAC acks the suspend
2922 * request.
2923 */
2924 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2925 {
2926 /* check that a suspend has been requested and is no longer pending */
2927
2928 /*
2929 * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
2930 * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
2931 * chnstatus register.
2932 * The tx fifo suspend completion is independent of the DMA suspend completion and
2933 * may be acked before or after the DMA is suspended.
2934 */
2935 if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
2936 (R_REG(wlc_hw->osh, &wlc_hw->regs->chnstatus) &
2937 (1 << tx_fifo)) == 0)
2938 return true;
2939
2940 return false;
2941 }
2942
2943 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2944 {
2945 u8 fifo = 1 << tx_fifo;
2946
2947 /* Two clients of this code, 11h Quiet period and scanning. */
2948
2949 /* only suspend if not already suspended */
2950 if ((wlc_hw->suspended_fifos & fifo) == fifo)
2951 return;
2952
2953 /* force the core awake only if not already */
2954 if (wlc_hw->suspended_fifos == 0)
2955 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
2956
2957 wlc_hw->suspended_fifos |= fifo;
2958
2959 if (wlc_hw->di[tx_fifo]) {
2960 /* Suspending AMPDU transmissions in the middle can cause underflow
2961 * which may result in mismatch between ucode and driver
2962 * so suspend the mac before suspending the FIFO
2963 */
2964 if (WLC_PHY_11N_CAP(wlc_hw->band))
2965 wlc_suspend_mac_and_wait(wlc_hw->wlc);
2966
2967 dma_txsuspend(wlc_hw->di[tx_fifo]);
2968
2969 if (WLC_PHY_11N_CAP(wlc_hw->band))
2970 wlc_enable_mac(wlc_hw->wlc);
2971 }
2972 }
2973
2974 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2975 {
2976 /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
2977 * here for PIO otherwise the watchdog will catch the inconsistency and fire
2978 */
2979 /* Two clients of this code, 11h Quiet period and scanning. */
2980 if (wlc_hw->di[tx_fifo])
2981 dma_txresume(wlc_hw->di[tx_fifo]);
2982
2983 /* allow core to sleep again */
2984 if (wlc_hw->suspended_fifos == 0)
2985 return;
2986 else {
2987 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2988 if (wlc_hw->suspended_fifos == 0)
2989 wlc_ucode_wake_override_clear(wlc_hw,
2990 WLC_WAKE_OVERRIDE_TXFIFO);
2991 }
2992 }
2993
2994 /*
2995 * Read and clear macintmask and macintstatus and intstatus registers.
2996 * This routine should be called with interrupts off
2997 * Return:
2998 * -1 if DEVICEREMOVED(wlc) evaluates to true;
2999 * 0 if the interrupt is not for us, or we are in some special cases;
3000 * device interrupt status bits otherwise.
3001 */
3002 static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
3003 {
3004 struct wlc_hw_info *wlc_hw = wlc->hw;
3005 d11regs_t *regs = wlc_hw->regs;
3006 u32 macintstatus;
3007 struct osl_info *osh;
3008
3009 osh = wlc_hw->osh;
3010
3011 /* macintstatus includes a DMA interrupt summary bit */
3012 macintstatus = R_REG(osh, &regs->macintstatus);
3013
3014 WL_TRACE("wl%d: macintstatus: 0x%x\n", wlc_hw->unit, macintstatus);
3015
3016 /* detect cardbus removed, in power down(suspend) and in reset */
3017 if (DEVICEREMOVED(wlc))
3018 return -1;
3019
3020 /* DEVICEREMOVED succeeds even when the core is still resetting,
3021 * handle that case here.
3022 */
3023 if (macintstatus == 0xffffffff)
3024 return 0;
3025
3026 /* defer unsolicited interrupts */
3027 macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
3028
3029 /* if not for us */
3030 if (macintstatus == 0)
3031 return 0;
3032
3033 /* interrupts are already turned off for CFE build
3034 * Caution: For CFE Turning off the interrupts again has some undesired
3035 * consequences
3036 */
3037 /* turn off the interrupts */
3038 W_REG(osh, &regs->macintmask, 0);
3039 (void)R_REG(osh, &regs->macintmask); /* sync readback */
3040 wlc->macintmask = 0;
3041
3042 /* clear device interrupts */
3043 W_REG(osh, &regs->macintstatus, macintstatus);
3044
3045 /* MI_DMAINT is indication of non-zero intstatus */
3046 if (macintstatus & MI_DMAINT) {
3047 /*
3048 * only fifo interrupt enabled is I_RI in RX_FIFO. If
3049 * MI_DMAINT is set, assume it is set and clear the interrupt.
3050 */
3051 W_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus,
3052 DEF_RXINTMASK);
3053 }
3054
3055 return macintstatus;
3056 }
3057
3058 /* Update wlc->macintstatus and wlc->intstatus[]. */
3059 /* Return true if they are updated successfully. false otherwise */
3060 bool wlc_intrsupd(struct wlc_info *wlc)
3061 {
3062 u32 macintstatus;
3063
3064 ASSERT(wlc->macintstatus != 0);
3065
3066 /* read and clear macintstatus and intstatus registers */
3067 macintstatus = wlc_intstatus(wlc, false);
3068
3069 /* device is removed */
3070 if (macintstatus == 0xffffffff)
3071 return false;
3072
3073 /* update interrupt status in software */
3074 wlc->macintstatus |= macintstatus;
3075
3076 return true;
3077 }
3078
3079 /*
3080 * First-level interrupt processing.
3081 * Return true if this was our interrupt, false otherwise.
3082 * *wantdpc will be set to true if further wlc_dpc() processing is required,
3083 * false otherwise.
3084 */
3085 bool BCMFASTPATH wlc_isr(struct wlc_info *wlc, bool *wantdpc)
3086 {
3087 struct wlc_hw_info *wlc_hw = wlc->hw;
3088 u32 macintstatus;
3089
3090 *wantdpc = false;
3091
3092 if (!wlc_hw->up || !wlc->macintmask)
3093 return false;
3094
3095 /* read and clear macintstatus and intstatus registers */
3096 macintstatus = wlc_intstatus(wlc, true);
3097
3098 if (macintstatus == 0xffffffff)
3099 WL_ERROR("DEVICEREMOVED detected in the ISR code path\n");
3100
3101 /* it is not for us */
3102 if (macintstatus == 0)
3103 return false;
3104
3105 *wantdpc = true;
3106
3107 /* save interrupt status bits */
3108 ASSERT(wlc->macintstatus == 0);
3109 wlc->macintstatus = macintstatus;
3110
3111 return true;
3112
3113 }
3114
3115 static bool BCMFASTPATH
3116 wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
3117 {
3118 /* discard intermediate indications for ucode with one legitimate case:
3119 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
3120 * tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
3121 * transmission count)
3122 */
3123 if (!(txs->status & TX_STATUS_AMPDU)
3124 && (txs->status & TX_STATUS_INTERMEDIATE)) {
3125 return false;
3126 }
3127
3128 return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
3129 }
3130
3131 /* process tx completion events in BMAC
3132 * Return true if more tx status need to be processed. false otherwise.
3133 */
3134 static bool BCMFASTPATH
3135 wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
3136 {
3137 bool morepending = false;
3138 struct wlc_info *wlc = wlc_hw->wlc;
3139 d11regs_t *regs;
3140 struct osl_info *osh;
3141 tx_status_t txstatus, *txs;
3142 u32 s1, s2;
3143 uint n = 0;
3144 /*
3145 * Param 'max_tx_num' indicates max. # tx status to process before
3146 * break out.
3147 */
3148 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3149
3150 WL_TRACE("wl%d: wlc_bmac_txstatus\n", wlc_hw->unit);
3151
3152 txs = &txstatus;
3153 regs = wlc_hw->regs;
3154 osh = wlc_hw->osh;
3155 while (!(*fatal)
3156 && (s1 = R_REG(osh, &regs->frmtxstatus)) & TXS_V) {
3157
3158 if (s1 == 0xffffffff) {
3159 WL_ERROR("wl%d: %s: dead chip\n",
3160 wlc_hw->unit, __func__);
3161 ASSERT(s1 != 0xffffffff);
3162 return morepending;
3163 }
3164
3165 s2 = R_REG(osh, &regs->frmtxstatus2);
3166
3167 txs->status = s1 & TXS_STATUS_MASK;
3168 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3169 txs->sequence = s2 & TXS_SEQ_MASK;
3170 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3171 txs->lasttxtime = 0;
3172
3173 *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3174
3175 /* !give others some time to run! */
3176 if (++n >= max_tx_num)
3177 break;
3178 }
3179
3180 if (*fatal)
3181 return 0;
3182
3183 if (n >= max_tx_num)
3184 morepending = true;
3185
3186 if (!pktq_empty(&wlc->active_queue->q))
3187 wlc_send_q(wlc, wlc->active_queue);
3188
3189 return morepending;
3190 }
3191
3192 void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3193 {
3194 struct wlc_hw_info *wlc_hw = wlc->hw;
3195 d11regs_t *regs = wlc_hw->regs;
3196 u32 mc, mi;
3197 struct osl_info *osh;
3198
3199 WL_TRACE("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n",
3200 wlc_hw->unit, wlc_hw->band->bandunit);
3201
3202 /*
3203 * Track overlapping suspend requests
3204 */
3205 wlc_hw->mac_suspend_depth++;
3206 if (wlc_hw->mac_suspend_depth > 1)
3207 return;
3208
3209 osh = wlc_hw->osh;
3210
3211 /* force the core awake */
3212 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3213
3214 mc = R_REG(osh, &regs->maccontrol);
3215
3216 if (mc == 0xffffffff) {
3217 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3218 wl_down(wlc->wl);
3219 return;
3220 }
3221 ASSERT(!(mc & MCTL_PSM_JMP_0));
3222 ASSERT(mc & MCTL_PSM_RUN);
3223 ASSERT(mc & MCTL_EN_MAC);
3224
3225 mi = R_REG(osh, &regs->macintstatus);
3226 if (mi == 0xffffffff) {
3227 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3228 wl_down(wlc->wl);
3229 return;
3230 }
3231 ASSERT(!(mi & MI_MACSSPNDD));
3232
3233 wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3234
3235 SPINWAIT(!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD),
3236 WLC_MAX_MAC_SUSPEND);
3237
3238 if (!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD)) {
3239 WL_ERROR("wl%d: wlc_suspend_mac_and_wait: waited %d uS and MI_MACSSPNDD is still not on.\n",
3240 wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3241 WL_ERROR("wl%d: psmdebug 0x%08x, phydebug 0x%08x, psm_brc 0x%04x\n",
3242 wlc_hw->unit,
3243 R_REG(osh, &regs->psmdebug),
3244 R_REG(osh, &regs->phydebug),
3245 R_REG(osh, &regs->psm_brc));
3246 }
3247
3248 mc = R_REG(osh, &regs->maccontrol);
3249 if (mc == 0xffffffff) {
3250 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3251 wl_down(wlc->wl);
3252 return;
3253 }
3254 ASSERT(!(mc & MCTL_PSM_JMP_0));
3255 ASSERT(mc & MCTL_PSM_RUN);
3256 ASSERT(!(mc & MCTL_EN_MAC));
3257 }
3258
3259 void wlc_enable_mac(struct wlc_info *wlc)
3260 {
3261 struct wlc_hw_info *wlc_hw = wlc->hw;
3262 d11regs_t *regs = wlc_hw->regs;
3263 u32 mc, mi;
3264 struct osl_info *osh;
3265
3266 WL_TRACE("wl%d: wlc_enable_mac: bandunit %d\n",
3267 wlc_hw->unit, wlc->band->bandunit);
3268
3269 /*
3270 * Track overlapping suspend requests
3271 */
3272 ASSERT(wlc_hw->mac_suspend_depth > 0);
3273 wlc_hw->mac_suspend_depth--;
3274 if (wlc_hw->mac_suspend_depth > 0)
3275 return;
3276
3277 osh = wlc_hw->osh;
3278
3279 mc = R_REG(osh, &regs->maccontrol);
3280 ASSERT(!(mc & MCTL_PSM_JMP_0));
3281 ASSERT(!(mc & MCTL_EN_MAC));
3282 ASSERT(mc & MCTL_PSM_RUN);
3283
3284 wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3285 W_REG(osh, &regs->macintstatus, MI_MACSSPNDD);
3286
3287 mc = R_REG(osh, &regs->maccontrol);
3288 ASSERT(!(mc & MCTL_PSM_JMP_0));
3289 ASSERT(mc & MCTL_EN_MAC);
3290 ASSERT(mc & MCTL_PSM_RUN);
3291
3292 mi = R_REG(osh, &regs->macintstatus);
3293 ASSERT(!(mi & MI_MACSSPNDD));
3294
3295 wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3296 }
3297
3298 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
3299 {
3300 u8 rate;
3301 u8 rates[8] = {
3302 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3303 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3304 };
3305 u16 entry_ptr;
3306 u16 pctl1;
3307 uint i;
3308
3309 if (!WLC_PHY_11N_CAP(wlc_hw->band))
3310 return;
3311
3312 /* walk the phy rate table and update the entries */
3313 for (i = 0; i < ARRAY_SIZE(rates); i++) {
3314 rate = rates[i];
3315
3316 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3317
3318 /* read the SHM Rate Table entry OFDM PCTL1 values */
3319 pctl1 =
3320 wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3321
3322 /* modify the value */
3323 pctl1 &= ~PHY_TXC1_MODE_MASK;
3324 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3325
3326 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3327 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3328 pctl1);
3329 }
3330 }
3331
3332 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3333 {
3334 uint i;
3335 u8 plcp_rate = 0;
3336 struct plcp_signal_rate_lookup {
3337 u8 rate;
3338 u8 signal_rate;
3339 };
3340 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3341 const struct plcp_signal_rate_lookup rate_lookup[] = {
3342 {WLC_RATE_6M, 0xB},
3343 {WLC_RATE_9M, 0xF},
3344 {WLC_RATE_12M, 0xA},
3345 {WLC_RATE_18M, 0xE},
3346 {WLC_RATE_24M, 0x9},
3347 {WLC_RATE_36M, 0xD},
3348 {WLC_RATE_48M, 0x8},
3349 {WLC_RATE_54M, 0xC}
3350 };
3351
3352 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3353 if (rate == rate_lookup[i].rate) {
3354 plcp_rate = rate_lookup[i].signal_rate;
3355 break;
3356 }
3357 }
3358
3359 /* Find the SHM pointer to the rate table entry by looking in the
3360 * Direct-map Table
3361 */
3362 return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3363 }
3364
3365 void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
3366 {
3367 wlc_hw->hw_stf_ss_opmode = stf_mode;
3368
3369 if (wlc_hw->clk)
3370 wlc_upd_ofdm_pctl1_table(wlc_hw);
3371 }
3372
3373 void BCMFASTPATH
3374 wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
3375 u32 *tsf_h_ptr)
3376 {
3377 d11regs_t *regs = wlc_hw->regs;
3378
3379 /* read the tsf timer low, then high to get an atomic read */
3380 *tsf_l_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerlow);
3381 *tsf_h_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerhigh);
3382
3383 return;
3384 }
3385
3386 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
3387 {
3388 d11regs_t *regs;
3389 u32 w, val;
3390 struct osl_info *osh;
3391
3392 WL_TRACE("wl%d: validate_chip_access\n", wlc_hw->unit);
3393
3394 regs = wlc_hw->regs;
3395 osh = wlc_hw->osh;
3396
3397 /* Validate dchip register access */
3398
3399 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3400 (void)R_REG(osh, &regs->objaddr);
3401 w = R_REG(osh, &regs->objdata);
3402
3403 /* Can we write and read back a 32bit register? */
3404 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3405 (void)R_REG(osh, &regs->objaddr);
3406 W_REG(osh, &regs->objdata, (u32) 0xaa5555aa);
3407
3408 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3409 (void)R_REG(osh, &regs->objaddr);
3410 val = R_REG(osh, &regs->objdata);
3411 if (val != (u32) 0xaa5555aa) {
3412 WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n",
3413 wlc_hw->unit, val);
3414 return false;
3415 }
3416
3417 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3418 (void)R_REG(osh, &regs->objaddr);
3419 W_REG(osh, &regs->objdata, (u32) 0x55aaaa55);
3420
3421 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3422 (void)R_REG(osh, &regs->objaddr);
3423 val = R_REG(osh, &regs->objdata);
3424 if (val != (u32) 0x55aaaa55) {
3425 WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n",
3426 wlc_hw->unit, val);
3427 return false;
3428 }
3429
3430 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3431 (void)R_REG(osh, &regs->objaddr);
3432 W_REG(osh, &regs->objdata, w);
3433
3434 /* clear CFPStart */
3435 W_REG(osh, &regs->tsf_cfpstart, 0);
3436
3437 w = R_REG(osh, &regs->maccontrol);
3438 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3439 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3440 WL_ERROR("wl%d: validate_chip_access: maccontrol = 0x%x, expected 0x%x or 0x%x\n",
3441 wlc_hw->unit, w,
3442 (MCTL_IHR_EN | MCTL_WAKE),
3443 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3444 return false;
3445 }
3446
3447 return true;
3448 }
3449
3450 #define PHYPLL_WAIT_US 100000
3451
3452 void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
3453 {
3454 d11regs_t *regs;
3455 struct osl_info *osh;
3456 u32 tmp;
3457
3458 WL_TRACE("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit);
3459
3460 tmp = 0;
3461 regs = wlc_hw->regs;
3462 osh = wlc_hw->osh;
3463
3464 if (on) {
3465 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3466 OR_REG(osh, &regs->clk_ctl_st,
3467 (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3468 CCS_ERSRC_REQ_PHYPLL));
3469 SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3470 (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3471 PHYPLL_WAIT_US);
3472
3473 tmp = R_REG(osh, &regs->clk_ctl_st);
3474 if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3475 (CCS_ERSRC_AVAIL_HT)) {
3476 WL_ERROR("%s: turn on PHY PLL failed\n",
3477 __func__);
3478 ASSERT(0);
3479 }
3480 } else {
3481 OR_REG(osh, &regs->clk_ctl_st,
3482 (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3483 SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3484 (CCS_ERSRC_AVAIL_D11PLL |
3485 CCS_ERSRC_AVAIL_PHYPLL)) !=
3486 (CCS_ERSRC_AVAIL_D11PLL |
3487 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3488
3489 tmp = R_REG(osh, &regs->clk_ctl_st);
3490 if ((tmp &
3491 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3492 !=
3493 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3494 WL_ERROR("%s: turn on PHY PLL failed\n",
3495 __func__);
3496 ASSERT(0);
3497 }
3498 }
3499 } else {
3500 /* Since the PLL may be shared, other cores can still be requesting it;
3501 * so we'll deassert the request but not wait for status to comply.
3502 */
3503 AND_REG(osh, &regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3504 tmp = R_REG(osh, &regs->clk_ctl_st);
3505 }
3506 }
3507
3508 void wlc_coredisable(struct wlc_hw_info *wlc_hw)
3509 {
3510 bool dev_gone;
3511
3512 WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
3513
3514 ASSERT(!wlc_hw->up);
3515
3516 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3517
3518 if (dev_gone)
3519 return;
3520
3521 if (wlc_hw->noreset)
3522 return;
3523
3524 /* radio off */
3525 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3526
3527 /* turn off analog core */
3528 wlc_phy_anacore(wlc_hw->band->pi, OFF);
3529
3530 /* turn off PHYPLL to save power */
3531 wlc_bmac_core_phypll_ctl(wlc_hw, false);
3532
3533 /* No need to set wlc->pub->radio_active = OFF
3534 * because this function needs down capability and
3535 * radio_active is designed for BCMNODOWN.
3536 */
3537
3538 /* remove gpio controls */
3539 if (wlc_hw->ucode_dbgsel)
3540 si_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3541
3542 wlc_hw->clk = false;
3543 si_core_disable(wlc_hw->sih, 0);
3544 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3545 }
3546
3547 /* power both the pll and external oscillator on/off */
3548 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
3549 {
3550 WL_TRACE("wl%d: wlc_bmac_xtal: want %d\n", wlc_hw->unit, want);
3551
3552 /* dont power down if plldown is false or we must poll hw radio disable */
3553 if (!want && wlc_hw->pllreq)
3554 return;
3555
3556 if (wlc_hw->sih)
3557 si_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3558
3559 wlc_hw->sbclk = want;
3560 if (!wlc_hw->sbclk) {
3561 wlc_hw->clk = false;
3562 if (wlc_hw->band && wlc_hw->band->pi)
3563 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3564 }
3565 }
3566
3567 static void wlc_flushqueues(struct wlc_info *wlc)
3568 {
3569 struct wlc_hw_info *wlc_hw = wlc->hw;
3570 uint i;
3571
3572 wlc->txpend16165war = 0;
3573
3574 /* free any posted tx packets */
3575 for (i = 0; i < NFIFO; i++)
3576 if (wlc_hw->di[i]) {
3577 dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3578 TXPKTPENDCLR(wlc, i);
3579 WL_TRACE("wlc_flushqueues: pktpend fifo %d cleared\n",
3580 i);
3581 }
3582
3583 /* free any posted rx packets */
3584 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3585 }
3586
3587 u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
3588 {
3589 return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3590 }
3591
3592 void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
3593 {
3594 wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3595 }
3596
3597 /* Set a range of shared memory to a value.
3598 * SHM 'offset' needs to be an even address and
3599 * Buffer length 'len' must be an even number of bytes
3600 */
3601 void wlc_bmac_set_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v, int len)
3602 {
3603 int i;
3604
3605 /* offset and len need to be even */
3606 ASSERT((offset & 1) == 0);
3607 ASSERT((len & 1) == 0);
3608
3609 if (len <= 0)
3610 return;
3611
3612 for (i = 0; i < len; i += 2) {
3613 wlc_bmac_write_objmem(wlc_hw, offset + i, v, OBJADDR_SHM_SEL);
3614 }
3615 }
3616
3617 static u16
3618 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
3619 {
3620 d11regs_t *regs = wlc_hw->regs;
3621 volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3622 volatile u16 *objdata_hi = objdata_lo + 1;
3623 u16 v;
3624
3625 ASSERT((offset & 1) == 0);
3626
3627 W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3628 (void)R_REG(wlc_hw->osh, &regs->objaddr);
3629 if (offset & 2) {
3630 v = R_REG(wlc_hw->osh, objdata_hi);
3631 } else {
3632 v = R_REG(wlc_hw->osh, objdata_lo);
3633 }
3634
3635 return v;
3636 }
3637
3638 static void
3639 wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
3640 {
3641 d11regs_t *regs = wlc_hw->regs;
3642 volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3643 volatile u16 *objdata_hi = objdata_lo + 1;
3644
3645 ASSERT((offset & 1) == 0);
3646
3647 W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3648 (void)R_REG(wlc_hw->osh, &regs->objaddr);
3649 if (offset & 2) {
3650 W_REG(wlc_hw->osh, objdata_hi, v);
3651 } else {
3652 W_REG(wlc_hw->osh, objdata_lo, v);
3653 }
3654 }
3655
3656 /* Copy a buffer to shared memory of specified type .
3657 * SHM 'offset' needs to be an even address and
3658 * Buffer length 'len' must be an even number of bytes
3659 * 'sel' selects the type of memory
3660 */
3661 void
3662 wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
3663 int len, u32 sel)
3664 {
3665 u16 v;
3666 const u8 *p = (const u8 *)buf;
3667 int i;
3668
3669 /* offset and len need to be even */
3670 ASSERT((offset & 1) == 0);
3671 ASSERT((len & 1) == 0);
3672
3673 if (len <= 0)
3674 return;
3675
3676 for (i = 0; i < len; i += 2) {
3677 v = p[i] | (p[i + 1] << 8);
3678 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3679 }
3680 }
3681
3682 /* Copy a piece of shared memory of specified type to a buffer .
3683 * SHM 'offset' needs to be an even address and
3684 * Buffer length 'len' must be an even number of bytes
3685 * 'sel' selects the type of memory
3686 */
3687 void
3688 wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
3689 int len, u32 sel)
3690 {
3691 u16 v;
3692 u8 *p = (u8 *) buf;
3693 int i;
3694
3695 /* offset and len need to be even */
3696 ASSERT((offset & 1) == 0);
3697 ASSERT((len & 1) == 0);
3698
3699 if (len <= 0)
3700 return;
3701
3702 for (i = 0; i < len; i += 2) {
3703 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
3704 p[i] = v & 0xFF;
3705 p[i + 1] = (v >> 8) & 0xFF;
3706 }
3707 }
3708
3709 void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
3710 {
3711 WL_TRACE("wlc_bmac_copyfrom_vars, nvram vars totlen=%d\n",
3712 wlc_hw->vars_size);
3713
3714 *buf = wlc_hw->vars;
3715 *len = wlc_hw->vars_size;
3716 }
3717
3718 void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
3719 {
3720 wlc_hw->SRL = SRL;
3721 wlc_hw->LRL = LRL;
3722
3723 /* write retry limit to SCR, shouldn't need to suspend */
3724 if (wlc_hw->up) {
3725 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
3726 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3727 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
3728 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->SRL);
3729 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
3730 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3731 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
3732 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->LRL);
3733 }
3734 }
3735
3736 void wlc_bmac_set_noreset(struct wlc_hw_info *wlc_hw, bool noreset_flag)
3737 {
3738 wlc_hw->noreset = noreset_flag;
3739 }
3740
3741 void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
3742 {
3743 ASSERT(req_bit);
3744
3745 if (set) {
3746 if (mboolisset(wlc_hw->pllreq, req_bit))
3747 return;
3748
3749 mboolset(wlc_hw->pllreq, req_bit);
3750
3751 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3752 if (!wlc_hw->sbclk) {
3753 wlc_bmac_xtal(wlc_hw, ON);
3754 }
3755 }
3756 } else {
3757 if (!mboolisset(wlc_hw->pllreq, req_bit))
3758 return;
3759
3760 mboolclr(wlc_hw->pllreq, req_bit);
3761
3762 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3763 if (wlc_hw->sbclk) {
3764 wlc_bmac_xtal(wlc_hw, OFF);
3765 }
3766 }
3767 }
3768
3769 return;
3770 }
3771
3772 /* this will be true for all ai chips */
3773 bool wlc_bmac_taclear(struct wlc_hw_info *wlc_hw, bool ta_ok)
3774 {
3775 return true;
3776 }
3777
3778 u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3779 {
3780 u16 table_ptr;
3781 u8 phy_rate, index;
3782
3783 /* get the phy specific rate encoding for the PLCP SIGNAL field */
3784 /* XXX4321 fixup needed ? */
3785 if (IS_OFDM(rate))
3786 table_ptr = M_RT_DIRMAP_A;
3787 else
3788 table_ptr = M_RT_DIRMAP_B;
3789
3790 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
3791 * the index into the rate table.
3792 */
3793 phy_rate = rate_info[rate] & RATE_MASK;
3794 index = phy_rate & 0xf;
3795
3796 /* Find the SHM pointer to the rate table entry by looking in the
3797 * Direct-map Table
3798 */
3799 return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
3800 }
3801
3802 void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
3803 {
3804 wlc_hw->antsel_avail = antsel_avail;
3805 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree