drivers/scsi/qla4xxx/ql4_def.h

   1 /*
   2  * QLogic iSCSI HBA Driver
   3  * Copyright (c)  2003-2010 QLogic Corporation
   4  *
   5  * See LICENSE.qla4xxx for copyright and licensing details.
   6  */
   7
   8 #ifndef __QL4_DEF_H
   9 #define __QL4_DEF_H
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/types.h>
  14 #include <linux/module.h>
  15 #include <linux/list.h>
  16 #include <linux/pci.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/sched.h>
  19 #include <linux/slab.h>
  20 #include <linux/dmapool.h>
  21 #include <linux/mempool.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/delay.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/mutex.h>
  27 #include <linux/aer.h>
  28 #include <linux/bsg-lib.h>
  29
  30 #include <net/tcp.h>
  31 #include <scsi/scsi.h>
  32 #include <scsi/scsi_host.h>
  33 #include <scsi/scsi_device.h>
  34 #include <scsi/scsi_cmnd.h>
  35 #include <scsi/scsi_transport.h>
  36 #include <scsi/scsi_transport_iscsi.h>
  37 #include <scsi/scsi_bsg_iscsi.h>
  38 #include <scsi/scsi_netlink.h>
  39 #include <scsi/libiscsi.h>
  40
  41 #include "ql4_dbg.h"
  42 #include "ql4_nx.h"
  43 #include "ql4_fw.h"
  44 #include "ql4_nvram.h"
  45
  46 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
  47 #define PCI_DEVICE_ID_QLOGIC_ISP4010    0x4010
  48 #endif
  49
  50 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
  51 #define PCI_DEVICE_ID_QLOGIC_ISP4022    0x4022
  52 #endif
  53
  54 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
  55 #define PCI_DEVICE_ID_QLOGIC_ISP4032    0x4032
  56 #endif
  57
  58 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
  59 #define PCI_DEVICE_ID_QLOGIC_ISP8022    0x8022
  60 #endif
  61
  62 #define ISP4XXX_PCI_FN_1        0x1
  63 #define ISP4XXX_PCI_FN_2        0x3
  64
  65 #define QLA_SUCCESS                     0
  66 #define QLA_ERROR                       1
  67
  68 /*
  69  * Data bit definitions
  70  */
  71 #define BIT_0   0x1
  72 #define BIT_1   0x2
  73 #define BIT_2   0x4
  74 #define BIT_3   0x8
  75 #define BIT_4   0x10
  76 #define BIT_5   0x20
  77 #define BIT_6   0x40
  78 #define BIT_7   0x80
  79 #define BIT_8   0x100
  80 #define BIT_9   0x200
  81 #define BIT_10  0x400
  82 #define BIT_11  0x800
  83 #define BIT_12  0x1000
  84 #define BIT_13  0x2000
  85 #define BIT_14  0x4000
  86 #define BIT_15  0x8000
  87 #define BIT_16  0x10000
  88 #define BIT_17  0x20000
  89 #define BIT_18  0x40000
  90 #define BIT_19  0x80000
  91 #define BIT_20  0x100000
  92 #define BIT_21  0x200000
  93 #define BIT_22  0x400000
  94 #define BIT_23  0x800000
  95 #define BIT_24  0x1000000
  96 #define BIT_25  0x2000000
  97 #define BIT_26  0x4000000
  98 #define BIT_27  0x8000000
  99 #define BIT_28  0x10000000
 100 #define BIT_29  0x20000000
 101 #define BIT_30  0x40000000
 102 #define BIT_31  0x80000000
 103
 104 /**
 105  * Macros to help code, maintain, etc.
 106  **/
 107 #define ql4_printk(level, ha, format, arg...) \
 108         dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
 109
 110
 111 /*
 112  * Host adapter default definitions
 113  ***********************************/
 114 #define MAX_HBAS                16
 115 #define MAX_BUSES               1
 116 #define MAX_TARGETS             MAX_DEV_DB_ENTRIES
 117 #define MAX_LUNS                0xffff
 118 #define MAX_AEN_ENTRIES         MAX_DEV_DB_ENTRIES
 119 #define MAX_DDB_ENTRIES         MAX_DEV_DB_ENTRIES
 120 #define MAX_PDU_ENTRIES         32
 121 #define INVALID_ENTRY           0xFFFF
 122 #define MAX_CMDS_TO_RISC        1024
 123 #define MAX_SRBS                MAX_CMDS_TO_RISC
 124 #define MBOX_AEN_REG_COUNT      8
 125 #define MAX_INIT_RETRIES        5
 126
 127 /*
 128  * Buffer sizes
 129  */
 130 #define REQUEST_QUEUE_DEPTH             MAX_CMDS_TO_RISC
 131 #define RESPONSE_QUEUE_DEPTH            64
 132 #define QUEUE_SIZE                      64
 133 #define DMA_BUFFER_SIZE                 512
 134
 135 /*
 136  * Misc
 137  */
 138 #define MAC_ADDR_LEN                    6       /* in bytes */
 139 #define IP_ADDR_LEN                     4       /* in bytes */
 140 #define IPv6_ADDR_LEN                   16      /* IPv6 address size */
 141 #define DRIVER_NAME                     "qla4xxx"
 142
 143 #define MAX_LINKED_CMDS_PER_LUN         3
 144 #define MAX_REQS_SERVICED_PER_INTR      1
 145
 146 #define ISCSI_IPADDR_SIZE               4       /* IP address size */
 147 #define ISCSI_ALIAS_SIZE                32      /* ISCSI Alias name size */
 148 #define ISCSI_NAME_SIZE                 0xE0    /* ISCSI Name size */
 149
 150 #define QL4_SESS_RECOVERY_TMO           30      /* iSCSI session */
 151                                                 /* recovery timeout */
 152
 153 #define LSDW(x) ((u32)((u64)(x)))
 154 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
 155
 156 /*
 157  * Retry & Timeout Values
 158  */
 159 #define MBOX_TOV                        60
 160 #define SOFT_RESET_TOV                  30
 161 #define RESET_INTR_TOV                  3
 162 #define SEMAPHORE_TOV                   10
 163 #define ADAPTER_INIT_TOV                30
 164 #define ADAPTER_RESET_TOV               180
 165 #define EXTEND_CMD_TOV                  60
 166 #define WAIT_CMD_TOV                    30
 167 #define EH_WAIT_CMD_TOV                 120
 168 #define FIRMWARE_UP_TOV                 60
 169 #define RESET_FIRMWARE_TOV              30
 170 #define LOGOUT_TOV                      10
 171 #define IOCB_TOV_MARGIN                 10
 172 #define RELOGIN_TOV                     18
 173 #define ISNS_DEREG_TOV                  5
 174 #define HBA_ONLINE_TOV                  30
 175 #define DISABLE_ACB_TOV                 30
 176
 177 #define MAX_RESET_HA_RETRIES            2
 178
 179 #define CMD_SP(Cmnd)                    ((Cmnd)->SCp.ptr)
 180
 181 /*
 182  * SCSI Request Block structure  (srb)  that is placed
 183  * on cmd->SCp location of every I/O     [We have 22 bytes available]
 184  */
 185 struct srb {
 186         struct list_head list;  /* (8)   */
 187         struct scsi_qla_host *ha;       /* HA the SP is queued on */
 188         struct ddb_entry *ddb;
 189         uint16_t flags;         /* (1) Status flags. */
 190
 191 #define SRB_DMA_VALID           BIT_3   /* DMA Buffer mapped. */
 192 #define SRB_GOT_SENSE           BIT_4   /* sense data received. */
 193         uint8_t state;          /* (1) Status flags. */
 194
 195 #define SRB_NO_QUEUE_STATE       0      /* Request is in between states */
 196 #define SRB_FREE_STATE           1
 197 #define SRB_ACTIVE_STATE         3
 198 #define SRB_ACTIVE_TIMEOUT_STATE 4
 199 #define SRB_SUSPENDED_STATE      7      /* Request in suspended state */
 200
 201         struct scsi_cmnd *cmd;  /* (4) SCSI command block */
 202         dma_addr_t dma_handle;  /* (4) for unmap of single transfers */
 203         struct kref srb_ref;    /* reference count for this srb */
 204         uint8_t err_id;         /* error id */
 205 #define SRB_ERR_PORT       1    /* Request failed because "port down" */
 206 #define SRB_ERR_LOOP       2    /* Request failed because "loop down" */
 207 #define SRB_ERR_DEVICE     3    /* Request failed because "device error" */
 208 #define SRB_ERR_OTHER      4
 209
 210         uint16_t reserved;
 211         uint16_t iocb_tov;
 212         uint16_t iocb_cnt;      /* Number of used iocbs */
 213         uint16_t cc_stat;
 214
 215         /* Used for extended sense / status continuation */
 216         uint8_t *req_sense_ptr;
 217         uint16_t req_sense_len;
 218         uint16_t reserved2;
 219 };
 220
 221 /*
 222  * Asynchronous Event Queue structure
 223  */
 224 struct aen {
 225         uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
 226 };
 227
 228 struct ql4_aen_log {
 229         int count;
 230         struct aen entry[MAX_AEN_ENTRIES];
 231 };
 232
 233 /*
 234  * Device Database (DDB) structure
 235  */
 236 struct ddb_entry {
 237         struct scsi_qla_host *ha;
 238         struct iscsi_cls_session *sess;
 239         struct iscsi_cls_conn *conn;
 240
 241         uint16_t fw_ddb_index;  /* DDB firmware index */
 242         uint32_t fw_ddb_device_state; /* F/W Device State  -- see ql4_fw.h */
 243 };
 244
 245 /*
 246  * DDB states.
 247  */
 248 #define DDB_STATE_DEAD          0       /* We can no longer talk to
 249                                          * this device */
 250 #define DDB_STATE_ONLINE        1       /* Device ready to accept
 251                                          * commands */
 252 #define DDB_STATE_MISSING       2       /* Device logged off, trying
 253                                          * to re-login */
 254
 255 /*
 256  * DDB flags.
 257  */
 258 #define DF_RELOGIN              0       /* Relogin to device */
 259 #define DF_ISNS_DISCOVERED      2       /* Device was discovered via iSNS */
 260 #define DF_FO_MASKED            3
 261
 262
 263
 264 struct ql82xx_hw_data {
 265         /* Offsets for flash/nvram access (set to ~0 if not used). */
 266         uint32_t flash_conf_off;
 267         uint32_t flash_data_off;
 268
 269         uint32_t fdt_wrt_disable;
 270         uint32_t fdt_erase_cmd;
 271         uint32_t fdt_block_size;
 272         uint32_t fdt_unprotect_sec_cmd;
 273         uint32_t fdt_protect_sec_cmd;
 274
 275         uint32_t flt_region_flt;
 276         uint32_t flt_region_fdt;
 277         uint32_t flt_region_boot;
 278         uint32_t flt_region_bootload;
 279         uint32_t flt_region_fw;
 280
 281         uint32_t flt_iscsi_param;
 282         uint32_t flt_region_chap;
 283         uint32_t flt_chap_size;
 284 };
 285
 286 struct qla4_8xxx_legacy_intr_set {
 287         uint32_t int_vec_bit;
 288         uint32_t tgt_status_reg;
 289         uint32_t tgt_mask_reg;
 290         uint32_t pci_int_reg;
 291 };
 292
 293 /* MSI-X Support */
 294
 295 #define QLA_MSIX_DEFAULT        0x00
 296 #define QLA_MSIX_RSP_Q          0x01
 297
 298 #define QLA_MSIX_ENTRIES        2
 299 #define QLA_MIDX_DEFAULT        0
 300 #define QLA_MIDX_RSP_Q          1
 301
 302 struct ql4_msix_entry {
 303         int have_irq;
 304         uint16_t msix_vector;
 305         uint16_t msix_entry;
 306 };
 307
 308 /*
 309  * ISP Operations
 310  */
 311 struct isp_operations {
 312         int (*iospace_config) (struct scsi_qla_host *ha);
 313         void (*pci_config) (struct scsi_qla_host *);
 314         void (*disable_intrs) (struct scsi_qla_host *);
 315         void (*enable_intrs) (struct scsi_qla_host *);
 316         int (*start_firmware) (struct scsi_qla_host *);
 317         irqreturn_t (*intr_handler) (int , void *);
 318         void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
 319         int (*reset_chip) (struct scsi_qla_host *);
 320         int (*reset_firmware) (struct scsi_qla_host *);
 321         void (*queue_iocb) (struct scsi_qla_host *);
 322         void (*complete_iocb) (struct scsi_qla_host *);
 323         uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
 324         uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
 325         int (*get_sys_info) (struct scsi_qla_host *);
 326 };
 327
 328 /*qla4xxx ipaddress configuration details */
 329 struct ipaddress_config {
 330         uint16_t ipv4_options;
 331         uint16_t tcp_options;
 332         uint16_t ipv4_vlan_tag;
 333         uint8_t ipv4_addr_state;
 334         uint8_t ip_address[IP_ADDR_LEN];
 335         uint8_t subnet_mask[IP_ADDR_LEN];
 336         uint8_t gateway[IP_ADDR_LEN];
 337         uint32_t ipv6_options;
 338         uint32_t ipv6_addl_options;
 339         uint8_t ipv6_link_local_state;
 340         uint8_t ipv6_addr0_state;
 341         uint8_t ipv6_addr1_state;
 342         uint8_t ipv6_default_router_state;
 343         uint16_t ipv6_vlan_tag;
 344         struct in6_addr ipv6_link_local_addr;
 345         struct in6_addr ipv6_addr0;
 346         struct in6_addr ipv6_addr1;
 347         struct in6_addr ipv6_default_router_addr;
 348         uint16_t eth_mtu_size;
 349         uint16_t ipv4_port;
 350         uint16_t ipv6_port;
 351 };
 352
 353 #define QL4_CHAP_MAX_NAME_LEN 256
 354 #define QL4_CHAP_MAX_SECRET_LEN 100
 355 #define LOCAL_CHAP      0
 356 #define BIDI_CHAP       1
 357
 358 struct ql4_chap_format {
 359         u8  intr_chap_name[QL4_CHAP_MAX_NAME_LEN];
 360         u8  intr_secret[QL4_CHAP_MAX_SECRET_LEN];
 361         u8  target_chap_name[QL4_CHAP_MAX_NAME_LEN];
 362         u8  target_secret[QL4_CHAP_MAX_SECRET_LEN];
 363         u16 intr_chap_name_length;
 364         u16 intr_secret_length;
 365         u16 target_chap_name_length;
 366         u16 target_secret_length;
 367 };
 368
 369 struct ip_address_format {
 370         u8 ip_type;
 371         u8 ip_address[16];
 372 };
 373
 374 struct  ql4_conn_info {
 375         u16     dest_port;
 376         struct  ip_address_format dest_ipaddr;
 377         struct  ql4_chap_format chap;
 378 };
 379
 380 struct ql4_boot_session_info {
 381         u8      target_name[224];
 382         struct  ql4_conn_info conn_list[1];
 383 };
 384
 385 struct ql4_boot_tgt_info {
 386         struct ql4_boot_session_info boot_pri_sess;
 387         struct ql4_boot_session_info boot_sec_sess;
 388 };
 389
 390 /*
 391  * Linux Host Adapter structure
 392  */
 393 struct scsi_qla_host {
 394         /* Linux adapter configuration data */
 395         unsigned long flags;
 396
 397 #define AF_ONLINE                       0 /* 0x00000001 */
 398 #define AF_INIT_DONE                    1 /* 0x00000002 */
 399 #define AF_MBOX_COMMAND                 2 /* 0x00000004 */
 400 #define AF_MBOX_COMMAND_DONE            3 /* 0x00000008 */
 401 #define AF_INTERRUPTS_ON                6 /* 0x00000040 */
 402 #define AF_GET_CRASH_RECORD             7 /* 0x00000080 */
 403 #define AF_LINK_UP                      8 /* 0x00000100 */
 404 #define AF_IRQ_ATTACHED                 10 /* 0x00000400 */
 405 #define AF_DISABLE_ACB_COMPLETE         11 /* 0x00000800 */
 406 #define AF_HA_REMOVAL                   12 /* 0x00001000 */
 407 #define AF_INTx_ENABLED                 15 /* 0x00008000 */
 408 #define AF_MSI_ENABLED                  16 /* 0x00010000 */
 409 #define AF_MSIX_ENABLED                 17 /* 0x00020000 */
 410 #define AF_MBOX_COMMAND_NOPOLL          18 /* 0x00040000 */
 411 #define AF_FW_RECOVERY                  19 /* 0x00080000 */
 412 #define AF_EEH_BUSY                     20 /* 0x00100000 */
 413 #define AF_PCI_CHANNEL_IO_PERM_FAILURE  21 /* 0x00200000 */
 414
 415         unsigned long dpc_flags;
 416
 417 #define DPC_RESET_HA                    1 /* 0x00000002 */
 418 #define DPC_RETRY_RESET_HA              2 /* 0x00000004 */
 419 #define DPC_RELOGIN_DEVICE              3 /* 0x00000008 */
 420 #define DPC_RESET_HA_FW_CONTEXT         4 /* 0x00000010 */
 421 #define DPC_RESET_HA_INTR               5 /* 0x00000020 */
 422 #define DPC_ISNS_RESTART                7 /* 0x00000080 */
 423 #define DPC_AEN                         9 /* 0x00000200 */
 424 #define DPC_GET_DHCP_IP_ADDR            15 /* 0x00008000 */
 425 #define DPC_LINK_CHANGED                18 /* 0x00040000 */
 426 #define DPC_RESET_ACTIVE                20 /* 0x00040000 */
 427 #define DPC_HA_UNRECOVERABLE            21 /* 0x00080000 ISP-82xx only*/
 428 #define DPC_HA_NEED_QUIESCENT           22 /* 0x00100000 ISP-82xx only*/
 429
 430
 431         struct Scsi_Host *host; /* pointer to host data */
 432         uint32_t tot_ddbs;
 433
 434         uint16_t iocb_cnt;
 435
 436         /* SRB cache. */
 437 #define SRB_MIN_REQ     128
 438         mempool_t *srb_mempool;
 439
 440         /* pci information */
 441         struct pci_dev *pdev;
 442
 443         struct isp_reg __iomem *reg; /* Base I/O address */
 444         unsigned long pio_address;
 445         unsigned long pio_length;
 446 #define MIN_IOBASE_LEN          0x100
 447
 448         uint16_t req_q_count;
 449
 450         unsigned long host_no;
 451
 452         /* NVRAM registers */
 453         struct eeprom_data *nvram;
 454         spinlock_t hardware_lock ____cacheline_aligned;
 455         uint32_t eeprom_cmd_data;
 456
 457         /* Counters for general statistics */
 458         uint64_t isr_count;
 459         uint64_t adapter_error_count;
 460         uint64_t device_error_count;
 461         uint64_t total_io_count;
 462         uint64_t total_mbytes_xferred;
 463         uint64_t link_failure_count;
 464         uint64_t invalid_crc_count;
 465         uint32_t bytes_xfered;
 466         uint32_t spurious_int_count;
 467         uint32_t aborted_io_count;
 468         uint32_t io_timeout_count;
 469         uint32_t mailbox_timeout_count;
 470         uint32_t seconds_since_last_intr;
 471         uint32_t seconds_since_last_heartbeat;
 472         uint32_t mac_index;
 473
 474         /* Info Needed for Management App */
 475         /* --- From GetFwVersion --- */
 476         uint32_t firmware_version[2];
 477         uint32_t patch_number;
 478         uint32_t build_number;
 479         uint32_t board_id;
 480
 481         /* --- From Init_FW --- */
 482         /* init_cb_t *init_cb; */
 483         uint16_t firmware_options;
 484         uint8_t alias[32];
 485         uint8_t name_string[256];
 486         uint8_t heartbeat_interval;
 487
 488         /* --- From FlashSysInfo --- */
 489         uint8_t my_mac[MAC_ADDR_LEN];
 490         uint8_t serial_number[16];
 491         uint16_t port_num;
 492         /* --- From GetFwState --- */
 493         uint32_t firmware_state;
 494         uint32_t addl_fw_state;
 495
 496         /* Linux kernel thread */
 497         struct workqueue_struct *dpc_thread;
 498         struct work_struct dpc_work;
 499
 500         /* Linux timer thread */
 501         struct timer_list timer;
 502         uint32_t timer_active;
 503
 504         /* Recovery Timers */
 505         atomic_t check_relogin_timeouts;
 506         uint32_t retry_reset_ha_cnt;
 507         uint32_t isp_reset_timer;       /* reset test timer */
 508         uint32_t nic_reset_timer;       /* simulated nic reset test timer */
 509         int eh_start;
 510         struct list_head free_srb_q;
 511         uint16_t free_srb_q_count;
 512         uint16_t num_srbs_allocated;
 513
 514         /* DMA Memory Block */
 515         void *queues;
 516         dma_addr_t queues_dma;
 517         unsigned long queues_len;
 518
 519 #define MEM_ALIGN_VALUE \
 520             ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
 521              sizeof(struct queue_entry))
 522         /* request and response queue variables */
 523         dma_addr_t request_dma;
 524         struct queue_entry *request_ring;
 525         struct queue_entry *request_ptr;
 526         dma_addr_t response_dma;
 527         struct queue_entry *response_ring;
 528         struct queue_entry *response_ptr;
 529         dma_addr_t shadow_regs_dma;
 530         struct shadow_regs *shadow_regs;
 531         uint16_t request_in;    /* Current indexes. */
 532         uint16_t request_out;
 533         uint16_t response_in;
 534         uint16_t response_out;
 535
 536         /* aen queue variables */
 537         uint16_t aen_q_count;   /* Number of available aen_q entries */
 538         uint16_t aen_in;        /* Current indexes */
 539         uint16_t aen_out;
 540         struct aen aen_q[MAX_AEN_ENTRIES];
 541
 542         struct ql4_aen_log aen_log;/* tracks all aens */
 543
 544         /* This mutex protects several threads to do mailbox commands
 545          * concurrently.
 546          */
 547         struct mutex  mbox_sem;
 548
 549         /* temporary mailbox status registers */
 550         volatile uint8_t mbox_status_count;
 551         volatile uint32_t mbox_status[MBOX_REG_COUNT];
 552
 553         /* FW ddb index map */
 554         struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
 555
 556         /* Saved srb for status continuation entry processing */
 557         struct srb *status_srb;
 558
 559         uint8_t acb_version;
 560
 561         /* qla82xx specific fields */
 562         struct device_reg_82xx  __iomem *qla4_8xxx_reg; /* Base I/O address */
 563         unsigned long nx_pcibase;       /* Base I/O address */
 564         uint8_t *nx_db_rd_ptr;          /* Doorbell read pointer */
 565         unsigned long nx_db_wr_ptr;     /* Door bell write pointer */
 566         unsigned long first_page_group_start;
 567         unsigned long first_page_group_end;
 568
 569         uint32_t crb_win;
 570         uint32_t curr_window;
 571         uint32_t ddr_mn_window;
 572         unsigned long mn_win_crb;
 573         unsigned long ms_win_crb;
 574         int qdr_sn_window;
 575         rwlock_t hw_lock;
 576         uint16_t func_num;
 577         int link_width;
 578
 579         struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
 580         u32 nx_crb_mask;
 581
 582         uint8_t revision_id;
 583         uint32_t fw_heartbeat_counter;
 584
 585         struct isp_operations *isp_ops;
 586         struct ql82xx_hw_data hw;
 587
 588         struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];
 589
 590         uint32_t nx_dev_init_timeout;
 591         uint32_t nx_reset_timeout;
 592
 593         struct completion mbx_intr_comp;
 594
 595         struct ipaddress_config ip_config;
 596         struct iscsi_iface *iface_ipv4;
 597         struct iscsi_iface *iface_ipv6_0;
 598         struct iscsi_iface *iface_ipv6_1;
 599
 600         /* --- From About Firmware --- */
 601         uint16_t iscsi_major;
 602         uint16_t iscsi_minor;
 603         uint16_t bootload_major;
 604         uint16_t bootload_minor;
 605         uint16_t bootload_patch;
 606         uint16_t bootload_build;
 607
 608         uint32_t flash_state;
 609 #define QLFLASH_WAITING         0
 610 #define QLFLASH_READING         1
 611 #define QLFLASH_WRITING         2
 612         struct dma_pool *chap_dma_pool;
 613         uint8_t *chap_list; /* CHAP table cache */
 614         struct mutex  chap_sem;
 615 #define CHAP_DMA_BLOCK_SIZE    512
 616         struct workqueue_struct *task_wq;
 617         unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG];
 618 #define SYSFS_FLAG_FW_SEL_BOOT 2
 619         struct iscsi_boot_kset *boot_kset;
 620         struct ql4_boot_tgt_info boot_tgt;
 621         uint16_t phy_port_num;
 622         uint16_t phy_port_cnt;
 623         uint16_t iscsi_pci_func_cnt;
 624         uint8_t model_name[16];
 625         struct completion disable_acb_comp;
 626 };
 627
 628 struct ql4_task_data {
 629         struct scsi_qla_host *ha;
 630         uint8_t iocb_req_cnt;
 631         dma_addr_t data_dma;
 632         void *req_buffer;
 633         dma_addr_t req_dma;
 634         void *resp_buffer;
 635         dma_addr_t resp_dma;
 636         uint32_t resp_len;
 637         struct iscsi_task *task;
 638         struct passthru_status sts;
 639         struct work_struct task_work;
 640 };
 641
 642 struct qla_endpoint {
 643         struct Scsi_Host *host;
 644         struct sockaddr dst_addr;
 645 };
 646
 647 struct qla_conn {
 648         struct qla_endpoint *qla_ep;
 649 };
 650
 651 static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
 652 {
 653         return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0);
 654 }
 655
 656 static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
 657 {
 658         return ((ha->ip_config.ipv6_options &
 659                 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
 660 }
 661
 662 static inline int is_qla4010(struct scsi_qla_host *ha)
 663 {
 664         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
 665 }
 666
 667 static inline int is_qla4022(struct scsi_qla_host *ha)
 668 {
 669         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
 670 }
 671
 672 static inline int is_qla4032(struct scsi_qla_host *ha)
 673 {
 674         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
 675 }
 676
 677 static inline int is_qla40XX(struct scsi_qla_host *ha)
 678 {
 679         return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha);
 680 }
 681
 682 static inline int is_qla8022(struct scsi_qla_host *ha)
 683 {
 684         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
 685 }
 686
 687 /* Note: Currently AER/EEH is now supported only for 8022 cards
 688  * This function needs to be updated when AER/EEH is enabled
 689  * for other cards.
 690  */
 691 static inline int is_aer_supported(struct scsi_qla_host *ha)
 692 {
 693         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
 694 }
 695
 696 static inline int adapter_up(struct scsi_qla_host *ha)
 697 {
 698         return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
 699                 (test_bit(AF_LINK_UP, &ha->flags) != 0);
 700 }
 701
 702 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
 703 {
 704         return (struct scsi_qla_host *)iscsi_host_priv(shost);
 705 }
 706
 707 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
 708 {
 709         return (is_qla4010(ha) ?
 710                 &ha->reg->u1.isp4010.nvram :
 711                 &ha->reg->u1.isp4022.semaphore);
 712 }
 713
 714 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
 715 {
 716         return (is_qla4010(ha) ?
 717                 &ha->reg->u1.isp4010.nvram :
 718                 &ha->reg->u1.isp4022.nvram);
 719 }
 720
 721 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
 722 {
 723         return (is_qla4010(ha) ?
 724                 &ha->reg->u2.isp4010.ext_hw_conf :
 725                 &ha->reg->u2.isp4022.p0.ext_hw_conf);
 726 }
 727
 728 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
 729 {
 730         return (is_qla4010(ha) ?
 731                 &ha->reg->u2.isp4010.port_status :
 732                 &ha->reg->u2.isp4022.p0.port_status);
 733 }
 734
 735 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
 736 {
 737         return (is_qla4010(ha) ?
 738                 &ha->reg->u2.isp4010.port_ctrl :
 739                 &ha->reg->u2.isp4022.p0.port_ctrl);
 740 }
 741
 742 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
 743 {
 744         return (is_qla4010(ha) ?
 745                 &ha->reg->u2.isp4010.port_err_status :
 746                 &ha->reg->u2.isp4022.p0.port_err_status);
 747 }
 748
 749 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
 750 {
 751         return (is_qla4010(ha) ?
 752                 &ha->reg->u2.isp4010.gp_out :
 753                 &ha->reg->u2.isp4022.p0.gp_out);
 754 }
 755
 756 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
 757 {
 758         return (is_qla4010(ha) ?
 759                 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
 760                 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
 761 }
 762
 763 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
 764 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
 765 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
 766
 767 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
 768 {
 769         if (is_qla4010(a))
 770                 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
 771                                            QL4010_FLASH_SEM_BITS);
 772         else
 773                 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
 774                                            (QL4022_RESOURCE_BITS_BASE_CODE |
 775                                             (a->mac_index)) << 13);
 776 }
 777
 778 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
 779 {
 780         if (is_qla4010(a))
 781                 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
 782         else
 783                 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
 784 }
 785
 786 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
 787 {
 788         if (is_qla4010(a))
 789                 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
 790                                            QL4010_NVRAM_SEM_BITS);
 791         else
 792                 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
 793                                            (QL4022_RESOURCE_BITS_BASE_CODE |
 794                                             (a->mac_index)) << 10);
 795 }
 796
 797 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
 798 {
 799         if (is_qla4010(a))
 800                 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
 801         else
 802                 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
 803 }
 804
 805 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
 806 {
 807         if (is_qla4010(a))
 808                 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
 809                                        QL4010_DRVR_SEM_BITS);
 810         else
 811                 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
 812                                        (QL4022_RESOURCE_BITS_BASE_CODE |
 813                                         (a->mac_index)) << 1);
 814 }
 815
 816 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
 817 {
 818         if (is_qla4010(a))
 819                 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
 820         else
 821                 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
 822 }
 823
 824 static inline int ql4xxx_reset_active(struct scsi_qla_host *ha)
 825 {
 826         return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
 827                test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
 828                test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) ||
 829                test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) ||
 830                test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) ||
 831                test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
 832
 833 }
 834 /*---------------------------------------------------------------------------*/
 835
 836 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
 837 #define PRESERVE_DDB_LIST       0
 838 #define REBUILD_DDB_LIST        1
 839
 840 /* Defines for process_aen() */
 841 #define PROCESS_ALL_AENS         0
 842 #define FLUSH_DDB_CHANGED_AENS   1
 843
 844 #endif  /*_QLA4XXX_H */