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tty/serial: Add explicit PORT_TEGRA type
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / tty / serial / sh-sci.c
blobf35b8fb94b8383aceded2aaa983a75edee39126c
1 /*
2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #undef DEBUG
25
26 #include <linux/module.h>
27 #include <linux/errno.h>
28 #include <linux/timer.h>
29 #include <linux/interrupt.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial.h>
33 #include <linux/major.h>
34 #include <linux/string.h>
35 #include <linux/sysrq.h>
36 #include <linux/ioport.h>
37 #include <linux/mm.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/console.h>
41 #include <linux/platform_device.h>
42 #include <linux/serial_sci.h>
43 #include <linux/notifier.h>
44 #include <linux/cpufreq.h>
45 #include <linux/clk.h>
46 #include <linux/ctype.h>
47 #include <linux/err.h>
48 #include <linux/dmaengine.h>
49 #include <linux/scatterlist.h>
50 #include <linux/slab.h>
51
52 #ifdef CONFIG_SUPERH
53 #include <asm/sh_bios.h>
54 #endif
55
56 #ifdef CONFIG_H8300
57 #include <asm/gpio.h>
58 #endif
59
60 #include "sh-sci.h"
61
62 struct sci_port {
63 struct uart_port port;
64
65 /* Platform configuration */
66 struct plat_sci_port *cfg;
67
68 /* Port enable callback */
69 void (*enable)(struct uart_port *port);
70
71 /* Port disable callback */
72 void (*disable)(struct uart_port *port);
73
74 /* Break timer */
75 struct timer_list break_timer;
76 int break_flag;
77
78 /* Interface clock */
79 struct clk *iclk;
80 /* Function clock */
81 struct clk *fclk;
82
83 struct dma_chan *chan_tx;
84 struct dma_chan *chan_rx;
85
86 #ifdef CONFIG_SERIAL_SH_SCI_DMA
87 struct dma_async_tx_descriptor *desc_tx;
88 struct dma_async_tx_descriptor *desc_rx[2];
89 dma_cookie_t cookie_tx;
90 dma_cookie_t cookie_rx[2];
91 dma_cookie_t active_rx;
92 struct scatterlist sg_tx;
93 unsigned int sg_len_tx;
94 struct scatterlist sg_rx[2];
95 size_t buf_len_rx;
96 struct sh_dmae_slave param_tx;
97 struct sh_dmae_slave param_rx;
98 struct work_struct work_tx;
99 struct work_struct work_rx;
100 struct timer_list rx_timer;
101 unsigned int rx_timeout;
102 #endif
103
104 struct notifier_block freq_transition;
105 };
106
107 /* Function prototypes */
108 static void sci_start_tx(struct uart_port *port);
109 static void sci_stop_tx(struct uart_port *port);
110 static void sci_start_rx(struct uart_port *port);
111
112 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
113
114 static struct sci_port sci_ports[SCI_NPORTS];
115 static struct uart_driver sci_uart_driver;
116
117 static inline struct sci_port *
118 to_sci_port(struct uart_port *uart)
119 {
120 return container_of(uart, struct sci_port, port);
121 }
122
123 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
124
125 #ifdef CONFIG_CONSOLE_POLL
126 static int sci_poll_get_char(struct uart_port *port)
127 {
128 unsigned short status;
129 int c;
130
131 do {
132 status = sci_in(port, SCxSR);
133 if (status & SCxSR_ERRORS(port)) {
134 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
135 continue;
136 }
137 break;
138 } while (1);
139
140 if (!(status & SCxSR_RDxF(port)))
141 return NO_POLL_CHAR;
142
143 c = sci_in(port, SCxRDR);
144
145 /* Dummy read */
146 sci_in(port, SCxSR);
147 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
148
149 return c;
150 }
151 #endif
152
153 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
154 {
155 unsigned short status;
156
157 do {
158 status = sci_in(port, SCxSR);
159 } while (!(status & SCxSR_TDxE(port)));
160
161 sci_out(port, SCxTDR, c);
162 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
163 }
164 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
165
166 #if defined(__H8300H__) || defined(__H8300S__)
167 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
168 {
169 int ch = (port->mapbase - SMR0) >> 3;
170
171 /* set DDR regs */
172 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
173 h8300_sci_pins[ch].rx,
174 H8300_GPIO_INPUT);
175 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
176 h8300_sci_pins[ch].tx,
177 H8300_GPIO_OUTPUT);
178
179 /* tx mark output*/
180 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
181 }
182 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
183 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
184 {
185 if (port->mapbase == 0xA4400000) {
186 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
187 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
188 } else if (port->mapbase == 0xA4410000)
189 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
190 }
191 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
192 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
193 {
194 unsigned short data;
195
196 if (cflag & CRTSCTS) {
197 /* enable RTS/CTS */
198 if (port->mapbase == 0xa4430000) { /* SCIF0 */
199 /* Clear PTCR bit 9-2; enable all scif pins but sck */
200 data = __raw_readw(PORT_PTCR);
201 __raw_writew((data & 0xfc03), PORT_PTCR);
202 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
203 /* Clear PVCR bit 9-2 */
204 data = __raw_readw(PORT_PVCR);
205 __raw_writew((data & 0xfc03), PORT_PVCR);
206 }
207 } else {
208 if (port->mapbase == 0xa4430000) { /* SCIF0 */
209 /* Clear PTCR bit 5-2; enable only tx and rx */
210 data = __raw_readw(PORT_PTCR);
211 __raw_writew((data & 0xffc3), PORT_PTCR);
212 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
213 /* Clear PVCR bit 5-2 */
214 data = __raw_readw(PORT_PVCR);
215 __raw_writew((data & 0xffc3), PORT_PVCR);
216 }
217 }
218 }
219 #elif defined(CONFIG_CPU_SH3)
220 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
221 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
222 {
223 unsigned short data;
224
225 /* We need to set SCPCR to enable RTS/CTS */
226 data = __raw_readw(SCPCR);
227 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
228 __raw_writew(data & 0x0fcf, SCPCR);
229
230 if (!(cflag & CRTSCTS)) {
231 /* We need to set SCPCR to enable RTS/CTS */
232 data = __raw_readw(SCPCR);
233 /* Clear out SCP7MD1,0, SCP4MD1,0,
234 Set SCP6MD1,0 = {01} (output) */
235 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
236
237 data = __raw_readb(SCPDR);
238 /* Set /RTS2 (bit6) = 0 */
239 __raw_writeb(data & 0xbf, SCPDR);
240 }
241 }
242 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
243 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
244 {
245 unsigned short data;
246
247 if (port->mapbase == 0xffe00000) {
248 data = __raw_readw(PSCR);
249 data &= ~0x03cf;
250 if (!(cflag & CRTSCTS))
251 data |= 0x0340;
252
253 __raw_writew(data, PSCR);
254 }
255 }
256 #elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
257 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
258 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
259 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
260 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
261 defined(CONFIG_CPU_SUBTYPE_SHX3)
262 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
263 {
264 if (!(cflag & CRTSCTS))
265 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
266 }
267 #elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
268 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
269 {
270 if (!(cflag & CRTSCTS))
271 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
272 }
273 #else
274 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
275 {
276 /* Nothing to do */
277 }
278 #endif
279
280 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
281 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
282 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
283 defined(CONFIG_CPU_SUBTYPE_SH7786)
284 static int scif_txfill(struct uart_port *port)
285 {
286 return sci_in(port, SCTFDR) & 0xff;
287 }
288
289 static int scif_txroom(struct uart_port *port)
290 {
291 return SCIF_TXROOM_MAX - scif_txfill(port);
292 }
293
294 static int scif_rxfill(struct uart_port *port)
295 {
296 return sci_in(port, SCRFDR) & 0xff;
297 }
298 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
299 static int scif_txfill(struct uart_port *port)
300 {
301 if (port->mapbase == 0xffe00000 ||
302 port->mapbase == 0xffe08000)
303 /* SCIF0/1*/
304 return sci_in(port, SCTFDR) & 0xff;
305 else
306 /* SCIF2 */
307 return sci_in(port, SCFDR) >> 8;
308 }
309
310 static int scif_txroom(struct uart_port *port)
311 {
312 if (port->mapbase == 0xffe00000 ||
313 port->mapbase == 0xffe08000)
314 /* SCIF0/1*/
315 return SCIF_TXROOM_MAX - scif_txfill(port);
316 else
317 /* SCIF2 */
318 return SCIF2_TXROOM_MAX - scif_txfill(port);
319 }
320
321 static int scif_rxfill(struct uart_port *port)
322 {
323 if ((port->mapbase == 0xffe00000) ||
324 (port->mapbase == 0xffe08000)) {
325 /* SCIF0/1*/
326 return sci_in(port, SCRFDR) & 0xff;
327 } else {
328 /* SCIF2 */
329 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
330 }
331 }
332 #elif defined(CONFIG_ARCH_SH7372)
333 static int scif_txfill(struct uart_port *port)
334 {
335 if (port->type == PORT_SCIFA)
336 return sci_in(port, SCFDR) >> 8;
337 else
338 return sci_in(port, SCTFDR);
339 }
340
341 static int scif_txroom(struct uart_port *port)
342 {
343 return port->fifosize - scif_txfill(port);
344 }
345
346 static int scif_rxfill(struct uart_port *port)
347 {
348 if (port->type == PORT_SCIFA)
349 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
350 else
351 return sci_in(port, SCRFDR);
352 }
353 #else
354 static int scif_txfill(struct uart_port *port)
355 {
356 return sci_in(port, SCFDR) >> 8;
357 }
358
359 static int scif_txroom(struct uart_port *port)
360 {
361 return SCIF_TXROOM_MAX - scif_txfill(port);
362 }
363
364 static int scif_rxfill(struct uart_port *port)
365 {
366 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
367 }
368 #endif
369
370 static int sci_txfill(struct uart_port *port)
371 {
372 return !(sci_in(port, SCxSR) & SCI_TDRE);
373 }
374
375 static int sci_txroom(struct uart_port *port)
376 {
377 return !sci_txfill(port);
378 }
379
380 static int sci_rxfill(struct uart_port *port)
381 {
382 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
383 }
384
385 /* ********************************************************************** *
386 * the interrupt related routines *
387 * ********************************************************************** */
388
389 static void sci_transmit_chars(struct uart_port *port)
390 {
391 struct circ_buf *xmit = &port->state->xmit;
392 unsigned int stopped = uart_tx_stopped(port);
393 unsigned short status;
394 unsigned short ctrl;
395 int count;
396
397 status = sci_in(port, SCxSR);
398 if (!(status & SCxSR_TDxE(port))) {
399 ctrl = sci_in(port, SCSCR);
400 if (uart_circ_empty(xmit))
401 ctrl &= ~SCSCR_TIE;
402 else
403 ctrl |= SCSCR_TIE;
404 sci_out(port, SCSCR, ctrl);
405 return;
406 }
407
408 if (port->type == PORT_SCI)
409 count = sci_txroom(port);
410 else
411 count = scif_txroom(port);
412
413 do {
414 unsigned char c;
415
416 if (port->x_char) {
417 c = port->x_char;
418 port->x_char = 0;
419 } else if (!uart_circ_empty(xmit) && !stopped) {
420 c = xmit->buf[xmit->tail];
421 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
422 } else {
423 break;
424 }
425
426 sci_out(port, SCxTDR, c);
427
428 port->icount.tx++;
429 } while (--count > 0);
430
431 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
432
433 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
434 uart_write_wakeup(port);
435 if (uart_circ_empty(xmit)) {
436 sci_stop_tx(port);
437 } else {
438 ctrl = sci_in(port, SCSCR);
439
440 if (port->type != PORT_SCI) {
441 sci_in(port, SCxSR); /* Dummy read */
442 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
443 }
444
445 ctrl |= SCSCR_TIE;
446 sci_out(port, SCSCR, ctrl);
447 }
448 }
449
450 /* On SH3, SCIF may read end-of-break as a space->mark char */
451 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
452
453 static void sci_receive_chars(struct uart_port *port)
454 {
455 struct sci_port *sci_port = to_sci_port(port);
456 struct tty_struct *tty = port->state->port.tty;
457 int i, count, copied = 0;
458 unsigned short status;
459 unsigned char flag;
460
461 status = sci_in(port, SCxSR);
462 if (!(status & SCxSR_RDxF(port)))
463 return;
464
465 while (1) {
466 if (port->type == PORT_SCI)
467 count = sci_rxfill(port);
468 else
469 count = scif_rxfill(port);
470
471 /* Don't copy more bytes than there is room for in the buffer */
472 count = tty_buffer_request_room(tty, count);
473
474 /* If for any reason we can't copy more data, we're done! */
475 if (count == 0)
476 break;
477
478 if (port->type == PORT_SCI) {
479 char c = sci_in(port, SCxRDR);
480 if (uart_handle_sysrq_char(port, c) ||
481 sci_port->break_flag)
482 count = 0;
483 else
484 tty_insert_flip_char(tty, c, TTY_NORMAL);
485 } else {
486 for (i = 0; i < count; i++) {
487 char c = sci_in(port, SCxRDR);
488 status = sci_in(port, SCxSR);
489 #if defined(CONFIG_CPU_SH3)
490 /* Skip "chars" during break */
491 if (sci_port->break_flag) {
492 if ((c == 0) &&
493 (status & SCxSR_FER(port))) {
494 count--; i--;
495 continue;
496 }
497
498 /* Nonzero => end-of-break */
499 dev_dbg(port->dev, "debounce<%02x>\n", c);
500 sci_port->break_flag = 0;
501
502 if (STEPFN(c)) {
503 count--; i--;
504 continue;
505 }
506 }
507 #endif /* CONFIG_CPU_SH3 */
508 if (uart_handle_sysrq_char(port, c)) {
509 count--; i--;
510 continue;
511 }
512
513 /* Store data and status */
514 if (status & SCxSR_FER(port)) {
515 flag = TTY_FRAME;
516 dev_notice(port->dev, "frame error\n");
517 } else if (status & SCxSR_PER(port)) {
518 flag = TTY_PARITY;
519 dev_notice(port->dev, "parity error\n");
520 } else
521 flag = TTY_NORMAL;
522
523 tty_insert_flip_char(tty, c, flag);
524 }
525 }
526
527 sci_in(port, SCxSR); /* dummy read */
528 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
529
530 copied += count;
531 port->icount.rx += count;
532 }
533
534 if (copied) {
535 /* Tell the rest of the system the news. New characters! */
536 tty_flip_buffer_push(tty);
537 } else {
538 sci_in(port, SCxSR); /* dummy read */
539 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
540 }
541 }
542
543 #define SCI_BREAK_JIFFIES (HZ/20)
544
545 /*
546 * The sci generates interrupts during the break,
547 * 1 per millisecond or so during the break period, for 9600 baud.
548 * So dont bother disabling interrupts.
549 * But dont want more than 1 break event.
550 * Use a kernel timer to periodically poll the rx line until
551 * the break is finished.
552 */
553 static inline void sci_schedule_break_timer(struct sci_port *port)
554 {
555 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
556 }
557
558 /* Ensure that two consecutive samples find the break over. */
559 static void sci_break_timer(unsigned long data)
560 {
561 struct sci_port *port = (struct sci_port *)data;
562
563 if (sci_rxd_in(&port->port) == 0) {
564 port->break_flag = 1;
565 sci_schedule_break_timer(port);
566 } else if (port->break_flag == 1) {
567 /* break is over. */
568 port->break_flag = 2;
569 sci_schedule_break_timer(port);
570 } else
571 port->break_flag = 0;
572 }
573
574 static int sci_handle_errors(struct uart_port *port)
575 {
576 int copied = 0;
577 unsigned short status = sci_in(port, SCxSR);
578 struct tty_struct *tty = port->state->port.tty;
579
580 if (status & SCxSR_ORER(port)) {
581 /* overrun error */
582 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
583 copied++;
584
585 dev_notice(port->dev, "overrun error");
586 }
587
588 if (status & SCxSR_FER(port)) {
589 if (sci_rxd_in(port) == 0) {
590 /* Notify of BREAK */
591 struct sci_port *sci_port = to_sci_port(port);
592
593 if (!sci_port->break_flag) {
594 sci_port->break_flag = 1;
595 sci_schedule_break_timer(sci_port);
596
597 /* Do sysrq handling. */
598 if (uart_handle_break(port))
599 return 0;
600
601 dev_dbg(port->dev, "BREAK detected\n");
602
603 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
604 copied++;
605 }
606
607 } else {
608 /* frame error */
609 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
610 copied++;
611
612 dev_notice(port->dev, "frame error\n");
613 }
614 }
615
616 if (status & SCxSR_PER(port)) {
617 /* parity error */
618 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
619 copied++;
620
621 dev_notice(port->dev, "parity error");
622 }
623
624 if (copied)
625 tty_flip_buffer_push(tty);
626
627 return copied;
628 }
629
630 static int sci_handle_fifo_overrun(struct uart_port *port)
631 {
632 struct tty_struct *tty = port->state->port.tty;
633 int copied = 0;
634
635 if (port->type != PORT_SCIF)
636 return 0;
637
638 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
639 sci_out(port, SCLSR, 0);
640
641 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
642 tty_flip_buffer_push(tty);
643
644 dev_notice(port->dev, "overrun error\n");
645 copied++;
646 }
647
648 return copied;
649 }
650
651 static int sci_handle_breaks(struct uart_port *port)
652 {
653 int copied = 0;
654 unsigned short status = sci_in(port, SCxSR);
655 struct tty_struct *tty = port->state->port.tty;
656 struct sci_port *s = to_sci_port(port);
657
658 if (uart_handle_break(port))
659 return 0;
660
661 if (!s->break_flag && status & SCxSR_BRK(port)) {
662 #if defined(CONFIG_CPU_SH3)
663 /* Debounce break */
664 s->break_flag = 1;
665 #endif
666 /* Notify of BREAK */
667 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
668 copied++;
669
670 dev_dbg(port->dev, "BREAK detected\n");
671 }
672
673 if (copied)
674 tty_flip_buffer_push(tty);
675
676 copied += sci_handle_fifo_overrun(port);
677
678 return copied;
679 }
680
681 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
682 {
683 #ifdef CONFIG_SERIAL_SH_SCI_DMA
684 struct uart_port *port = ptr;
685 struct sci_port *s = to_sci_port(port);
686
687 if (s->chan_rx) {
688 u16 scr = sci_in(port, SCSCR);
689 u16 ssr = sci_in(port, SCxSR);
690
691 /* Disable future Rx interrupts */
692 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
693 disable_irq_nosync(irq);
694 scr |= 0x4000;
695 } else {
696 scr &= ~SCSCR_RIE;
697 }
698 sci_out(port, SCSCR, scr);
699 /* Clear current interrupt */
700 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
701 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
702 jiffies, s->rx_timeout);
703 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
704
705 return IRQ_HANDLED;
706 }
707 #endif
708
709 /* I think sci_receive_chars has to be called irrespective
710 * of whether the I_IXOFF is set, otherwise, how is the interrupt
711 * to be disabled?
712 */
713 sci_receive_chars(ptr);
714
715 return IRQ_HANDLED;
716 }
717
718 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
719 {
720 struct uart_port *port = ptr;
721 unsigned long flags;
722
723 spin_lock_irqsave(&port->lock, flags);
724 sci_transmit_chars(port);
725 spin_unlock_irqrestore(&port->lock, flags);
726
727 return IRQ_HANDLED;
728 }
729
730 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
731 {
732 struct uart_port *port = ptr;
733
734 /* Handle errors */
735 if (port->type == PORT_SCI) {
736 if (sci_handle_errors(port)) {
737 /* discard character in rx buffer */
738 sci_in(port, SCxSR);
739 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
740 }
741 } else {
742 sci_handle_fifo_overrun(port);
743 sci_rx_interrupt(irq, ptr);
744 }
745
746 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
747
748 /* Kick the transmission */
749 sci_tx_interrupt(irq, ptr);
750
751 return IRQ_HANDLED;
752 }
753
754 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
755 {
756 struct uart_port *port = ptr;
757
758 /* Handle BREAKs */
759 sci_handle_breaks(port);
760 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
761
762 return IRQ_HANDLED;
763 }
764
765 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
766 {
767 /*
768 * Not all ports (such as SCIFA) will support REIE. Rather than
769 * special-casing the port type, we check the port initialization
770 * IRQ enable mask to see whether the IRQ is desired at all. If
771 * it's unset, it's logically inferred that there's no point in
772 * testing for it.
773 */
774 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
775 }
776
777 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
778 {
779 unsigned short ssr_status, scr_status, err_enabled;
780 struct uart_port *port = ptr;
781 struct sci_port *s = to_sci_port(port);
782 irqreturn_t ret = IRQ_NONE;
783
784 ssr_status = sci_in(port, SCxSR);
785 scr_status = sci_in(port, SCSCR);
786 err_enabled = scr_status & port_rx_irq_mask(port);
787
788 /* Tx Interrupt */
789 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
790 !s->chan_tx)
791 ret = sci_tx_interrupt(irq, ptr);
792
793 /*
794 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
795 * DR flags
796 */
797 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
798 (scr_status & SCSCR_RIE))
799 ret = sci_rx_interrupt(irq, ptr);
800
801 /* Error Interrupt */
802 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
803 ret = sci_er_interrupt(irq, ptr);
804
805 /* Break Interrupt */
806 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
807 ret = sci_br_interrupt(irq, ptr);
808
809 return ret;
810 }
811
812 /*
813 * Here we define a transition notifier so that we can update all of our
814 * ports' baud rate when the peripheral clock changes.
815 */
816 static int sci_notifier(struct notifier_block *self,
817 unsigned long phase, void *p)
818 {
819 struct sci_port *sci_port;
820 unsigned long flags;
821
822 sci_port = container_of(self, struct sci_port, freq_transition);
823
824 if ((phase == CPUFREQ_POSTCHANGE) ||
825 (phase == CPUFREQ_RESUMECHANGE)) {
826 struct uart_port *port = &sci_port->port;
827
828 spin_lock_irqsave(&port->lock, flags);
829 port->uartclk = clk_get_rate(sci_port->iclk);
830 spin_unlock_irqrestore(&port->lock, flags);
831 }
832
833 return NOTIFY_OK;
834 }
835
836 static void sci_clk_enable(struct uart_port *port)
837 {
838 struct sci_port *sci_port = to_sci_port(port);
839
840 clk_enable(sci_port->iclk);
841 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
842 clk_enable(sci_port->fclk);
843 }
844
845 static void sci_clk_disable(struct uart_port *port)
846 {
847 struct sci_port *sci_port = to_sci_port(port);
848
849 clk_disable(sci_port->fclk);
850 clk_disable(sci_port->iclk);
851 }
852
853 static int sci_request_irq(struct sci_port *port)
854 {
855 int i;
856 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
857 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
858 sci_br_interrupt,
859 };
860 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
861 "SCI Transmit Data Empty", "SCI Break" };
862
863 if (port->cfg->irqs[0] == port->cfg->irqs[1]) {
864 if (unlikely(!port->cfg->irqs[0]))
865 return -ENODEV;
866
867 if (request_irq(port->cfg->irqs[0], sci_mpxed_interrupt,
868 IRQF_DISABLED, "sci", port)) {
869 dev_err(port->port.dev, "Can't allocate IRQ\n");
870 return -ENODEV;
871 }
872 } else {
873 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
874 if (unlikely(!port->cfg->irqs[i]))
875 continue;
876
877 if (request_irq(port->cfg->irqs[i], handlers[i],
878 IRQF_DISABLED, desc[i], port)) {
879 dev_err(port->port.dev, "Can't allocate IRQ\n");
880 return -ENODEV;
881 }
882 }
883 }
884
885 return 0;
886 }
887
888 static void sci_free_irq(struct sci_port *port)
889 {
890 int i;
891
892 if (port->cfg->irqs[0] == port->cfg->irqs[1])
893 free_irq(port->cfg->irqs[0], port);
894 else {
895 for (i = 0; i < ARRAY_SIZE(port->cfg->irqs); i++) {
896 if (!port->cfg->irqs[i])
897 continue;
898
899 free_irq(port->cfg->irqs[i], port);
900 }
901 }
902 }
903
904 static unsigned int sci_tx_empty(struct uart_port *port)
905 {
906 unsigned short status = sci_in(port, SCxSR);
907 unsigned short in_tx_fifo = scif_txfill(port);
908
909 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
910 }
911
912 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
913 {
914 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
915 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
916 /* If you have signals for DTR and DCD, please implement here. */
917 }
918
919 static unsigned int sci_get_mctrl(struct uart_port *port)
920 {
921 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
922 and CTS/RTS */
923
924 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
925 }
926
927 #ifdef CONFIG_SERIAL_SH_SCI_DMA
928 static void sci_dma_tx_complete(void *arg)
929 {
930 struct sci_port *s = arg;
931 struct uart_port *port = &s->port;
932 struct circ_buf *xmit = &port->state->xmit;
933 unsigned long flags;
934
935 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
936
937 spin_lock_irqsave(&port->lock, flags);
938
939 xmit->tail += sg_dma_len(&s->sg_tx);
940 xmit->tail &= UART_XMIT_SIZE - 1;
941
942 port->icount.tx += sg_dma_len(&s->sg_tx);
943
944 async_tx_ack(s->desc_tx);
945 s->cookie_tx = -EINVAL;
946 s->desc_tx = NULL;
947
948 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
949 uart_write_wakeup(port);
950
951 if (!uart_circ_empty(xmit)) {
952 schedule_work(&s->work_tx);
953 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
954 u16 ctrl = sci_in(port, SCSCR);
955 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE);
956 }
957
958 spin_unlock_irqrestore(&port->lock, flags);
959 }
960
961 /* Locking: called with port lock held */
962 static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
963 size_t count)
964 {
965 struct uart_port *port = &s->port;
966 int i, active, room;
967
968 room = tty_buffer_request_room(tty, count);
969
970 if (s->active_rx == s->cookie_rx[0]) {
971 active = 0;
972 } else if (s->active_rx == s->cookie_rx[1]) {
973 active = 1;
974 } else {
975 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
976 return 0;
977 }
978
979 if (room < count)
980 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
981 count - room);
982 if (!room)
983 return room;
984
985 for (i = 0; i < room; i++)
986 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
987 TTY_NORMAL);
988
989 port->icount.rx += room;
990
991 return room;
992 }
993
994 static void sci_dma_rx_complete(void *arg)
995 {
996 struct sci_port *s = arg;
997 struct uart_port *port = &s->port;
998 struct tty_struct *tty = port->state->port.tty;
999 unsigned long flags;
1000 int count;
1001
1002 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
1003
1004 spin_lock_irqsave(&port->lock, flags);
1005
1006 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1007
1008 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1009
1010 spin_unlock_irqrestore(&port->lock, flags);
1011
1012 if (count)
1013 tty_flip_buffer_push(tty);
1014
1015 schedule_work(&s->work_rx);
1016 }
1017
1018 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1019 {
1020 struct dma_chan *chan = s->chan_rx;
1021 struct uart_port *port = &s->port;
1022
1023 s->chan_rx = NULL;
1024 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1025 dma_release_channel(chan);
1026 if (sg_dma_address(&s->sg_rx[0]))
1027 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1028 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1029 if (enable_pio)
1030 sci_start_rx(port);
1031 }
1032
1033 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1034 {
1035 struct dma_chan *chan = s->chan_tx;
1036 struct uart_port *port = &s->port;
1037
1038 s->chan_tx = NULL;
1039 s->cookie_tx = -EINVAL;
1040 dma_release_channel(chan);
1041 if (enable_pio)
1042 sci_start_tx(port);
1043 }
1044
1045 static void sci_submit_rx(struct sci_port *s)
1046 {
1047 struct dma_chan *chan = s->chan_rx;
1048 int i;
1049
1050 for (i = 0; i < 2; i++) {
1051 struct scatterlist *sg = &s->sg_rx[i];
1052 struct dma_async_tx_descriptor *desc;
1053
1054 desc = chan->device->device_prep_slave_sg(chan,
1055 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1056
1057 if (desc) {
1058 s->desc_rx[i] = desc;
1059 desc->callback = sci_dma_rx_complete;
1060 desc->callback_param = s;
1061 s->cookie_rx[i] = desc->tx_submit(desc);
1062 }
1063
1064 if (!desc || s->cookie_rx[i] < 0) {
1065 if (i) {
1066 async_tx_ack(s->desc_rx[0]);
1067 s->cookie_rx[0] = -EINVAL;
1068 }
1069 if (desc) {
1070 async_tx_ack(desc);
1071 s->cookie_rx[i] = -EINVAL;
1072 }
1073 dev_warn(s->port.dev,
1074 "failed to re-start DMA, using PIO\n");
1075 sci_rx_dma_release(s, true);
1076 return;
1077 }
1078 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1079 s->cookie_rx[i], i);
1080 }
1081
1082 s->active_rx = s->cookie_rx[0];
1083
1084 dma_async_issue_pending(chan);
1085 }
1086
1087 static void work_fn_rx(struct work_struct *work)
1088 {
1089 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1090 struct uart_port *port = &s->port;
1091 struct dma_async_tx_descriptor *desc;
1092 int new;
1093
1094 if (s->active_rx == s->cookie_rx[0]) {
1095 new = 0;
1096 } else if (s->active_rx == s->cookie_rx[1]) {
1097 new = 1;
1098 } else {
1099 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1100 return;
1101 }
1102 desc = s->desc_rx[new];
1103
1104 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1105 DMA_SUCCESS) {
1106 /* Handle incomplete DMA receive */
1107 struct tty_struct *tty = port->state->port.tty;
1108 struct dma_chan *chan = s->chan_rx;
1109 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1110 async_tx);
1111 unsigned long flags;
1112 int count;
1113
1114 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
1115 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1116 sh_desc->partial, sh_desc->cookie);
1117
1118 spin_lock_irqsave(&port->lock, flags);
1119 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1120 spin_unlock_irqrestore(&port->lock, flags);
1121
1122 if (count)
1123 tty_flip_buffer_push(tty);
1124
1125 sci_submit_rx(s);
1126
1127 return;
1128 }
1129
1130 s->cookie_rx[new] = desc->tx_submit(desc);
1131 if (s->cookie_rx[new] < 0) {
1132 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1133 sci_rx_dma_release(s, true);
1134 return;
1135 }
1136
1137 s->active_rx = s->cookie_rx[!new];
1138
1139 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1140 s->cookie_rx[new], new, s->active_rx);
1141 }
1142
1143 static void work_fn_tx(struct work_struct *work)
1144 {
1145 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1146 struct dma_async_tx_descriptor *desc;
1147 struct dma_chan *chan = s->chan_tx;
1148 struct uart_port *port = &s->port;
1149 struct circ_buf *xmit = &port->state->xmit;
1150 struct scatterlist *sg = &s->sg_tx;
1151
1152 /*
1153 * DMA is idle now.
1154 * Port xmit buffer is already mapped, and it is one page... Just adjust
1155 * offsets and lengths. Since it is a circular buffer, we have to
1156 * transmit till the end, and then the rest. Take the port lock to get a
1157 * consistent xmit buffer state.
1158 */
1159 spin_lock_irq(&port->lock);
1160 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1161 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1162 sg->offset;
1163 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1164 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1165 spin_unlock_irq(&port->lock);
1166
1167 BUG_ON(!sg_dma_len(sg));
1168
1169 desc = chan->device->device_prep_slave_sg(chan,
1170 sg, s->sg_len_tx, DMA_TO_DEVICE,
1171 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1172 if (!desc) {
1173 /* switch to PIO */
1174 sci_tx_dma_release(s, true);
1175 return;
1176 }
1177
1178 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1179
1180 spin_lock_irq(&port->lock);
1181 s->desc_tx = desc;
1182 desc->callback = sci_dma_tx_complete;
1183 desc->callback_param = s;
1184 spin_unlock_irq(&port->lock);
1185 s->cookie_tx = desc->tx_submit(desc);
1186 if (s->cookie_tx < 0) {
1187 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1188 /* switch to PIO */
1189 sci_tx_dma_release(s, true);
1190 return;
1191 }
1192
1193 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1194 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1195
1196 dma_async_issue_pending(chan);
1197 }
1198 #endif
1199
1200 static void sci_start_tx(struct uart_port *port)
1201 {
1202 struct sci_port *s = to_sci_port(port);
1203 unsigned short ctrl;
1204
1205 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1206 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1207 u16 new, scr = sci_in(port, SCSCR);
1208 if (s->chan_tx)
1209 new = scr | 0x8000;
1210 else
1211 new = scr & ~0x8000;
1212 if (new != scr)
1213 sci_out(port, SCSCR, new);
1214 }
1215
1216 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1217 s->cookie_tx < 0)
1218 schedule_work(&s->work_tx);
1219 #endif
1220
1221 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1222 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1223 ctrl = sci_in(port, SCSCR);
1224 sci_out(port, SCSCR, ctrl | SCSCR_TIE);
1225 }
1226 }
1227
1228 static void sci_stop_tx(struct uart_port *port)
1229 {
1230 unsigned short ctrl;
1231
1232 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1233 ctrl = sci_in(port, SCSCR);
1234
1235 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1236 ctrl &= ~0x8000;
1237
1238 ctrl &= ~SCSCR_TIE;
1239
1240 sci_out(port, SCSCR, ctrl);
1241 }
1242
1243 static void sci_start_rx(struct uart_port *port)
1244 {
1245 unsigned short ctrl;
1246
1247 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port);
1248
1249 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1250 ctrl &= ~0x4000;
1251
1252 sci_out(port, SCSCR, ctrl);
1253 }
1254
1255 static void sci_stop_rx(struct uart_port *port)
1256 {
1257 unsigned short ctrl;
1258
1259 ctrl = sci_in(port, SCSCR);
1260
1261 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1262 ctrl &= ~0x4000;
1263
1264 ctrl &= ~port_rx_irq_mask(port);
1265
1266 sci_out(port, SCSCR, ctrl);
1267 }
1268
1269 static void sci_enable_ms(struct uart_port *port)
1270 {
1271 /* Nothing here yet .. */
1272 }
1273
1274 static void sci_break_ctl(struct uart_port *port, int break_state)
1275 {
1276 /* Nothing here yet .. */
1277 }
1278
1279 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1280 static bool filter(struct dma_chan *chan, void *slave)
1281 {
1282 struct sh_dmae_slave *param = slave;
1283
1284 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1285 param->slave_id);
1286
1287 if (param->dma_dev == chan->device->dev) {
1288 chan->private = param;
1289 return true;
1290 } else {
1291 return false;
1292 }
1293 }
1294
1295 static void rx_timer_fn(unsigned long arg)
1296 {
1297 struct sci_port *s = (struct sci_port *)arg;
1298 struct uart_port *port = &s->port;
1299 u16 scr = sci_in(port, SCSCR);
1300
1301 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1302 scr &= ~0x4000;
1303 enable_irq(s->cfg->irqs[1]);
1304 }
1305 sci_out(port, SCSCR, scr | SCSCR_RIE);
1306 dev_dbg(port->dev, "DMA Rx timed out\n");
1307 schedule_work(&s->work_rx);
1308 }
1309
1310 static void sci_request_dma(struct uart_port *port)
1311 {
1312 struct sci_port *s = to_sci_port(port);
1313 struct sh_dmae_slave *param;
1314 struct dma_chan *chan;
1315 dma_cap_mask_t mask;
1316 int nent;
1317
1318 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
1319 port->line, s->cfg->dma_dev);
1320
1321 if (!s->cfg->dma_dev)
1322 return;
1323
1324 dma_cap_zero(mask);
1325 dma_cap_set(DMA_SLAVE, mask);
1326
1327 param = &s->param_tx;
1328
1329 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1330 param->slave_id = s->cfg->dma_slave_tx;
1331 param->dma_dev = s->cfg->dma_dev;
1332
1333 s->cookie_tx = -EINVAL;
1334 chan = dma_request_channel(mask, filter, param);
1335 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1336 if (chan) {
1337 s->chan_tx = chan;
1338 sg_init_table(&s->sg_tx, 1);
1339 /* UART circular tx buffer is an aligned page. */
1340 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1341 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1342 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1343 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1344 if (!nent)
1345 sci_tx_dma_release(s, false);
1346 else
1347 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1348 sg_dma_len(&s->sg_tx),
1349 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1350
1351 s->sg_len_tx = nent;
1352
1353 INIT_WORK(&s->work_tx, work_fn_tx);
1354 }
1355
1356 param = &s->param_rx;
1357
1358 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1359 param->slave_id = s->cfg->dma_slave_rx;
1360 param->dma_dev = s->cfg->dma_dev;
1361
1362 chan = dma_request_channel(mask, filter, param);
1363 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1364 if (chan) {
1365 dma_addr_t dma[2];
1366 void *buf[2];
1367 int i;
1368
1369 s->chan_rx = chan;
1370
1371 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1372 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1373 &dma[0], GFP_KERNEL);
1374
1375 if (!buf[0]) {
1376 dev_warn(port->dev,
1377 "failed to allocate dma buffer, using PIO\n");
1378 sci_rx_dma_release(s, true);
1379 return;
1380 }
1381
1382 buf[1] = buf[0] + s->buf_len_rx;
1383 dma[1] = dma[0] + s->buf_len_rx;
1384
1385 for (i = 0; i < 2; i++) {
1386 struct scatterlist *sg = &s->sg_rx[i];
1387
1388 sg_init_table(sg, 1);
1389 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1390 (int)buf[i] & ~PAGE_MASK);
1391 sg_dma_address(sg) = dma[i];
1392 }
1393
1394 INIT_WORK(&s->work_rx, work_fn_rx);
1395 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1396
1397 sci_submit_rx(s);
1398 }
1399 }
1400
1401 static void sci_free_dma(struct uart_port *port)
1402 {
1403 struct sci_port *s = to_sci_port(port);
1404
1405 if (!s->cfg->dma_dev)
1406 return;
1407
1408 if (s->chan_tx)
1409 sci_tx_dma_release(s, false);
1410 if (s->chan_rx)
1411 sci_rx_dma_release(s, false);
1412 }
1413 #else
1414 static inline void sci_request_dma(struct uart_port *port)
1415 {
1416 }
1417
1418 static inline void sci_free_dma(struct uart_port *port)
1419 {
1420 }
1421 #endif
1422
1423 static int sci_startup(struct uart_port *port)
1424 {
1425 struct sci_port *s = to_sci_port(port);
1426 int ret;
1427
1428 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1429
1430 if (s->enable)
1431 s->enable(port);
1432
1433 ret = sci_request_irq(s);
1434 if (unlikely(ret < 0))
1435 return ret;
1436
1437 sci_request_dma(port);
1438
1439 sci_start_tx(port);
1440 sci_start_rx(port);
1441
1442 return 0;
1443 }
1444
1445 static void sci_shutdown(struct uart_port *port)
1446 {
1447 struct sci_port *s = to_sci_port(port);
1448
1449 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1450
1451 sci_stop_rx(port);
1452 sci_stop_tx(port);
1453
1454 sci_free_dma(port);
1455 sci_free_irq(s);
1456
1457 if (s->disable)
1458 s->disable(port);
1459 }
1460
1461 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1462 unsigned long freq)
1463 {
1464 switch (algo_id) {
1465 case SCBRR_ALGO_1:
1466 return ((freq + 16 * bps) / (16 * bps) - 1);
1467 case SCBRR_ALGO_2:
1468 return ((freq + 16 * bps) / (32 * bps) - 1);
1469 case SCBRR_ALGO_3:
1470 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1471 case SCBRR_ALGO_4:
1472 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1473 case SCBRR_ALGO_5:
1474 return (((freq * 1000 / 32) / bps) - 1);
1475 }
1476
1477 /* Warn, but use a safe default */
1478 WARN_ON(1);
1479
1480 return ((freq + 16 * bps) / (32 * bps) - 1);
1481 }
1482
1483 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1484 struct ktermios *old)
1485 {
1486 struct sci_port *s = to_sci_port(port);
1487 unsigned int status, baud, smr_val, max_baud;
1488 int t = -1;
1489 u16 scfcr = 0;
1490
1491 /*
1492 * earlyprintk comes here early on with port->uartclk set to zero.
1493 * the clock framework is not up and running at this point so here
1494 * we assume that 115200 is the maximum baud rate. please note that
1495 * the baud rate is not programmed during earlyprintk - it is assumed
1496 * that the previous boot loader has enabled required clocks and
1497 * setup the baud rate generator hardware for us already.
1498 */
1499 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1500
1501 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1502 if (likely(baud && port->uartclk))
1503 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
1504
1505 if (s->enable)
1506 s->enable(port);
1507
1508 do {
1509 status = sci_in(port, SCxSR);
1510 } while (!(status & SCxSR_TEND(port)));
1511
1512 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1513
1514 if (port->type != PORT_SCI)
1515 sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST);
1516
1517 smr_val = sci_in(port, SCSMR) & 3;
1518
1519 if ((termios->c_cflag & CSIZE) == CS7)
1520 smr_val |= 0x40;
1521 if (termios->c_cflag & PARENB)
1522 smr_val |= 0x20;
1523 if (termios->c_cflag & PARODD)
1524 smr_val |= 0x30;
1525 if (termios->c_cflag & CSTOPB)
1526 smr_val |= 0x08;
1527
1528 uart_update_timeout(port, termios->c_cflag, baud);
1529
1530 sci_out(port, SCSMR, smr_val);
1531
1532 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
1533 s->cfg->scscr);
1534
1535 if (t > 0) {
1536 if (t >= 256) {
1537 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1538 t >>= 2;
1539 } else
1540 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1541
1542 sci_out(port, SCBRR, t);
1543 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1544 }
1545
1546 sci_init_pins(port, termios->c_cflag);
1547 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0));
1548
1549 sci_out(port, SCSCR, s->cfg->scscr);
1550
1551 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1552 /*
1553 * Calculate delay for 1.5 DMA buffers: see
1554 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1555 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1556 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1557 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1558 * sizes), but it has been found out experimentally, that this is not
1559 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1560 * as a minimum seem to work perfectly.
1561 */
1562 if (s->chan_rx) {
1563 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1564 port->fifosize / 2;
1565 dev_dbg(port->dev,
1566 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1567 s->rx_timeout * 1000 / HZ, port->timeout);
1568 if (s->rx_timeout < msecs_to_jiffies(20))
1569 s->rx_timeout = msecs_to_jiffies(20);
1570 }
1571 #endif
1572
1573 if ((termios->c_cflag & CREAD) != 0)
1574 sci_start_rx(port);
1575
1576 if (s->disable)
1577 s->disable(port);
1578 }
1579
1580 static const char *sci_type(struct uart_port *port)
1581 {
1582 switch (port->type) {
1583 case PORT_IRDA:
1584 return "irda";
1585 case PORT_SCI:
1586 return "sci";
1587 case PORT_SCIF:
1588 return "scif";
1589 case PORT_SCIFA:
1590 return "scifa";
1591 case PORT_SCIFB:
1592 return "scifb";
1593 }
1594
1595 return NULL;
1596 }
1597
1598 static inline unsigned long sci_port_size(struct uart_port *port)
1599 {
1600 /*
1601 * Pick an arbitrary size that encapsulates all of the base
1602 * registers by default. This can be optimized later, or derived
1603 * from platform resource data at such a time that ports begin to
1604 * behave more erratically.
1605 */
1606 return 64;
1607 }
1608
1609 static int sci_remap_port(struct uart_port *port)
1610 {
1611 unsigned long size = sci_port_size(port);
1612
1613 /*
1614 * Nothing to do if there's already an established membase.
1615 */
1616 if (port->membase)
1617 return 0;
1618
1619 if (port->flags & UPF_IOREMAP) {
1620 port->membase = ioremap_nocache(port->mapbase, size);
1621 if (unlikely(!port->membase)) {
1622 dev_err(port->dev, "can't remap port#%d\n", port->line);
1623 return -ENXIO;
1624 }
1625 } else {
1626 /*
1627 * For the simple (and majority of) cases where we don't
1628 * need to do any remapping, just cast the cookie
1629 * directly.
1630 */
1631 port->membase = (void __iomem *)port->mapbase;
1632 }
1633
1634 return 0;
1635 }
1636
1637 static void sci_release_port(struct uart_port *port)
1638 {
1639 if (port->flags & UPF_IOREMAP) {
1640 iounmap(port->membase);
1641 port->membase = NULL;
1642 }
1643
1644 release_mem_region(port->mapbase, sci_port_size(port));
1645 }
1646
1647 static int sci_request_port(struct uart_port *port)
1648 {
1649 unsigned long size = sci_port_size(port);
1650 struct resource *res;
1651 int ret;
1652
1653 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
1654 if (unlikely(res == NULL))
1655 return -EBUSY;
1656
1657 ret = sci_remap_port(port);
1658 if (unlikely(ret != 0)) {
1659 release_resource(res);
1660 return ret;
1661 }
1662
1663 return 0;
1664 }
1665
1666 static void sci_config_port(struct uart_port *port, int flags)
1667 {
1668 if (flags & UART_CONFIG_TYPE) {
1669 struct sci_port *sport = to_sci_port(port);
1670
1671 port->type = sport->cfg->type;
1672 sci_request_port(port);
1673 }
1674 }
1675
1676 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1677 {
1678 struct sci_port *s = to_sci_port(port);
1679
1680 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1681 return -EINVAL;
1682 if (ser->baud_base < 2400)
1683 /* No paper tape reader for Mitch.. */
1684 return -EINVAL;
1685
1686 return 0;
1687 }
1688
1689 static struct uart_ops sci_uart_ops = {
1690 .tx_empty = sci_tx_empty,
1691 .set_mctrl = sci_set_mctrl,
1692 .get_mctrl = sci_get_mctrl,
1693 .start_tx = sci_start_tx,
1694 .stop_tx = sci_stop_tx,
1695 .stop_rx = sci_stop_rx,
1696 .enable_ms = sci_enable_ms,
1697 .break_ctl = sci_break_ctl,
1698 .startup = sci_startup,
1699 .shutdown = sci_shutdown,
1700 .set_termios = sci_set_termios,
1701 .type = sci_type,
1702 .release_port = sci_release_port,
1703 .request_port = sci_request_port,
1704 .config_port = sci_config_port,
1705 .verify_port = sci_verify_port,
1706 #ifdef CONFIG_CONSOLE_POLL
1707 .poll_get_char = sci_poll_get_char,
1708 .poll_put_char = sci_poll_put_char,
1709 #endif
1710 };
1711
1712 static int __devinit sci_init_single(struct platform_device *dev,
1713 struct sci_port *sci_port,
1714 unsigned int index,
1715 struct plat_sci_port *p)
1716 {
1717 struct uart_port *port = &sci_port->port;
1718
1719 port->ops = &sci_uart_ops;
1720 port->iotype = UPIO_MEM;
1721 port->line = index;
1722
1723 switch (p->type) {
1724 case PORT_SCIFB:
1725 port->fifosize = 256;
1726 break;
1727 case PORT_SCIFA:
1728 port->fifosize = 64;
1729 break;
1730 case PORT_SCIF:
1731 port->fifosize = 16;
1732 break;
1733 default:
1734 port->fifosize = 1;
1735 break;
1736 }
1737
1738 if (dev) {
1739 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1740 if (IS_ERR(sci_port->iclk)) {
1741 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
1742 if (IS_ERR(sci_port->iclk)) {
1743 dev_err(&dev->dev, "can't get iclk\n");
1744 return PTR_ERR(sci_port->iclk);
1745 }
1746 }
1747
1748 /*
1749 * The function clock is optional, ignore it if we can't
1750 * find it.
1751 */
1752 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
1753 if (IS_ERR(sci_port->fclk))
1754 sci_port->fclk = NULL;
1755
1756 sci_port->enable = sci_clk_enable;
1757 sci_port->disable = sci_clk_disable;
1758 port->dev = &dev->dev;
1759 }
1760
1761 sci_port->break_timer.data = (unsigned long)sci_port;
1762 sci_port->break_timer.function = sci_break_timer;
1763 init_timer(&sci_port->break_timer);
1764
1765 sci_port->cfg = p;
1766
1767 port->mapbase = p->mapbase;
1768 port->type = p->type;
1769 port->flags = p->flags;
1770
1771 /*
1772 * The UART port needs an IRQ value, so we peg this to the TX IRQ
1773 * for the multi-IRQ ports, which is where we are primarily
1774 * concerned with the shutdown path synchronization.
1775 *
1776 * For the muxed case there's nothing more to do.
1777 */
1778 port->irq = p->irqs[SCIx_TXI_IRQ];
1779
1780 if (p->dma_dev)
1781 dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n",
1782 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
1783
1784 return 0;
1785 }
1786
1787 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1788 static void serial_console_putchar(struct uart_port *port, int ch)
1789 {
1790 sci_poll_put_char(port, ch);
1791 }
1792
1793 /*
1794 * Print a string to the serial port trying not to disturb
1795 * any possible real use of the port...
1796 */
1797 static void serial_console_write(struct console *co, const char *s,
1798 unsigned count)
1799 {
1800 struct sci_port *sci_port = &sci_ports[co->index];
1801 struct uart_port *port = &sci_port->port;
1802 unsigned short bits;
1803
1804 if (sci_port->enable)
1805 sci_port->enable(port);
1806
1807 uart_console_write(port, s, count, serial_console_putchar);
1808
1809 /* wait until fifo is empty and last bit has been transmitted */
1810 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1811 while ((sci_in(port, SCxSR) & bits) != bits)
1812 cpu_relax();
1813
1814 if (sci_port->disable)
1815 sci_port->disable(port);
1816 }
1817
1818 static int __devinit serial_console_setup(struct console *co, char *options)
1819 {
1820 struct sci_port *sci_port;
1821 struct uart_port *port;
1822 int baud = 115200;
1823 int bits = 8;
1824 int parity = 'n';
1825 int flow = 'n';
1826 int ret;
1827
1828 /*
1829 * Refuse to handle any bogus ports.
1830 */
1831 if (co->index < 0 || co->index >= SCI_NPORTS)
1832 return -ENODEV;
1833
1834 sci_port = &sci_ports[co->index];
1835 port = &sci_port->port;
1836
1837 /*
1838 * Refuse to handle uninitialized ports.
1839 */
1840 if (!port->ops)
1841 return -ENODEV;
1842
1843 ret = sci_remap_port(port);
1844 if (unlikely(ret != 0))
1845 return ret;
1846
1847 if (sci_port->enable)
1848 sci_port->enable(port);
1849
1850 if (options)
1851 uart_parse_options(options, &baud, &parity, &bits, &flow);
1852
1853 ret = uart_set_options(port, co, baud, parity, bits, flow);
1854 #if defined(__H8300H__) || defined(__H8300S__)
1855 /* disable rx interrupt */
1856 if (ret == 0)
1857 sci_stop_rx(port);
1858 #endif
1859 /* TODO: disable clock */
1860 return ret;
1861 }
1862
1863 static struct console serial_console = {
1864 .name = "ttySC",
1865 .device = uart_console_device,
1866 .write = serial_console_write,
1867 .setup = serial_console_setup,
1868 .flags = CON_PRINTBUFFER,
1869 .index = -1,
1870 .data = &sci_uart_driver,
1871 };
1872
1873 static struct console early_serial_console = {
1874 .name = "early_ttySC",
1875 .write = serial_console_write,
1876 .flags = CON_PRINTBUFFER,
1877 .index = -1,
1878 };
1879
1880 static char early_serial_buf[32];
1881
1882 static int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
1883 {
1884 struct plat_sci_port *cfg = pdev->dev.platform_data;
1885
1886 if (early_serial_console.data)
1887 return -EEXIST;
1888
1889 early_serial_console.index = pdev->id;
1890
1891 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
1892
1893 serial_console_setup(&early_serial_console, early_serial_buf);
1894
1895 if (!strstr(early_serial_buf, "keep"))
1896 early_serial_console.flags |= CON_BOOT;
1897
1898 register_console(&early_serial_console);
1899 return 0;
1900 }
1901
1902 #define SCI_CONSOLE (&serial_console)
1903
1904 #else
1905 static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
1906 {
1907 return -EINVAL;
1908 }
1909
1910 #define SCI_CONSOLE NULL
1911
1912 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1913
1914 static char banner[] __initdata =
1915 KERN_INFO "SuperH SCI(F) driver initialized\n";
1916
1917 static struct uart_driver sci_uart_driver = {
1918 .owner = THIS_MODULE,
1919 .driver_name = "sci",
1920 .dev_name = "ttySC",
1921 .major = SCI_MAJOR,
1922 .minor = SCI_MINOR_START,
1923 .nr = SCI_NPORTS,
1924 .cons = SCI_CONSOLE,
1925 };
1926
1927 static int sci_remove(struct platform_device *dev)
1928 {
1929 struct sci_port *port = platform_get_drvdata(dev);
1930
1931 cpufreq_unregister_notifier(&port->freq_transition,
1932 CPUFREQ_TRANSITION_NOTIFIER);
1933
1934 uart_remove_one_port(&sci_uart_driver, &port->port);
1935
1936 clk_put(port->iclk);
1937 clk_put(port->fclk);
1938
1939 return 0;
1940 }
1941
1942 static int __devinit sci_probe_single(struct platform_device *dev,
1943 unsigned int index,
1944 struct plat_sci_port *p,
1945 struct sci_port *sciport)
1946 {
1947 int ret;
1948
1949 /* Sanity check */
1950 if (unlikely(index >= SCI_NPORTS)) {
1951 dev_notice(&dev->dev, "Attempting to register port "
1952 "%d when only %d are available.\n",
1953 index+1, SCI_NPORTS);
1954 dev_notice(&dev->dev, "Consider bumping "
1955 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1956 return 0;
1957 }
1958
1959 ret = sci_init_single(dev, sciport, index, p);
1960 if (ret)
1961 return ret;
1962
1963 return uart_add_one_port(&sci_uart_driver, &sciport->port);
1964 }
1965
1966 static int __devinit sci_probe(struct platform_device *dev)
1967 {
1968 struct plat_sci_port *p = dev->dev.platform_data;
1969 struct sci_port *sp = &sci_ports[dev->id];
1970 int ret;
1971
1972 /*
1973 * If we've come here via earlyprintk initialization, head off to
1974 * the special early probe. We don't have sufficient device state
1975 * to make it beyond this yet.
1976 */
1977 if (is_early_platform_device(dev))
1978 return sci_probe_earlyprintk(dev);
1979
1980 platform_set_drvdata(dev, sp);
1981
1982 ret = sci_probe_single(dev, dev->id, p, sp);
1983 if (ret)
1984 goto err_unreg;
1985
1986 sp->freq_transition.notifier_call = sci_notifier;
1987
1988 ret = cpufreq_register_notifier(&sp->freq_transition,
1989 CPUFREQ_TRANSITION_NOTIFIER);
1990 if (unlikely(ret < 0))
1991 goto err_unreg;
1992
1993 #ifdef CONFIG_SH_STANDARD_BIOS
1994 sh_bios_gdb_detach();
1995 #endif
1996
1997 return 0;
1998
1999 err_unreg:
2000 sci_remove(dev);
2001 return ret;
2002 }
2003
2004 static int sci_suspend(struct device *dev)
2005 {
2006 struct sci_port *sport = dev_get_drvdata(dev);
2007
2008 if (sport)
2009 uart_suspend_port(&sci_uart_driver, &sport->port);
2010
2011 return 0;
2012 }
2013
2014 static int sci_resume(struct device *dev)
2015 {
2016 struct sci_port *sport = dev_get_drvdata(dev);
2017
2018 if (sport)
2019 uart_resume_port(&sci_uart_driver, &sport->port);
2020
2021 return 0;
2022 }
2023
2024 static const struct dev_pm_ops sci_dev_pm_ops = {
2025 .suspend = sci_suspend,
2026 .resume = sci_resume,
2027 };
2028
2029 static struct platform_driver sci_driver = {
2030 .probe = sci_probe,
2031 .remove = sci_remove,
2032 .driver = {
2033 .name = "sh-sci",
2034 .owner = THIS_MODULE,
2035 .pm = &sci_dev_pm_ops,
2036 },
2037 };
2038
2039 static int __init sci_init(void)
2040 {
2041 int ret;
2042
2043 printk(banner);
2044
2045 ret = uart_register_driver(&sci_uart_driver);
2046 if (likely(ret == 0)) {
2047 ret = platform_driver_register(&sci_driver);
2048 if (unlikely(ret))
2049 uart_unregister_driver(&sci_uart_driver);
2050 }
2051
2052 return ret;
2053 }
2054
2055 static void __exit sci_exit(void)
2056 {
2057 platform_driver_unregister(&sci_driver);
2058 uart_unregister_driver(&sci_uart_driver);
2059 }
2060
2061 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2062 early_platform_init_buffer("earlyprintk", &sci_driver,
2063 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2064 #endif
2065 module_init(sci_init);
2066 module_exit(sci_exit);
2067
2068 MODULE_LICENSE("GPL");
2069 MODULE_ALIAS("platform:sh-sci");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree