?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
tty/serial: Add explicit PORT_TEGRA type
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / tty / serial / imx.c
blobdf6828654f48a32951cb6cdc3bb1b3f3e3712288
1 /*
2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
29
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #define SUPPORT_SYSRQ
32 #endif
33
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
48
49 #include <asm/io.h>
50 #include <asm/irq.h>
51 #include <mach/hardware.h>
52 #include <mach/imx-uart.h>
53
54 /* Register definitions */
55 #define URXD0 0x0 /* Receiver Register */
56 #define URTX0 0x40 /* Transmitter Register */
57 #define UCR1 0x80 /* Control Register 1 */
58 #define UCR2 0x84 /* Control Register 2 */
59 #define UCR3 0x88 /* Control Register 3 */
60 #define UCR4 0x8c /* Control Register 4 */
61 #define UFCR 0x90 /* FIFO Control Register */
62 #define USR1 0x94 /* Status Register 1 */
63 #define USR2 0x98 /* Status Register 2 */
64 #define UESC 0x9c /* Escape Character Register */
65 #define UTIM 0xa0 /* Escape Timer Register */
66 #define UBIR 0xa4 /* BRM Incremental Register */
67 #define UBMR 0xa8 /* BRM Modulator Register */
68 #define UBRC 0xac /* Baud Rate Count Register */
69 #define MX2_ONEMS 0xb0 /* One Millisecond register */
70 #define UTS (cpu_is_mx1() ? 0xd0 : 0xb4) /* UART Test Register */
71
72 /* UART Control Register Bit Fields.*/
73 #define URXD_CHARRDY (1<<15)
74 #define URXD_ERR (1<<14)
75 #define URXD_OVRRUN (1<<13)
76 #define URXD_FRMERR (1<<12)
77 #define URXD_BRK (1<<11)
78 #define URXD_PRERR (1<<10)
79 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
80 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
81 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
82 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
83 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
84 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
85 #define UCR1_IREN (1<<7) /* Infrared interface enable */
86 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
87 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
88 #define UCR1_SNDBRK (1<<4) /* Send break */
89 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
90 #define MX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, mx1 only */
91 #define UCR1_DOZE (1<<1) /* Doze */
92 #define UCR1_UARTEN (1<<0) /* UART enabled */
93 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
94 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
95 #define UCR2_CTSC (1<<13) /* CTS pin control */
96 #define UCR2_CTS (1<<12) /* Clear to send */
97 #define UCR2_ESCEN (1<<11) /* Escape enable */
98 #define UCR2_PREN (1<<8) /* Parity enable */
99 #define UCR2_PROE (1<<7) /* Parity odd/even */
100 #define UCR2_STPB (1<<6) /* Stop */
101 #define UCR2_WS (1<<5) /* Word size */
102 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
103 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
104 #define UCR2_RXEN (1<<1) /* Receiver enabled */
105 #define UCR2_SRST (1<<0) /* SW reset */
106 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
107 #define UCR3_PARERREN (1<<12) /* Parity enable */
108 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
109 #define UCR3_DSR (1<<10) /* Data set ready */
110 #define UCR3_DCD (1<<9) /* Data carrier detect */
111 #define UCR3_RI (1<<8) /* Ring indicator */
112 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
113 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
114 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
115 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
116 #define MX1_UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */
117 #define MX1_UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */
118 #define MX2_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */
119 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
120 #define UCR3_BPEN (1<<0) /* Preset registers enable */
121 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
122 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
123 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
124 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127 #define UCR4_IRSC (1<<5) /* IR special case */
128 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
132 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
134 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
135 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
136 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
137 #define USR1_RTSS (1<<14) /* RTS pin status */
138 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
139 #define USR1_RTSD (1<<12) /* RTS delta */
140 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
141 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
142 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
143 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
144 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
145 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
146 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
147 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
148 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
149 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
150 #define USR2_IDLE (1<<12) /* Idle condition */
151 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
152 #define USR2_WAKE (1<<7) /* Wake */
153 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
154 #define USR2_TXDC (1<<3) /* Transmitter complete */
155 #define USR2_BRCD (1<<2) /* Break condition */
156 #define USR2_ORE (1<<1) /* Overrun error */
157 #define USR2_RDR (1<<0) /* Recv data ready */
158 #define UTS_FRCPERR (1<<13) /* Force parity error */
159 #define UTS_LOOP (1<<12) /* Loop tx and rx */
160 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
161 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
162 #define UTS_TXFULL (1<<4) /* TxFIFO full */
163 #define UTS_RXFULL (1<<3) /* RxFIFO full */
164 #define UTS_SOFTRST (1<<0) /* Software reset */
165
166 /* We've been assigned a range on the "Low-density serial ports" major */
167 #define SERIAL_IMX_MAJOR 207
168 #define MINOR_START 16
169 #define DEV_NAME "ttymxc"
170 #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
171
172 /*
173 * This determines how often we check the modem status signals
174 * for any change. They generally aren't connected to an IRQ
175 * so we have to poll them. We also check immediately before
176 * filling the TX fifo incase CTS has been dropped.
177 */
178 #define MCTRL_TIMEOUT (250*HZ/1000)
179
180 #define DRIVER_NAME "IMX-uart"
181
182 #define UART_NR 8
183
184 struct imx_port {
185 struct uart_port port;
186 struct timer_list timer;
187 unsigned int old_status;
188 int txirq,rxirq,rtsirq;
189 unsigned int have_rtscts:1;
190 unsigned int use_irda:1;
191 unsigned int irda_inv_rx:1;
192 unsigned int irda_inv_tx:1;
193 unsigned short trcv_delay; /* transceiver delay */
194 struct clk *clk;
195 };
196
197 #ifdef CONFIG_IRDA
198 #define USE_IRDA(sport) ((sport)->use_irda)
199 #else
200 #define USE_IRDA(sport) (0)
201 #endif
202
203 /*
204 * Handle any change of modem status signal since we were last called.
205 */
206 static void imx_mctrl_check(struct imx_port *sport)
207 {
208 unsigned int status, changed;
209
210 status = sport->port.ops->get_mctrl(&sport->port);
211 changed = status ^ sport->old_status;
212
213 if (changed == 0)
214 return;
215
216 sport->old_status = status;
217
218 if (changed & TIOCM_RI)
219 sport->port.icount.rng++;
220 if (changed & TIOCM_DSR)
221 sport->port.icount.dsr++;
222 if (changed & TIOCM_CAR)
223 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
224 if (changed & TIOCM_CTS)
225 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
226
227 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
228 }
229
230 /*
231 * This is our per-port timeout handler, for checking the
232 * modem status signals.
233 */
234 static void imx_timeout(unsigned long data)
235 {
236 struct imx_port *sport = (struct imx_port *)data;
237 unsigned long flags;
238
239 if (sport->port.state) {
240 spin_lock_irqsave(&sport->port.lock, flags);
241 imx_mctrl_check(sport);
242 spin_unlock_irqrestore(&sport->port.lock, flags);
243
244 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
245 }
246 }
247
248 /*
249 * interrupts disabled on entry
250 */
251 static void imx_stop_tx(struct uart_port *port)
252 {
253 struct imx_port *sport = (struct imx_port *)port;
254 unsigned long temp;
255
256 if (USE_IRDA(sport)) {
257 /* half duplex - wait for end of transmission */
258 int n = 256;
259 while ((--n > 0) &&
260 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
261 udelay(5);
262 barrier();
263 }
264 /*
265 * irda transceiver - wait a bit more to avoid
266 * cutoff, hardware dependent
267 */
268 udelay(sport->trcv_delay);
269
270 /*
271 * half duplex - reactivate receive mode,
272 * flush receive pipe echo crap
273 */
274 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
275 temp = readl(sport->port.membase + UCR1);
276 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
277 writel(temp, sport->port.membase + UCR1);
278
279 temp = readl(sport->port.membase + UCR4);
280 temp &= ~(UCR4_TCEN);
281 writel(temp, sport->port.membase + UCR4);
282
283 while (readl(sport->port.membase + URXD0) &
284 URXD_CHARRDY)
285 barrier();
286
287 temp = readl(sport->port.membase + UCR1);
288 temp |= UCR1_RRDYEN;
289 writel(temp, sport->port.membase + UCR1);
290
291 temp = readl(sport->port.membase + UCR4);
292 temp |= UCR4_DREN;
293 writel(temp, sport->port.membase + UCR4);
294 }
295 return;
296 }
297
298 temp = readl(sport->port.membase + UCR1);
299 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
300 }
301
302 /*
303 * interrupts disabled on entry
304 */
305 static void imx_stop_rx(struct uart_port *port)
306 {
307 struct imx_port *sport = (struct imx_port *)port;
308 unsigned long temp;
309
310 temp = readl(sport->port.membase + UCR2);
311 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
312 }
313
314 /*
315 * Set the modem control timer to fire immediately.
316 */
317 static void imx_enable_ms(struct uart_port *port)
318 {
319 struct imx_port *sport = (struct imx_port *)port;
320
321 mod_timer(&sport->timer, jiffies);
322 }
323
324 static inline void imx_transmit_buffer(struct imx_port *sport)
325 {
326 struct circ_buf *xmit = &sport->port.state->xmit;
327
328 while (!uart_circ_empty(xmit) &&
329 !(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
330 /* send xmit->buf[xmit->tail]
331 * out the port here */
332 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
333 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
334 sport->port.icount.tx++;
335 }
336
337 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
338 uart_write_wakeup(&sport->port);
339
340 if (uart_circ_empty(xmit))
341 imx_stop_tx(&sport->port);
342 }
343
344 /*
345 * interrupts disabled on entry
346 */
347 static void imx_start_tx(struct uart_port *port)
348 {
349 struct imx_port *sport = (struct imx_port *)port;
350 unsigned long temp;
351
352 if (USE_IRDA(sport)) {
353 /* half duplex in IrDA mode; have to disable receive mode */
354 temp = readl(sport->port.membase + UCR4);
355 temp &= ~(UCR4_DREN);
356 writel(temp, sport->port.membase + UCR4);
357
358 temp = readl(sport->port.membase + UCR1);
359 temp &= ~(UCR1_RRDYEN);
360 writel(temp, sport->port.membase + UCR1);
361 }
362
363 temp = readl(sport->port.membase + UCR1);
364 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
365
366 if (USE_IRDA(sport)) {
367 temp = readl(sport->port.membase + UCR1);
368 temp |= UCR1_TRDYEN;
369 writel(temp, sport->port.membase + UCR1);
370
371 temp = readl(sport->port.membase + UCR4);
372 temp |= UCR4_TCEN;
373 writel(temp, sport->port.membase + UCR4);
374 }
375
376 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
377 imx_transmit_buffer(sport);
378 }
379
380 static irqreturn_t imx_rtsint(int irq, void *dev_id)
381 {
382 struct imx_port *sport = dev_id;
383 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
384 unsigned long flags;
385
386 spin_lock_irqsave(&sport->port.lock, flags);
387
388 writel(USR1_RTSD, sport->port.membase + USR1);
389 uart_handle_cts_change(&sport->port, !!val);
390 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
391
392 spin_unlock_irqrestore(&sport->port.lock, flags);
393 return IRQ_HANDLED;
394 }
395
396 static irqreturn_t imx_txint(int irq, void *dev_id)
397 {
398 struct imx_port *sport = dev_id;
399 struct circ_buf *xmit = &sport->port.state->xmit;
400 unsigned long flags;
401
402 spin_lock_irqsave(&sport->port.lock,flags);
403 if (sport->port.x_char)
404 {
405 /* Send next char */
406 writel(sport->port.x_char, sport->port.membase + URTX0);
407 goto out;
408 }
409
410 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
411 imx_stop_tx(&sport->port);
412 goto out;
413 }
414
415 imx_transmit_buffer(sport);
416
417 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
418 uart_write_wakeup(&sport->port);
419
420 out:
421 spin_unlock_irqrestore(&sport->port.lock,flags);
422 return IRQ_HANDLED;
423 }
424
425 static irqreturn_t imx_rxint(int irq, void *dev_id)
426 {
427 struct imx_port *sport = dev_id;
428 unsigned int rx,flg,ignored = 0;
429 struct tty_struct *tty = sport->port.state->port.tty;
430 unsigned long flags, temp;
431
432 spin_lock_irqsave(&sport->port.lock,flags);
433
434 while (readl(sport->port.membase + USR2) & USR2_RDR) {
435 flg = TTY_NORMAL;
436 sport->port.icount.rx++;
437
438 rx = readl(sport->port.membase + URXD0);
439
440 temp = readl(sport->port.membase + USR2);
441 if (temp & USR2_BRCD) {
442 writel(USR2_BRCD, sport->port.membase + USR2);
443 if (uart_handle_break(&sport->port))
444 continue;
445 }
446
447 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
448 continue;
449
450 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
451 if (rx & URXD_PRERR)
452 sport->port.icount.parity++;
453 else if (rx & URXD_FRMERR)
454 sport->port.icount.frame++;
455 if (rx & URXD_OVRRUN)
456 sport->port.icount.overrun++;
457
458 if (rx & sport->port.ignore_status_mask) {
459 if (++ignored > 100)
460 goto out;
461 continue;
462 }
463
464 rx &= sport->port.read_status_mask;
465
466 if (rx & URXD_PRERR)
467 flg = TTY_PARITY;
468 else if (rx & URXD_FRMERR)
469 flg = TTY_FRAME;
470 if (rx & URXD_OVRRUN)
471 flg = TTY_OVERRUN;
472
473 #ifdef SUPPORT_SYSRQ
474 sport->port.sysrq = 0;
475 #endif
476 }
477
478 tty_insert_flip_char(tty, rx, flg);
479 }
480
481 out:
482 spin_unlock_irqrestore(&sport->port.lock,flags);
483 tty_flip_buffer_push(tty);
484 return IRQ_HANDLED;
485 }
486
487 static irqreturn_t imx_int(int irq, void *dev_id)
488 {
489 struct imx_port *sport = dev_id;
490 unsigned int sts;
491
492 sts = readl(sport->port.membase + USR1);
493
494 if (sts & USR1_RRDY)
495 imx_rxint(irq, dev_id);
496
497 if (sts & USR1_TRDY &&
498 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
499 imx_txint(irq, dev_id);
500
501 if (sts & USR1_RTSD)
502 imx_rtsint(irq, dev_id);
503
504 return IRQ_HANDLED;
505 }
506
507 /*
508 * Return TIOCSER_TEMT when transmitter is not busy.
509 */
510 static unsigned int imx_tx_empty(struct uart_port *port)
511 {
512 struct imx_port *sport = (struct imx_port *)port;
513
514 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
515 }
516
517 /*
518 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
519 */
520 static unsigned int imx_get_mctrl(struct uart_port *port)
521 {
522 struct imx_port *sport = (struct imx_port *)port;
523 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
524
525 if (readl(sport->port.membase + USR1) & USR1_RTSS)
526 tmp |= TIOCM_CTS;
527
528 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
529 tmp |= TIOCM_RTS;
530
531 return tmp;
532 }
533
534 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
535 {
536 struct imx_port *sport = (struct imx_port *)port;
537 unsigned long temp;
538
539 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
540
541 if (mctrl & TIOCM_RTS)
542 temp |= UCR2_CTS;
543
544 writel(temp, sport->port.membase + UCR2);
545 }
546
547 /*
548 * Interrupts always disabled.
549 */
550 static void imx_break_ctl(struct uart_port *port, int break_state)
551 {
552 struct imx_port *sport = (struct imx_port *)port;
553 unsigned long flags, temp;
554
555 spin_lock_irqsave(&sport->port.lock, flags);
556
557 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
558
559 if ( break_state != 0 )
560 temp |= UCR1_SNDBRK;
561
562 writel(temp, sport->port.membase + UCR1);
563
564 spin_unlock_irqrestore(&sport->port.lock, flags);
565 }
566
567 #define TXTL 2 /* reset default */
568 #define RXTL 1 /* reset default */
569
570 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
571 {
572 unsigned int val;
573 unsigned int ufcr_rfdiv;
574
575 /* set receiver / transmitter trigger level.
576 * RFDIV is set such way to satisfy requested uartclk value
577 */
578 val = TXTL << 10 | RXTL;
579 ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2)
580 / sport->port.uartclk;
581
582 if(!ufcr_rfdiv)
583 ufcr_rfdiv = 1;
584
585 val |= UFCR_RFDIV_REG(ufcr_rfdiv);
586
587 writel(val, sport->port.membase + UFCR);
588
589 return 0;
590 }
591
592 /* half the RX buffer size */
593 #define CTSTL 16
594
595 static int imx_startup(struct uart_port *port)
596 {
597 struct imx_port *sport = (struct imx_port *)port;
598 int retval;
599 unsigned long flags, temp;
600
601 imx_setup_ufcr(sport, 0);
602
603 /* disable the DREN bit (Data Ready interrupt enable) before
604 * requesting IRQs
605 */
606 temp = readl(sport->port.membase + UCR4);
607
608 if (USE_IRDA(sport))
609 temp |= UCR4_IRSC;
610
611 /* set the trigger level for CTS */
612 temp &= ~(UCR4_CTSTL_MASK<< UCR4_CTSTL_SHF);
613 temp |= CTSTL<< UCR4_CTSTL_SHF;
614
615 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
616
617 if (USE_IRDA(sport)) {
618 /* reset fifo's and state machines */
619 int i = 100;
620 temp = readl(sport->port.membase + UCR2);
621 temp &= ~UCR2_SRST;
622 writel(temp, sport->port.membase + UCR2);
623 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
624 (--i > 0)) {
625 udelay(1);
626 }
627 }
628
629 /*
630 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
631 * chips only have one interrupt.
632 */
633 if (sport->txirq > 0) {
634 retval = request_irq(sport->rxirq, imx_rxint, 0,
635 DRIVER_NAME, sport);
636 if (retval)
637 goto error_out1;
638
639 retval = request_irq(sport->txirq, imx_txint, 0,
640 DRIVER_NAME, sport);
641 if (retval)
642 goto error_out2;
643
644 /* do not use RTS IRQ on IrDA */
645 if (!USE_IRDA(sport)) {
646 retval = request_irq(sport->rtsirq, imx_rtsint,
647 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
648 IRQF_TRIGGER_FALLING |
649 IRQF_TRIGGER_RISING,
650 DRIVER_NAME, sport);
651 if (retval)
652 goto error_out3;
653 }
654 } else {
655 retval = request_irq(sport->port.irq, imx_int, 0,
656 DRIVER_NAME, sport);
657 if (retval) {
658 free_irq(sport->port.irq, sport);
659 goto error_out1;
660 }
661 }
662
663 /*
664 * Finally, clear and enable interrupts
665 */
666 writel(USR1_RTSD, sport->port.membase + USR1);
667
668 temp = readl(sport->port.membase + UCR1);
669 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
670
671 if (USE_IRDA(sport)) {
672 temp |= UCR1_IREN;
673 temp &= ~(UCR1_RTSDEN);
674 }
675
676 writel(temp, sport->port.membase + UCR1);
677
678 temp = readl(sport->port.membase + UCR2);
679 temp |= (UCR2_RXEN | UCR2_TXEN);
680 writel(temp, sport->port.membase + UCR2);
681
682 if (USE_IRDA(sport)) {
683 /* clear RX-FIFO */
684 int i = 64;
685 while ((--i > 0) &&
686 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
687 barrier();
688 }
689 }
690
691 if (!cpu_is_mx1()) {
692 temp = readl(sport->port.membase + UCR3);
693 temp |= MX2_UCR3_RXDMUXSEL;
694 writel(temp, sport->port.membase + UCR3);
695 }
696
697 if (USE_IRDA(sport)) {
698 temp = readl(sport->port.membase + UCR4);
699 if (sport->irda_inv_rx)
700 temp |= UCR4_INVR;
701 else
702 temp &= ~(UCR4_INVR);
703 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
704
705 temp = readl(sport->port.membase + UCR3);
706 if (sport->irda_inv_tx)
707 temp |= UCR3_INVT;
708 else
709 temp &= ~(UCR3_INVT);
710 writel(temp, sport->port.membase + UCR3);
711 }
712
713 /*
714 * Enable modem status interrupts
715 */
716 spin_lock_irqsave(&sport->port.lock,flags);
717 imx_enable_ms(&sport->port);
718 spin_unlock_irqrestore(&sport->port.lock,flags);
719
720 if (USE_IRDA(sport)) {
721 struct imxuart_platform_data *pdata;
722 pdata = sport->port.dev->platform_data;
723 sport->irda_inv_rx = pdata->irda_inv_rx;
724 sport->irda_inv_tx = pdata->irda_inv_tx;
725 sport->trcv_delay = pdata->transceiver_delay;
726 if (pdata->irda_enable)
727 pdata->irda_enable(1);
728 }
729
730 return 0;
731
732 error_out3:
733 if (sport->txirq)
734 free_irq(sport->txirq, sport);
735 error_out2:
736 if (sport->rxirq)
737 free_irq(sport->rxirq, sport);
738 error_out1:
739 return retval;
740 }
741
742 static void imx_shutdown(struct uart_port *port)
743 {
744 struct imx_port *sport = (struct imx_port *)port;
745 unsigned long temp;
746
747 temp = readl(sport->port.membase + UCR2);
748 temp &= ~(UCR2_TXEN);
749 writel(temp, sport->port.membase + UCR2);
750
751 if (USE_IRDA(sport)) {
752 struct imxuart_platform_data *pdata;
753 pdata = sport->port.dev->platform_data;
754 if (pdata->irda_enable)
755 pdata->irda_enable(0);
756 }
757
758 /*
759 * Stop our timer.
760 */
761 del_timer_sync(&sport->timer);
762
763 /*
764 * Free the interrupts
765 */
766 if (sport->txirq > 0) {
767 if (!USE_IRDA(sport))
768 free_irq(sport->rtsirq, sport);
769 free_irq(sport->txirq, sport);
770 free_irq(sport->rxirq, sport);
771 } else
772 free_irq(sport->port.irq, sport);
773
774 /*
775 * Disable all interrupts, port and break condition.
776 */
777
778 temp = readl(sport->port.membase + UCR1);
779 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
780 if (USE_IRDA(sport))
781 temp &= ~(UCR1_IREN);
782
783 writel(temp, sport->port.membase + UCR1);
784 }
785
786 static void
787 imx_set_termios(struct uart_port *port, struct ktermios *termios,
788 struct ktermios *old)
789 {
790 struct imx_port *sport = (struct imx_port *)port;
791 unsigned long flags;
792 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
793 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
794 unsigned int div, ufcr;
795 unsigned long num, denom;
796 uint64_t tdiv64;
797
798 /*
799 * If we don't support modem control lines, don't allow
800 * these to be set.
801 */
802 if (0) {
803 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
804 termios->c_cflag |= CLOCAL;
805 }
806
807 /*
808 * We only support CS7 and CS8.
809 */
810 while ((termios->c_cflag & CSIZE) != CS7 &&
811 (termios->c_cflag & CSIZE) != CS8) {
812 termios->c_cflag &= ~CSIZE;
813 termios->c_cflag |= old_csize;
814 old_csize = CS8;
815 }
816
817 if ((termios->c_cflag & CSIZE) == CS8)
818 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
819 else
820 ucr2 = UCR2_SRST | UCR2_IRTS;
821
822 if (termios->c_cflag & CRTSCTS) {
823 if( sport->have_rtscts ) {
824 ucr2 &= ~UCR2_IRTS;
825 ucr2 |= UCR2_CTSC;
826 } else {
827 termios->c_cflag &= ~CRTSCTS;
828 }
829 }
830
831 if (termios->c_cflag & CSTOPB)
832 ucr2 |= UCR2_STPB;
833 if (termios->c_cflag & PARENB) {
834 ucr2 |= UCR2_PREN;
835 if (termios->c_cflag & PARODD)
836 ucr2 |= UCR2_PROE;
837 }
838
839 /*
840 * Ask the core to calculate the divisor for us.
841 */
842 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
843 quot = uart_get_divisor(port, baud);
844
845 spin_lock_irqsave(&sport->port.lock, flags);
846
847 sport->port.read_status_mask = 0;
848 if (termios->c_iflag & INPCK)
849 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
850 if (termios->c_iflag & (BRKINT | PARMRK))
851 sport->port.read_status_mask |= URXD_BRK;
852
853 /*
854 * Characters to ignore
855 */
856 sport->port.ignore_status_mask = 0;
857 if (termios->c_iflag & IGNPAR)
858 sport->port.ignore_status_mask |= URXD_PRERR;
859 if (termios->c_iflag & IGNBRK) {
860 sport->port.ignore_status_mask |= URXD_BRK;
861 /*
862 * If we're ignoring parity and break indicators,
863 * ignore overruns too (for real raw support).
864 */
865 if (termios->c_iflag & IGNPAR)
866 sport->port.ignore_status_mask |= URXD_OVRRUN;
867 }
868
869 del_timer_sync(&sport->timer);
870
871 /*
872 * Update the per-port timeout.
873 */
874 uart_update_timeout(port, termios->c_cflag, baud);
875
876 /*
877 * disable interrupts and drain transmitter
878 */
879 old_ucr1 = readl(sport->port.membase + UCR1);
880 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
881 sport->port.membase + UCR1);
882
883 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
884 barrier();
885
886 /* then, disable everything */
887 old_txrxen = readl(sport->port.membase + UCR2);
888 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
889 sport->port.membase + UCR2);
890 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
891
892 if (USE_IRDA(sport)) {
893 /*
894 * use maximum available submodule frequency to
895 * avoid missing short pulses due to low sampling rate
896 */
897 div = 1;
898 } else {
899 div = sport->port.uartclk / (baud * 16);
900 if (div > 7)
901 div = 7;
902 if (!div)
903 div = 1;
904 }
905
906 rational_best_approximation(16 * div * baud, sport->port.uartclk,
907 1 << 16, 1 << 16, &num, &denom);
908
909 tdiv64 = sport->port.uartclk;
910 tdiv64 *= num;
911 do_div(tdiv64, denom * 16 * div);
912 tty_termios_encode_baud_rate(termios,
913 (speed_t)tdiv64, (speed_t)tdiv64);
914
915 num -= 1;
916 denom -= 1;
917
918 ufcr = readl(sport->port.membase + UFCR);
919 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
920 writel(ufcr, sport->port.membase + UFCR);
921
922 writel(num, sport->port.membase + UBIR);
923 writel(denom, sport->port.membase + UBMR);
924
925 if (!cpu_is_mx1())
926 writel(sport->port.uartclk / div / 1000,
927 sport->port.membase + MX2_ONEMS);
928
929 writel(old_ucr1, sport->port.membase + UCR1);
930
931 /* set the parity, stop bits and data size */
932 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
933
934 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
935 imx_enable_ms(&sport->port);
936
937 spin_unlock_irqrestore(&sport->port.lock, flags);
938 }
939
940 static const char *imx_type(struct uart_port *port)
941 {
942 struct imx_port *sport = (struct imx_port *)port;
943
944 return sport->port.type == PORT_IMX ? "IMX" : NULL;
945 }
946
947 /*
948 * Release the memory region(s) being used by 'port'.
949 */
950 static void imx_release_port(struct uart_port *port)
951 {
952 struct platform_device *pdev = to_platform_device(port->dev);
953 struct resource *mmres;
954
955 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
956 release_mem_region(mmres->start, mmres->end - mmres->start + 1);
957 }
958
959 /*
960 * Request the memory region(s) being used by 'port'.
961 */
962 static int imx_request_port(struct uart_port *port)
963 {
964 struct platform_device *pdev = to_platform_device(port->dev);
965 struct resource *mmres;
966 void *ret;
967
968 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
969 if (!mmres)
970 return -ENODEV;
971
972 ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1,
973 "imx-uart");
974
975 return ret ? 0 : -EBUSY;
976 }
977
978 /*
979 * Configure/autoconfigure the port.
980 */
981 static void imx_config_port(struct uart_port *port, int flags)
982 {
983 struct imx_port *sport = (struct imx_port *)port;
984
985 if (flags & UART_CONFIG_TYPE &&
986 imx_request_port(&sport->port) == 0)
987 sport->port.type = PORT_IMX;
988 }
989
990 /*
991 * Verify the new serial_struct (for TIOCSSERIAL).
992 * The only change we allow are to the flags and type, and
993 * even then only between PORT_IMX and PORT_UNKNOWN
994 */
995 static int
996 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
997 {
998 struct imx_port *sport = (struct imx_port *)port;
999 int ret = 0;
1000
1001 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1002 ret = -EINVAL;
1003 if (sport->port.irq != ser->irq)
1004 ret = -EINVAL;
1005 if (ser->io_type != UPIO_MEM)
1006 ret = -EINVAL;
1007 if (sport->port.uartclk / 16 != ser->baud_base)
1008 ret = -EINVAL;
1009 if ((void *)sport->port.mapbase != ser->iomem_base)
1010 ret = -EINVAL;
1011 if (sport->port.iobase != ser->port)
1012 ret = -EINVAL;
1013 if (ser->hub6 != 0)
1014 ret = -EINVAL;
1015 return ret;
1016 }
1017
1018 static struct uart_ops imx_pops = {
1019 .tx_empty = imx_tx_empty,
1020 .set_mctrl = imx_set_mctrl,
1021 .get_mctrl = imx_get_mctrl,
1022 .stop_tx = imx_stop_tx,
1023 .start_tx = imx_start_tx,
1024 .stop_rx = imx_stop_rx,
1025 .enable_ms = imx_enable_ms,
1026 .break_ctl = imx_break_ctl,
1027 .startup = imx_startup,
1028 .shutdown = imx_shutdown,
1029 .set_termios = imx_set_termios,
1030 .type = imx_type,
1031 .release_port = imx_release_port,
1032 .request_port = imx_request_port,
1033 .config_port = imx_config_port,
1034 .verify_port = imx_verify_port,
1035 };
1036
1037 static struct imx_port *imx_ports[UART_NR];
1038
1039 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1040 static void imx_console_putchar(struct uart_port *port, int ch)
1041 {
1042 struct imx_port *sport = (struct imx_port *)port;
1043
1044 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
1045 barrier();
1046
1047 writel(ch, sport->port.membase + URTX0);
1048 }
1049
1050 /*
1051 * Interrupts are disabled on entering
1052 */
1053 static void
1054 imx_console_write(struct console *co, const char *s, unsigned int count)
1055 {
1056 struct imx_port *sport = imx_ports[co->index];
1057 unsigned int old_ucr1, old_ucr2, ucr1;
1058
1059 /*
1060 * First, save UCR1/2 and then disable interrupts
1061 */
1062 ucr1 = old_ucr1 = readl(sport->port.membase + UCR1);
1063 old_ucr2 = readl(sport->port.membase + UCR2);
1064
1065 if (cpu_is_mx1())
1066 ucr1 |= MX1_UCR1_UARTCLKEN;
1067 ucr1 |= UCR1_UARTEN;
1068 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1069
1070 writel(ucr1, sport->port.membase + UCR1);
1071
1072 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1073
1074 uart_console_write(&sport->port, s, count, imx_console_putchar);
1075
1076 /*
1077 * Finally, wait for transmitter to become empty
1078 * and restore UCR1/2
1079 */
1080 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1081
1082 writel(old_ucr1, sport->port.membase + UCR1);
1083 writel(old_ucr2, sport->port.membase + UCR2);
1084 }
1085
1086 /*
1087 * If the port was already initialised (eg, by a boot loader),
1088 * try to determine the current setup.
1089 */
1090 static void __init
1091 imx_console_get_options(struct imx_port *sport, int *baud,
1092 int *parity, int *bits)
1093 {
1094
1095 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1096 /* ok, the port was enabled */
1097 unsigned int ucr2, ubir,ubmr, uartclk;
1098 unsigned int baud_raw;
1099 unsigned int ucfr_rfdiv;
1100
1101 ucr2 = readl(sport->port.membase + UCR2);
1102
1103 *parity = 'n';
1104 if (ucr2 & UCR2_PREN) {
1105 if (ucr2 & UCR2_PROE)
1106 *parity = 'o';
1107 else
1108 *parity = 'e';
1109 }
1110
1111 if (ucr2 & UCR2_WS)
1112 *bits = 8;
1113 else
1114 *bits = 7;
1115
1116 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1117 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1118
1119 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1120 if (ucfr_rfdiv == 6)
1121 ucfr_rfdiv = 7;
1122 else
1123 ucfr_rfdiv = 6 - ucfr_rfdiv;
1124
1125 uartclk = clk_get_rate(sport->clk);
1126 uartclk /= ucfr_rfdiv;
1127
1128 { /*
1129 * The next code provides exact computation of
1130 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1131 * without need of float support or long long division,
1132 * which would be required to prevent 32bit arithmetic overflow
1133 */
1134 unsigned int mul = ubir + 1;
1135 unsigned int div = 16 * (ubmr + 1);
1136 unsigned int rem = uartclk % div;
1137
1138 baud_raw = (uartclk / div) * mul;
1139 baud_raw += (rem * mul + div / 2) / div;
1140 *baud = (baud_raw + 50) / 100 * 100;
1141 }
1142
1143 if(*baud != baud_raw)
1144 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1145 baud_raw, *baud);
1146 }
1147 }
1148
1149 static int __init
1150 imx_console_setup(struct console *co, char *options)
1151 {
1152 struct imx_port *sport;
1153 int baud = 9600;
1154 int bits = 8;
1155 int parity = 'n';
1156 int flow = 'n';
1157
1158 /*
1159 * Check whether an invalid uart number has been specified, and
1160 * if so, search for the first available port that does have
1161 * console support.
1162 */
1163 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1164 co->index = 0;
1165 sport = imx_ports[co->index];
1166 if(sport == NULL)
1167 return -ENODEV;
1168
1169 if (options)
1170 uart_parse_options(options, &baud, &parity, &bits, &flow);
1171 else
1172 imx_console_get_options(sport, &baud, &parity, &bits);
1173
1174 imx_setup_ufcr(sport, 0);
1175
1176 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1177 }
1178
1179 static struct uart_driver imx_reg;
1180 static struct console imx_console = {
1181 .name = DEV_NAME,
1182 .write = imx_console_write,
1183 .device = uart_console_device,
1184 .setup = imx_console_setup,
1185 .flags = CON_PRINTBUFFER,
1186 .index = -1,
1187 .data = &imx_reg,
1188 };
1189
1190 #define IMX_CONSOLE &imx_console
1191 #else
1192 #define IMX_CONSOLE NULL
1193 #endif
1194
1195 static struct uart_driver imx_reg = {
1196 .owner = THIS_MODULE,
1197 .driver_name = DRIVER_NAME,
1198 .dev_name = DEV_NAME,
1199 .major = SERIAL_IMX_MAJOR,
1200 .minor = MINOR_START,
1201 .nr = ARRAY_SIZE(imx_ports),
1202 .cons = IMX_CONSOLE,
1203 };
1204
1205 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1206 {
1207 struct imx_port *sport = platform_get_drvdata(dev);
1208
1209 if (sport)
1210 uart_suspend_port(&imx_reg, &sport->port);
1211
1212 return 0;
1213 }
1214
1215 static int serial_imx_resume(struct platform_device *dev)
1216 {
1217 struct imx_port *sport = platform_get_drvdata(dev);
1218
1219 if (sport)
1220 uart_resume_port(&imx_reg, &sport->port);
1221
1222 return 0;
1223 }
1224
1225 static int serial_imx_probe(struct platform_device *pdev)
1226 {
1227 struct imx_port *sport;
1228 struct imxuart_platform_data *pdata;
1229 void __iomem *base;
1230 int ret = 0;
1231 struct resource *res;
1232
1233 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1234 if (!sport)
1235 return -ENOMEM;
1236
1237 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1238 if (!res) {
1239 ret = -ENODEV;
1240 goto free;
1241 }
1242
1243 base = ioremap(res->start, PAGE_SIZE);
1244 if (!base) {
1245 ret = -ENOMEM;
1246 goto free;
1247 }
1248
1249 sport->port.dev = &pdev->dev;
1250 sport->port.mapbase = res->start;
1251 sport->port.membase = base;
1252 sport->port.type = PORT_IMX,
1253 sport->port.iotype = UPIO_MEM;
1254 sport->port.irq = platform_get_irq(pdev, 0);
1255 sport->rxirq = platform_get_irq(pdev, 0);
1256 sport->txirq = platform_get_irq(pdev, 1);
1257 sport->rtsirq = platform_get_irq(pdev, 2);
1258 sport->port.fifosize = 32;
1259 sport->port.ops = &imx_pops;
1260 sport->port.flags = UPF_BOOT_AUTOCONF;
1261 sport->port.line = pdev->id;
1262 init_timer(&sport->timer);
1263 sport->timer.function = imx_timeout;
1264 sport->timer.data = (unsigned long)sport;
1265
1266 sport->clk = clk_get(&pdev->dev, "uart");
1267 if (IS_ERR(sport->clk)) {
1268 ret = PTR_ERR(sport->clk);
1269 goto unmap;
1270 }
1271 clk_enable(sport->clk);
1272
1273 sport->port.uartclk = clk_get_rate(sport->clk);
1274
1275 imx_ports[pdev->id] = sport;
1276
1277 pdata = pdev->dev.platform_data;
1278 if (pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1279 sport->have_rtscts = 1;
1280
1281 #ifdef CONFIG_IRDA
1282 if (pdata && (pdata->flags & IMXUART_IRDA))
1283 sport->use_irda = 1;
1284 #endif
1285
1286 if (pdata && pdata->init) {
1287 ret = pdata->init(pdev);
1288 if (ret)
1289 goto clkput;
1290 }
1291
1292 ret = uart_add_one_port(&imx_reg, &sport->port);
1293 if (ret)
1294 goto deinit;
1295 platform_set_drvdata(pdev, &sport->port);
1296
1297 return 0;
1298 deinit:
1299 if (pdata && pdata->exit)
1300 pdata->exit(pdev);
1301 clkput:
1302 clk_put(sport->clk);
1303 clk_disable(sport->clk);
1304 unmap:
1305 iounmap(sport->port.membase);
1306 free:
1307 kfree(sport);
1308
1309 return ret;
1310 }
1311
1312 static int serial_imx_remove(struct platform_device *pdev)
1313 {
1314 struct imxuart_platform_data *pdata;
1315 struct imx_port *sport = platform_get_drvdata(pdev);
1316
1317 pdata = pdev->dev.platform_data;
1318
1319 platform_set_drvdata(pdev, NULL);
1320
1321 if (sport) {
1322 uart_remove_one_port(&imx_reg, &sport->port);
1323 clk_put(sport->clk);
1324 }
1325
1326 clk_disable(sport->clk);
1327
1328 if (pdata && pdata->exit)
1329 pdata->exit(pdev);
1330
1331 iounmap(sport->port.membase);
1332 kfree(sport);
1333
1334 return 0;
1335 }
1336
1337 static struct platform_driver serial_imx_driver = {
1338 .probe = serial_imx_probe,
1339 .remove = serial_imx_remove,
1340
1341 .suspend = serial_imx_suspend,
1342 .resume = serial_imx_resume,
1343 .driver = {
1344 .name = "imx-uart",
1345 .owner = THIS_MODULE,
1346 },
1347 };
1348
1349 static int __init imx_serial_init(void)
1350 {
1351 int ret;
1352
1353 printk(KERN_INFO "Serial: IMX driver\n");
1354
1355 ret = uart_register_driver(&imx_reg);
1356 if (ret)
1357 return ret;
1358
1359 ret = platform_driver_register(&serial_imx_driver);
1360 if (ret != 0)
1361 uart_unregister_driver(&imx_reg);
1362
1363 return 0;
1364 }
1365
1366 static void __exit imx_serial_exit(void)
1367 {
1368 platform_driver_unregister(&serial_imx_driver);
1369 uart_unregister_driver(&imx_reg);
1370 }
1371
1372 module_init(imx_serial_init);
1373 module_exit(imx_serial_exit);
1374
1375 MODULE_AUTHOR("Sascha Hauer");
1376 MODULE_DESCRIPTION("IMX generic serial port driver");
1377 MODULE_LICENSE("GPL");
1378 MODULE_ALIAS("platform:imx-uart");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree