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tty/serial: Add explicit PORT_TEGRA type
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / tty / serial / amba-pl011.c
blob8dc0541feecc18c2c185cead4394f5357d25eee1
1 /*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
31
32 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33 #define SUPPORT_SYSRQ
34 #endif
35
36 #include <linux/module.h>
37 #include <linux/ioport.h>
38 #include <linux/init.h>
39 #include <linux/console.h>
40 #include <linux/sysrq.h>
41 #include <linux/device.h>
42 #include <linux/tty.h>
43 #include <linux/tty_flip.h>
44 #include <linux/serial_core.h>
45 #include <linux/serial.h>
46 #include <linux/amba/bus.h>
47 #include <linux/amba/serial.h>
48 #include <linux/clk.h>
49 #include <linux/slab.h>
50 #include <linux/dmaengine.h>
51 #include <linux/dma-mapping.h>
52 #include <linux/scatterlist.h>
53
54 #include <asm/io.h>
55 #include <asm/sizes.h>
56
57 #define UART_NR 14
58
59 #define SERIAL_AMBA_MAJOR 204
60 #define SERIAL_AMBA_MINOR 64
61 #define SERIAL_AMBA_NR UART_NR
62
63 #define AMBA_ISR_PASS_LIMIT 256
64
65 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
66 #define UART_DUMMY_DR_RX (1 << 16)
67
68 /* There is by now at least one vendor with differing details, so handle it */
69 struct vendor_data {
70 unsigned int ifls;
71 unsigned int fifosize;
72 unsigned int lcrh_tx;
73 unsigned int lcrh_rx;
74 bool oversampling;
75 bool dma_threshold;
76 };
77
78 static struct vendor_data vendor_arm = {
79 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
80 .fifosize = 16,
81 .lcrh_tx = UART011_LCRH,
82 .lcrh_rx = UART011_LCRH,
83 .oversampling = false,
84 .dma_threshold = false,
85 };
86
87 static struct vendor_data vendor_st = {
88 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
89 .fifosize = 64,
90 .lcrh_tx = ST_UART011_LCRH_TX,
91 .lcrh_rx = ST_UART011_LCRH_RX,
92 .oversampling = true,
93 .dma_threshold = true,
94 };
95
96 /* Deals with DMA transactions */
97
98 struct pl011_sgbuf {
99 struct scatterlist sg;
100 char *buf;
101 };
102
103 struct pl011_dmarx_data {
104 struct dma_chan *chan;
105 struct completion complete;
106 bool use_buf_b;
107 struct pl011_sgbuf sgbuf_a;
108 struct pl011_sgbuf sgbuf_b;
109 dma_cookie_t cookie;
110 bool running;
111 };
112
113 struct pl011_dmatx_data {
114 struct dma_chan *chan;
115 struct scatterlist sg;
116 char *buf;
117 bool queued;
118 };
119
120 /*
121 * We wrap our port structure around the generic uart_port.
122 */
123 struct uart_amba_port {
124 struct uart_port port;
125 struct clk *clk;
126 const struct vendor_data *vendor;
127 unsigned int dmacr; /* dma control reg */
128 unsigned int im; /* interrupt mask */
129 unsigned int old_status;
130 unsigned int fifosize; /* vendor-specific */
131 unsigned int lcrh_tx; /* vendor-specific */
132 unsigned int lcrh_rx; /* vendor-specific */
133 bool autorts;
134 char type[12];
135 #ifdef CONFIG_DMA_ENGINE
136 /* DMA stuff */
137 bool using_tx_dma;
138 bool using_rx_dma;
139 struct pl011_dmarx_data dmarx;
140 struct pl011_dmatx_data dmatx;
141 #endif
142 };
143
144 /*
145 * Reads up to 256 characters from the FIFO or until it's empty and
146 * inserts them into the TTY layer. Returns the number of characters
147 * read from the FIFO.
148 */
149 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
150 {
151 u16 status, ch;
152 unsigned int flag, max_count = 256;
153 int fifotaken = 0;
154
155 while (max_count--) {
156 status = readw(uap->port.membase + UART01x_FR);
157 if (status & UART01x_FR_RXFE)
158 break;
159
160 /* Take chars from the FIFO and update status */
161 ch = readw(uap->port.membase + UART01x_DR) |
162 UART_DUMMY_DR_RX;
163 flag = TTY_NORMAL;
164 uap->port.icount.rx++;
165 fifotaken++;
166
167 if (unlikely(ch & UART_DR_ERROR)) {
168 if (ch & UART011_DR_BE) {
169 ch &= ~(UART011_DR_FE | UART011_DR_PE);
170 uap->port.icount.brk++;
171 if (uart_handle_break(&uap->port))
172 continue;
173 } else if (ch & UART011_DR_PE)
174 uap->port.icount.parity++;
175 else if (ch & UART011_DR_FE)
176 uap->port.icount.frame++;
177 if (ch & UART011_DR_OE)
178 uap->port.icount.overrun++;
179
180 ch &= uap->port.read_status_mask;
181
182 if (ch & UART011_DR_BE)
183 flag = TTY_BREAK;
184 else if (ch & UART011_DR_PE)
185 flag = TTY_PARITY;
186 else if (ch & UART011_DR_FE)
187 flag = TTY_FRAME;
188 }
189
190 if (uart_handle_sysrq_char(&uap->port, ch & 255))
191 continue;
192
193 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
194 }
195
196 return fifotaken;
197 }
198
199
200 /*
201 * All the DMA operation mode stuff goes inside this ifdef.
202 * This assumes that you have a generic DMA device interface,
203 * no custom DMA interfaces are supported.
204 */
205 #ifdef CONFIG_DMA_ENGINE
206
207 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
208
209 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
210 enum dma_data_direction dir)
211 {
212 sg->buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
213 if (!sg->buf)
214 return -ENOMEM;
215
216 sg_init_one(&sg->sg, sg->buf, PL011_DMA_BUFFER_SIZE);
217
218 if (dma_map_sg(chan->device->dev, &sg->sg, 1, dir) != 1) {
219 kfree(sg->buf);
220 return -EINVAL;
221 }
222 return 0;
223 }
224
225 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
226 enum dma_data_direction dir)
227 {
228 if (sg->buf) {
229 dma_unmap_sg(chan->device->dev, &sg->sg, 1, dir);
230 kfree(sg->buf);
231 }
232 }
233
234 static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
235 {
236 /* DMA is the sole user of the platform data right now */
237 struct amba_pl011_data *plat = uap->port.dev->platform_data;
238 struct dma_slave_config tx_conf = {
239 .dst_addr = uap->port.mapbase + UART01x_DR,
240 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
241 .direction = DMA_TO_DEVICE,
242 .dst_maxburst = uap->fifosize >> 1,
243 };
244 struct dma_chan *chan;
245 dma_cap_mask_t mask;
246
247 /* We need platform data */
248 if (!plat || !plat->dma_filter) {
249 dev_info(uap->port.dev, "no DMA platform data\n");
250 return;
251 }
252
253 /* Try to acquire a generic DMA engine slave TX channel */
254 dma_cap_zero(mask);
255 dma_cap_set(DMA_SLAVE, mask);
256
257 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param);
258 if (!chan) {
259 dev_err(uap->port.dev, "no TX DMA channel!\n");
260 return;
261 }
262
263 dmaengine_slave_config(chan, &tx_conf);
264 uap->dmatx.chan = chan;
265
266 dev_info(uap->port.dev, "DMA channel TX %s\n",
267 dma_chan_name(uap->dmatx.chan));
268
269 /* Optionally make use of an RX channel as well */
270 if (plat->dma_rx_param) {
271 struct dma_slave_config rx_conf = {
272 .src_addr = uap->port.mapbase + UART01x_DR,
273 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
274 .direction = DMA_FROM_DEVICE,
275 .src_maxburst = uap->fifosize >> 1,
276 };
277
278 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
279 if (!chan) {
280 dev_err(uap->port.dev, "no RX DMA channel!\n");
281 return;
282 }
283
284 dmaengine_slave_config(chan, &rx_conf);
285 uap->dmarx.chan = chan;
286
287 dev_info(uap->port.dev, "DMA channel RX %s\n",
288 dma_chan_name(uap->dmarx.chan));
289 }
290 }
291
292 #ifndef MODULE
293 /*
294 * Stack up the UARTs and let the above initcall be done at device
295 * initcall time, because the serial driver is called as an arch
296 * initcall, and at this time the DMA subsystem is not yet registered.
297 * At this point the driver will switch over to using DMA where desired.
298 */
299 struct dma_uap {
300 struct list_head node;
301 struct uart_amba_port *uap;
302 };
303
304 static LIST_HEAD(pl011_dma_uarts);
305
306 static int __init pl011_dma_initcall(void)
307 {
308 struct list_head *node, *tmp;
309
310 list_for_each_safe(node, tmp, &pl011_dma_uarts) {
311 struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
312 pl011_dma_probe_initcall(dmau->uap);
313 list_del(node);
314 kfree(dmau);
315 }
316 return 0;
317 }
318
319 device_initcall(pl011_dma_initcall);
320
321 static void pl011_dma_probe(struct uart_amba_port *uap)
322 {
323 struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
324 if (dmau) {
325 dmau->uap = uap;
326 list_add_tail(&dmau->node, &pl011_dma_uarts);
327 }
328 }
329 #else
330 static void pl011_dma_probe(struct uart_amba_port *uap)
331 {
332 pl011_dma_probe_initcall(uap);
333 }
334 #endif
335
336 static void pl011_dma_remove(struct uart_amba_port *uap)
337 {
338 /* TODO: remove the initcall if it has not yet executed */
339 if (uap->dmatx.chan)
340 dma_release_channel(uap->dmatx.chan);
341 if (uap->dmarx.chan)
342 dma_release_channel(uap->dmarx.chan);
343 }
344
345 /* Forward declare this for the refill routine */
346 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
347
348 /*
349 * The current DMA TX buffer has been sent.
350 * Try to queue up another DMA buffer.
351 */
352 static void pl011_dma_tx_callback(void *data)
353 {
354 struct uart_amba_port *uap = data;
355 struct pl011_dmatx_data *dmatx = &uap->dmatx;
356 unsigned long flags;
357 u16 dmacr;
358
359 spin_lock_irqsave(&uap->port.lock, flags);
360 if (uap->dmatx.queued)
361 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
362 DMA_TO_DEVICE);
363
364 dmacr = uap->dmacr;
365 uap->dmacr = dmacr & ~UART011_TXDMAE;
366 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
367
368 /*
369 * If TX DMA was disabled, it means that we've stopped the DMA for
370 * some reason (eg, XOFF received, or we want to send an X-char.)
371 *
372 * Note: we need to be careful here of a potential race between DMA
373 * and the rest of the driver - if the driver disables TX DMA while
374 * a TX buffer completing, we must update the tx queued status to
375 * get further refills (hence we check dmacr).
376 */
377 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
378 uart_circ_empty(&uap->port.state->xmit)) {
379 uap->dmatx.queued = false;
380 spin_unlock_irqrestore(&uap->port.lock, flags);
381 return;
382 }
383
384 if (pl011_dma_tx_refill(uap) <= 0) {
385 /*
386 * We didn't queue a DMA buffer for some reason, but we
387 * have data pending to be sent. Re-enable the TX IRQ.
388 */
389 uap->im |= UART011_TXIM;
390 writew(uap->im, uap->port.membase + UART011_IMSC);
391 }
392 spin_unlock_irqrestore(&uap->port.lock, flags);
393 }
394
395 /*
396 * Try to refill the TX DMA buffer.
397 * Locking: called with port lock held and IRQs disabled.
398 * Returns:
399 * 1 if we queued up a TX DMA buffer.
400 * 0 if we didn't want to handle this by DMA
401 * <0 on error
402 */
403 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
404 {
405 struct pl011_dmatx_data *dmatx = &uap->dmatx;
406 struct dma_chan *chan = dmatx->chan;
407 struct dma_device *dma_dev = chan->device;
408 struct dma_async_tx_descriptor *desc;
409 struct circ_buf *xmit = &uap->port.state->xmit;
410 unsigned int count;
411
412 /*
413 * Try to avoid the overhead involved in using DMA if the
414 * transaction fits in the first half of the FIFO, by using
415 * the standard interrupt handling. This ensures that we
416 * issue a uart_write_wakeup() at the appropriate time.
417 */
418 count = uart_circ_chars_pending(xmit);
419 if (count < (uap->fifosize >> 1)) {
420 uap->dmatx.queued = false;
421 return 0;
422 }
423
424 /*
425 * Bodge: don't send the last character by DMA, as this
426 * will prevent XON from notifying us to restart DMA.
427 */
428 count -= 1;
429
430 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
431 if (count > PL011_DMA_BUFFER_SIZE)
432 count = PL011_DMA_BUFFER_SIZE;
433
434 if (xmit->tail < xmit->head)
435 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
436 else {
437 size_t first = UART_XMIT_SIZE - xmit->tail;
438 size_t second = xmit->head;
439
440 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
441 if (second)
442 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
443 }
444
445 dmatx->sg.length = count;
446
447 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
448 uap->dmatx.queued = false;
449 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
450 return -EBUSY;
451 }
452
453 desc = dma_dev->device_prep_slave_sg(chan, &dmatx->sg, 1, DMA_TO_DEVICE,
454 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
455 if (!desc) {
456 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
457 uap->dmatx.queued = false;
458 /*
459 * If DMA cannot be used right now, we complete this
460 * transaction via IRQ and let the TTY layer retry.
461 */
462 dev_dbg(uap->port.dev, "TX DMA busy\n");
463 return -EBUSY;
464 }
465
466 /* Some data to go along to the callback */
467 desc->callback = pl011_dma_tx_callback;
468 desc->callback_param = uap;
469
470 /* All errors should happen at prepare time */
471 dmaengine_submit(desc);
472
473 /* Fire the DMA transaction */
474 dma_dev->device_issue_pending(chan);
475
476 uap->dmacr |= UART011_TXDMAE;
477 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
478 uap->dmatx.queued = true;
479
480 /*
481 * Now we know that DMA will fire, so advance the ring buffer
482 * with the stuff we just dispatched.
483 */
484 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
485 uap->port.icount.tx += count;
486
487 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
488 uart_write_wakeup(&uap->port);
489
490 return 1;
491 }
492
493 /*
494 * We received a transmit interrupt without a pending X-char but with
495 * pending characters.
496 * Locking: called with port lock held and IRQs disabled.
497 * Returns:
498 * false if we want to use PIO to transmit
499 * true if we queued a DMA buffer
500 */
501 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
502 {
503 if (!uap->using_tx_dma)
504 return false;
505
506 /*
507 * If we already have a TX buffer queued, but received a
508 * TX interrupt, it will be because we've just sent an X-char.
509 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
510 */
511 if (uap->dmatx.queued) {
512 uap->dmacr |= UART011_TXDMAE;
513 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
514 uap->im &= ~UART011_TXIM;
515 writew(uap->im, uap->port.membase + UART011_IMSC);
516 return true;
517 }
518
519 /*
520 * We don't have a TX buffer queued, so try to queue one.
521 * If we successfully queued a buffer, mask the TX IRQ.
522 */
523 if (pl011_dma_tx_refill(uap) > 0) {
524 uap->im &= ~UART011_TXIM;
525 writew(uap->im, uap->port.membase + UART011_IMSC);
526 return true;
527 }
528 return false;
529 }
530
531 /*
532 * Stop the DMA transmit (eg, due to received XOFF).
533 * Locking: called with port lock held and IRQs disabled.
534 */
535 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
536 {
537 if (uap->dmatx.queued) {
538 uap->dmacr &= ~UART011_TXDMAE;
539 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
540 }
541 }
542
543 /*
544 * Try to start a DMA transmit, or in the case of an XON/OFF
545 * character queued for send, try to get that character out ASAP.
546 * Locking: called with port lock held and IRQs disabled.
547 * Returns:
548 * false if we want the TX IRQ to be enabled
549 * true if we have a buffer queued
550 */
551 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
552 {
553 u16 dmacr;
554
555 if (!uap->using_tx_dma)
556 return false;
557
558 if (!uap->port.x_char) {
559 /* no X-char, try to push chars out in DMA mode */
560 bool ret = true;
561
562 if (!uap->dmatx.queued) {
563 if (pl011_dma_tx_refill(uap) > 0) {
564 uap->im &= ~UART011_TXIM;
565 ret = true;
566 } else {
567 uap->im |= UART011_TXIM;
568 ret = false;
569 }
570 writew(uap->im, uap->port.membase + UART011_IMSC);
571 } else if (!(uap->dmacr & UART011_TXDMAE)) {
572 uap->dmacr |= UART011_TXDMAE;
573 writew(uap->dmacr,
574 uap->port.membase + UART011_DMACR);
575 }
576 return ret;
577 }
578
579 /*
580 * We have an X-char to send. Disable DMA to prevent it loading
581 * the TX fifo, and then see if we can stuff it into the FIFO.
582 */
583 dmacr = uap->dmacr;
584 uap->dmacr &= ~UART011_TXDMAE;
585 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
586
587 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
588 /*
589 * No space in the FIFO, so enable the transmit interrupt
590 * so we know when there is space. Note that once we've
591 * loaded the character, we should just re-enable DMA.
592 */
593 return false;
594 }
595
596 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
597 uap->port.icount.tx++;
598 uap->port.x_char = 0;
599
600 /* Success - restore the DMA state */
601 uap->dmacr = dmacr;
602 writew(dmacr, uap->port.membase + UART011_DMACR);
603
604 return true;
605 }
606
607 /*
608 * Flush the transmit buffer.
609 * Locking: called with port lock held and IRQs disabled.
610 */
611 static void pl011_dma_flush_buffer(struct uart_port *port)
612 {
613 struct uart_amba_port *uap = (struct uart_amba_port *)port;
614
615 if (!uap->using_tx_dma)
616 return;
617
618 /* Avoid deadlock with the DMA engine callback */
619 spin_unlock(&uap->port.lock);
620 dmaengine_terminate_all(uap->dmatx.chan);
621 spin_lock(&uap->port.lock);
622 if (uap->dmatx.queued) {
623 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
624 DMA_TO_DEVICE);
625 uap->dmatx.queued = false;
626 uap->dmacr &= ~UART011_TXDMAE;
627 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
628 }
629 }
630
631 static void pl011_dma_rx_callback(void *data);
632
633 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
634 {
635 struct dma_chan *rxchan = uap->dmarx.chan;
636 struct dma_device *dma_dev;
637 struct pl011_dmarx_data *dmarx = &uap->dmarx;
638 struct dma_async_tx_descriptor *desc;
639 struct pl011_sgbuf *sgbuf;
640
641 if (!rxchan)
642 return -EIO;
643
644 /* Start the RX DMA job */
645 sgbuf = uap->dmarx.use_buf_b ?
646 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
647 dma_dev = rxchan->device;
648 desc = rxchan->device->device_prep_slave_sg(rxchan, &sgbuf->sg, 1,
649 DMA_FROM_DEVICE,
650 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
651 /*
652 * If the DMA engine is busy and cannot prepare a
653 * channel, no big deal, the driver will fall back
654 * to interrupt mode as a result of this error code.
655 */
656 if (!desc) {
657 uap->dmarx.running = false;
658 dmaengine_terminate_all(rxchan);
659 return -EBUSY;
660 }
661
662 /* Some data to go along to the callback */
663 desc->callback = pl011_dma_rx_callback;
664 desc->callback_param = uap;
665 dmarx->cookie = dmaengine_submit(desc);
666 dma_async_issue_pending(rxchan);
667
668 uap->dmacr |= UART011_RXDMAE;
669 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
670 uap->dmarx.running = true;
671
672 uap->im &= ~UART011_RXIM;
673 writew(uap->im, uap->port.membase + UART011_IMSC);
674
675 return 0;
676 }
677
678 /*
679 * This is called when either the DMA job is complete, or
680 * the FIFO timeout interrupt occurred. This must be called
681 * with the port spinlock uap->port.lock held.
682 */
683 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
684 u32 pending, bool use_buf_b,
685 bool readfifo)
686 {
687 struct tty_struct *tty = uap->port.state->port.tty;
688 struct pl011_sgbuf *sgbuf = use_buf_b ?
689 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
690 struct device *dev = uap->dmarx.chan->device->dev;
691 int dma_count = 0;
692 u32 fifotaken = 0; /* only used for vdbg() */
693
694 /* Pick everything from the DMA first */
695 if (pending) {
696 /* Sync in buffer */
697 dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
698
699 /*
700 * First take all chars in the DMA pipe, then look in the FIFO.
701 * Note that tty_insert_flip_buf() tries to take as many chars
702 * as it can.
703 */
704 dma_count = tty_insert_flip_string(uap->port.state->port.tty,
705 sgbuf->buf, pending);
706
707 /* Return buffer to device */
708 dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
709
710 uap->port.icount.rx += dma_count;
711 if (dma_count < pending)
712 dev_warn(uap->port.dev,
713 "couldn't insert all characters (TTY is full?)\n");
714 }
715
716 /*
717 * Only continue with trying to read the FIFO if all DMA chars have
718 * been taken first.
719 */
720 if (dma_count == pending && readfifo) {
721 /* Clear any error flags */
722 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
723 uap->port.membase + UART011_ICR);
724
725 /*
726 * If we read all the DMA'd characters, and we had an
727 * incomplete buffer, that could be due to an rx error, or
728 * maybe we just timed out. Read any pending chars and check
729 * the error status.
730 *
731 * Error conditions will only occur in the FIFO, these will
732 * trigger an immediate interrupt and stop the DMA job, so we
733 * will always find the error in the FIFO, never in the DMA
734 * buffer.
735 */
736 fifotaken = pl011_fifo_to_tty(uap);
737 }
738
739 spin_unlock(&uap->port.lock);
740 dev_vdbg(uap->port.dev,
741 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
742 dma_count, fifotaken);
743 tty_flip_buffer_push(tty);
744 spin_lock(&uap->port.lock);
745 }
746
747 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
748 {
749 struct pl011_dmarx_data *dmarx = &uap->dmarx;
750 struct dma_chan *rxchan = dmarx->chan;
751 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
752 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
753 size_t pending;
754 struct dma_tx_state state;
755 enum dma_status dmastat;
756
757 /*
758 * Pause the transfer so we can trust the current counter,
759 * do this before we pause the PL011 block, else we may
760 * overflow the FIFO.
761 */
762 if (dmaengine_pause(rxchan))
763 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
764 dmastat = rxchan->device->device_tx_status(rxchan,
765 dmarx->cookie, &state);
766 if (dmastat != DMA_PAUSED)
767 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
768
769 /* Disable RX DMA - incoming data will wait in the FIFO */
770 uap->dmacr &= ~UART011_RXDMAE;
771 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
772 uap->dmarx.running = false;
773
774 pending = sgbuf->sg.length - state.residue;
775 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
776 /* Then we terminate the transfer - we now know our residue */
777 dmaengine_terminate_all(rxchan);
778
779 /*
780 * This will take the chars we have so far and insert
781 * into the framework.
782 */
783 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
784
785 /* Switch buffer & re-trigger DMA job */
786 dmarx->use_buf_b = !dmarx->use_buf_b;
787 if (pl011_dma_rx_trigger_dma(uap)) {
788 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
789 "fall back to interrupt mode\n");
790 uap->im |= UART011_RXIM;
791 writew(uap->im, uap->port.membase + UART011_IMSC);
792 }
793 }
794
795 static void pl011_dma_rx_callback(void *data)
796 {
797 struct uart_amba_port *uap = data;
798 struct pl011_dmarx_data *dmarx = &uap->dmarx;
799 bool lastbuf = dmarx->use_buf_b;
800 int ret;
801
802 /*
803 * This completion interrupt occurs typically when the
804 * RX buffer is totally stuffed but no timeout has yet
805 * occurred. When that happens, we just want the RX
806 * routine to flush out the secondary DMA buffer while
807 * we immediately trigger the next DMA job.
808 */
809 spin_lock_irq(&uap->port.lock);
810 uap->dmarx.running = false;
811 dmarx->use_buf_b = !lastbuf;
812 ret = pl011_dma_rx_trigger_dma(uap);
813
814 pl011_dma_rx_chars(uap, PL011_DMA_BUFFER_SIZE, lastbuf, false);
815 spin_unlock_irq(&uap->port.lock);
816 /*
817 * Do this check after we picked the DMA chars so we don't
818 * get some IRQ immediately from RX.
819 */
820 if (ret) {
821 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
822 "fall back to interrupt mode\n");
823 uap->im |= UART011_RXIM;
824 writew(uap->im, uap->port.membase + UART011_IMSC);
825 }
826 }
827
828 /*
829 * Stop accepting received characters, when we're shutting down or
830 * suspending this port.
831 * Locking: called with port lock held and IRQs disabled.
832 */
833 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
834 {
835 /* FIXME. Just disable the DMA enable */
836 uap->dmacr &= ~UART011_RXDMAE;
837 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
838 }
839
840 static void pl011_dma_startup(struct uart_amba_port *uap)
841 {
842 int ret;
843
844 if (!uap->dmatx.chan)
845 return;
846
847 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
848 if (!uap->dmatx.buf) {
849 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
850 uap->port.fifosize = uap->fifosize;
851 return;
852 }
853
854 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
855
856 /* The DMA buffer is now the FIFO the TTY subsystem can use */
857 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
858 uap->using_tx_dma = true;
859
860 if (!uap->dmarx.chan)
861 goto skip_rx;
862
863 /* Allocate and map DMA RX buffers */
864 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
865 DMA_FROM_DEVICE);
866 if (ret) {
867 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
868 "RX buffer A", ret);
869 goto skip_rx;
870 }
871
872 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
873 DMA_FROM_DEVICE);
874 if (ret) {
875 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
876 "RX buffer B", ret);
877 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
878 DMA_FROM_DEVICE);
879 goto skip_rx;
880 }
881
882 uap->using_rx_dma = true;
883
884 skip_rx:
885 /* Turn on DMA error (RX/TX will be enabled on demand) */
886 uap->dmacr |= UART011_DMAONERR;
887 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
888
889 /*
890 * ST Micro variants has some specific dma burst threshold
891 * compensation. Set this to 16 bytes, so burst will only
892 * be issued above/below 16 bytes.
893 */
894 if (uap->vendor->dma_threshold)
895 writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
896 uap->port.membase + ST_UART011_DMAWM);
897
898 if (uap->using_rx_dma) {
899 if (pl011_dma_rx_trigger_dma(uap))
900 dev_dbg(uap->port.dev, "could not trigger initial "
901 "RX DMA job, fall back to interrupt mode\n");
902 }
903 }
904
905 static void pl011_dma_shutdown(struct uart_amba_port *uap)
906 {
907 if (!(uap->using_tx_dma || uap->using_rx_dma))
908 return;
909
910 /* Disable RX and TX DMA */
911 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
912 barrier();
913
914 spin_lock_irq(&uap->port.lock);
915 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
916 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
917 spin_unlock_irq(&uap->port.lock);
918
919 if (uap->using_tx_dma) {
920 /* In theory, this should already be done by pl011_dma_flush_buffer */
921 dmaengine_terminate_all(uap->dmatx.chan);
922 if (uap->dmatx.queued) {
923 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
924 DMA_TO_DEVICE);
925 uap->dmatx.queued = false;
926 }
927
928 kfree(uap->dmatx.buf);
929 uap->using_tx_dma = false;
930 }
931
932 if (uap->using_rx_dma) {
933 dmaengine_terminate_all(uap->dmarx.chan);
934 /* Clean up the RX DMA */
935 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
936 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
937 uap->using_rx_dma = false;
938 }
939 }
940
941 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
942 {
943 return uap->using_rx_dma;
944 }
945
946 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
947 {
948 return uap->using_rx_dma && uap->dmarx.running;
949 }
950
951
952 #else
953 /* Blank functions if the DMA engine is not available */
954 static inline void pl011_dma_probe(struct uart_amba_port *uap)
955 {
956 }
957
958 static inline void pl011_dma_remove(struct uart_amba_port *uap)
959 {
960 }
961
962 static inline void pl011_dma_startup(struct uart_amba_port *uap)
963 {
964 }
965
966 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
967 {
968 }
969
970 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
971 {
972 return false;
973 }
974
975 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
976 {
977 }
978
979 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
980 {
981 return false;
982 }
983
984 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
985 {
986 }
987
988 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
989 {
990 }
991
992 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
993 {
994 return -EIO;
995 }
996
997 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
998 {
999 return false;
1000 }
1001
1002 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1003 {
1004 return false;
1005 }
1006
1007 #define pl011_dma_flush_buffer NULL
1008 #endif
1009
1010
1011 static void pl011_stop_tx(struct uart_port *port)
1012 {
1013 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1014
1015 uap->im &= ~UART011_TXIM;
1016 writew(uap->im, uap->port.membase + UART011_IMSC);
1017 pl011_dma_tx_stop(uap);
1018 }
1019
1020 static void pl011_start_tx(struct uart_port *port)
1021 {
1022 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1023
1024 if (!pl011_dma_tx_start(uap)) {
1025 uap->im |= UART011_TXIM;
1026 writew(uap->im, uap->port.membase + UART011_IMSC);
1027 }
1028 }
1029
1030 static void pl011_stop_rx(struct uart_port *port)
1031 {
1032 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1033
1034 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1035 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1036 writew(uap->im, uap->port.membase + UART011_IMSC);
1037
1038 pl011_dma_rx_stop(uap);
1039 }
1040
1041 static void pl011_enable_ms(struct uart_port *port)
1042 {
1043 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1044
1045 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1046 writew(uap->im, uap->port.membase + UART011_IMSC);
1047 }
1048
1049 static void pl011_rx_chars(struct uart_amba_port *uap)
1050 {
1051 struct tty_struct *tty = uap->port.state->port.tty;
1052
1053 pl011_fifo_to_tty(uap);
1054
1055 spin_unlock(&uap->port.lock);
1056 tty_flip_buffer_push(tty);
1057 /*
1058 * If we were temporarily out of DMA mode for a while,
1059 * attempt to switch back to DMA mode again.
1060 */
1061 if (pl011_dma_rx_available(uap)) {
1062 if (pl011_dma_rx_trigger_dma(uap)) {
1063 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1064 "fall back to interrupt mode again\n");
1065 uap->im |= UART011_RXIM;
1066 } else
1067 uap->im &= ~UART011_RXIM;
1068 writew(uap->im, uap->port.membase + UART011_IMSC);
1069 }
1070 spin_lock(&uap->port.lock);
1071 }
1072
1073 static void pl011_tx_chars(struct uart_amba_port *uap)
1074 {
1075 struct circ_buf *xmit = &uap->port.state->xmit;
1076 int count;
1077
1078 if (uap->port.x_char) {
1079 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
1080 uap->port.icount.tx++;
1081 uap->port.x_char = 0;
1082 return;
1083 }
1084 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1085 pl011_stop_tx(&uap->port);
1086 return;
1087 }
1088
1089 /* If we are using DMA mode, try to send some characters. */
1090 if (pl011_dma_tx_irq(uap))
1091 return;
1092
1093 count = uap->fifosize >> 1;
1094 do {
1095 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
1096 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1097 uap->port.icount.tx++;
1098 if (uart_circ_empty(xmit))
1099 break;
1100 } while (--count > 0);
1101
1102 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1103 uart_write_wakeup(&uap->port);
1104
1105 if (uart_circ_empty(xmit))
1106 pl011_stop_tx(&uap->port);
1107 }
1108
1109 static void pl011_modem_status(struct uart_amba_port *uap)
1110 {
1111 unsigned int status, delta;
1112
1113 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1114
1115 delta = status ^ uap->old_status;
1116 uap->old_status = status;
1117
1118 if (!delta)
1119 return;
1120
1121 if (delta & UART01x_FR_DCD)
1122 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1123
1124 if (delta & UART01x_FR_DSR)
1125 uap->port.icount.dsr++;
1126
1127 if (delta & UART01x_FR_CTS)
1128 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1129
1130 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1131 }
1132
1133 static irqreturn_t pl011_int(int irq, void *dev_id)
1134 {
1135 struct uart_amba_port *uap = dev_id;
1136 unsigned long flags;
1137 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1138 int handled = 0;
1139
1140 spin_lock_irqsave(&uap->port.lock, flags);
1141
1142 status = readw(uap->port.membase + UART011_MIS);
1143 if (status) {
1144 do {
1145 writew(status & ~(UART011_TXIS|UART011_RTIS|
1146 UART011_RXIS),
1147 uap->port.membase + UART011_ICR);
1148
1149 if (status & (UART011_RTIS|UART011_RXIS)) {
1150 if (pl011_dma_rx_running(uap))
1151 pl011_dma_rx_irq(uap);
1152 else
1153 pl011_rx_chars(uap);
1154 }
1155 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1156 UART011_CTSMIS|UART011_RIMIS))
1157 pl011_modem_status(uap);
1158 if (status & UART011_TXIS)
1159 pl011_tx_chars(uap);
1160
1161 if (pass_counter-- == 0)
1162 break;
1163
1164 status = readw(uap->port.membase + UART011_MIS);
1165 } while (status != 0);
1166 handled = 1;
1167 }
1168
1169 spin_unlock_irqrestore(&uap->port.lock, flags);
1170
1171 return IRQ_RETVAL(handled);
1172 }
1173
1174 static unsigned int pl01x_tx_empty(struct uart_port *port)
1175 {
1176 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1177 unsigned int status = readw(uap->port.membase + UART01x_FR);
1178 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1179 }
1180
1181 static unsigned int pl01x_get_mctrl(struct uart_port *port)
1182 {
1183 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1184 unsigned int result = 0;
1185 unsigned int status = readw(uap->port.membase + UART01x_FR);
1186
1187 #define TIOCMBIT(uartbit, tiocmbit) \
1188 if (status & uartbit) \
1189 result |= tiocmbit
1190
1191 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1192 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1193 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1194 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1195 #undef TIOCMBIT
1196 return result;
1197 }
1198
1199 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1200 {
1201 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1202 unsigned int cr;
1203
1204 cr = readw(uap->port.membase + UART011_CR);
1205
1206 #define TIOCMBIT(tiocmbit, uartbit) \
1207 if (mctrl & tiocmbit) \
1208 cr |= uartbit; \
1209 else \
1210 cr &= ~uartbit
1211
1212 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1213 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1214 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1215 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1216 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1217
1218 if (uap->autorts) {
1219 /* We need to disable auto-RTS if we want to turn RTS off */
1220 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1221 }
1222 #undef TIOCMBIT
1223
1224 writew(cr, uap->port.membase + UART011_CR);
1225 }
1226
1227 static void pl011_break_ctl(struct uart_port *port, int break_state)
1228 {
1229 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1230 unsigned long flags;
1231 unsigned int lcr_h;
1232
1233 spin_lock_irqsave(&uap->port.lock, flags);
1234 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1235 if (break_state == -1)
1236 lcr_h |= UART01x_LCRH_BRK;
1237 else
1238 lcr_h &= ~UART01x_LCRH_BRK;
1239 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
1240 spin_unlock_irqrestore(&uap->port.lock, flags);
1241 }
1242
1243 #ifdef CONFIG_CONSOLE_POLL
1244 static int pl010_get_poll_char(struct uart_port *port)
1245 {
1246 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1247 unsigned int status;
1248
1249 status = readw(uap->port.membase + UART01x_FR);
1250 if (status & UART01x_FR_RXFE)
1251 return NO_POLL_CHAR;
1252
1253 return readw(uap->port.membase + UART01x_DR);
1254 }
1255
1256 static void pl010_put_poll_char(struct uart_port *port,
1257 unsigned char ch)
1258 {
1259 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1260
1261 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1262 barrier();
1263
1264 writew(ch, uap->port.membase + UART01x_DR);
1265 }
1266
1267 #endif /* CONFIG_CONSOLE_POLL */
1268
1269 static int pl011_startup(struct uart_port *port)
1270 {
1271 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1272 unsigned int cr;
1273 int retval;
1274
1275 /*
1276 * Try to enable the clock producer.
1277 */
1278 retval = clk_enable(uap->clk);
1279 if (retval)
1280 goto out;
1281
1282 uap->port.uartclk = clk_get_rate(uap->clk);
1283
1284 /*
1285 * Allocate the IRQ
1286 */
1287 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1288 if (retval)
1289 goto clk_dis;
1290
1291 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
1292
1293 /*
1294 * Provoke TX FIFO interrupt into asserting.
1295 */
1296 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
1297 writew(cr, uap->port.membase + UART011_CR);
1298 writew(0, uap->port.membase + UART011_FBRD);
1299 writew(1, uap->port.membase + UART011_IBRD);
1300 writew(0, uap->port.membase + uap->lcrh_rx);
1301 if (uap->lcrh_tx != uap->lcrh_rx) {
1302 int i;
1303 /*
1304 * Wait 10 PCLKs before writing LCRH_TX register,
1305 * to get this delay write read only register 10 times
1306 */
1307 for (i = 0; i < 10; ++i)
1308 writew(0xff, uap->port.membase + UART011_MIS);
1309 writew(0, uap->port.membase + uap->lcrh_tx);
1310 }
1311 writew(0, uap->port.membase + UART01x_DR);
1312 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1313 barrier();
1314
1315 cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1316 writew(cr, uap->port.membase + UART011_CR);
1317
1318 /* Clear pending error interrupts */
1319 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
1320 uap->port.membase + UART011_ICR);
1321
1322 /*
1323 * initialise the old status of the modem signals
1324 */
1325 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1326
1327 /* Startup DMA */
1328 pl011_dma_startup(uap);
1329
1330 /*
1331 * Finally, enable interrupts, only timeouts when using DMA
1332 * if initial RX DMA job failed, start in interrupt mode
1333 * as well.
1334 */
1335 spin_lock_irq(&uap->port.lock);
1336 uap->im = UART011_RTIM;
1337 if (!pl011_dma_rx_running(uap))
1338 uap->im |= UART011_RXIM;
1339 writew(uap->im, uap->port.membase + UART011_IMSC);
1340 spin_unlock_irq(&uap->port.lock);
1341
1342 return 0;
1343
1344 clk_dis:
1345 clk_disable(uap->clk);
1346 out:
1347 return retval;
1348 }
1349
1350 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1351 unsigned int lcrh)
1352 {
1353 unsigned long val;
1354
1355 val = readw(uap->port.membase + lcrh);
1356 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1357 writew(val, uap->port.membase + lcrh);
1358 }
1359
1360 static void pl011_shutdown(struct uart_port *port)
1361 {
1362 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1363
1364 /*
1365 * disable all interrupts
1366 */
1367 spin_lock_irq(&uap->port.lock);
1368 uap->im = 0;
1369 writew(uap->im, uap->port.membase + UART011_IMSC);
1370 writew(0xffff, uap->port.membase + UART011_ICR);
1371 spin_unlock_irq(&uap->port.lock);
1372
1373 pl011_dma_shutdown(uap);
1374
1375 /*
1376 * Free the interrupt
1377 */
1378 free_irq(uap->port.irq, uap);
1379
1380 /*
1381 * disable the port
1382 */
1383 uap->autorts = false;
1384 writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
1385
1386 /*
1387 * disable break condition and fifos
1388 */
1389 pl011_shutdown_channel(uap, uap->lcrh_rx);
1390 if (uap->lcrh_rx != uap->lcrh_tx)
1391 pl011_shutdown_channel(uap, uap->lcrh_tx);
1392
1393 /*
1394 * Shut down the clock producer
1395 */
1396 clk_disable(uap->clk);
1397 }
1398
1399 static void
1400 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1401 struct ktermios *old)
1402 {
1403 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1404 unsigned int lcr_h, old_cr;
1405 unsigned long flags;
1406 unsigned int baud, quot, clkdiv;
1407
1408 if (uap->vendor->oversampling)
1409 clkdiv = 8;
1410 else
1411 clkdiv = 16;
1412
1413 /*
1414 * Ask the core to calculate the divisor for us.
1415 */
1416 baud = uart_get_baud_rate(port, termios, old, 0,
1417 port->uartclk / clkdiv);
1418
1419 if (baud > port->uartclk/16)
1420 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1421 else
1422 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1423
1424 switch (termios->c_cflag & CSIZE) {
1425 case CS5:
1426 lcr_h = UART01x_LCRH_WLEN_5;
1427 break;
1428 case CS6:
1429 lcr_h = UART01x_LCRH_WLEN_6;
1430 break;
1431 case CS7:
1432 lcr_h = UART01x_LCRH_WLEN_7;
1433 break;
1434 default: // CS8
1435 lcr_h = UART01x_LCRH_WLEN_8;
1436 break;
1437 }
1438 if (termios->c_cflag & CSTOPB)
1439 lcr_h |= UART01x_LCRH_STP2;
1440 if (termios->c_cflag & PARENB) {
1441 lcr_h |= UART01x_LCRH_PEN;
1442 if (!(termios->c_cflag & PARODD))
1443 lcr_h |= UART01x_LCRH_EPS;
1444 }
1445 if (uap->fifosize > 1)
1446 lcr_h |= UART01x_LCRH_FEN;
1447
1448 spin_lock_irqsave(&port->lock, flags);
1449
1450 /*
1451 * Update the per-port timeout.
1452 */
1453 uart_update_timeout(port, termios->c_cflag, baud);
1454
1455 port->read_status_mask = UART011_DR_OE | 255;
1456 if (termios->c_iflag & INPCK)
1457 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1458 if (termios->c_iflag & (BRKINT | PARMRK))
1459 port->read_status_mask |= UART011_DR_BE;
1460
1461 /*
1462 * Characters to ignore
1463 */
1464 port->ignore_status_mask = 0;
1465 if (termios->c_iflag & IGNPAR)
1466 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1467 if (termios->c_iflag & IGNBRK) {
1468 port->ignore_status_mask |= UART011_DR_BE;
1469 /*
1470 * If we're ignoring parity and break indicators,
1471 * ignore overruns too (for real raw support).
1472 */
1473 if (termios->c_iflag & IGNPAR)
1474 port->ignore_status_mask |= UART011_DR_OE;
1475 }
1476
1477 /*
1478 * Ignore all characters if CREAD is not set.
1479 */
1480 if ((termios->c_cflag & CREAD) == 0)
1481 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1482
1483 if (UART_ENABLE_MS(port, termios->c_cflag))
1484 pl011_enable_ms(port);
1485
1486 /* first, disable everything */
1487 old_cr = readw(port->membase + UART011_CR);
1488 writew(0, port->membase + UART011_CR);
1489
1490 if (termios->c_cflag & CRTSCTS) {
1491 if (old_cr & UART011_CR_RTS)
1492 old_cr |= UART011_CR_RTSEN;
1493
1494 old_cr |= UART011_CR_CTSEN;
1495 uap->autorts = true;
1496 } else {
1497 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1498 uap->autorts = false;
1499 }
1500
1501 if (uap->vendor->oversampling) {
1502 if (baud > port->uartclk / 16)
1503 old_cr |= ST_UART011_CR_OVSFACT;
1504 else
1505 old_cr &= ~ST_UART011_CR_OVSFACT;
1506 }
1507
1508 /* Set baud rate */
1509 writew(quot & 0x3f, port->membase + UART011_FBRD);
1510 writew(quot >> 6, port->membase + UART011_IBRD);
1511
1512 /*
1513 * ----------v----------v----------v----------v-----
1514 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
1515 * ----------^----------^----------^----------^-----
1516 */
1517 writew(lcr_h, port->membase + uap->lcrh_rx);
1518 if (uap->lcrh_rx != uap->lcrh_tx) {
1519 int i;
1520 /*
1521 * Wait 10 PCLKs before writing LCRH_TX register,
1522 * to get this delay write read only register 10 times
1523 */
1524 for (i = 0; i < 10; ++i)
1525 writew(0xff, uap->port.membase + UART011_MIS);
1526 writew(lcr_h, port->membase + uap->lcrh_tx);
1527 }
1528 writew(old_cr, port->membase + UART011_CR);
1529
1530 spin_unlock_irqrestore(&port->lock, flags);
1531 }
1532
1533 static const char *pl011_type(struct uart_port *port)
1534 {
1535 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1536 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1537 }
1538
1539 /*
1540 * Release the memory region(s) being used by 'port'
1541 */
1542 static void pl010_release_port(struct uart_port *port)
1543 {
1544 release_mem_region(port->mapbase, SZ_4K);
1545 }
1546
1547 /*
1548 * Request the memory region(s) being used by 'port'
1549 */
1550 static int pl010_request_port(struct uart_port *port)
1551 {
1552 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
1553 != NULL ? 0 : -EBUSY;
1554 }
1555
1556 /*
1557 * Configure/autoconfigure the port.
1558 */
1559 static void pl010_config_port(struct uart_port *port, int flags)
1560 {
1561 if (flags & UART_CONFIG_TYPE) {
1562 port->type = PORT_AMBA;
1563 pl010_request_port(port);
1564 }
1565 }
1566
1567 /*
1568 * verify the new serial_struct (for TIOCSSERIAL).
1569 */
1570 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
1571 {
1572 int ret = 0;
1573 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
1574 ret = -EINVAL;
1575 if (ser->irq < 0 || ser->irq >= nr_irqs)
1576 ret = -EINVAL;
1577 if (ser->baud_base < 9600)
1578 ret = -EINVAL;
1579 return ret;
1580 }
1581
1582 static struct uart_ops amba_pl011_pops = {
1583 .tx_empty = pl01x_tx_empty,
1584 .set_mctrl = pl011_set_mctrl,
1585 .get_mctrl = pl01x_get_mctrl,
1586 .stop_tx = pl011_stop_tx,
1587 .start_tx = pl011_start_tx,
1588 .stop_rx = pl011_stop_rx,
1589 .enable_ms = pl011_enable_ms,
1590 .break_ctl = pl011_break_ctl,
1591 .startup = pl011_startup,
1592 .shutdown = pl011_shutdown,
1593 .flush_buffer = pl011_dma_flush_buffer,
1594 .set_termios = pl011_set_termios,
1595 .type = pl011_type,
1596 .release_port = pl010_release_port,
1597 .request_port = pl010_request_port,
1598 .config_port = pl010_config_port,
1599 .verify_port = pl010_verify_port,
1600 #ifdef CONFIG_CONSOLE_POLL
1601 .poll_get_char = pl010_get_poll_char,
1602 .poll_put_char = pl010_put_poll_char,
1603 #endif
1604 };
1605
1606 static struct uart_amba_port *amba_ports[UART_NR];
1607
1608 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
1609
1610 static void pl011_console_putchar(struct uart_port *port, int ch)
1611 {
1612 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1613
1614 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1615 barrier();
1616 writew(ch, uap->port.membase + UART01x_DR);
1617 }
1618
1619 static void
1620 pl011_console_write(struct console *co, const char *s, unsigned int count)
1621 {
1622 struct uart_amba_port *uap = amba_ports[co->index];
1623 unsigned int status, old_cr, new_cr;
1624
1625 clk_enable(uap->clk);
1626
1627 /*
1628 * First save the CR then disable the interrupts
1629 */
1630 old_cr = readw(uap->port.membase + UART011_CR);
1631 new_cr = old_cr & ~UART011_CR_CTSEN;
1632 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1633 writew(new_cr, uap->port.membase + UART011_CR);
1634
1635 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1636
1637 /*
1638 * Finally, wait for transmitter to become empty
1639 * and restore the TCR
1640 */
1641 do {
1642 status = readw(uap->port.membase + UART01x_FR);
1643 } while (status & UART01x_FR_BUSY);
1644 writew(old_cr, uap->port.membase + UART011_CR);
1645
1646 clk_disable(uap->clk);
1647 }
1648
1649 static void __init
1650 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
1651 int *parity, int *bits)
1652 {
1653 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
1654 unsigned int lcr_h, ibrd, fbrd;
1655
1656 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1657
1658 *parity = 'n';
1659 if (lcr_h & UART01x_LCRH_PEN) {
1660 if (lcr_h & UART01x_LCRH_EPS)
1661 *parity = 'e';
1662 else
1663 *parity = 'o';
1664 }
1665
1666 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
1667 *bits = 7;
1668 else
1669 *bits = 8;
1670
1671 ibrd = readw(uap->port.membase + UART011_IBRD);
1672 fbrd = readw(uap->port.membase + UART011_FBRD);
1673
1674 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
1675
1676 if (uap->vendor->oversampling) {
1677 if (readw(uap->port.membase + UART011_CR)
1678 & ST_UART011_CR_OVSFACT)
1679 *baud *= 2;
1680 }
1681 }
1682 }
1683
1684 static int __init pl011_console_setup(struct console *co, char *options)
1685 {
1686 struct uart_amba_port *uap;
1687 int baud = 38400;
1688 int bits = 8;
1689 int parity = 'n';
1690 int flow = 'n';
1691
1692 /*
1693 * Check whether an invalid uart number has been specified, and
1694 * if so, search for the first available port that does have
1695 * console support.
1696 */
1697 if (co->index >= UART_NR)
1698 co->index = 0;
1699 uap = amba_ports[co->index];
1700 if (!uap)
1701 return -ENODEV;
1702
1703 uap->port.uartclk = clk_get_rate(uap->clk);
1704
1705 if (options)
1706 uart_parse_options(options, &baud, &parity, &bits, &flow);
1707 else
1708 pl011_console_get_options(uap, &baud, &parity, &bits);
1709
1710 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
1711 }
1712
1713 static struct uart_driver amba_reg;
1714 static struct console amba_console = {
1715 .name = "ttyAMA",
1716 .write = pl011_console_write,
1717 .device = uart_console_device,
1718 .setup = pl011_console_setup,
1719 .flags = CON_PRINTBUFFER,
1720 .index = -1,
1721 .data = &amba_reg,
1722 };
1723
1724 #define AMBA_CONSOLE (&amba_console)
1725 #else
1726 #define AMBA_CONSOLE NULL
1727 #endif
1728
1729 static struct uart_driver amba_reg = {
1730 .owner = THIS_MODULE,
1731 .driver_name = "ttyAMA",
1732 .dev_name = "ttyAMA",
1733 .major = SERIAL_AMBA_MAJOR,
1734 .minor = SERIAL_AMBA_MINOR,
1735 .nr = UART_NR,
1736 .cons = AMBA_CONSOLE,
1737 };
1738
1739 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
1740 {
1741 struct uart_amba_port *uap;
1742 struct vendor_data *vendor = id->data;
1743 void __iomem *base;
1744 int i, ret;
1745
1746 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1747 if (amba_ports[i] == NULL)
1748 break;
1749
1750 if (i == ARRAY_SIZE(amba_ports)) {
1751 ret = -EBUSY;
1752 goto out;
1753 }
1754
1755 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
1756 if (uap == NULL) {
1757 ret = -ENOMEM;
1758 goto out;
1759 }
1760
1761 base = ioremap(dev->res.start, resource_size(&dev->res));
1762 if (!base) {
1763 ret = -ENOMEM;
1764 goto free;
1765 }
1766
1767 uap->clk = clk_get(&dev->dev, NULL);
1768 if (IS_ERR(uap->clk)) {
1769 ret = PTR_ERR(uap->clk);
1770 goto unmap;
1771 }
1772
1773 uap->vendor = vendor;
1774 uap->lcrh_rx = vendor->lcrh_rx;
1775 uap->lcrh_tx = vendor->lcrh_tx;
1776 uap->fifosize = vendor->fifosize;
1777 uap->port.dev = &dev->dev;
1778 uap->port.mapbase = dev->res.start;
1779 uap->port.membase = base;
1780 uap->port.iotype = UPIO_MEM;
1781 uap->port.irq = dev->irq[0];
1782 uap->port.fifosize = uap->fifosize;
1783 uap->port.ops = &amba_pl011_pops;
1784 uap->port.flags = UPF_BOOT_AUTOCONF;
1785 uap->port.line = i;
1786 pl011_dma_probe(uap);
1787
1788 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
1789
1790 amba_ports[i] = uap;
1791
1792 amba_set_drvdata(dev, uap);
1793 ret = uart_add_one_port(&amba_reg, &uap->port);
1794 if (ret) {
1795 amba_set_drvdata(dev, NULL);
1796 amba_ports[i] = NULL;
1797 pl011_dma_remove(uap);
1798 clk_put(uap->clk);
1799 unmap:
1800 iounmap(base);
1801 free:
1802 kfree(uap);
1803 }
1804 out:
1805 return ret;
1806 }
1807
1808 static int pl011_remove(struct amba_device *dev)
1809 {
1810 struct uart_amba_port *uap = amba_get_drvdata(dev);
1811 int i;
1812
1813 amba_set_drvdata(dev, NULL);
1814
1815 uart_remove_one_port(&amba_reg, &uap->port);
1816
1817 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1818 if (amba_ports[i] == uap)
1819 amba_ports[i] = NULL;
1820
1821 pl011_dma_remove(uap);
1822 iounmap(uap->port.membase);
1823 clk_put(uap->clk);
1824 kfree(uap);
1825 return 0;
1826 }
1827
1828 #ifdef CONFIG_PM
1829 static int pl011_suspend(struct amba_device *dev, pm_message_t state)
1830 {
1831 struct uart_amba_port *uap = amba_get_drvdata(dev);
1832
1833 if (!uap)
1834 return -EINVAL;
1835
1836 return uart_suspend_port(&amba_reg, &uap->port);
1837 }
1838
1839 static int pl011_resume(struct amba_device *dev)
1840 {
1841 struct uart_amba_port *uap = amba_get_drvdata(dev);
1842
1843 if (!uap)
1844 return -EINVAL;
1845
1846 return uart_resume_port(&amba_reg, &uap->port);
1847 }
1848 #endif
1849
1850 static struct amba_id pl011_ids[] = {
1851 {
1852 .id = 0x00041011,
1853 .mask = 0x000fffff,
1854 .data = &vendor_arm,
1855 },
1856 {
1857 .id = 0x00380802,
1858 .mask = 0x00ffffff,
1859 .data = &vendor_st,
1860 },
1861 { 0, 0 },
1862 };
1863
1864 static struct amba_driver pl011_driver = {
1865 .drv = {
1866 .name = "uart-pl011",
1867 },
1868 .id_table = pl011_ids,
1869 .probe = pl011_probe,
1870 .remove = pl011_remove,
1871 #ifdef CONFIG_PM
1872 .suspend = pl011_suspend,
1873 .resume = pl011_resume,
1874 #endif
1875 };
1876
1877 static int __init pl011_init(void)
1878 {
1879 int ret;
1880 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
1881
1882 ret = uart_register_driver(&amba_reg);
1883 if (ret == 0) {
1884 ret = amba_driver_register(&pl011_driver);
1885 if (ret)
1886 uart_unregister_driver(&amba_reg);
1887 }
1888 return ret;
1889 }
1890
1891 static void __exit pl011_exit(void)
1892 {
1893 amba_driver_unregister(&pl011_driver);
1894 uart_unregister_driver(&amba_reg);
1895 }
1896
1897 /*
1898 * While this can be a module, if builtin it's most likely the console
1899 * So let's leave module_exit but move module_init to an earlier place
1900 */
1901 arch_initcall(pl011_init);
1902 module_exit(pl011_exit);
1903
1904 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
1905 MODULE_DESCRIPTION("ARM AMBA serial port driver");
1906 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree