drivers/scsi/ipr.h

   1 /*
   2  * ipr.h -- driver for IBM Power Linux RAID adapters
   3  *
   4  * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
   5  *
   6  * Copyright (C) 2003, 2004 IBM Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  *
  22  * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
  23  *                              that broke 64bit platforms.
  24  */
  25
  26 #ifndef _IPR_H
  27 #define _IPR_H
  28
  29 #include <linux/types.h>
  30 #include <linux/completion.h>
  31 #include <linux/libata.h>
  32 #include <linux/list.h>
  33 #include <linux/kref.h>
  34 #include <scsi/scsi.h>
  35 #include <scsi/scsi_cmnd.h>
  36
  37 /*
  38  * Literals
  39  */
  40 #define IPR_DRIVER_VERSION "2.5.0"
  41 #define IPR_DRIVER_DATE "(February 11, 2010)"
  42
  43 /*
  44  * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
  45  *      ops per device for devices not running tagged command queuing.
  46  *      This can be adjusted at runtime through sysfs device attributes.
  47  */
  48 #define IPR_MAX_CMD_PER_LUN                             6
  49 #define IPR_MAX_CMD_PER_ATA_LUN                 1
  50
  51 /*
  52  * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
  53  *      ops the mid-layer can send to the adapter.
  54  */
  55 #define IPR_NUM_BASE_CMD_BLKS                           100
  56
  57 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E    0x0339
  58
  59 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2          0x033D
  60 #define PCI_DEVICE_ID_IBM_CROC_ASIC_E2          0x034A
  61
  62 #define IPR_SUBS_DEV_ID_2780    0x0264
  63 #define IPR_SUBS_DEV_ID_5702    0x0266
  64 #define IPR_SUBS_DEV_ID_5703    0x0278
  65 #define IPR_SUBS_DEV_ID_572E    0x028D
  66 #define IPR_SUBS_DEV_ID_573E    0x02D3
  67 #define IPR_SUBS_DEV_ID_573D    0x02D4
  68 #define IPR_SUBS_DEV_ID_571A    0x02C0
  69 #define IPR_SUBS_DEV_ID_571B    0x02BE
  70 #define IPR_SUBS_DEV_ID_571E    0x02BF
  71 #define IPR_SUBS_DEV_ID_571F    0x02D5
  72 #define IPR_SUBS_DEV_ID_572A    0x02C1
  73 #define IPR_SUBS_DEV_ID_572B    0x02C2
  74 #define IPR_SUBS_DEV_ID_572F    0x02C3
  75 #define IPR_SUBS_DEV_ID_574E    0x030A
  76 #define IPR_SUBS_DEV_ID_575B    0x030D
  77 #define IPR_SUBS_DEV_ID_575C    0x0338
  78 #define IPR_SUBS_DEV_ID_57B3    0x033A
  79 #define IPR_SUBS_DEV_ID_57B7    0x0360
  80 #define IPR_SUBS_DEV_ID_57B8    0x02C2
  81
  82 #define IPR_SUBS_DEV_ID_57B4    0x033B
  83 #define IPR_SUBS_DEV_ID_57B2    0x035F
  84 #define IPR_SUBS_DEV_ID_57C6    0x0357
  85 #define IPR_SUBS_DEV_ID_57CC    0x035C
  86
  87 #define IPR_SUBS_DEV_ID_57B5    0x033C
  88 #define IPR_SUBS_DEV_ID_57CE    0x035E
  89 #define IPR_SUBS_DEV_ID_57B1    0x0355
  90
  91 #define IPR_SUBS_DEV_ID_574D    0x0356
  92 #define IPR_SUBS_DEV_ID_575D    0x035D
  93
  94 #define IPR_NAME                                "ipr"
  95
  96 /*
  97  * Return codes
  98  */
  99 #define IPR_RC_JOB_CONTINUE             1
 100 #define IPR_RC_JOB_RETURN               2
 101
 102 /*
 103  * IOASCs
 104  */
 105 #define IPR_IOASC_NR_INIT_CMD_REQUIRED          0x02040200
 106 #define IPR_IOASC_NR_IOA_RESET_REQUIRED         0x02048000
 107 #define IPR_IOASC_SYNC_REQUIRED                 0x023f0000
 108 #define IPR_IOASC_MED_DO_NOT_REALLOC            0x03110C00
 109 #define IPR_IOASC_HW_SEL_TIMEOUT                        0x04050000
 110 #define IPR_IOASC_HW_DEV_BUS_STATUS                     0x04448500
 111 #define IPR_IOASC_IOASC_MASK                    0xFFFFFF00
 112 #define IPR_IOASC_SCSI_STATUS_MASK              0x000000FF
 113 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT    0x05240000
 114 #define IPR_IOASC_IR_RESOURCE_HANDLE            0x05250000
 115 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA         0x05258100
 116 #define IPR_IOASA_IR_DUAL_IOA_DISABLED          0x052C8000
 117 #define IPR_IOASC_BUS_WAS_RESET                 0x06290000
 118 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER                0x06298000
 119 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST      0x0B5A0000
 120
 121 #define IPR_FIRST_DRIVER_IOASC                  0x10000000
 122 #define IPR_IOASC_IOA_WAS_RESET                 0x10000001
 123 #define IPR_IOASC_PCI_ACCESS_ERROR                      0x10000002
 124
 125 /* Driver data flags */
 126 #define IPR_USE_LONG_TRANSOP_TIMEOUT            0x00000001
 127 #define IPR_USE_PCI_WARM_RESET                  0x00000002
 128
 129 #define IPR_DEFAULT_MAX_ERROR_DUMP                      984
 130 #define IPR_NUM_LOG_HCAMS                               2
 131 #define IPR_NUM_CFG_CHG_HCAMS                           2
 132 #define IPR_NUM_HCAMS   (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
 133
 134 #define IPR_MAX_SIS64_TARGETS_PER_BUS                   1024
 135 #define IPR_MAX_SIS64_LUNS_PER_TARGET                   0xffffffff
 136
 137 #define IPR_MAX_NUM_TARGETS_PER_BUS                     256
 138 #define IPR_MAX_NUM_LUNS_PER_TARGET                     256
 139 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET        8
 140 #define IPR_VSET_BUS                                    0xff
 141 #define IPR_IOA_BUS                                             0xff
 142 #define IPR_IOA_TARGET                                  0xff
 143 #define IPR_IOA_LUN                                             0xff
 144 #define IPR_MAX_NUM_BUSES                               16
 145 #define IPR_MAX_BUS_TO_SCAN                             IPR_MAX_NUM_BUSES
 146
 147 #define IPR_NUM_RESET_RELOAD_RETRIES            3
 148
 149 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
 150 #define IPR_NUM_INTERNAL_CMD_BLKS       (IPR_NUM_HCAMS + \
 151                                      ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
 152
 153 #define IPR_MAX_COMMANDS                IPR_NUM_BASE_CMD_BLKS
 154 #define IPR_NUM_CMD_BLKS                (IPR_NUM_BASE_CMD_BLKS + \
 155                                                 IPR_NUM_INTERNAL_CMD_BLKS)
 156
 157 #define IPR_MAX_PHYSICAL_DEVS                           192
 158 #define IPR_DEFAULT_SIS64_DEVS                          1024
 159 #define IPR_MAX_SIS64_DEVS                              4096
 160
 161 #define IPR_MAX_SGLIST                                  64
 162 #define IPR_IOA_MAX_SECTORS                             32767
 163 #define IPR_VSET_MAX_SECTORS                            512
 164 #define IPR_MAX_CDB_LEN                                 16
 165 #define IPR_MAX_HRRQ_RETRIES                            3
 166
 167 #define IPR_DEFAULT_BUS_WIDTH                           16
 168 #define IPR_80MBs_SCSI_RATE             ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
 169 #define IPR_U160_SCSI_RATE      ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
 170 #define IPR_U320_SCSI_RATE      ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
 171 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
 172
 173 #define IPR_IOA_RES_HANDLE                              0xffffffff
 174 #define IPR_INVALID_RES_HANDLE                  0
 175 #define IPR_IOA_RES_ADDR                                0x00ffffff
 176
 177 /*
 178  * Adapter Commands
 179  */
 180 #define IPR_QUERY_RSRC_STATE                            0xC2
 181 #define IPR_RESET_DEVICE                                0xC3
 182 #define IPR_RESET_TYPE_SELECT                           0x80
 183 #define IPR_LUN_RESET                                   0x40
 184 #define IPR_TARGET_RESET                                        0x20
 185 #define IPR_BUS_RESET                                   0x10
 186 #define IPR_ATA_PHY_RESET                                       0x80
 187 #define IPR_ID_HOST_RR_Q                                0xC4
 188 #define IPR_QUERY_IOA_CONFIG                            0xC5
 189 #define IPR_CANCEL_ALL_REQUESTS                 0xCE
 190 #define IPR_HOST_CONTROLLED_ASYNC                       0xCF
 191 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE      0x01
 192 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA           0x02
 193 #define IPR_SET_SUPPORTED_DEVICES                       0xFB
 194 #define IPR_SET_ALL_SUPPORTED_DEVICES                   0x80
 195 #define IPR_IOA_SHUTDOWN                                0xF7
 196 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE                    0x05
 197
 198 /*
 199  * Timeouts
 200  */
 201 #define IPR_SHUTDOWN_TIMEOUT                    (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
 202 #define IPR_VSET_RW_TIMEOUT                     (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
 203 #define IPR_ABBREV_SHUTDOWN_TIMEOUT             (10 * HZ)
 204 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO   (2 * 60 * HZ)
 205 #define IPR_DEVICE_RESET_TIMEOUT                (ipr_fastfail ? 10 * HZ : 30 * HZ)
 206 #define IPR_CANCEL_ALL_TIMEOUT          (ipr_fastfail ? 10 * HZ : 30 * HZ)
 207 #define IPR_ABORT_TASK_TIMEOUT          (ipr_fastfail ? 10 * HZ : 30 * HZ)
 208 #define IPR_INTERNAL_TIMEOUT                    (ipr_fastfail ? 10 * HZ : 30 * HZ)
 209 #define IPR_WRITE_BUFFER_TIMEOUT                (10 * 60 * HZ)
 210 #define IPR_SET_SUP_DEVICE_TIMEOUT              (2 * 60 * HZ)
 211 #define IPR_REQUEST_SENSE_TIMEOUT               (10 * HZ)
 212 #define IPR_OPERATIONAL_TIMEOUT         (5 * 60)
 213 #define IPR_LONG_OPERATIONAL_TIMEOUT    (12 * 60)
 214 #define IPR_WAIT_FOR_RESET_TIMEOUT              (2 * HZ)
 215 #define IPR_CHECK_FOR_RESET_TIMEOUT             (HZ / 10)
 216 #define IPR_WAIT_FOR_BIST_TIMEOUT               (2 * HZ)
 217 #define IPR_PCI_RESET_TIMEOUT                   (HZ / 2)
 218 #define IPR_DUMP_TIMEOUT                        (15 * HZ)
 219
 220 /*
 221  * SCSI Literals
 222  */
 223 #define IPR_VENDOR_ID_LEN                       8
 224 #define IPR_PROD_ID_LEN                         16
 225 #define IPR_SERIAL_NUM_LEN                      8
 226
 227 /*
 228  * Hardware literals
 229  */
 230 #define IPR_FMT2_MBX_ADDR_MASK                          0x0fffffff
 231 #define IPR_FMT2_MBX_BAR_SEL_MASK                       0xf0000000
 232 #define IPR_FMT2_MKR_BAR_SEL_SHIFT                      28
 233 #define IPR_GET_FMT2_BAR_SEL(mbx) \
 234 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
 235 #define IPR_SDT_FMT2_BAR0_SEL                           0x0
 236 #define IPR_SDT_FMT2_BAR1_SEL                           0x1
 237 #define IPR_SDT_FMT2_BAR2_SEL                           0x2
 238 #define IPR_SDT_FMT2_BAR3_SEL                           0x3
 239 #define IPR_SDT_FMT2_BAR4_SEL                           0x4
 240 #define IPR_SDT_FMT2_BAR5_SEL                           0x5
 241 #define IPR_SDT_FMT2_EXP_ROM_SEL                        0x8
 242 #define IPR_FMT2_SDT_READY_TO_USE                       0xC4D4E3F2
 243 #define IPR_FMT3_SDT_READY_TO_USE                       0xC4D4E3F3
 244 #define IPR_DOORBELL                                    0x82800000
 245 #define IPR_RUNTIME_RESET                               0x40000000
 246
 247 #define IPR_IPL_INIT_MIN_STAGE_TIME                     5
 248 #define IPR_IPL_INIT_DEFAULT_STAGE_TIME                 15
 249 #define IPR_IPL_INIT_STAGE_UNKNOWN                      0x0
 250 #define IPR_IPL_INIT_STAGE_TRANSOP                      0xB0000000
 251 #define IPR_IPL_INIT_STAGE_MASK                         0xff000000
 252 #define IPR_IPL_INIT_STAGE_TIME_MASK                    0x0000ffff
 253 #define IPR_PCII_IPL_STAGE_CHANGE                       (0x80000000 >> 0)
 254
 255 #define IPR_PCII_IOA_TRANS_TO_OPER                      (0x80000000 >> 0)
 256 #define IPR_PCII_IOARCB_XFER_FAILED                     (0x80000000 >> 3)
 257 #define IPR_PCII_IOA_UNIT_CHECKED                       (0x80000000 >> 4)
 258 #define IPR_PCII_NO_HOST_RRQ                            (0x80000000 >> 5)
 259 #define IPR_PCII_CRITICAL_OPERATION                     (0x80000000 >> 6)
 260 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE           (0x80000000 >> 7)
 261 #define IPR_PCII_IOARRIN_LOST                           (0x80000000 >> 27)
 262 #define IPR_PCII_MMIO_ERROR                             (0x80000000 >> 28)
 263 #define IPR_PCII_PROC_ERR_STATE                 (0x80000000 >> 29)
 264 #define IPR_PCII_HRRQ_UPDATED                           (0x80000000 >> 30)
 265 #define IPR_PCII_CORE_ISSUED_RST_REQ            (0x80000000 >> 31)
 266
 267 #define IPR_PCII_ERROR_INTERRUPTS \
 268 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
 269 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
 270
 271 #define IPR_PCII_OPER_INTERRUPTS \
 272 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
 273
 274 #define IPR_UPROCI_RESET_ALERT                  (0x80000000 >> 7)
 275 #define IPR_UPROCI_IO_DEBUG_ALERT                       (0x80000000 >> 9)
 276 #define IPR_UPROCI_SIS64_START_BIST                     (0x80000000 >> 23)
 277
 278 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC            200000  /* 200 ms */
 279 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC           200000  /* 200 ms */
 280
 281 /*
 282  * Dump literals
 283  */
 284 #define IPR_MAX_IOA_DUMP_SIZE                           (4 * 1024 * 1024)
 285 #define IPR_NUM_SDT_ENTRIES                             511
 286 #define IPR_MAX_NUM_DUMP_PAGES  ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
 287
 288 /*
 289  * Misc literals
 290  */
 291 #define IPR_NUM_IOADL_ENTRIES                   IPR_MAX_SGLIST
 292
 293 /*
 294  * Adapter interface types
 295  */
 296
 297 struct ipr_res_addr {
 298         u8 reserved;
 299         u8 bus;
 300         u8 target;
 301         u8 lun;
 302 #define IPR_GET_PHYS_LOC(res_addr) \
 303         (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
 304 }__attribute__((packed, aligned (4)));
 305
 306 struct ipr_std_inq_vpids {
 307         u8 vendor_id[IPR_VENDOR_ID_LEN];
 308         u8 product_id[IPR_PROD_ID_LEN];
 309 }__attribute__((packed));
 310
 311 struct ipr_vpd {
 312         struct ipr_std_inq_vpids vpids;
 313         u8 sn[IPR_SERIAL_NUM_LEN];
 314 }__attribute__((packed));
 315
 316 struct ipr_ext_vpd {
 317         struct ipr_vpd vpd;
 318         __be32 wwid[2];
 319 }__attribute__((packed));
 320
 321 struct ipr_std_inq_data {
 322         u8 peri_qual_dev_type;
 323 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
 324 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
 325
 326         u8 removeable_medium_rsvd;
 327 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
 328
 329 #define IPR_IS_DASD_DEVICE(std_inq) \
 330 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
 331 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
 332
 333 #define IPR_IS_SES_DEVICE(std_inq) \
 334 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
 335
 336         u8 version;
 337         u8 aen_naca_fmt;
 338         u8 additional_len;
 339         u8 sccs_rsvd;
 340         u8 bq_enc_multi;
 341         u8 sync_cmdq_flags;
 342
 343         struct ipr_std_inq_vpids vpids;
 344
 345         u8 ros_rsvd_ram_rsvd[4];
 346
 347         u8 serial_num[IPR_SERIAL_NUM_LEN];
 348 }__attribute__ ((packed));
 349
 350 #define IPR_RES_TYPE_AF_DASD            0x00
 351 #define IPR_RES_TYPE_GENERIC_SCSI       0x01
 352 #define IPR_RES_TYPE_VOLUME_SET         0x02
 353 #define IPR_RES_TYPE_REMOTE_AF_DASD     0x03
 354 #define IPR_RES_TYPE_GENERIC_ATA        0x04
 355 #define IPR_RES_TYPE_ARRAY              0x05
 356 #define IPR_RES_TYPE_IOAFP              0xff
 357
 358 struct ipr_config_table_entry {
 359         u8 proto;
 360 #define IPR_PROTO_SATA                  0x02
 361 #define IPR_PROTO_SATA_ATAPI            0x03
 362 #define IPR_PROTO_SAS_STP               0x06
 363 #define IPR_PROTO_SAS_STP_ATAPI         0x07
 364         u8 array_id;
 365         u8 flags;
 366 #define IPR_IS_IOA_RESOURCE             0x80
 367         u8 rsvd_subtype;
 368
 369 #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
 370 #define IPR_QUEUE_FROZEN_MODEL          0
 371 #define IPR_QUEUE_NACA_MODEL            1
 372
 373         struct ipr_res_addr res_addr;
 374         __be32 res_handle;
 375         __be32 reserved4[2];
 376         struct ipr_std_inq_data std_inq_data;
 377 }__attribute__ ((packed, aligned (4)));
 378
 379 struct ipr_config_table_entry64 {
 380         u8 res_type;
 381         u8 proto;
 382         u8 vset_num;
 383         u8 array_id;
 384         __be16 flags;
 385         __be16 res_flags;
 386 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
 387         __be32 res_handle;
 388         u8 dev_id_type;
 389         u8 reserved[3];
 390         __be64 dev_id;
 391         __be64 lun;
 392         __be64 lun_wwn[2];
 393 #define IPR_MAX_RES_PATH_LENGTH         24
 394         __be64 res_path;
 395         struct ipr_std_inq_data std_inq_data;
 396         u8 reserved2[4];
 397         __be64 reserved3[2]; // description text
 398         u8 reserved4[8];
 399 }__attribute__ ((packed, aligned (8)));
 400
 401 struct ipr_config_table_hdr {
 402         u8 num_entries;
 403         u8 flags;
 404 #define IPR_UCODE_DOWNLOAD_REQ  0x10
 405         __be16 reserved;
 406 }__attribute__((packed, aligned (4)));
 407
 408 struct ipr_config_table_hdr64 {
 409         __be16 num_entries;
 410         __be16 reserved;
 411         u8 flags;
 412         u8 reserved2[11];
 413 }__attribute__((packed, aligned (4)));
 414
 415 struct ipr_config_table {
 416         struct ipr_config_table_hdr hdr;
 417         struct ipr_config_table_entry dev[0];
 418 }__attribute__((packed, aligned (4)));
 419
 420 struct ipr_config_table64 {
 421         struct ipr_config_table_hdr64 hdr64;
 422         struct ipr_config_table_entry64 dev[0];
 423 }__attribute__((packed, aligned (8)));
 424
 425 struct ipr_config_table_entry_wrapper {
 426         union {
 427                 struct ipr_config_table_entry *cfgte;
 428                 struct ipr_config_table_entry64 *cfgte64;
 429         } u;
 430 };
 431
 432 struct ipr_hostrcb_cfg_ch_not {
 433         union {
 434                 struct ipr_config_table_entry cfgte;
 435                 struct ipr_config_table_entry64 cfgte64;
 436         } u;
 437         u8 reserved[936];
 438 }__attribute__((packed, aligned (4)));
 439
 440 struct ipr_supported_device {
 441         __be16 data_length;
 442         u8 reserved;
 443         u8 num_records;
 444         struct ipr_std_inq_vpids vpids;
 445         u8 reserved2[16];
 446 }__attribute__((packed, aligned (4)));
 447
 448 /* Command packet structure */
 449 struct ipr_cmd_pkt {
 450         __be16 reserved;                /* Reserved by IOA */
 451         u8 request_type;
 452 #define IPR_RQTYPE_SCSICDB              0x00
 453 #define IPR_RQTYPE_IOACMD               0x01
 454 #define IPR_RQTYPE_HCAM                 0x02
 455 #define IPR_RQTYPE_ATA_PASSTHRU 0x04
 456
 457         u8 reserved2;
 458
 459         u8 flags_hi;
 460 #define IPR_FLAGS_HI_WRITE_NOT_READ             0x80
 461 #define IPR_FLAGS_HI_NO_ULEN_CHK                0x20
 462 #define IPR_FLAGS_HI_SYNC_OVERRIDE              0x10
 463 #define IPR_FLAGS_HI_SYNC_COMPLETE              0x08
 464 #define IPR_FLAGS_HI_NO_LINK_DESC               0x04
 465
 466         u8 flags_lo;
 467 #define IPR_FLAGS_LO_ALIGNED_BFR                0x20
 468 #define IPR_FLAGS_LO_DELAY_AFTER_RST    0x10
 469 #define IPR_FLAGS_LO_UNTAGGED_TASK              0x00
 470 #define IPR_FLAGS_LO_SIMPLE_TASK                0x02
 471 #define IPR_FLAGS_LO_ORDERED_TASK               0x04
 472 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK             0x06
 473 #define IPR_FLAGS_LO_ACA_TASK                   0x08
 474
 475         u8 cdb[16];
 476         __be16 timeout;
 477 }__attribute__ ((packed, aligned(4)));
 478
 479 struct ipr_ioarcb_ata_regs {    /* 22 bytes */
 480         u8 flags;
 481 #define IPR_ATA_FLAG_PACKET_CMD                 0x80
 482 #define IPR_ATA_FLAG_XFER_TYPE_DMA                      0x40
 483 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION  0x20
 484         u8 reserved[3];
 485
 486         __be16 data;
 487         u8 feature;
 488         u8 nsect;
 489         u8 lbal;
 490         u8 lbam;
 491         u8 lbah;
 492         u8 device;
 493         u8 command;
 494         u8 reserved2[3];
 495         u8 hob_feature;
 496         u8 hob_nsect;
 497         u8 hob_lbal;
 498         u8 hob_lbam;
 499         u8 hob_lbah;
 500         u8 ctl;
 501 }__attribute__ ((packed, aligned(4)));
 502
 503 struct ipr_ioadl_desc {
 504         __be32 flags_and_data_len;
 505 #define IPR_IOADL_FLAGS_MASK            0xff000000
 506 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
 507 #define IPR_IOADL_DATA_LEN_MASK         0x00ffffff
 508 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
 509 #define IPR_IOADL_FLAGS_READ            0x48000000
 510 #define IPR_IOADL_FLAGS_READ_LAST       0x49000000
 511 #define IPR_IOADL_FLAGS_WRITE           0x68000000
 512 #define IPR_IOADL_FLAGS_WRITE_LAST      0x69000000
 513 #define IPR_IOADL_FLAGS_LAST            0x01000000
 514
 515         __be32 address;
 516 }__attribute__((packed, aligned (8)));
 517
 518 struct ipr_ioadl64_desc {
 519         __be32 flags;
 520         __be32 data_len;
 521         __be64 address;
 522 }__attribute__((packed, aligned (16)));
 523
 524 struct ipr_ata64_ioadl {
 525         struct ipr_ioarcb_ata_regs regs;
 526         u16 reserved[5];
 527         struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
 528 }__attribute__((packed, aligned (16)));
 529
 530 struct ipr_ioarcb_add_data {
 531         union {
 532                 struct ipr_ioarcb_ata_regs regs;
 533                 struct ipr_ioadl_desc ioadl[5];
 534                 __be32 add_cmd_parms[10];
 535         } u;
 536 }__attribute__ ((packed, aligned (4)));
 537
 538 struct ipr_ioarcb_sis64_add_addr_ecb {
 539         __be64 ioasa_host_pci_addr;
 540         __be64 data_ioadl_addr;
 541         __be64 reserved;
 542         __be32 ext_control_buf[4];
 543 }__attribute__((packed, aligned (8)));
 544
 545 /* IOA Request Control Block    128 bytes  */
 546 struct ipr_ioarcb {
 547         union {
 548                 __be32 ioarcb_host_pci_addr;
 549                 __be64 ioarcb_host_pci_addr64;
 550         } a;
 551         __be32 res_handle;
 552         __be32 host_response_handle;
 553         __be32 reserved1;
 554         __be32 reserved2;
 555         __be32 reserved3;
 556
 557         __be32 data_transfer_length;
 558         __be32 read_data_transfer_length;
 559         __be32 write_ioadl_addr;
 560         __be32 ioadl_len;
 561         __be32 read_ioadl_addr;
 562         __be32 read_ioadl_len;
 563
 564         __be32 ioasa_host_pci_addr;
 565         __be16 ioasa_len;
 566         __be16 reserved4;
 567
 568         struct ipr_cmd_pkt cmd_pkt;
 569
 570         __be16 add_cmd_parms_offset;
 571         __be16 add_cmd_parms_len;
 572
 573         union {
 574                 struct ipr_ioarcb_add_data add_data;
 575                 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
 576         } u;
 577
 578 }__attribute__((packed, aligned (4)));
 579
 580 struct ipr_ioasa_vset {
 581         __be32 failing_lba_hi;
 582         __be32 failing_lba_lo;
 583         __be32 reserved;
 584 }__attribute__((packed, aligned (4)));
 585
 586 struct ipr_ioasa_af_dasd {
 587         __be32 failing_lba;
 588         __be32 reserved[2];
 589 }__attribute__((packed, aligned (4)));
 590
 591 struct ipr_ioasa_gpdd {
 592         u8 end_state;
 593         u8 bus_phase;
 594         __be16 reserved;
 595         __be32 ioa_data[2];
 596 }__attribute__((packed, aligned (4)));
 597
 598 struct ipr_ioasa_gata {
 599         u8 error;
 600         u8 nsect;               /* Interrupt reason */
 601         u8 lbal;
 602         u8 lbam;
 603         u8 lbah;
 604         u8 device;
 605         u8 status;
 606         u8 alt_status;  /* ATA CTL */
 607         u8 hob_nsect;
 608         u8 hob_lbal;
 609         u8 hob_lbam;
 610         u8 hob_lbah;
 611 }__attribute__((packed, aligned (4)));
 612
 613 struct ipr_auto_sense {
 614         __be16 auto_sense_len;
 615         __be16 ioa_data_len;
 616         __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
 617 };
 618
 619 struct ipr_ioasa_hdr {
 620         __be32 ioasc;
 621 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
 622 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
 623 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
 624 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
 625
 626         __be16 ret_stat_len;    /* Length of the returned IOASA */
 627
 628         __be16 avail_stat_len;  /* Total Length of status available. */
 629
 630         __be32 residual_data_len;       /* number of bytes in the host data */
 631         /* buffers that were not used by the IOARCB command. */
 632
 633         __be32 ilid;
 634 #define IPR_NO_ILID                     0
 635 #define IPR_DRIVER_ILID         0xffffffff
 636
 637         __be32 fd_ioasc;
 638
 639         __be32 fd_phys_locator;
 640
 641         __be32 fd_res_handle;
 642
 643         __be32 ioasc_specific;  /* status code specific field */
 644 #define IPR_ADDITIONAL_STATUS_FMT               0x80000000
 645 #define IPR_AUTOSENSE_VALID                     0x40000000
 646 #define IPR_ATA_DEVICE_WAS_RESET                0x20000000
 647 #define IPR_IOASC_SPECIFIC_MASK         0x00ffffff
 648 #define IPR_FIELD_POINTER_VALID         (0x80000000 >> 8)
 649 #define IPR_FIELD_POINTER_MASK          0x0000ffff
 650
 651 }__attribute__((packed, aligned (4)));
 652
 653 struct ipr_ioasa {
 654         struct ipr_ioasa_hdr hdr;
 655
 656         union {
 657                 struct ipr_ioasa_vset vset;
 658                 struct ipr_ioasa_af_dasd dasd;
 659                 struct ipr_ioasa_gpdd gpdd;
 660                 struct ipr_ioasa_gata gata;
 661         } u;
 662
 663         struct ipr_auto_sense auto_sense;
 664 }__attribute__((packed, aligned (4)));
 665
 666 struct ipr_ioasa64 {
 667         struct ipr_ioasa_hdr hdr;
 668         u8 fd_res_path[8];
 669
 670         union {
 671                 struct ipr_ioasa_vset vset;
 672                 struct ipr_ioasa_af_dasd dasd;
 673                 struct ipr_ioasa_gpdd gpdd;
 674                 struct ipr_ioasa_gata gata;
 675         } u;
 676
 677         struct ipr_auto_sense auto_sense;
 678 }__attribute__((packed, aligned (4)));
 679
 680 struct ipr_mode_parm_hdr {
 681         u8 length;
 682         u8 medium_type;
 683         u8 device_spec_parms;
 684         u8 block_desc_len;
 685 }__attribute__((packed));
 686
 687 struct ipr_mode_pages {
 688         struct ipr_mode_parm_hdr hdr;
 689         u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
 690 }__attribute__((packed));
 691
 692 struct ipr_mode_page_hdr {
 693         u8 ps_page_code;
 694 #define IPR_MODE_PAGE_PS        0x80
 695 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
 696         u8 page_length;
 697 }__attribute__ ((packed));
 698
 699 struct ipr_dev_bus_entry {
 700         struct ipr_res_addr res_addr;
 701         u8 flags;
 702 #define IPR_SCSI_ATTR_ENABLE_QAS                        0x80
 703 #define IPR_SCSI_ATTR_DISABLE_QAS                       0x40
 704 #define IPR_SCSI_ATTR_QAS_MASK                          0xC0
 705 #define IPR_SCSI_ATTR_ENABLE_TM                         0x20
 706 #define IPR_SCSI_ATTR_NO_TERM_PWR                       0x10
 707 #define IPR_SCSI_ATTR_TM_SUPPORTED                      0x08
 708 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED     0x04
 709
 710         u8 scsi_id;
 711         u8 bus_width;
 712         u8 extended_reset_delay;
 713 #define IPR_EXTENDED_RESET_DELAY        7
 714
 715         __be32 max_xfer_rate;
 716
 717         u8 spinup_delay;
 718         u8 reserved3;
 719         __be16 reserved4;
 720 }__attribute__((packed, aligned (4)));
 721
 722 struct ipr_mode_page28 {
 723         struct ipr_mode_page_hdr hdr;
 724         u8 num_entries;
 725         u8 entry_length;
 726         struct ipr_dev_bus_entry bus[0];
 727 }__attribute__((packed));
 728
 729 struct ipr_mode_page24 {
 730         struct ipr_mode_page_hdr hdr;
 731         u8 flags;
 732 #define IPR_ENABLE_DUAL_IOA_AF 0x80
 733 }__attribute__((packed));
 734
 735 struct ipr_ioa_vpd {
 736         struct ipr_std_inq_data std_inq_data;
 737         u8 ascii_part_num[12];
 738         u8 reserved[40];
 739         u8 ascii_plant_code[4];
 740 }__attribute__((packed));
 741
 742 struct ipr_inquiry_page3 {
 743         u8 peri_qual_dev_type;
 744         u8 page_code;
 745         u8 reserved1;
 746         u8 page_length;
 747         u8 ascii_len;
 748         u8 reserved2[3];
 749         u8 load_id[4];
 750         u8 major_release;
 751         u8 card_type;
 752         u8 minor_release[2];
 753         u8 ptf_number[4];
 754         u8 patch_number[4];
 755 }__attribute__((packed));
 756
 757 struct ipr_inquiry_cap {
 758         u8 peri_qual_dev_type;
 759         u8 page_code;
 760         u8 reserved1;
 761         u8 page_length;
 762         u8 ascii_len;
 763         u8 reserved2;
 764         u8 sis_version[2];
 765         u8 cap;
 766 #define IPR_CAP_DUAL_IOA_RAID           0x80
 767         u8 reserved3[15];
 768 }__attribute__((packed));
 769
 770 #define IPR_INQUIRY_PAGE0_ENTRIES 20
 771 struct ipr_inquiry_page0 {
 772         u8 peri_qual_dev_type;
 773         u8 page_code;
 774         u8 reserved1;
 775         u8 len;
 776         u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
 777 }__attribute__((packed));
 778
 779 struct ipr_hostrcb_device_data_entry {
 780         struct ipr_vpd vpd;
 781         struct ipr_res_addr dev_res_addr;
 782         struct ipr_vpd new_vpd;
 783         struct ipr_vpd ioa_last_with_dev_vpd;
 784         struct ipr_vpd cfc_last_with_dev_vpd;
 785         __be32 ioa_data[5];
 786 }__attribute__((packed, aligned (4)));
 787
 788 struct ipr_hostrcb_device_data_entry_enhanced {
 789         struct ipr_ext_vpd vpd;
 790         u8 ccin[4];
 791         struct ipr_res_addr dev_res_addr;
 792         struct ipr_ext_vpd new_vpd;
 793         u8 new_ccin[4];
 794         struct ipr_ext_vpd ioa_last_with_dev_vpd;
 795         struct ipr_ext_vpd cfc_last_with_dev_vpd;
 796 }__attribute__((packed, aligned (4)));
 797
 798 struct ipr_hostrcb64_device_data_entry_enhanced {
 799         struct ipr_ext_vpd vpd;
 800         u8 ccin[4];
 801         u8 res_path[8];
 802         struct ipr_ext_vpd new_vpd;
 803         u8 new_ccin[4];
 804         struct ipr_ext_vpd ioa_last_with_dev_vpd;
 805         struct ipr_ext_vpd cfc_last_with_dev_vpd;
 806 }__attribute__((packed, aligned (4)));
 807
 808 struct ipr_hostrcb_array_data_entry {
 809         struct ipr_vpd vpd;
 810         struct ipr_res_addr expected_dev_res_addr;
 811         struct ipr_res_addr dev_res_addr;
 812 }__attribute__((packed, aligned (4)));
 813
 814 struct ipr_hostrcb64_array_data_entry {
 815         struct ipr_ext_vpd vpd;
 816         u8 ccin[4];
 817         u8 expected_res_path[8];
 818         u8 res_path[8];
 819 }__attribute__((packed, aligned (4)));
 820
 821 struct ipr_hostrcb_array_data_entry_enhanced {
 822         struct ipr_ext_vpd vpd;
 823         u8 ccin[4];
 824         struct ipr_res_addr expected_dev_res_addr;
 825         struct ipr_res_addr dev_res_addr;
 826 }__attribute__((packed, aligned (4)));
 827
 828 struct ipr_hostrcb_type_ff_error {
 829         __be32 ioa_data[758];
 830 }__attribute__((packed, aligned (4)));
 831
 832 struct ipr_hostrcb_type_01_error {
 833         __be32 seek_counter;
 834         __be32 read_counter;
 835         u8 sense_data[32];
 836         __be32 ioa_data[236];
 837 }__attribute__((packed, aligned (4)));
 838
 839 struct ipr_hostrcb_type_02_error {
 840         struct ipr_vpd ioa_vpd;
 841         struct ipr_vpd cfc_vpd;
 842         struct ipr_vpd ioa_last_attached_to_cfc_vpd;
 843         struct ipr_vpd cfc_last_attached_to_ioa_vpd;
 844         __be32 ioa_data[3];
 845 }__attribute__((packed, aligned (4)));
 846
 847 struct ipr_hostrcb_type_12_error {
 848         struct ipr_ext_vpd ioa_vpd;
 849         struct ipr_ext_vpd cfc_vpd;
 850         struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
 851         struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
 852         __be32 ioa_data[3];
 853 }__attribute__((packed, aligned (4)));
 854
 855 struct ipr_hostrcb_type_03_error {
 856         struct ipr_vpd ioa_vpd;
 857         struct ipr_vpd cfc_vpd;
 858         __be32 errors_detected;
 859         __be32 errors_logged;
 860         u8 ioa_data[12];
 861         struct ipr_hostrcb_device_data_entry dev[3];
 862 }__attribute__((packed, aligned (4)));
 863
 864 struct ipr_hostrcb_type_13_error {
 865         struct ipr_ext_vpd ioa_vpd;
 866         struct ipr_ext_vpd cfc_vpd;
 867         __be32 errors_detected;
 868         __be32 errors_logged;
 869         struct ipr_hostrcb_device_data_entry_enhanced dev[3];
 870 }__attribute__((packed, aligned (4)));
 871
 872 struct ipr_hostrcb_type_23_error {
 873         struct ipr_ext_vpd ioa_vpd;
 874         struct ipr_ext_vpd cfc_vpd;
 875         __be32 errors_detected;
 876         __be32 errors_logged;
 877         struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
 878 }__attribute__((packed, aligned (4)));
 879
 880 struct ipr_hostrcb_type_04_error {
 881         struct ipr_vpd ioa_vpd;
 882         struct ipr_vpd cfc_vpd;
 883         u8 ioa_data[12];
 884         struct ipr_hostrcb_array_data_entry array_member[10];
 885         __be32 exposed_mode_adn;
 886         __be32 array_id;
 887         struct ipr_vpd incomp_dev_vpd;
 888         __be32 ioa_data2;
 889         struct ipr_hostrcb_array_data_entry array_member2[8];
 890         struct ipr_res_addr last_func_vset_res_addr;
 891         u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
 892         u8 protection_level[8];
 893 }__attribute__((packed, aligned (4)));
 894
 895 struct ipr_hostrcb_type_14_error {
 896         struct ipr_ext_vpd ioa_vpd;
 897         struct ipr_ext_vpd cfc_vpd;
 898         __be32 exposed_mode_adn;
 899         __be32 array_id;
 900         struct ipr_res_addr last_func_vset_res_addr;
 901         u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
 902         u8 protection_level[8];
 903         __be32 num_entries;
 904         struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
 905 }__attribute__((packed, aligned (4)));
 906
 907 struct ipr_hostrcb_type_24_error {
 908         struct ipr_ext_vpd ioa_vpd;
 909         struct ipr_ext_vpd cfc_vpd;
 910         u8 reserved[2];
 911         u8 exposed_mode_adn;
 912 #define IPR_INVALID_ARRAY_DEV_NUM               0xff
 913         u8 array_id;
 914         u8 last_res_path[8];
 915         u8 protection_level[8];
 916         struct ipr_ext_vpd array_vpd;
 917         u8 description[16];
 918         u8 reserved2[3];
 919         u8 num_entries;
 920         struct ipr_hostrcb64_array_data_entry array_member[32];
 921 }__attribute__((packed, aligned (4)));
 922
 923 struct ipr_hostrcb_type_07_error {
 924         u8 failure_reason[64];
 925         struct ipr_vpd vpd;
 926         u32 data[222];
 927 }__attribute__((packed, aligned (4)));
 928
 929 struct ipr_hostrcb_type_17_error {
 930         u8 failure_reason[64];
 931         struct ipr_ext_vpd vpd;
 932         u32 data[476];
 933 }__attribute__((packed, aligned (4)));
 934
 935 struct ipr_hostrcb_config_element {
 936         u8 type_status;
 937 #define IPR_PATH_CFG_TYPE_MASK  0xF0
 938 #define IPR_PATH_CFG_NOT_EXIST  0x00
 939 #define IPR_PATH_CFG_IOA_PORT           0x10
 940 #define IPR_PATH_CFG_EXP_PORT           0x20
 941 #define IPR_PATH_CFG_DEVICE_PORT        0x30
 942 #define IPR_PATH_CFG_DEVICE_LUN 0x40
 943
 944 #define IPR_PATH_CFG_STATUS_MASK        0x0F
 945 #define IPR_PATH_CFG_NO_PROB            0x00
 946 #define IPR_PATH_CFG_DEGRADED           0x01
 947 #define IPR_PATH_CFG_FAILED             0x02
 948 #define IPR_PATH_CFG_SUSPECT            0x03
 949 #define IPR_PATH_NOT_DETECTED           0x04
 950 #define IPR_PATH_INCORRECT_CONN 0x05
 951
 952         u8 cascaded_expander;
 953         u8 phy;
 954         u8 link_rate;
 955 #define IPR_PHY_LINK_RATE_MASK  0x0F
 956
 957         __be32 wwid[2];
 958 }__attribute__((packed, aligned (4)));
 959
 960 struct ipr_hostrcb64_config_element {
 961         __be16 length;
 962         u8 descriptor_id;
 963 #define IPR_DESCRIPTOR_MASK             0xC0
 964 #define IPR_DESCRIPTOR_SIS64            0x00
 965
 966         u8 reserved;
 967         u8 type_status;
 968
 969         u8 reserved2[2];
 970         u8 link_rate;
 971
 972         u8 res_path[8];
 973         __be32 wwid[2];
 974 }__attribute__((packed, aligned (8)));
 975
 976 struct ipr_hostrcb_fabric_desc {
 977         __be16 length;
 978         u8 ioa_port;
 979         u8 cascaded_expander;
 980         u8 phy;
 981         u8 path_state;
 982 #define IPR_PATH_ACTIVE_MASK            0xC0
 983 #define IPR_PATH_NO_INFO                0x00
 984 #define IPR_PATH_ACTIVE                 0x40
 985 #define IPR_PATH_NOT_ACTIVE             0x80
 986
 987 #define IPR_PATH_STATE_MASK             0x0F
 988 #define IPR_PATH_STATE_NO_INFO  0x00
 989 #define IPR_PATH_HEALTHY                0x01
 990 #define IPR_PATH_DEGRADED               0x02
 991 #define IPR_PATH_FAILED                 0x03
 992
 993         __be16 num_entries;
 994         struct ipr_hostrcb_config_element elem[1];
 995 }__attribute__((packed, aligned (4)));
 996
 997 struct ipr_hostrcb64_fabric_desc {
 998         __be16 length;
 999         u8 descriptor_id;
1000
1001         u8 reserved[2];
1002         u8 path_state;
1003
1004         u8 reserved2[2];
1005         u8 res_path[8];
1006         u8 reserved3[6];
1007         __be16 num_entries;
1008         struct ipr_hostrcb64_config_element elem[1];
1009 }__attribute__((packed, aligned (8)));
1010
1011 #define for_each_fabric_cfg(fabric, cfg) \
1012                 for (cfg = (fabric)->elem; \
1013                         cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1014                         cfg++)
1015
1016 struct ipr_hostrcb_type_20_error {
1017         u8 failure_reason[64];
1018         u8 reserved[3];
1019         u8 num_entries;
1020         struct ipr_hostrcb_fabric_desc desc[1];
1021 }__attribute__((packed, aligned (4)));
1022
1023 struct ipr_hostrcb_type_30_error {
1024         u8 failure_reason[64];
1025         u8 reserved[3];
1026         u8 num_entries;
1027         struct ipr_hostrcb64_fabric_desc desc[1];
1028 }__attribute__((packed, aligned (4)));
1029
1030 struct ipr_hostrcb_error {
1031         __be32 fd_ioasc;
1032         struct ipr_res_addr fd_res_addr;
1033         __be32 fd_res_handle;
1034         __be32 prc;
1035         union {
1036                 struct ipr_hostrcb_type_ff_error type_ff_error;
1037                 struct ipr_hostrcb_type_01_error type_01_error;
1038                 struct ipr_hostrcb_type_02_error type_02_error;
1039                 struct ipr_hostrcb_type_03_error type_03_error;
1040                 struct ipr_hostrcb_type_04_error type_04_error;
1041                 struct ipr_hostrcb_type_07_error type_07_error;
1042                 struct ipr_hostrcb_type_12_error type_12_error;
1043                 struct ipr_hostrcb_type_13_error type_13_error;
1044                 struct ipr_hostrcb_type_14_error type_14_error;
1045                 struct ipr_hostrcb_type_17_error type_17_error;
1046                 struct ipr_hostrcb_type_20_error type_20_error;
1047         } u;
1048 }__attribute__((packed, aligned (4)));
1049
1050 struct ipr_hostrcb64_error {
1051         __be32 fd_ioasc;
1052         __be32 ioa_fw_level;
1053         __be32 fd_res_handle;
1054         __be32 prc;
1055         __be64 fd_dev_id;
1056         __be64 fd_lun;
1057         u8 fd_res_path[8];
1058         __be64 time_stamp;
1059         u8 reserved[16];
1060         union {
1061                 struct ipr_hostrcb_type_ff_error type_ff_error;
1062                 struct ipr_hostrcb_type_12_error type_12_error;
1063                 struct ipr_hostrcb_type_17_error type_17_error;
1064                 struct ipr_hostrcb_type_23_error type_23_error;
1065                 struct ipr_hostrcb_type_24_error type_24_error;
1066                 struct ipr_hostrcb_type_30_error type_30_error;
1067         } u;
1068 }__attribute__((packed, aligned (8)));
1069
1070 struct ipr_hostrcb_raw {
1071         __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1072 }__attribute__((packed, aligned (4)));
1073
1074 struct ipr_hcam {
1075         u8 op_code;
1076 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE                      0xE1
1077 #define IPR_HOST_RCB_OP_CODE_LOG_DATA                           0xE2
1078
1079         u8 notify_type;
1080 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED        0x00
1081 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY                       0x01
1082 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY                       0x02
1083 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY         0x10
1084 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY       0x11
1085
1086         u8 notifications_lost;
1087 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST                      0
1088 #define IPR_HOST_RCB_NOTIFICATIONS_LOST                         0x80
1089
1090         u8 flags;
1091 #define IPR_HOSTRCB_INTERNAL_OPER       0x80
1092 #define IPR_HOSTRCB_ERR_RESP_SENT       0x40
1093
1094         u8 overlay_id;
1095 #define IPR_HOST_RCB_OVERLAY_ID_1                               0x01
1096 #define IPR_HOST_RCB_OVERLAY_ID_2                               0x02
1097 #define IPR_HOST_RCB_OVERLAY_ID_3                               0x03
1098 #define IPR_HOST_RCB_OVERLAY_ID_4                               0x04
1099 #define IPR_HOST_RCB_OVERLAY_ID_6                               0x06
1100 #define IPR_HOST_RCB_OVERLAY_ID_7                               0x07
1101 #define IPR_HOST_RCB_OVERLAY_ID_12                              0x12
1102 #define IPR_HOST_RCB_OVERLAY_ID_13                              0x13
1103 #define IPR_HOST_RCB_OVERLAY_ID_14                              0x14
1104 #define IPR_HOST_RCB_OVERLAY_ID_16                              0x16
1105 #define IPR_HOST_RCB_OVERLAY_ID_17                              0x17
1106 #define IPR_HOST_RCB_OVERLAY_ID_20                              0x20
1107 #define IPR_HOST_RCB_OVERLAY_ID_23                              0x23
1108 #define IPR_HOST_RCB_OVERLAY_ID_24                              0x24
1109 #define IPR_HOST_RCB_OVERLAY_ID_26                              0x26
1110 #define IPR_HOST_RCB_OVERLAY_ID_30                              0x30
1111 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT                         0xFF
1112
1113         u8 reserved1[3];
1114         __be32 ilid;
1115         __be32 time_since_last_ioa_reset;
1116         __be32 reserved2;
1117         __be32 length;
1118
1119         union {
1120                 struct ipr_hostrcb_error error;
1121                 struct ipr_hostrcb64_error error64;
1122                 struct ipr_hostrcb_cfg_ch_not ccn;
1123                 struct ipr_hostrcb_raw raw;
1124         } u;
1125 }__attribute__((packed, aligned (4)));
1126
1127 struct ipr_hostrcb {
1128         struct ipr_hcam hcam;
1129         dma_addr_t hostrcb_dma;
1130         struct list_head queue;
1131         struct ipr_ioa_cfg *ioa_cfg;
1132         char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1133 };
1134
1135 /* IPR smart dump table structures */
1136 struct ipr_sdt_entry {
1137         __be32 start_token;
1138         __be32 end_token;
1139         u8 reserved[4];
1140
1141         u8 flags;
1142 #define IPR_SDT_ENDIAN          0x80
1143 #define IPR_SDT_VALID_ENTRY     0x20
1144
1145         u8 resv;
1146         __be16 priority;
1147 }__attribute__((packed, aligned (4)));
1148
1149 struct ipr_sdt_header {
1150         __be32 state;
1151         __be32 num_entries;
1152         __be32 num_entries_used;
1153         __be32 dump_size;
1154 }__attribute__((packed, aligned (4)));
1155
1156 struct ipr_sdt {
1157         struct ipr_sdt_header hdr;
1158         struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
1159 }__attribute__((packed, aligned (4)));
1160
1161 struct ipr_uc_sdt {
1162         struct ipr_sdt_header hdr;
1163         struct ipr_sdt_entry entry[1];
1164 }__attribute__((packed, aligned (4)));
1165
1166 /*
1167  * Driver types
1168  */
1169 struct ipr_bus_attributes {
1170         u8 bus;
1171         u8 qas_enabled;
1172         u8 bus_width;
1173         u8 reserved;
1174         u32 max_xfer_rate;
1175 };
1176
1177 struct ipr_sata_port {
1178         struct ipr_ioa_cfg *ioa_cfg;
1179         struct ata_port *ap;
1180         struct ipr_resource_entry *res;
1181         struct ipr_ioasa_gata ioasa;
1182 };
1183
1184 struct ipr_resource_entry {
1185         u8 needs_sync_complete:1;
1186         u8 in_erp:1;
1187         u8 add_to_ml:1;
1188         u8 del_from_ml:1;
1189         u8 resetting_device:1;
1190
1191         u32 bus;                /* AKA channel */
1192         u32 target;             /* AKA id */
1193         u32 lun;
1194 #define IPR_ARRAY_VIRTUAL_BUS                   0x1
1195 #define IPR_VSET_VIRTUAL_BUS                    0x2
1196 #define IPR_IOAFP_VIRTUAL_BUS                   0x3
1197
1198 #define IPR_GET_RES_PHYS_LOC(res) \
1199         (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1200
1201         u8 ata_class;
1202
1203         u8 flags;
1204         __be16 res_flags;
1205
1206         u8 type;
1207
1208         u8 qmodel;
1209         struct ipr_std_inq_data std_inq_data;
1210
1211         __be32 res_handle;
1212         __be64 dev_id;
1213         struct scsi_lun dev_lun;
1214         u8 res_path[8];
1215
1216         struct ipr_ioa_cfg *ioa_cfg;
1217         struct scsi_device *sdev;
1218         struct ipr_sata_port *sata_port;
1219         struct list_head queue;
1220 }; /* struct ipr_resource_entry */
1221
1222 struct ipr_resource_hdr {
1223         u16 num_entries;
1224         u16 reserved;
1225 };
1226
1227 struct ipr_misc_cbs {
1228         struct ipr_ioa_vpd ioa_vpd;
1229         struct ipr_inquiry_page0 page0_data;
1230         struct ipr_inquiry_page3 page3_data;
1231         struct ipr_inquiry_cap cap;
1232         struct ipr_mode_pages mode_pages;
1233         struct ipr_supported_device supp_dev;
1234 };
1235
1236 struct ipr_interrupt_offsets {
1237         unsigned long set_interrupt_mask_reg;
1238         unsigned long clr_interrupt_mask_reg;
1239         unsigned long clr_interrupt_mask_reg32;
1240         unsigned long sense_interrupt_mask_reg;
1241         unsigned long sense_interrupt_mask_reg32;
1242         unsigned long clr_interrupt_reg;
1243         unsigned long clr_interrupt_reg32;
1244
1245         unsigned long sense_interrupt_reg;
1246         unsigned long sense_interrupt_reg32;
1247         unsigned long ioarrin_reg;
1248         unsigned long sense_uproc_interrupt_reg;
1249         unsigned long sense_uproc_interrupt_reg32;
1250         unsigned long set_uproc_interrupt_reg;
1251         unsigned long set_uproc_interrupt_reg32;
1252         unsigned long clr_uproc_interrupt_reg;
1253         unsigned long clr_uproc_interrupt_reg32;
1254
1255         unsigned long init_feedback_reg;
1256
1257         unsigned long dump_addr_reg;
1258         unsigned long dump_data_reg;
1259
1260 #define IPR_ENDIAN_SWAP_KEY             0x00080800
1261         unsigned long endian_swap_reg;
1262 };
1263
1264 struct ipr_interrupts {
1265         void __iomem *set_interrupt_mask_reg;
1266         void __iomem *clr_interrupt_mask_reg;
1267         void __iomem *clr_interrupt_mask_reg32;
1268         void __iomem *sense_interrupt_mask_reg;
1269         void __iomem *sense_interrupt_mask_reg32;
1270         void __iomem *clr_interrupt_reg;
1271         void __iomem *clr_interrupt_reg32;
1272
1273         void __iomem *sense_interrupt_reg;
1274         void __iomem *sense_interrupt_reg32;
1275         void __iomem *ioarrin_reg;
1276         void __iomem *sense_uproc_interrupt_reg;
1277         void __iomem *sense_uproc_interrupt_reg32;
1278         void __iomem *set_uproc_interrupt_reg;
1279         void __iomem *set_uproc_interrupt_reg32;
1280         void __iomem *clr_uproc_interrupt_reg;
1281         void __iomem *clr_uproc_interrupt_reg32;
1282
1283         void __iomem *init_feedback_reg;
1284
1285         void __iomem *dump_addr_reg;
1286         void __iomem *dump_data_reg;
1287
1288         void __iomem *endian_swap_reg;
1289 };
1290
1291 struct ipr_chip_cfg_t {
1292         u32 mailbox;
1293         u8 cache_line_size;
1294         struct ipr_interrupt_offsets regs;
1295 };
1296
1297 struct ipr_chip_t {
1298         u16 vendor;
1299         u16 device;
1300         u16 intr_type;
1301 #define IPR_USE_LSI                     0x00
1302 #define IPR_USE_MSI                     0x01
1303         u16 sis_type;
1304 #define IPR_SIS32                       0x00
1305 #define IPR_SIS64                       0x01
1306         u16 bist_method;
1307 #define IPR_PCI_CFG                     0x00
1308 #define IPR_MMIO                        0x01
1309         const struct ipr_chip_cfg_t *cfg;
1310 };
1311
1312 enum ipr_shutdown_type {
1313         IPR_SHUTDOWN_NORMAL = 0x00,
1314         IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1315         IPR_SHUTDOWN_ABBREV = 0x80,
1316         IPR_SHUTDOWN_NONE = 0x100
1317 };
1318
1319 struct ipr_trace_entry {
1320         u32 time;
1321
1322         u8 op_code;
1323         u8 ata_op_code;
1324         u8 type;
1325 #define IPR_TRACE_START                 0x00
1326 #define IPR_TRACE_FINISH                0xff
1327         u8 cmd_index;
1328
1329         __be32 res_handle;
1330         union {
1331                 u32 ioasc;
1332                 u32 add_data;
1333                 u32 res_addr;
1334         } u;
1335 };
1336
1337 struct ipr_sglist {
1338         u32 order;
1339         u32 num_sg;
1340         u32 num_dma_sg;
1341         u32 buffer_len;
1342         struct scatterlist scatterlist[1];
1343 };
1344
1345 enum ipr_sdt_state {
1346         INACTIVE,
1347         WAIT_FOR_DUMP,
1348         GET_DUMP,
1349         ABORT_DUMP,
1350         DUMP_OBTAINED
1351 };
1352
1353 /* Per-controller data */
1354 struct ipr_ioa_cfg {
1355         char eye_catcher[8];
1356 #define IPR_EYECATCHER                  "iprcfg"
1357
1358         struct list_head queue;
1359
1360         u8 allow_interrupts:1;
1361         u8 in_reset_reload:1;
1362         u8 in_ioa_bringdown:1;
1363         u8 ioa_unit_checked:1;
1364         u8 ioa_is_dead:1;
1365         u8 dump_taken:1;
1366         u8 allow_cmds:1;
1367         u8 allow_ml_add_del:1;
1368         u8 needs_hard_reset:1;
1369         u8 dual_raid:1;
1370         u8 needs_warm_reset:1;
1371         u8 msi_received:1;
1372         u8 sis64:1;
1373
1374         u8 revid;
1375
1376         /*
1377          * Bitmaps for SIS64 generated target values
1378          */
1379         unsigned long *target_ids;
1380         unsigned long *array_ids;
1381         unsigned long *vset_ids;
1382
1383         u16 type; /* CCIN of the card */
1384
1385         u8 log_level;
1386 #define IPR_MAX_LOG_LEVEL                       4
1387 #define IPR_DEFAULT_LOG_LEVEL           2
1388
1389 #define IPR_NUM_TRACE_INDEX_BITS        8
1390 #define IPR_NUM_TRACE_ENTRIES           (1 << IPR_NUM_TRACE_INDEX_BITS)
1391 #define IPR_TRACE_SIZE  (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1392         char trace_start[8];
1393 #define IPR_TRACE_START_LABEL                   "trace"
1394         struct ipr_trace_entry *trace;
1395         u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1396
1397         /*
1398          * Queue for free command blocks
1399          */
1400         char ipr_free_label[8];
1401 #define IPR_FREEQ_LABEL                 "free-q"
1402         struct list_head free_q;
1403
1404         /*
1405          * Queue for command blocks outstanding to the adapter
1406          */
1407         char ipr_pending_label[8];
1408 #define IPR_PENDQ_LABEL                 "pend-q"
1409         struct list_head pending_q;
1410
1411         char cfg_table_start[8];
1412 #define IPR_CFG_TBL_START               "cfg"
1413         union {
1414                 struct ipr_config_table *cfg_table;
1415                 struct ipr_config_table64 *cfg_table64;
1416         } u;
1417         dma_addr_t cfg_table_dma;
1418         u32 cfg_table_size;
1419         u32 max_devs_supported;
1420
1421         char resource_table_label[8];
1422 #define IPR_RES_TABLE_LABEL             "res_tbl"
1423         struct ipr_resource_entry *res_entries;
1424         struct list_head free_res_q;
1425         struct list_head used_res_q;
1426
1427         char ipr_hcam_label[8];
1428 #define IPR_HCAM_LABEL                  "hcams"
1429         struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1430         dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1431         struct list_head hostrcb_free_q;
1432         struct list_head hostrcb_pending_q;
1433
1434         __be32 *host_rrq;
1435         dma_addr_t host_rrq_dma;
1436 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK   0xfffffffc
1437 #define IPR_HRRQ_RESP_BIT_SET                   0x00000002
1438 #define IPR_HRRQ_TOGGLE_BIT                             0x00000001
1439 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT  2
1440         volatile __be32 *hrrq_start;
1441         volatile __be32 *hrrq_end;
1442         volatile __be32 *hrrq_curr;
1443         volatile u32 toggle_bit;
1444
1445         struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1446
1447         unsigned int transop_timeout;
1448         const struct ipr_chip_cfg_t *chip_cfg;
1449         const struct ipr_chip_t *ipr_chip;
1450
1451         void __iomem *hdw_dma_regs;     /* iomapped PCI memory space */
1452         unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1453         void __iomem *ioa_mailbox;
1454         struct ipr_interrupts regs;
1455
1456         u16 saved_pcix_cmd_reg;
1457         u16 reset_retries;
1458
1459         u32 errors_logged;
1460         u32 doorbell;
1461
1462         struct Scsi_Host *host;
1463         struct pci_dev *pdev;
1464         struct ipr_sglist *ucode_sglist;
1465         u8 saved_mode_page_len;
1466
1467         struct work_struct work_q;
1468
1469         wait_queue_head_t reset_wait_q;
1470         wait_queue_head_t msi_wait_q;
1471
1472         struct ipr_dump *dump;
1473         enum ipr_sdt_state sdt_state;
1474
1475         struct ipr_misc_cbs *vpd_cbs;
1476         dma_addr_t vpd_cbs_dma;
1477
1478         struct pci_pool *ipr_cmd_pool;
1479
1480         struct ipr_cmnd *reset_cmd;
1481         int (*reset) (struct ipr_cmnd *);
1482
1483         struct ata_host ata_host;
1484         char ipr_cmd_label[8];
1485 #define IPR_CMD_LABEL           "ipr_cmd"
1486         struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
1487         dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
1488 }; /* struct ipr_ioa_cfg */
1489
1490 struct ipr_cmnd {
1491         struct ipr_ioarcb ioarcb;
1492         union {
1493                 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1494                 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1495                 struct ipr_ata64_ioadl ata_ioadl;
1496         } i;
1497         union {
1498                 struct ipr_ioasa ioasa;
1499                 struct ipr_ioasa64 ioasa64;
1500         } s;
1501         struct list_head queue;
1502         struct scsi_cmnd *scsi_cmd;
1503         struct ata_queued_cmd *qc;
1504         struct completion completion;
1505         struct timer_list timer;
1506         void (*done) (struct ipr_cmnd *);
1507         int (*job_step) (struct ipr_cmnd *);
1508         int (*job_step_failed) (struct ipr_cmnd *);
1509         u16 cmd_index;
1510         u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1511         dma_addr_t sense_buffer_dma;
1512         unsigned short dma_use_sg;
1513         dma_addr_t dma_addr;
1514         struct ipr_cmnd *sibling;
1515         union {
1516                 enum ipr_shutdown_type shutdown_type;
1517                 struct ipr_hostrcb *hostrcb;
1518                 unsigned long time_left;
1519                 unsigned long scratch;
1520                 struct ipr_resource_entry *res;
1521                 struct scsi_device *sdev;
1522         } u;
1523
1524         struct ipr_ioa_cfg *ioa_cfg;
1525 };
1526
1527 struct ipr_ses_table_entry {
1528         char product_id[17];
1529         char compare_product_id_byte[17];
1530         u32 max_bus_speed_limit;        /* MB/sec limit for this backplane */
1531 };
1532
1533 struct ipr_dump_header {
1534         u32 eye_catcher;
1535 #define IPR_DUMP_EYE_CATCHER            0xC5D4E3F2
1536         u32 len;
1537         u32 num_entries;
1538         u32 first_entry_offset;
1539         u32 status;
1540 #define IPR_DUMP_STATUS_SUCCESS                 0
1541 #define IPR_DUMP_STATUS_QUAL_SUCCESS            2
1542 #define IPR_DUMP_STATUS_FAILED                  0xffffffff
1543         u32 os;
1544 #define IPR_DUMP_OS_LINUX       0x4C4E5558
1545         u32 driver_name;
1546 #define IPR_DUMP_DRIVER_NAME    0x49505232
1547 }__attribute__((packed, aligned (4)));
1548
1549 struct ipr_dump_entry_header {
1550         u32 eye_catcher;
1551 #define IPR_DUMP_EYE_CATCHER            0xC5D4E3F2
1552         u32 len;
1553         u32 num_elems;
1554         u32 offset;
1555         u32 data_type;
1556 #define IPR_DUMP_DATA_TYPE_ASCII        0x41534349
1557 #define IPR_DUMP_DATA_TYPE_BINARY       0x42494E41
1558         u32 id;
1559 #define IPR_DUMP_IOA_DUMP_ID            0x494F4131
1560 #define IPR_DUMP_LOCATION_ID            0x4C4F4341
1561 #define IPR_DUMP_TRACE_ID               0x54524143
1562 #define IPR_DUMP_DRIVER_VERSION_ID      0x44525652
1563 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1564 #define IPR_DUMP_IOA_CTRL_BLK           0x494F4342
1565 #define IPR_DUMP_PEND_OPS               0x414F5053
1566         u32 status;
1567 }__attribute__((packed, aligned (4)));
1568
1569 struct ipr_dump_location_entry {
1570         struct ipr_dump_entry_header hdr;
1571         u8 location[20];
1572 }__attribute__((packed));
1573
1574 struct ipr_dump_trace_entry {
1575         struct ipr_dump_entry_header hdr;
1576         u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1577 }__attribute__((packed, aligned (4)));
1578
1579 struct ipr_dump_version_entry {
1580         struct ipr_dump_entry_header hdr;
1581         u8 version[sizeof(IPR_DRIVER_VERSION)];
1582 };
1583
1584 struct ipr_dump_ioa_type_entry {
1585         struct ipr_dump_entry_header hdr;
1586         u32 type;
1587         u32 fw_version;
1588 };
1589
1590 struct ipr_driver_dump {
1591         struct ipr_dump_header hdr;
1592         struct ipr_dump_version_entry version_entry;
1593         struct ipr_dump_location_entry location_entry;
1594         struct ipr_dump_ioa_type_entry ioa_type_entry;
1595         struct ipr_dump_trace_entry trace_entry;
1596 }__attribute__((packed));
1597
1598 struct ipr_ioa_dump {
1599         struct ipr_dump_entry_header hdr;
1600         struct ipr_sdt sdt;
1601         __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1602         u32 reserved;
1603         u32 next_page_index;
1604         u32 page_offset;
1605         u32 format;
1606 }__attribute__((packed, aligned (4)));
1607
1608 struct ipr_dump {
1609         struct kref kref;
1610         struct ipr_ioa_cfg *ioa_cfg;
1611         struct ipr_driver_dump driver_dump;
1612         struct ipr_ioa_dump ioa_dump;
1613 };
1614
1615 struct ipr_error_table_t {
1616         u32 ioasc;
1617         int log_ioasa;
1618         int log_hcam;
1619         char *error;
1620 };
1621
1622 struct ipr_software_inq_lid_info {
1623         __be32 load_id;
1624         __be32 timestamp[3];
1625 }__attribute__((packed, aligned (4)));
1626
1627 struct ipr_ucode_image_header {
1628         __be32 header_length;
1629         __be32 lid_table_offset;
1630         u8 major_release;
1631         u8 card_type;
1632         u8 minor_release[2];
1633         u8 reserved[20];
1634         char eyecatcher[16];
1635         __be32 num_lids;
1636         struct ipr_software_inq_lid_info lid[1];
1637 }__attribute__((packed, aligned (4)));
1638
1639 /*
1640  * Macros
1641  */
1642 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1643
1644 #ifdef CONFIG_SCSI_IPR_TRACE
1645 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1646 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1647 #else
1648 #define ipr_create_trace_file(kobj, attr) 0
1649 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1650 #endif
1651
1652 #ifdef CONFIG_SCSI_IPR_DUMP
1653 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1654 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1655 #else
1656 #define ipr_create_dump_file(kobj, attr) 0
1657 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1658 #endif
1659
1660 /*
1661  * Error logging macros
1662  */
1663 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1664 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1665 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1666
1667 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1668         printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1669                 bus, target, lun, ##__VA_ARGS__)
1670
1671 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1672         ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1673
1674 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1675         printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1676                 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1677
1678 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1679         ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1680
1681 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...)                        \
1682 {                                                                       \
1683         if ((res).bus >= IPR_MAX_NUM_BUSES) {                           \
1684                 ipr_err(fmt": unknown\n", ##__VA_ARGS__);               \
1685         } else {                                                        \
1686                 ipr_err(fmt": %d:%d:%d:%d\n",                           \
1687                         ##__VA_ARGS__, (ioa_cfg)->host->host_no,        \
1688                         (res).bus, (res).target, (res).lun);            \
1689         }                                                               \
1690 }
1691
1692 #define ipr_hcam_err(hostrcb, fmt, ...)                                 \
1693 {                                                                       \
1694         if (ipr_is_device(hostrcb)) {                                   \
1695                 if ((hostrcb)->ioa_cfg->sis64) {                        \
1696                         printk(KERN_ERR IPR_NAME ": %s: " fmt,          \
1697                                 ipr_format_res_path(hostrcb->hcam.u.error64.fd_res_path, \
1698                                         hostrcb->rp_buffer,             \
1699                                         sizeof(hostrcb->rp_buffer)),    \
1700                                 __VA_ARGS__);                           \
1701                 } else {                                                \
1702                         ipr_ra_err((hostrcb)->ioa_cfg,                  \
1703                                 (hostrcb)->hcam.u.error.fd_res_addr,    \
1704                                 fmt, __VA_ARGS__);                      \
1705                 }                                                       \
1706         } else {                                                        \
1707                 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1708         }                                                               \
1709 }
1710
1711 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1712         __FILE__, __func__, __LINE__)
1713
1714 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1715 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1716
1717 #define ipr_err_separator \
1718 ipr_err("----------------------------------------------------------\n")
1719
1720
1721 /*
1722  * Inlines
1723  */
1724
1725 /**
1726  * ipr_is_ioa_resource - Determine if a resource is the IOA
1727  * @res:        resource entry struct
1728  *
1729  * Return value:
1730  *      1 if IOA / 0 if not IOA
1731  **/
1732 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1733 {
1734         return res->type == IPR_RES_TYPE_IOAFP;
1735 }
1736
1737 /**
1738  * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1739  * @res:        resource entry struct
1740  *
1741  * Return value:
1742  *      1 if AF DASD / 0 if not AF DASD
1743  **/
1744 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1745 {
1746         return res->type == IPR_RES_TYPE_AF_DASD ||
1747                 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1748 }
1749
1750 /**
1751  * ipr_is_vset_device - Determine if a resource is a VSET
1752  * @res:        resource entry struct
1753  *
1754  * Return value:
1755  *      1 if VSET / 0 if not VSET
1756  **/
1757 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1758 {
1759         return res->type == IPR_RES_TYPE_VOLUME_SET;
1760 }
1761
1762 /**
1763  * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1764  * @res:        resource entry struct
1765  *
1766  * Return value:
1767  *      1 if GSCSI / 0 if not GSCSI
1768  **/
1769 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1770 {
1771         return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1772 }
1773
1774 /**
1775  * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1776  * @res:        resource entry struct
1777  *
1778  * Return value:
1779  *      1 if SCSI disk / 0 if not SCSI disk
1780  **/
1781 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1782 {
1783         if (ipr_is_af_dasd_device(res) ||
1784             (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1785                 return 1;
1786         else
1787                 return 0;
1788 }
1789
1790 /**
1791  * ipr_is_gata - Determine if a resource is a generic ATA resource
1792  * @res:        resource entry struct
1793  *
1794  * Return value:
1795  *      1 if GATA / 0 if not GATA
1796  **/
1797 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1798 {
1799         return res->type == IPR_RES_TYPE_GENERIC_ATA;
1800 }
1801
1802 /**
1803  * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1804  * @res:        resource entry struct
1805  *
1806  * Return value:
1807  *      1 if NACA queueing model / 0 if not NACA queueing model
1808  **/
1809 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1810 {
1811         if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1812                 return 1;
1813         return 0;
1814 }
1815
1816 /**
1817  * ipr_is_device - Determine if the hostrcb structure is related to a device
1818  * @hostrcb:    host resource control blocks struct
1819  *
1820  * Return value:
1821  *      1 if AF / 0 if not AF
1822  **/
1823 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1824 {
1825         struct ipr_res_addr *res_addr;
1826         u8 *res_path;
1827
1828         if (hostrcb->ioa_cfg->sis64) {
1829                 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1830                 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1831                     res_path[0] == 0x81) && res_path[2] != 0xFF)
1832                         return 1;
1833         } else {
1834                 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1835
1836                 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1837                     (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1838                         return 1;
1839         }
1840         return 0;
1841 }
1842
1843 /**
1844  * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1845  * @sdt_word:   SDT address
1846  *
1847  * Return value:
1848  *      1 if format 2 / 0 if not
1849  **/
1850 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1851 {
1852         u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1853
1854         switch (bar_sel) {
1855         case IPR_SDT_FMT2_BAR0_SEL:
1856         case IPR_SDT_FMT2_BAR1_SEL:
1857         case IPR_SDT_FMT2_BAR2_SEL:
1858         case IPR_SDT_FMT2_BAR3_SEL:
1859         case IPR_SDT_FMT2_BAR4_SEL:
1860         case IPR_SDT_FMT2_BAR5_SEL:
1861         case IPR_SDT_FMT2_EXP_ROM_SEL:
1862                 return 1;
1863         };
1864
1865         return 0;
1866 }
1867
1868 #ifndef writeq
1869 static inline void writeq(u64 val, void __iomem *addr)
1870 {
1871         writel(((u32) (val >> 32)), addr);
1872         writel(((u32) (val)), (addr + 4));
1873 }
1874 #endif
1875
1876 #endif /* _IPR_H */