arch/powerpc/kernel/power5+-pmu.c

   1 /*
   2  * Performance counter support for POWER5+/++ (not POWER5) processors.
   3  *
   4  * Copyright 2009 Paul Mackerras, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/perf_counter.h>
  13 #include <asm/reg.h>
  14
  15 /*
  16  * Bits in event code for POWER5+ (POWER5 GS) and POWER5++ (POWER5 GS DD3)
  17  */
  18 #define PM_PMC_SH       20      /* PMC number (1-based) for direct events */
  19 #define PM_PMC_MSK      0xf
  20 #define PM_PMC_MSKS     (PM_PMC_MSK << PM_PMC_SH)
  21 #define PM_UNIT_SH      16      /* TTMMUX number and setting - unit select */
  22 #define PM_UNIT_MSK     0xf
  23 #define PM_BYTE_SH      12      /* Byte number of event bus to use */
  24 #define PM_BYTE_MSK     7
  25 #define PM_GRS_SH       8       /* Storage subsystem mux select */
  26 #define PM_GRS_MSK      7
  27 #define PM_BUSEVENT_MSK 0x80    /* Set if event uses event bus */
  28 #define PM_PMCSEL_MSK   0x7f
  29
  30 /* Values in PM_UNIT field */
  31 #define PM_FPU          0
  32 #define PM_ISU0         1
  33 #define PM_IFU          2
  34 #define PM_ISU1         3
  35 #define PM_IDU          4
  36 #define PM_ISU0_ALT     6
  37 #define PM_GRS          7
  38 #define PM_LSU0         8
  39 #define PM_LSU1         0xc
  40 #define PM_LASTUNIT     0xc
  41
  42 /*
  43  * Bits in MMCR1 for POWER5+
  44  */
  45 #define MMCR1_TTM0SEL_SH        62
  46 #define MMCR1_TTM1SEL_SH        60
  47 #define MMCR1_TTM2SEL_SH        58
  48 #define MMCR1_TTM3SEL_SH        56
  49 #define MMCR1_TTMSEL_MSK        3
  50 #define MMCR1_TD_CP_DBG0SEL_SH  54
  51 #define MMCR1_TD_CP_DBG1SEL_SH  52
  52 #define MMCR1_TD_CP_DBG2SEL_SH  50
  53 #define MMCR1_TD_CP_DBG3SEL_SH  48
  54 #define MMCR1_GRS_L2SEL_SH      46
  55 #define MMCR1_GRS_L2SEL_MSK     3
  56 #define MMCR1_GRS_L3SEL_SH      44
  57 #define MMCR1_GRS_L3SEL_MSK     3
  58 #define MMCR1_GRS_MCSEL_SH      41
  59 #define MMCR1_GRS_MCSEL_MSK     7
  60 #define MMCR1_GRS_FABSEL_SH     39
  61 #define MMCR1_GRS_FABSEL_MSK    3
  62 #define MMCR1_PMC1_ADDER_SEL_SH 35
  63 #define MMCR1_PMC2_ADDER_SEL_SH 34
  64 #define MMCR1_PMC3_ADDER_SEL_SH 33
  65 #define MMCR1_PMC4_ADDER_SEL_SH 32
  66 #define MMCR1_PMC1SEL_SH        25
  67 #define MMCR1_PMC2SEL_SH        17
  68 #define MMCR1_PMC3SEL_SH        9
  69 #define MMCR1_PMC4SEL_SH        1
  70 #define MMCR1_PMCSEL_SH(n)      (MMCR1_PMC1SEL_SH - (n) * 8)
  71 #define MMCR1_PMCSEL_MSK        0x7f
  72
  73 /*
  74  * Bits in MMCRA
  75  */
  76
  77 /*
  78  * Layout of constraint bits:
  79  * 6666555555555544444444443333333333222222222211111111110000000000
  80  * 3210987654321098765432109876543210987654321098765432109876543210
  81  *             [  ><><>< ><> <><>[  >  <  ><  ><  ><  ><><><><><><>
  82  *             NC  G0G1G2 G3 T0T1 UC    B0  B1  B2  B3 P6P5P4P3P2P1
  83  *
  84  * NC - number of counters
  85  *     51: NC error 0x0008_0000_0000_0000
  86  *     48-50: number of events needing PMC1-4 0x0007_0000_0000_0000
  87  *
  88  * G0..G3 - GRS mux constraints
  89  *     46-47: GRS_L2SEL value
  90  *     44-45: GRS_L3SEL value
  91  *     41-44: GRS_MCSEL value
  92  *     39-40: GRS_FABSEL value
  93  *      Note that these match up with their bit positions in MMCR1
  94  *
  95  * T0 - TTM0 constraint
  96  *     36-37: TTM0SEL value (0=FPU, 2=IFU, 3=ISU1) 0x30_0000_0000
  97  *
  98  * T1 - TTM1 constraint
  99  *     34-35: TTM1SEL value (0=IDU, 3=GRS) 0x0c_0000_0000
 100  *
 101  * UC - unit constraint: can't have all three of FPU|IFU|ISU1, ISU0, IDU|GRS
 102  *     33: UC3 error 0x02_0000_0000
 103  *     32: FPU|IFU|ISU1 events needed 0x01_0000_0000
 104  *     31: ISU0 events needed 0x01_8000_0000
 105  *     30: IDU|GRS events needed 0x00_4000_0000
 106  *
 107  * B0
 108  *     24-27: Byte 0 event source 0x0f00_0000
 109  *            Encoding as for the event code
 110  *
 111  * B1, B2, B3
 112  *     20-23, 16-19, 12-15: Byte 1, 2, 3 event sources
 113  *
 114  * P6
 115  *     11: P6 error 0x800
 116  *     10-11: Count of events needing PMC6
 117  *
 118  * P1..P5
 119  *     0-9: Count of events needing PMC1..PMC5
 120  */
 121
 122 static const int grsel_shift[8] = {
 123         MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH,
 124         MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH,
 125         MMCR1_GRS_MCSEL_SH, MMCR1_GRS_FABSEL_SH
 126 };
 127
 128 /* Masks and values for using events from the various units */
 129 static unsigned long unit_cons[PM_LASTUNIT+1][2] = {
 130         [PM_FPU] =   { 0x3200000000ul, 0x0100000000ul },
 131         [PM_ISU0] =  { 0x0200000000ul, 0x0080000000ul },
 132         [PM_ISU1] =  { 0x3200000000ul, 0x3100000000ul },
 133         [PM_IFU] =   { 0x3200000000ul, 0x2100000000ul },
 134         [PM_IDU] =   { 0x0e00000000ul, 0x0040000000ul },
 135         [PM_GRS] =   { 0x0e00000000ul, 0x0c40000000ul },
 136 };
 137
 138 static int power5p_get_constraint(u64 event, unsigned long *maskp,
 139                                   unsigned long *valp)
 140 {
 141         int pmc, byte, unit, sh;
 142         int bit, fmask;
 143         unsigned long mask = 0, value = 0;
 144
 145         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 146         if (pmc) {
 147                 if (pmc > 6)
 148                         return -1;
 149                 sh = (pmc - 1) * 2;
 150                 mask |= 2 << sh;
 151                 value |= 1 << sh;
 152                 if (pmc >= 5 && !(event == 0x500009 || event == 0x600005))
 153                         return -1;
 154         }
 155         if (event & PM_BUSEVENT_MSK) {
 156                 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
 157                 if (unit > PM_LASTUNIT)
 158                         return -1;
 159                 if (unit == PM_ISU0_ALT)
 160                         unit = PM_ISU0;
 161                 mask |= unit_cons[unit][0];
 162                 value |= unit_cons[unit][1];
 163                 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
 164                 if (byte >= 4) {
 165                         if (unit != PM_LSU1)
 166                                 return -1;
 167                         /* Map LSU1 low word (bytes 4-7) to unit LSU1+1 */
 168                         ++unit;
 169                         byte &= 3;
 170                 }
 171                 if (unit == PM_GRS) {
 172                         bit = event & 7;
 173                         fmask = (bit == 6)? 7: 3;
 174                         sh = grsel_shift[bit];
 175                         mask |= (unsigned long)fmask << sh;
 176                         value |= (unsigned long)((event >> PM_GRS_SH) & fmask)
 177                                 << sh;
 178                 }
 179                 /* Set byte lane select field */
 180                 mask  |= 0xfUL << (24 - 4 * byte);
 181                 value |= (unsigned long)unit << (24 - 4 * byte);
 182         }
 183         if (pmc < 5) {
 184                 /* need a counter from PMC1-4 set */
 185                 mask  |= 0x8000000000000ul;
 186                 value |= 0x1000000000000ul;
 187         }
 188         *maskp = mask;
 189         *valp = value;
 190         return 0;
 191 }
 192
 193 static int power5p_limited_pmc_event(u64 event)
 194 {
 195         int pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 196
 197         return pmc == 5 || pmc == 6;
 198 }
 199
 200 #define MAX_ALT 3       /* at most 3 alternatives for any event */
 201
 202 static const unsigned int event_alternatives[][MAX_ALT] = {
 203         { 0x100c0,  0x40001f },                 /* PM_GCT_FULL_CYC */
 204         { 0x120e4,  0x400002 },                 /* PM_GRP_DISP_REJECT */
 205         { 0x230e2,  0x323087 },                 /* PM_BR_PRED_CR */
 206         { 0x230e3,  0x223087, 0x3230a0 },       /* PM_BR_PRED_TA */
 207         { 0x410c7,  0x441084 },                 /* PM_THRD_L2MISS_BOTH_CYC */
 208         { 0x800c4,  0xc20e0 },                  /* PM_DTLB_MISS */
 209         { 0xc50c6,  0xc60e0 },                  /* PM_MRK_DTLB_MISS */
 210         { 0x100005, 0x600005 },                 /* PM_RUN_CYC */
 211         { 0x100009, 0x200009 },                 /* PM_INST_CMPL */
 212         { 0x200015, 0x300015 },                 /* PM_LSU_LMQ_SRQ_EMPTY_CYC */
 213         { 0x300009, 0x400009 },                 /* PM_INST_DISP */
 214 };
 215
 216 /*
 217  * Scan the alternatives table for a match and return the
 218  * index into the alternatives table if found, else -1.
 219  */
 220 static int find_alternative(unsigned int event)
 221 {
 222         int i, j;
 223
 224         for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
 225                 if (event < event_alternatives[i][0])
 226                         break;
 227                 for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
 228                         if (event == event_alternatives[i][j])
 229                                 return i;
 230         }
 231         return -1;
 232 }
 233
 234 static const unsigned char bytedecode_alternatives[4][4] = {
 235         /* PMC 1 */     { 0x21, 0x23, 0x25, 0x27 },
 236         /* PMC 2 */     { 0x07, 0x17, 0x0e, 0x1e },
 237         /* PMC 3 */     { 0x20, 0x22, 0x24, 0x26 },
 238         /* PMC 4 */     { 0x07, 0x17, 0x0e, 0x1e }
 239 };
 240
 241 /*
 242  * Some direct events for decodes of event bus byte 3 have alternative
 243  * PMCSEL values on other counters.  This returns the alternative
 244  * event code for those that do, or -1 otherwise.  This also handles
 245  * alternative PCMSEL values for add events.
 246  */
 247 static s64 find_alternative_bdecode(u64 event)
 248 {
 249         int pmc, altpmc, pp, j;
 250
 251         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 252         if (pmc == 0 || pmc > 4)
 253                 return -1;
 254         altpmc = 5 - pmc;       /* 1 <-> 4, 2 <-> 3 */
 255         pp = event & PM_PMCSEL_MSK;
 256         for (j = 0; j < 4; ++j) {
 257                 if (bytedecode_alternatives[pmc - 1][j] == pp) {
 258                         return (event & ~(PM_PMC_MSKS | PM_PMCSEL_MSK)) |
 259                                 (altpmc << PM_PMC_SH) |
 260                                 bytedecode_alternatives[altpmc - 1][j];
 261                 }
 262         }
 263
 264         /* new decode alternatives for power5+ */
 265         if (pmc == 1 && (pp == 0x0d || pp == 0x0e))
 266                 return event + (2 << PM_PMC_SH) + (0x2e - 0x0d);
 267         if (pmc == 3 && (pp == 0x2e || pp == 0x2f))
 268                 return event - (2 << PM_PMC_SH) - (0x2e - 0x0d);
 269
 270         /* alternative add event encodings */
 271         if (pp == 0x10 || pp == 0x28)
 272                 return ((event ^ (0x10 ^ 0x28)) & ~PM_PMC_MSKS) |
 273                         (altpmc << PM_PMC_SH);
 274
 275         return -1;
 276 }
 277
 278 static int power5p_get_alternatives(u64 event, unsigned int flags, u64 alt[])
 279 {
 280         int i, j, nalt = 1;
 281         int nlim;
 282         s64 ae;
 283
 284         alt[0] = event;
 285         nalt = 1;
 286         nlim = power5p_limited_pmc_event(event);
 287         i = find_alternative(event);
 288         if (i >= 0) {
 289                 for (j = 0; j < MAX_ALT; ++j) {
 290                         ae = event_alternatives[i][j];
 291                         if (ae && ae != event)
 292                                 alt[nalt++] = ae;
 293                         nlim += power5p_limited_pmc_event(ae);
 294                 }
 295         } else {
 296                 ae = find_alternative_bdecode(event);
 297                 if (ae > 0)
 298                         alt[nalt++] = ae;
 299         }
 300
 301         if (flags & PPMU_ONLY_COUNT_RUN) {
 302                 /*
 303                  * We're only counting in RUN state,
 304                  * so PM_CYC is equivalent to PM_RUN_CYC
 305                  * and PM_INST_CMPL === PM_RUN_INST_CMPL.
 306                  * This doesn't include alternatives that don't provide
 307                  * any extra flexibility in assigning PMCs (e.g.
 308                  * 0x100005 for PM_RUN_CYC vs. 0xf for PM_CYC).
 309                  * Note that even with these additional alternatives
 310                  * we never end up with more than 3 alternatives for any event.
 311                  */
 312                 j = nalt;
 313                 for (i = 0; i < nalt; ++i) {
 314                         switch (alt[i]) {
 315                         case 0xf:       /* PM_CYC */
 316                                 alt[j++] = 0x600005;    /* PM_RUN_CYC */
 317                                 ++nlim;
 318                                 break;
 319                         case 0x600005:  /* PM_RUN_CYC */
 320                                 alt[j++] = 0xf;
 321                                 break;
 322                         case 0x100009:  /* PM_INST_CMPL */
 323                                 alt[j++] = 0x500009;    /* PM_RUN_INST_CMPL */
 324                                 ++nlim;
 325                                 break;
 326                         case 0x500009:  /* PM_RUN_INST_CMPL */
 327                                 alt[j++] = 0x100009;    /* PM_INST_CMPL */
 328                                 alt[j++] = 0x200009;
 329                                 break;
 330                         }
 331                 }
 332                 nalt = j;
 333         }
 334
 335         if (!(flags & PPMU_LIMITED_PMC_OK) && nlim) {
 336                 /* remove the limited PMC events */
 337                 j = 0;
 338                 for (i = 0; i < nalt; ++i) {
 339                         if (!power5p_limited_pmc_event(alt[i])) {
 340                                 alt[j] = alt[i];
 341                                 ++j;
 342                         }
 343                 }
 344                 nalt = j;
 345         } else if ((flags & PPMU_LIMITED_PMC_REQD) && nlim < nalt) {
 346                 /* remove all but the limited PMC events */
 347                 j = 0;
 348                 for (i = 0; i < nalt; ++i) {
 349                         if (power5p_limited_pmc_event(alt[i])) {
 350                                 alt[j] = alt[i];
 351                                 ++j;
 352                         }
 353                 }
 354                 nalt = j;
 355         }
 356
 357         return nalt;
 358 }
 359
 360 /*
 361  * Map of which direct events on which PMCs are marked instruction events.
 362  * Indexed by PMCSEL value, bit i (LE) set if PMC i is a marked event.
 363  * Bit 0 is set if it is marked for all PMCs.
 364  * The 0x80 bit indicates a byte decode PMCSEL value.
 365  */
 366 static unsigned char direct_event_is_marked[0x28] = {
 367         0,      /* 00 */
 368         0x1f,   /* 01 PM_IOPS_CMPL */
 369         0x2,    /* 02 PM_MRK_GRP_DISP */
 370         0xe,    /* 03 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
 371         0,      /* 04 */
 372         0x1c,   /* 05 PM_MRK_BRU_FIN, PM_MRK_INST_FIN, PM_MRK_CRU_FIN */
 373         0x80,   /* 06 */
 374         0x80,   /* 07 */
 375         0, 0, 0,/* 08 - 0a */
 376         0x18,   /* 0b PM_THRESH_TIMEO, PM_MRK_GRP_TIMEO */
 377         0,      /* 0c */
 378         0x80,   /* 0d */
 379         0x80,   /* 0e */
 380         0,      /* 0f */
 381         0,      /* 10 */
 382         0x14,   /* 11 PM_MRK_GRP_BR_REDIR, PM_MRK_GRP_IC_MISS */
 383         0,      /* 12 */
 384         0x10,   /* 13 PM_MRK_GRP_CMPL */
 385         0x1f,   /* 14 PM_GRP_MRK, PM_MRK_{FXU,FPU,LSU}_FIN */
 386         0x2,    /* 15 PM_MRK_GRP_ISSUED */
 387         0x80,   /* 16 */
 388         0x80,   /* 17 */
 389         0, 0, 0, 0, 0,
 390         0x80,   /* 1d */
 391         0x80,   /* 1e */
 392         0,      /* 1f */
 393         0x80,   /* 20 */
 394         0x80,   /* 21 */
 395         0x80,   /* 22 */
 396         0x80,   /* 23 */
 397         0x80,   /* 24 */
 398         0x80,   /* 25 */
 399         0x80,   /* 26 */
 400         0x80,   /* 27 */
 401 };
 402
 403 /*
 404  * Returns 1 if event counts things relating to marked instructions
 405  * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
 406  */
 407 static int power5p_marked_instr_event(u64 event)
 408 {
 409         int pmc, psel;
 410         int bit, byte, unit;
 411         u32 mask;
 412
 413         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 414         psel = event & PM_PMCSEL_MSK;
 415         if (pmc >= 5)
 416                 return 0;
 417
 418         bit = -1;
 419         if (psel < sizeof(direct_event_is_marked)) {
 420                 if (direct_event_is_marked[psel] & (1 << pmc))
 421                         return 1;
 422                 if (direct_event_is_marked[psel] & 0x80)
 423                         bit = 4;
 424                 else if (psel == 0x08)
 425                         bit = pmc - 1;
 426                 else if (psel == 0x10)
 427                         bit = 4 - pmc;
 428                 else if (psel == 0x1b && (pmc == 1 || pmc == 3))
 429                         bit = 4;
 430         } else if ((psel & 0x48) == 0x40) {
 431                 bit = psel & 7;
 432         } else if (psel == 0x28) {
 433                 bit = pmc - 1;
 434         } else if (pmc == 3 && (psel == 0x2e || psel == 0x2f)) {
 435                 bit = 4;
 436         }
 437
 438         if (!(event & PM_BUSEVENT_MSK) || bit == -1)
 439                 return 0;
 440
 441         byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
 442         unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
 443         if (unit == PM_LSU0) {
 444                 /* byte 1 bits 0-7, byte 2 bits 0,2-4,6 */
 445                 mask = 0x5dff00;
 446         } else if (unit == PM_LSU1 && byte >= 4) {
 447                 byte -= 4;
 448                 /* byte 5 bits 6-7, byte 6 bits 0,4, byte 7 bits 0-4,6 */
 449                 mask = 0x5f11c000;
 450         } else
 451                 return 0;
 452
 453         return (mask >> (byte * 8 + bit)) & 1;
 454 }
 455
 456 static int power5p_compute_mmcr(u64 event[], int n_ev,
 457                                 unsigned int hwc[], unsigned long mmcr[])
 458 {
 459         unsigned long mmcr1 = 0;
 460         unsigned long mmcra = 0;
 461         unsigned int pmc, unit, byte, psel;
 462         unsigned int ttm;
 463         int i, isbus, bit, grsel;
 464         unsigned int pmc_inuse = 0;
 465         unsigned char busbyte[4];
 466         unsigned char unituse[16];
 467         int ttmuse;
 468
 469         if (n_ev > 6)
 470                 return -1;
 471
 472         /* First pass to count resource use */
 473         memset(busbyte, 0, sizeof(busbyte));
 474         memset(unituse, 0, sizeof(unituse));
 475         for (i = 0; i < n_ev; ++i) {
 476                 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
 477                 if (pmc) {
 478                         if (pmc > 6)
 479                                 return -1;
 480                         if (pmc_inuse & (1 << (pmc - 1)))
 481                                 return -1;
 482                         pmc_inuse |= 1 << (pmc - 1);
 483                 }
 484                 if (event[i] & PM_BUSEVENT_MSK) {
 485                         unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
 486                         byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
 487                         if (unit > PM_LASTUNIT)
 488                                 return -1;
 489                         if (unit == PM_ISU0_ALT)
 490                                 unit = PM_ISU0;
 491                         if (byte >= 4) {
 492                                 if (unit != PM_LSU1)
 493                                         return -1;
 494                                 ++unit;
 495                                 byte &= 3;
 496                         }
 497                         if (busbyte[byte] && busbyte[byte] != unit)
 498                                 return -1;
 499                         busbyte[byte] = unit;
 500                         unituse[unit] = 1;
 501                 }
 502         }
 503
 504         /*
 505          * Assign resources and set multiplexer selects.
 506          *
 507          * PM_ISU0 can go either on TTM0 or TTM1, but that's the only
 508          * choice we have to deal with.
 509          */
 510         if (unituse[PM_ISU0] &
 511             (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_ISU1])) {
 512                 unituse[PM_ISU0_ALT] = 1;       /* move ISU to TTM1 */
 513                 unituse[PM_ISU0] = 0;
 514         }
 515         /* Set TTM[01]SEL fields. */
 516         ttmuse = 0;
 517         for (i = PM_FPU; i <= PM_ISU1; ++i) {
 518                 if (!unituse[i])
 519                         continue;
 520                 if (ttmuse++)
 521                         return -1;
 522                 mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH;
 523         }
 524         ttmuse = 0;
 525         for (; i <= PM_GRS; ++i) {
 526                 if (!unituse[i])
 527                         continue;
 528                 if (ttmuse++)
 529                         return -1;
 530                 mmcr1 |= (unsigned long)(i & 3) << MMCR1_TTM1SEL_SH;
 531         }
 532         if (ttmuse > 1)
 533                 return -1;
 534
 535         /* Set byte lane select fields, TTM[23]SEL and GRS_*SEL. */
 536         for (byte = 0; byte < 4; ++byte) {
 537                 unit = busbyte[byte];
 538                 if (!unit)
 539                         continue;
 540                 if (unit == PM_ISU0 && unituse[PM_ISU0_ALT]) {
 541                         /* get ISU0 through TTM1 rather than TTM0 */
 542                         unit = PM_ISU0_ALT;
 543                 } else if (unit == PM_LSU1 + 1) {
 544                         /* select lower word of LSU1 for this byte */
 545                         mmcr1 |= 1ul << (MMCR1_TTM3SEL_SH + 3 - byte);
 546                 }
 547                 ttm = unit >> 2;
 548                 mmcr1 |= (unsigned long)ttm
 549                         << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
 550         }
 551
 552         /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
 553         for (i = 0; i < n_ev; ++i) {
 554                 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
 555                 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
 556                 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
 557                 psel = event[i] & PM_PMCSEL_MSK;
 558                 isbus = event[i] & PM_BUSEVENT_MSK;
 559                 if (!pmc) {
 560                         /* Bus event or any-PMC direct event */
 561                         for (pmc = 0; pmc < 4; ++pmc) {
 562                                 if (!(pmc_inuse & (1 << pmc)))
 563                                         break;
 564                         }
 565                         if (pmc >= 4)
 566                                 return -1;
 567                         pmc_inuse |= 1 << pmc;
 568                 } else if (pmc <= 4) {
 569                         /* Direct event */
 570                         --pmc;
 571                         if (isbus && (byte & 2) &&
 572                             (psel == 8 || psel == 0x10 || psel == 0x28))
 573                                 /* add events on higher-numbered bus */
 574                                 mmcr1 |= 1ul << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
 575                 } else {
 576                         /* Instructions or run cycles on PMC5/6 */
 577                         --pmc;
 578                 }
 579                 if (isbus && unit == PM_GRS) {
 580                         bit = psel & 7;
 581                         grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;
 582                         mmcr1 |= (unsigned long)grsel << grsel_shift[bit];
 583                 }
 584                 if (power5p_marked_instr_event(event[i]))
 585                         mmcra |= MMCRA_SAMPLE_ENABLE;
 586                 if ((psel & 0x58) == 0x40 && (byte & 1) != ((pmc >> 1) & 1))
 587                         /* select alternate byte lane */
 588                         psel |= 0x10;
 589                 if (pmc <= 3)
 590                         mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
 591                 hwc[i] = pmc;
 592         }
 593
 594         /* Return MMCRx values */
 595         mmcr[0] = 0;
 596         if (pmc_inuse & 1)
 597                 mmcr[0] = MMCR0_PMC1CE;
 598         if (pmc_inuse & 0x3e)
 599                 mmcr[0] |= MMCR0_PMCjCE;
 600         mmcr[1] = mmcr1;
 601         mmcr[2] = mmcra;
 602         return 0;
 603 }
 604
 605 static void power5p_disable_pmc(unsigned int pmc, unsigned long mmcr[])
 606 {
 607         if (pmc <= 3)
 608                 mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
 609 }
 610
 611 static int power5p_generic_events[] = {
 612         [PERF_COUNT_HW_CPU_CYCLES]              = 0xf,
 613         [PERF_COUNT_HW_INSTRUCTIONS]            = 0x100009,
 614         [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x1c10a8, /* LD_REF_L1 */
 615         [PERF_COUNT_HW_CACHE_MISSES]            = 0x3c1088, /* LD_MISS_L1 */
 616         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x230e4,  /* BR_ISSUED */
 617         [PERF_COUNT_HW_BRANCH_MISSES]           = 0x230e5,  /* BR_MPRED_CR */
 618 };
 619
 620 #define C(x)    PERF_COUNT_HW_CACHE_##x
 621
 622 /*
 623  * Table of generalized cache-related events.
 624  * 0 means not supported, -1 means nonsensical, other values
 625  * are event codes.
 626  */
 627 static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 628         [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 629                 [C(OP_READ)] = {        0x1c10a8,       0x3c1088        },
 630                 [C(OP_WRITE)] = {       0x2c10a8,       0xc10c3         },
 631                 [C(OP_PREFETCH)] = {    0xc70e7,        -1              },
 632         },
 633         [C(L1I)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 634                 [C(OP_READ)] = {        0,              0               },
 635                 [C(OP_WRITE)] = {       -1,             -1              },
 636                 [C(OP_PREFETCH)] = {    0,              0               },
 637         },
 638         [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
 639                 [C(OP_READ)] = {        0,              0               },
 640                 [C(OP_WRITE)] = {       0,              0               },
 641                 [C(OP_PREFETCH)] = {    0xc50c3,        0               },
 642         },
 643         [C(DTLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
 644                 [C(OP_READ)] = {        0xc20e4,        0x800c4         },
 645                 [C(OP_WRITE)] = {       -1,             -1              },
 646                 [C(OP_PREFETCH)] = {    -1,             -1              },
 647         },
 648         [C(ITLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
 649                 [C(OP_READ)] = {        0,              0x800c0         },
 650                 [C(OP_WRITE)] = {       -1,             -1              },
 651                 [C(OP_PREFETCH)] = {    -1,             -1              },
 652         },
 653         [C(BPU)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 654                 [C(OP_READ)] = {        0x230e4,        0x230e5         },
 655                 [C(OP_WRITE)] = {       -1,             -1              },
 656                 [C(OP_PREFETCH)] = {    -1,             -1              },
 657         },
 658 };
 659
 660 struct power_pmu power5p_pmu = {
 661         .n_counter              = 6,
 662         .max_alternatives       = MAX_ALT,
 663         .add_fields             = 0x7000000000055ul,
 664         .test_adder             = 0x3000040000000ul,
 665         .compute_mmcr           = power5p_compute_mmcr,
 666         .get_constraint         = power5p_get_constraint,
 667         .get_alternatives       = power5p_get_alternatives,
 668         .disable_pmc            = power5p_disable_pmc,
 669         .limited_pmc_event      = power5p_limited_pmc_event,
 670         .flags                  = PPMU_LIMITED_PMC5_6,
 671         .n_generic              = ARRAY_SIZE(power5p_generic_events),
 672         .generic_events         = power5p_generic_events,
 673         .cache_events           = &power5p_cache_events,
 674 };