2 * AMD K7 AGPGART routines.
5 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/agp_backend.h>
9 #include <linux/page-flags.h>
11 #include <linux/slab.h>
14 #define AMD_MMBASE 0x14
15 #define AMD_APSIZE 0xac
16 #define AMD_MODECNTL 0xb0
17 #define AMD_MODECNTL2 0xb2
18 #define AMD_GARTENABLE 0x02 /* In mmio region (16-bit register) */
19 #define AMD_ATTBASE 0x04 /* In mmio region (32-bit register) */
20 #define AMD_TLBFLUSH 0x0c /* In mmio region (32-bit register) */
21 #define AMD_CACHEENTRY 0x10 /* In mmio region (32-bit register) */
23 static struct pci_device_id agp_amdk7_pci_table
[];
27 unsigned long __iomem
*remapped
;
30 static struct _amd_irongate_private
{
31 volatile u8 __iomem
*registers
;
32 struct amd_page_map
**gatt_pages
;
34 } amd_irongate_private
;
36 static int amd_create_page_map(struct amd_page_map
*page_map
)
40 page_map
->real
= (unsigned long *) __get_free_page(GFP_KERNEL
);
41 if (page_map
->real
== NULL
)
45 SetPageReserved(virt_to_page(page_map
->real
));
47 page_map
->remapped
= ioremap_nocache(virt_to_phys(page_map
->real
),
49 if (page_map
->remapped
== NULL
) {
50 ClearPageReserved(virt_to_page(page_map
->real
));
51 free_page((unsigned long) page_map
->real
);
52 page_map
->real
= NULL
;
57 set_memory_uc((unsigned long)page_map
->real
, 1);
58 page_map
->remapped
= page_map
->real
;
61 for (i
= 0; i
< PAGE_SIZE
/ sizeof(unsigned long); i
++) {
62 writel(agp_bridge
->scratch_page
, page_map
->remapped
+i
);
63 readl(page_map
->remapped
+i
); /* PCI Posting. */
69 static void amd_free_page_map(struct amd_page_map
*page_map
)
72 iounmap(page_map
->remapped
);
73 ClearPageReserved(virt_to_page(page_map
->real
));
75 set_memory_wb((unsigned long)page_map
->real
, 1);
77 free_page((unsigned long) page_map
->real
);
80 static void amd_free_gatt_pages(void)
83 struct amd_page_map
**tables
;
84 struct amd_page_map
*entry
;
86 tables
= amd_irongate_private
.gatt_pages
;
87 for (i
= 0; i
< amd_irongate_private
.num_tables
; i
++) {
90 if (entry
->real
!= NULL
)
91 amd_free_page_map(entry
);
96 amd_irongate_private
.gatt_pages
= NULL
;
99 static int amd_create_gatt_pages(int nr_tables
)
101 struct amd_page_map
**tables
;
102 struct amd_page_map
*entry
;
106 tables
= kzalloc((nr_tables
+ 1) * sizeof(struct amd_page_map
*),GFP_KERNEL
);
110 for (i
= 0; i
< nr_tables
; i
++) {
111 entry
= kzalloc(sizeof(struct amd_page_map
), GFP_KERNEL
);
117 retval
= amd_create_page_map(entry
);
121 amd_irongate_private
.num_tables
= i
;
122 amd_irongate_private
.gatt_pages
= tables
;
125 amd_free_gatt_pages();
130 /* Since we don't need contiguous memory we just try
131 * to get the gatt table once
134 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
135 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
136 GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
137 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
138 #define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
139 GET_PAGE_DIR_IDX(addr)]->remapped)
141 static int amd_create_gatt_table(struct agp_bridge_data
*bridge
)
143 struct aper_size_info_lvl2
*value
;
144 struct amd_page_map page_dir
;
150 value
= A_SIZE_LVL2(agp_bridge
->current_size
);
151 retval
= amd_create_page_map(&page_dir
);
155 retval
= amd_create_gatt_pages(value
->num_entries
/ 1024);
157 amd_free_page_map(&page_dir
);
161 agp_bridge
->gatt_table_real
= (u32
*)page_dir
.real
;
162 agp_bridge
->gatt_table
= (u32 __iomem
*)page_dir
.remapped
;
163 agp_bridge
->gatt_bus_addr
= virt_to_phys(page_dir
.real
);
165 /* Get the address for the gart region.
166 * This is a bus address even on the alpha, b/c its
167 * used to program the agp master not the cpu
170 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
171 addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
172 agp_bridge
->gart_bus_addr
= addr
;
174 /* Calculate the agp offset */
175 for (i
= 0; i
< value
->num_entries
/ 1024; i
++, addr
+= 0x00400000) {
176 writel(virt_to_phys(amd_irongate_private
.gatt_pages
[i
]->real
) | 1,
177 page_dir
.remapped
+GET_PAGE_DIR_OFF(addr
));
178 readl(page_dir
.remapped
+GET_PAGE_DIR_OFF(addr
)); /* PCI Posting. */
184 static int amd_free_gatt_table(struct agp_bridge_data
*bridge
)
186 struct amd_page_map page_dir
;
188 page_dir
.real
= (unsigned long *)agp_bridge
->gatt_table_real
;
189 page_dir
.remapped
= (unsigned long __iomem
*)agp_bridge
->gatt_table
;
191 amd_free_gatt_pages();
192 amd_free_page_map(&page_dir
);
196 static int amd_irongate_fetch_size(void)
200 struct aper_size_info_lvl2
*values
;
202 pci_read_config_dword(agp_bridge
->dev
, AMD_APSIZE
, &temp
);
203 temp
= (temp
& 0x0000000e);
204 values
= A_SIZE_LVL2(agp_bridge
->driver
->aperture_sizes
);
205 for (i
= 0; i
< agp_bridge
->driver
->num_aperture_sizes
; i
++) {
206 if (temp
== values
[i
].size_value
) {
207 agp_bridge
->previous_size
=
208 agp_bridge
->current_size
= (void *) (values
+ i
);
210 agp_bridge
->aperture_size_idx
= i
;
211 return values
[i
].size
;
218 static int amd_irongate_configure(void)
220 struct aper_size_info_lvl2
*current_size
;
224 current_size
= A_SIZE_LVL2(agp_bridge
->current_size
);
226 if (!amd_irongate_private
.registers
) {
227 /* Get the memory mapped registers */
228 pci_read_config_dword(agp_bridge
->dev
, AMD_MMBASE
, &temp
);
229 temp
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
230 amd_irongate_private
.registers
= (volatile u8 __iomem
*) ioremap(temp
, 4096);
231 if (!amd_irongate_private
.registers
)
235 /* Write out the address of the gatt table */
236 writel(agp_bridge
->gatt_bus_addr
, amd_irongate_private
.registers
+AMD_ATTBASE
);
237 readl(amd_irongate_private
.registers
+AMD_ATTBASE
); /* PCI Posting. */
239 /* Write the Sync register */
240 pci_write_config_byte(agp_bridge
->dev
, AMD_MODECNTL
, 0x80);
242 /* Set indexing mode */
243 pci_write_config_byte(agp_bridge
->dev
, AMD_MODECNTL2
, 0x00);
245 /* Write the enable register */
246 enable_reg
= readw(amd_irongate_private
.registers
+AMD_GARTENABLE
);
247 enable_reg
= (enable_reg
| 0x0004);
248 writew(enable_reg
, amd_irongate_private
.registers
+AMD_GARTENABLE
);
249 readw(amd_irongate_private
.registers
+AMD_GARTENABLE
); /* PCI Posting. */
251 /* Write out the size register */
252 pci_read_config_dword(agp_bridge
->dev
, AMD_APSIZE
, &temp
);
253 temp
= (((temp
& ~(0x0000000e)) | current_size
->size_value
) | 1);
254 pci_write_config_dword(agp_bridge
->dev
, AMD_APSIZE
, temp
);
257 writel(1, amd_irongate_private
.registers
+AMD_TLBFLUSH
);
258 readl(amd_irongate_private
.registers
+AMD_TLBFLUSH
); /* PCI Posting.*/
262 static void amd_irongate_cleanup(void)
264 struct aper_size_info_lvl2
*previous_size
;
268 previous_size
= A_SIZE_LVL2(agp_bridge
->previous_size
);
270 enable_reg
= readw(amd_irongate_private
.registers
+AMD_GARTENABLE
);
271 enable_reg
= (enable_reg
& ~(0x0004));
272 writew(enable_reg
, amd_irongate_private
.registers
+AMD_GARTENABLE
);
273 readw(amd_irongate_private
.registers
+AMD_GARTENABLE
); /* PCI Posting. */
275 /* Write back the previous size and disable gart translation */
276 pci_read_config_dword(agp_bridge
->dev
, AMD_APSIZE
, &temp
);
277 temp
= ((temp
& ~(0x0000000f)) | previous_size
->size_value
);
278 pci_write_config_dword(agp_bridge
->dev
, AMD_APSIZE
, temp
);
279 iounmap((void __iomem
*) amd_irongate_private
.registers
);
283 * This routine could be implemented by taking the addresses
284 * written to the GATT, and flushing them individually. However
285 * currently it just flushes the whole table. Which is probably
286 * more efficent, since agp_memory blocks can be a large number of
290 static void amd_irongate_tlbflush(struct agp_memory
*temp
)
292 writel(1, amd_irongate_private
.registers
+AMD_TLBFLUSH
);
293 readl(amd_irongate_private
.registers
+AMD_TLBFLUSH
); /* PCI Posting. */
296 static int amd_insert_memory(struct agp_memory
*mem
, off_t pg_start
, int type
)
298 int i
, j
, num_entries
;
299 unsigned long __iomem
*cur_gatt
;
302 num_entries
= A_SIZE_LVL2(agp_bridge
->current_size
)->num_entries
;
304 if (type
!= 0 || mem
->type
!= 0)
307 if ((pg_start
+ mem
->page_count
) > num_entries
)
311 while (j
< (pg_start
+ mem
->page_count
)) {
312 addr
= (j
* PAGE_SIZE
) + agp_bridge
->gart_bus_addr
;
313 cur_gatt
= GET_GATT(addr
);
314 if (!PGE_EMPTY(agp_bridge
, readl(cur_gatt
+GET_GATT_OFF(addr
))))
319 if (!mem
->is_flushed
) {
320 global_cache_flush();
321 mem
->is_flushed
= true;
324 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
325 addr
= (j
* PAGE_SIZE
) + agp_bridge
->gart_bus_addr
;
326 cur_gatt
= GET_GATT(addr
);
327 writel(agp_generic_mask_memory(agp_bridge
,
328 page_to_phys(mem
->pages
[i
]),
330 cur_gatt
+GET_GATT_OFF(addr
));
331 readl(cur_gatt
+GET_GATT_OFF(addr
)); /* PCI Posting. */
333 amd_irongate_tlbflush(mem
);
337 static int amd_remove_memory(struct agp_memory
*mem
, off_t pg_start
, int type
)
340 unsigned long __iomem
*cur_gatt
;
343 if (type
!= 0 || mem
->type
!= 0)
346 for (i
= pg_start
; i
< (mem
->page_count
+ pg_start
); i
++) {
347 addr
= (i
* PAGE_SIZE
) + agp_bridge
->gart_bus_addr
;
348 cur_gatt
= GET_GATT(addr
);
349 writel(agp_bridge
->scratch_page
, cur_gatt
+GET_GATT_OFF(addr
));
350 readl(cur_gatt
+GET_GATT_OFF(addr
)); /* PCI Posting. */
353 amd_irongate_tlbflush(mem
);
357 static const struct aper_size_info_lvl2 amd_irongate_sizes
[7] =
359 {2048, 524288, 0x0000000c},
360 {1024, 262144, 0x0000000a},
361 {512, 131072, 0x00000008},
362 {256, 65536, 0x00000006},
363 {128, 32768, 0x00000004},
364 {64, 16384, 0x00000002},
365 {32, 8192, 0x00000000}
368 static const struct gatt_mask amd_irongate_masks
[] =
370 {.mask
= 1, .type
= 0}
373 static const struct agp_bridge_driver amd_irongate_driver
= {
374 .owner
= THIS_MODULE
,
375 .aperture_sizes
= amd_irongate_sizes
,
376 .size_type
= LVL2_APER_SIZE
,
377 .num_aperture_sizes
= 7,
378 .configure
= amd_irongate_configure
,
379 .fetch_size
= amd_irongate_fetch_size
,
380 .cleanup
= amd_irongate_cleanup
,
381 .tlb_flush
= amd_irongate_tlbflush
,
382 .mask_memory
= agp_generic_mask_memory
,
383 .masks
= amd_irongate_masks
,
384 .agp_enable
= agp_generic_enable
,
385 .cache_flush
= global_cache_flush
,
386 .create_gatt_table
= amd_create_gatt_table
,
387 .free_gatt_table
= amd_free_gatt_table
,
388 .insert_memory
= amd_insert_memory
,
389 .remove_memory
= amd_remove_memory
,
390 .alloc_by_type
= agp_generic_alloc_by_type
,
391 .free_by_type
= agp_generic_free_by_type
,
392 .agp_alloc_page
= agp_generic_alloc_page
,
393 .agp_alloc_pages
= agp_generic_alloc_pages
,
394 .agp_destroy_page
= agp_generic_destroy_page
,
395 .agp_destroy_pages
= agp_generic_destroy_pages
,
396 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
399 static struct agp_device_ids amd_agp_device_ids
[] __devinitdata
=
402 .device_id
= PCI_DEVICE_ID_AMD_FE_GATE_7006
,
403 .chipset_name
= "Irongate",
406 .device_id
= PCI_DEVICE_ID_AMD_FE_GATE_700E
,
407 .chipset_name
= "761",
410 .device_id
= PCI_DEVICE_ID_AMD_FE_GATE_700C
,
411 .chipset_name
= "760MP",
413 { }, /* dummy final entry, always present */
416 static int __devinit
agp_amdk7_probe(struct pci_dev
*pdev
,
417 const struct pci_device_id
*ent
)
419 struct agp_bridge_data
*bridge
;
423 cap_ptr
= pci_find_capability(pdev
, PCI_CAP_ID_AGP
);
427 j
= ent
- agp_amdk7_pci_table
;
428 dev_info(&pdev
->dev
, "AMD %s chipset\n",
429 amd_agp_device_ids
[j
].chipset_name
);
431 bridge
= agp_alloc_bridge();
435 bridge
->driver
= &amd_irongate_driver
;
436 bridge
->dev_private_data
= &amd_irongate_private
,
438 bridge
->capndx
= cap_ptr
;
440 /* 751 Errata (22564_B-1.PDF)
441 erratum 20: strobe glitch with Nvidia NV10 GeForce cards.
442 system controller may experience noise due to strong drive strengths
444 if (agp_bridge
->dev
->device
== PCI_DEVICE_ID_AMD_FE_GATE_7006
) {
445 struct pci_dev
*gfxcard
=NULL
;
449 gfxcard
= pci_get_class(PCI_CLASS_DISPLAY_VGA
<<8, gfxcard
);
451 dev_info(&pdev
->dev
, "no AGP VGA controller\n");
454 cap_ptr
= pci_find_capability(gfxcard
, PCI_CAP_ID_AGP
);
457 /* With so many variants of NVidia cards, it's simpler just
458 to blacklist them all, and then whitelist them as needed
459 (if necessary at all). */
460 if (gfxcard
->vendor
== PCI_VENDOR_ID_NVIDIA
) {
461 agp_bridge
->flags
|= AGP_ERRATA_1X
;
462 dev_info(&pdev
->dev
, "AMD 751 chipset with NVidia GeForce; forcing 1X due to errata\n");
464 pci_dev_put(gfxcard
);
467 /* 761 Errata (23613_F.pdf)
468 * Revisions B0/B1 were a disaster.
469 * erratum 44: SYSCLK/AGPCLK skew causes 2X failures -- Force mode to 1X
470 * erratum 45: Timing problem prevents fast writes -- Disable fast write.
471 * erratum 46: Setup violation on AGP SBA pins - Disable side band addressing.
472 * With this lot disabled, we should prevent lockups. */
473 if (agp_bridge
->dev
->device
== PCI_DEVICE_ID_AMD_FE_GATE_700E
) {
474 if (pdev
->revision
== 0x10 || pdev
->revision
== 0x11) {
475 agp_bridge
->flags
= AGP_ERRATA_FASTWRITES
;
476 agp_bridge
->flags
|= AGP_ERRATA_SBA
;
477 agp_bridge
->flags
|= AGP_ERRATA_1X
;
478 dev_info(&pdev
->dev
, "AMD 761 chipset with errata; disabling AGP fast writes & SBA and forcing to 1X\n");
482 /* Fill in the mode register */
483 pci_read_config_dword(pdev
,
484 bridge
->capndx
+PCI_AGP_STATUS
,
487 pci_set_drvdata(pdev
, bridge
);
488 return agp_add_bridge(bridge
);
491 static void __devexit
agp_amdk7_remove(struct pci_dev
*pdev
)
493 struct agp_bridge_data
*bridge
= pci_get_drvdata(pdev
);
495 agp_remove_bridge(bridge
);
496 agp_put_bridge(bridge
);
501 static int agp_amdk7_suspend(struct pci_dev
*pdev
, pm_message_t state
)
503 pci_save_state(pdev
);
504 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
509 static int agp_amdk7_resume(struct pci_dev
*pdev
)
511 pci_set_power_state(pdev
, PCI_D0
);
512 pci_restore_state(pdev
);
514 return amd_irongate_driver
.configure();
517 #endif /* CONFIG_PM */
519 /* must be the same order as name table above */
520 static struct pci_device_id agp_amdk7_pci_table
[] = {
522 .class = (PCI_CLASS_BRIDGE_HOST
<< 8),
524 .vendor
= PCI_VENDOR_ID_AMD
,
525 .device
= PCI_DEVICE_ID_AMD_FE_GATE_7006
,
526 .subvendor
= PCI_ANY_ID
,
527 .subdevice
= PCI_ANY_ID
,
530 .class = (PCI_CLASS_BRIDGE_HOST
<< 8),
532 .vendor
= PCI_VENDOR_ID_AMD
,
533 .device
= PCI_DEVICE_ID_AMD_FE_GATE_700E
,
534 .subvendor
= PCI_ANY_ID
,
535 .subdevice
= PCI_ANY_ID
,
538 .class = (PCI_CLASS_BRIDGE_HOST
<< 8),
540 .vendor
= PCI_VENDOR_ID_AMD
,
541 .device
= PCI_DEVICE_ID_AMD_FE_GATE_700C
,
542 .subvendor
= PCI_ANY_ID
,
543 .subdevice
= PCI_ANY_ID
,
548 MODULE_DEVICE_TABLE(pci
, agp_amdk7_pci_table
);
550 static struct pci_driver agp_amdk7_pci_driver
= {
551 .name
= "agpgart-amdk7",
552 .id_table
= agp_amdk7_pci_table
,
553 .probe
= agp_amdk7_probe
,
554 .remove
= agp_amdk7_remove
,
556 .suspend
= agp_amdk7_suspend
,
557 .resume
= agp_amdk7_resume
,
561 static int __init
agp_amdk7_init(void)
565 return pci_register_driver(&agp_amdk7_pci_driver
);
568 static void __exit
agp_amdk7_cleanup(void)
570 pci_unregister_driver(&agp_amdk7_pci_driver
);
573 module_init(agp_amdk7_init
);
574 module_exit(agp_amdk7_cleanup
);
576 MODULE_LICENSE("GPL and additional rights");