2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
30 #include <plat/powerdomain.h>
33 * OMAP1510 GPIO registers
35 #define OMAP1510_GPIO_BASE 0xfffce000
36 #define OMAP1510_GPIO_DATA_INPUT 0x00
37 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
38 #define OMAP1510_GPIO_DIR_CONTROL 0x08
39 #define OMAP1510_GPIO_INT_CONTROL 0x0c
40 #define OMAP1510_GPIO_INT_MASK 0x10
41 #define OMAP1510_GPIO_INT_STATUS 0x14
42 #define OMAP1510_GPIO_PIN_CONTROL 0x18
44 #define OMAP1510_IH_GPIO_BASE 64
47 * OMAP1610 specific GPIO registers
49 #define OMAP1610_GPIO1_BASE 0xfffbe400
50 #define OMAP1610_GPIO2_BASE 0xfffbec00
51 #define OMAP1610_GPIO3_BASE 0xfffbb400
52 #define OMAP1610_GPIO4_BASE 0xfffbbc00
53 #define OMAP1610_GPIO_REVISION 0x0000
54 #define OMAP1610_GPIO_SYSCONFIG 0x0010
55 #define OMAP1610_GPIO_SYSSTATUS 0x0014
56 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
57 #define OMAP1610_GPIO_IRQENABLE1 0x001c
58 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
59 #define OMAP1610_GPIO_DATAIN 0x002c
60 #define OMAP1610_GPIO_DATAOUT 0x0030
61 #define OMAP1610_GPIO_DIRECTION 0x0034
62 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
63 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
64 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
65 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
66 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
67 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
68 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
69 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
72 * OMAP7XX specific GPIO registers
74 #define OMAP7XX_GPIO1_BASE 0xfffbc000
75 #define OMAP7XX_GPIO2_BASE 0xfffbc800
76 #define OMAP7XX_GPIO3_BASE 0xfffbd000
77 #define OMAP7XX_GPIO4_BASE 0xfffbd800
78 #define OMAP7XX_GPIO5_BASE 0xfffbe000
79 #define OMAP7XX_GPIO6_BASE 0xfffbe800
80 #define OMAP7XX_GPIO_DATA_INPUT 0x00
81 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
82 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
83 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
84 #define OMAP7XX_GPIO_INT_MASK 0x10
85 #define OMAP7XX_GPIO_INT_STATUS 0x14
87 #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
90 * omap24xx specific GPIO registers
92 #define OMAP242X_GPIO1_BASE 0x48018000
93 #define OMAP242X_GPIO2_BASE 0x4801a000
94 #define OMAP242X_GPIO3_BASE 0x4801c000
95 #define OMAP242X_GPIO4_BASE 0x4801e000
97 #define OMAP243X_GPIO1_BASE 0x4900C000
98 #define OMAP243X_GPIO2_BASE 0x4900E000
99 #define OMAP243X_GPIO3_BASE 0x49010000
100 #define OMAP243X_GPIO4_BASE 0x49012000
101 #define OMAP243X_GPIO5_BASE 0x480B6000
103 #define OMAP24XX_GPIO_REVISION 0x0000
104 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
105 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
106 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
107 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
108 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
109 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
110 #define OMAP24XX_GPIO_WAKE_EN 0x0020
111 #define OMAP24XX_GPIO_CTRL 0x0030
112 #define OMAP24XX_GPIO_OE 0x0034
113 #define OMAP24XX_GPIO_DATAIN 0x0038
114 #define OMAP24XX_GPIO_DATAOUT 0x003c
115 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
116 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
117 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
118 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
119 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
120 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
121 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
122 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
123 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
124 #define OMAP24XX_GPIO_SETWKUENA 0x0084
125 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
126 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
128 #define OMAP4_GPIO_REVISION 0x0000
129 #define OMAP4_GPIO_SYSCONFIG 0x0010
130 #define OMAP4_GPIO_EOI 0x0020
131 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
132 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
133 #define OMAP4_GPIO_IRQSTATUS0 0x002c
134 #define OMAP4_GPIO_IRQSTATUS1 0x0030
135 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
136 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
137 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
138 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
139 #define OMAP4_GPIO_IRQWAKEN0 0x0044
140 #define OMAP4_GPIO_IRQWAKEN1 0x0048
141 #define OMAP4_GPIO_SYSSTATUS 0x0104
142 #define OMAP4_GPIO_CTRL 0x0130
143 #define OMAP4_GPIO_OE 0x0134
144 #define OMAP4_GPIO_DATAIN 0x0138
145 #define OMAP4_GPIO_DATAOUT 0x013c
146 #define OMAP4_GPIO_LEVELDETECT0 0x0140
147 #define OMAP4_GPIO_LEVELDETECT1 0x0144
148 #define OMAP4_GPIO_RISINGDETECT 0x0148
149 #define OMAP4_GPIO_FALLINGDETECT 0x014c
150 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
151 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
152 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
153 #define OMAP4_GPIO_SETDATAOUT 0x0194
155 * omap34xx specific GPIO registers
158 #define OMAP34XX_GPIO1_BASE 0x48310000
159 #define OMAP34XX_GPIO2_BASE 0x49050000
160 #define OMAP34XX_GPIO3_BASE 0x49052000
161 #define OMAP34XX_GPIO4_BASE 0x49054000
162 #define OMAP34XX_GPIO5_BASE 0x49056000
163 #define OMAP34XX_GPIO6_BASE 0x49058000
166 * OMAP44XX specific GPIO registers
168 #define OMAP44XX_GPIO1_BASE 0x4a310000
169 #define OMAP44XX_GPIO2_BASE 0x48055000
170 #define OMAP44XX_GPIO3_BASE 0x48057000
171 #define OMAP44XX_GPIO4_BASE 0x48059000
172 #define OMAP44XX_GPIO5_BASE 0x4805B000
173 #define OMAP44XX_GPIO6_BASE 0x4805D000
179 u16 virtual_irq_start
;
181 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
185 #ifdef CONFIG_ARCH_OMAP2PLUS
186 u32 non_wakeup_gpios
;
187 u32 enabled_non_wakeup_gpios
;
190 u32 saved_fallingdetect
;
191 u32 saved_risingdetect
;
196 struct gpio_chip chip
;
201 #define METHOD_MPUIO 0
202 #define METHOD_GPIO_1510 1
203 #define METHOD_GPIO_1610 2
204 #define METHOD_GPIO_7XX 3
205 #define METHOD_GPIO_24XX 5
206 #define METHOD_GPIO_44XX 6
208 #ifdef CONFIG_ARCH_OMAP16XX
209 static struct gpio_bank gpio_bank_1610
[5] = {
210 { OMAP1_MPUIO_VBASE
, NULL
, INT_MPUIO
, IH_MPUIO_BASE
,
212 { OMAP1610_GPIO1_BASE
, NULL
, INT_GPIO_BANK1
, IH_GPIO_BASE
,
214 { OMAP1610_GPIO2_BASE
, NULL
, INT_1610_GPIO_BANK2
, IH_GPIO_BASE
+ 16,
216 { OMAP1610_GPIO3_BASE
, NULL
, INT_1610_GPIO_BANK3
, IH_GPIO_BASE
+ 32,
218 { OMAP1610_GPIO4_BASE
, NULL
, INT_1610_GPIO_BANK4
, IH_GPIO_BASE
+ 48,
223 #ifdef CONFIG_ARCH_OMAP15XX
224 static struct gpio_bank gpio_bank_1510
[2] = {
225 { OMAP1_MPUIO_VBASE
, NULL
, INT_MPUIO
, IH_MPUIO_BASE
,
227 { OMAP1510_GPIO_BASE
, NULL
, INT_GPIO_BANK1
, IH_GPIO_BASE
,
232 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
233 static struct gpio_bank gpio_bank_7xx
[7] = {
234 { OMAP1_MPUIO_VBASE
, NULL
, INT_7XX_MPUIO
, IH_MPUIO_BASE
,
236 { OMAP7XX_GPIO1_BASE
, NULL
, INT_7XX_GPIO_BANK1
, IH_GPIO_BASE
,
238 { OMAP7XX_GPIO2_BASE
, NULL
, INT_7XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32,
240 { OMAP7XX_GPIO3_BASE
, NULL
, INT_7XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64,
242 { OMAP7XX_GPIO4_BASE
, NULL
, INT_7XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96,
244 { OMAP7XX_GPIO5_BASE
, NULL
, INT_7XX_GPIO_BANK5
, IH_GPIO_BASE
+ 128,
246 { OMAP7XX_GPIO6_BASE
, NULL
, INT_7XX_GPIO_BANK6
, IH_GPIO_BASE
+ 160,
251 #ifdef CONFIG_ARCH_OMAP2
253 static struct gpio_bank gpio_bank_242x
[4] = {
254 { OMAP242X_GPIO1_BASE
, NULL
, INT_24XX_GPIO_BANK1
, IH_GPIO_BASE
,
256 { OMAP242X_GPIO2_BASE
, NULL
, INT_24XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32,
258 { OMAP242X_GPIO3_BASE
, NULL
, INT_24XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64,
260 { OMAP242X_GPIO4_BASE
, NULL
, INT_24XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96,
264 static struct gpio_bank gpio_bank_243x
[5] = {
265 { OMAP243X_GPIO1_BASE
, NULL
, INT_24XX_GPIO_BANK1
, IH_GPIO_BASE
,
267 { OMAP243X_GPIO2_BASE
, NULL
, INT_24XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32,
269 { OMAP243X_GPIO3_BASE
, NULL
, INT_24XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64,
271 { OMAP243X_GPIO4_BASE
, NULL
, INT_24XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96,
273 { OMAP243X_GPIO5_BASE
, NULL
, INT_24XX_GPIO_BANK5
, IH_GPIO_BASE
+ 128,
279 #ifdef CONFIG_ARCH_OMAP3
280 static struct gpio_bank gpio_bank_34xx
[6] = {
281 { OMAP34XX_GPIO1_BASE
, NULL
, INT_34XX_GPIO_BANK1
, IH_GPIO_BASE
,
283 { OMAP34XX_GPIO2_BASE
, NULL
, INT_34XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32,
285 { OMAP34XX_GPIO3_BASE
, NULL
, INT_34XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64,
287 { OMAP34XX_GPIO4_BASE
, NULL
, INT_34XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96,
289 { OMAP34XX_GPIO5_BASE
, NULL
, INT_34XX_GPIO_BANK5
, IH_GPIO_BASE
+ 128,
291 { OMAP34XX_GPIO6_BASE
, NULL
, INT_34XX_GPIO_BANK6
, IH_GPIO_BASE
+ 160,
295 struct omap3_gpio_regs
{
311 static struct omap3_gpio_regs gpio_context
[OMAP34XX_NR_GPIOS
];
314 #ifdef CONFIG_ARCH_OMAP4
315 static struct gpio_bank gpio_bank_44xx
[6] = {
316 { OMAP44XX_GPIO1_BASE
, NULL
, OMAP44XX_IRQ_GPIO1
, IH_GPIO_BASE
,
318 { OMAP44XX_GPIO2_BASE
, NULL
, OMAP44XX_IRQ_GPIO2
, IH_GPIO_BASE
+ 32,
320 { OMAP44XX_GPIO3_BASE
, NULL
, OMAP44XX_IRQ_GPIO3
, IH_GPIO_BASE
+ 64,
322 { OMAP44XX_GPIO4_BASE
, NULL
, OMAP44XX_IRQ_GPIO4
, IH_GPIO_BASE
+ 96,
324 { OMAP44XX_GPIO5_BASE
, NULL
, OMAP44XX_IRQ_GPIO5
, IH_GPIO_BASE
+ 128,
326 { OMAP44XX_GPIO6_BASE
, NULL
, OMAP44XX_IRQ_GPIO6
, IH_GPIO_BASE
+ 160,
332 static struct gpio_bank
*gpio_bank
;
333 static int gpio_bank_count
;
335 static inline struct gpio_bank
*get_gpio_bank(int gpio
)
337 if (cpu_is_omap15xx()) {
338 if (OMAP_GPIO_IS_MPUIO(gpio
))
339 return &gpio_bank
[0];
340 return &gpio_bank
[1];
342 if (cpu_is_omap16xx()) {
343 if (OMAP_GPIO_IS_MPUIO(gpio
))
344 return &gpio_bank
[0];
345 return &gpio_bank
[1 + (gpio
>> 4)];
347 if (cpu_is_omap7xx()) {
348 if (OMAP_GPIO_IS_MPUIO(gpio
))
349 return &gpio_bank
[0];
350 return &gpio_bank
[1 + (gpio
>> 5)];
352 if (cpu_is_omap24xx())
353 return &gpio_bank
[gpio
>> 5];
354 if (cpu_is_omap34xx() || cpu_is_omap44xx())
355 return &gpio_bank
[gpio
>> 5];
360 static inline int get_gpio_index(int gpio
)
362 if (cpu_is_omap7xx())
364 if (cpu_is_omap24xx())
366 if (cpu_is_omap34xx() || cpu_is_omap44xx())
371 static inline int gpio_valid(int gpio
)
375 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio
)) {
376 if (gpio
>= OMAP_MAX_GPIO_LINES
+ 16)
380 if (cpu_is_omap15xx() && gpio
< 16)
382 if ((cpu_is_omap16xx()) && gpio
< 64)
384 if (cpu_is_omap7xx() && gpio
< 192)
386 if (cpu_is_omap24xx() && gpio
< 128)
388 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio
< 192)
393 static int check_gpio(int gpio
)
395 if (unlikely(gpio_valid(gpio
) < 0)) {
396 printk(KERN_ERR
"omap-gpio: invalid GPIO %d\n", gpio
);
403 static void _set_gpio_direction(struct gpio_bank
*bank
, int gpio
, int is_input
)
405 void __iomem
*reg
= bank
->base
;
408 switch (bank
->method
) {
409 #ifdef CONFIG_ARCH_OMAP1
411 reg
+= OMAP_MPUIO_IO_CNTL
;
414 #ifdef CONFIG_ARCH_OMAP15XX
415 case METHOD_GPIO_1510
:
416 reg
+= OMAP1510_GPIO_DIR_CONTROL
;
419 #ifdef CONFIG_ARCH_OMAP16XX
420 case METHOD_GPIO_1610
:
421 reg
+= OMAP1610_GPIO_DIRECTION
;
424 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
425 case METHOD_GPIO_7XX
:
426 reg
+= OMAP7XX_GPIO_DIR_CONTROL
;
429 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
430 case METHOD_GPIO_24XX
:
431 reg
+= OMAP24XX_GPIO_OE
;
434 #if defined(CONFIG_ARCH_OMAP4)
435 case METHOD_GPIO_44XX
:
436 reg
+= OMAP4_GPIO_OE
;
443 l
= __raw_readl(reg
);
448 __raw_writel(l
, reg
);
451 static void _set_gpio_dataout(struct gpio_bank
*bank
, int gpio
, int enable
)
453 void __iomem
*reg
= bank
->base
;
456 switch (bank
->method
) {
457 #ifdef CONFIG_ARCH_OMAP1
459 reg
+= OMAP_MPUIO_OUTPUT
;
460 l
= __raw_readl(reg
);
467 #ifdef CONFIG_ARCH_OMAP15XX
468 case METHOD_GPIO_1510
:
469 reg
+= OMAP1510_GPIO_DATA_OUTPUT
;
470 l
= __raw_readl(reg
);
477 #ifdef CONFIG_ARCH_OMAP16XX
478 case METHOD_GPIO_1610
:
480 reg
+= OMAP1610_GPIO_SET_DATAOUT
;
482 reg
+= OMAP1610_GPIO_CLEAR_DATAOUT
;
486 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
487 case METHOD_GPIO_7XX
:
488 reg
+= OMAP7XX_GPIO_DATA_OUTPUT
;
489 l
= __raw_readl(reg
);
496 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
497 case METHOD_GPIO_24XX
:
499 reg
+= OMAP24XX_GPIO_SETDATAOUT
;
501 reg
+= OMAP24XX_GPIO_CLEARDATAOUT
;
505 #ifdef CONFIG_ARCH_OMAP4
506 case METHOD_GPIO_44XX
:
508 reg
+= OMAP4_GPIO_SETDATAOUT
;
510 reg
+= OMAP4_GPIO_CLEARDATAOUT
;
518 __raw_writel(l
, reg
);
521 static int _get_gpio_datain(struct gpio_bank
*bank
, int gpio
)
525 if (check_gpio(gpio
) < 0)
528 switch (bank
->method
) {
529 #ifdef CONFIG_ARCH_OMAP1
531 reg
+= OMAP_MPUIO_INPUT_LATCH
;
534 #ifdef CONFIG_ARCH_OMAP15XX
535 case METHOD_GPIO_1510
:
536 reg
+= OMAP1510_GPIO_DATA_INPUT
;
539 #ifdef CONFIG_ARCH_OMAP16XX
540 case METHOD_GPIO_1610
:
541 reg
+= OMAP1610_GPIO_DATAIN
;
544 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
545 case METHOD_GPIO_7XX
:
546 reg
+= OMAP7XX_GPIO_DATA_INPUT
;
549 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
550 case METHOD_GPIO_24XX
:
551 reg
+= OMAP24XX_GPIO_DATAIN
;
554 #ifdef CONFIG_ARCH_OMAP4
555 case METHOD_GPIO_44XX
:
556 reg
+= OMAP4_GPIO_DATAIN
;
562 return (__raw_readl(reg
)
563 & (1 << get_gpio_index(gpio
))) != 0;
566 static int _get_gpio_dataout(struct gpio_bank
*bank
, int gpio
)
570 if (check_gpio(gpio
) < 0)
574 switch (bank
->method
) {
575 #ifdef CONFIG_ARCH_OMAP1
577 reg
+= OMAP_MPUIO_OUTPUT
;
580 #ifdef CONFIG_ARCH_OMAP15XX
581 case METHOD_GPIO_1510
:
582 reg
+= OMAP1510_GPIO_DATA_OUTPUT
;
585 #ifdef CONFIG_ARCH_OMAP16XX
586 case METHOD_GPIO_1610
:
587 reg
+= OMAP1610_GPIO_DATAOUT
;
590 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
591 case METHOD_GPIO_7XX
:
592 reg
+= OMAP7XX_GPIO_DATA_OUTPUT
;
595 #ifdef CONFIG_ARCH_OMAP2PLUS
596 case METHOD_GPIO_24XX
:
597 case METHOD_GPIO_44XX
:
598 reg
+= OMAP24XX_GPIO_DATAOUT
;
605 return (__raw_readl(reg
) & (1 << get_gpio_index(gpio
))) != 0;
608 #define MOD_REG_BIT(reg, bit_mask, set) \
610 int l = __raw_readl(base + reg); \
611 if (set) l |= bit_mask; \
612 else l &= ~bit_mask; \
613 __raw_writel(l, base + reg); \
616 void omap_set_gpio_debounce(int gpio
, int enable
)
618 struct gpio_bank
*bank
;
621 u32 val
, l
= 1 << get_gpio_index(gpio
);
623 if (cpu_class_is_omap1())
626 bank
= get_gpio_bank(gpio
);
629 if (cpu_is_omap44xx())
630 reg
+= OMAP4_GPIO_DEBOUNCENABLE
;
632 reg
+= OMAP24XX_GPIO_DEBOUNCE_EN
;
634 if (!(bank
->mod_usage
& l
)) {
635 printk(KERN_ERR
"GPIO %d not requested\n", gpio
);
639 spin_lock_irqsave(&bank
->lock
, flags
);
640 val
= __raw_readl(reg
);
642 if (enable
&& !(val
& l
))
644 else if (!enable
&& (val
& l
))
649 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
651 clk_enable(bank
->dbck
);
653 clk_disable(bank
->dbck
);
656 __raw_writel(val
, reg
);
658 spin_unlock_irqrestore(&bank
->lock
, flags
);
660 EXPORT_SYMBOL(omap_set_gpio_debounce
);
662 void omap_set_gpio_debounce_time(int gpio
, int enc_time
)
664 struct gpio_bank
*bank
;
667 if (cpu_class_is_omap1())
670 bank
= get_gpio_bank(gpio
);
673 if (!bank
->mod_usage
) {
674 printk(KERN_ERR
"GPIO not requested\n");
680 if (cpu_is_omap44xx())
681 reg
+= OMAP4_GPIO_DEBOUNCINGTIME
;
683 reg
+= OMAP24XX_GPIO_DEBOUNCE_VAL
;
685 __raw_writel(enc_time
, reg
);
687 EXPORT_SYMBOL(omap_set_gpio_debounce_time
);
689 #ifdef CONFIG_ARCH_OMAP2PLUS
690 static inline void set_24xx_gpio_triggering(struct gpio_bank
*bank
, int gpio
,
693 void __iomem
*base
= bank
->base
;
694 u32 gpio_bit
= 1 << gpio
;
697 if (cpu_is_omap44xx()) {
698 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0
, gpio_bit
,
699 trigger
& IRQ_TYPE_LEVEL_LOW
);
700 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1
, gpio_bit
,
701 trigger
& IRQ_TYPE_LEVEL_HIGH
);
702 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT
, gpio_bit
,
703 trigger
& IRQ_TYPE_EDGE_RISING
);
704 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT
, gpio_bit
,
705 trigger
& IRQ_TYPE_EDGE_FALLING
);
707 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0
, gpio_bit
,
708 trigger
& IRQ_TYPE_LEVEL_LOW
);
709 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1
, gpio_bit
,
710 trigger
& IRQ_TYPE_LEVEL_HIGH
);
711 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT
, gpio_bit
,
712 trigger
& IRQ_TYPE_EDGE_RISING
);
713 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT
, gpio_bit
,
714 trigger
& IRQ_TYPE_EDGE_FALLING
);
716 if (likely(!(bank
->non_wakeup_gpios
& gpio_bit
))) {
717 if (cpu_is_omap44xx()) {
719 __raw_writel(1 << gpio
, bank
->base
+
720 OMAP4_GPIO_IRQWAKEN0
);
722 val
= __raw_readl(bank
->base
+
723 OMAP4_GPIO_IRQWAKEN0
);
724 __raw_writel(val
& (~(1 << gpio
)), bank
->base
+
725 OMAP4_GPIO_IRQWAKEN0
);
729 * GPIO wakeup request can only be generated on edge
732 if (trigger
& IRQ_TYPE_EDGE_BOTH
)
733 __raw_writel(1 << gpio
, bank
->base
734 + OMAP24XX_GPIO_SETWKUENA
);
736 __raw_writel(1 << gpio
, bank
->base
737 + OMAP24XX_GPIO_CLEARWKUENA
);
740 /* This part needs to be executed always for OMAP34xx */
741 if (cpu_is_omap34xx() || (bank
->non_wakeup_gpios
& gpio_bit
)) {
743 * Log the edge gpio and manually trigger the IRQ
744 * after resume if the input level changes
745 * to avoid irq lost during PER RET/OFF mode
746 * Applies for omap2 non-wakeup gpio and all omap3 gpios
748 if (trigger
& IRQ_TYPE_EDGE_BOTH
)
749 bank
->enabled_non_wakeup_gpios
|= gpio_bit
;
751 bank
->enabled_non_wakeup_gpios
&= ~gpio_bit
;
754 if (cpu_is_omap44xx()) {
756 __raw_readl(bank
->base
+ OMAP4_GPIO_LEVELDETECT0
) |
757 __raw_readl(bank
->base
+ OMAP4_GPIO_LEVELDETECT1
);
760 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
) |
761 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
766 #ifdef CONFIG_ARCH_OMAP1
768 * This only applies to chips that can't do both rising and falling edge
769 * detection at once. For all other chips, this function is a noop.
771 static void _toggle_gpio_edge_triggering(struct gpio_bank
*bank
, int gpio
)
773 void __iomem
*reg
= bank
->base
;
776 switch (bank
->method
) {
778 reg
+= OMAP_MPUIO_GPIO_INT_EDGE
;
780 #ifdef CONFIG_ARCH_OMAP15XX
781 case METHOD_GPIO_1510
:
782 reg
+= OMAP1510_GPIO_INT_CONTROL
;
785 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
786 case METHOD_GPIO_7XX
:
787 reg
+= OMAP7XX_GPIO_INT_CONTROL
;
794 l
= __raw_readl(reg
);
800 __raw_writel(l
, reg
);
804 static int _set_gpio_triggering(struct gpio_bank
*bank
, int gpio
, int trigger
)
806 void __iomem
*reg
= bank
->base
;
809 switch (bank
->method
) {
810 #ifdef CONFIG_ARCH_OMAP1
812 reg
+= OMAP_MPUIO_GPIO_INT_EDGE
;
813 l
= __raw_readl(reg
);
814 if ((trigger
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
)
815 bank
->toggle_mask
|= 1 << gpio
;
816 if (trigger
& IRQ_TYPE_EDGE_RISING
)
818 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
824 #ifdef CONFIG_ARCH_OMAP15XX
825 case METHOD_GPIO_1510
:
826 reg
+= OMAP1510_GPIO_INT_CONTROL
;
827 l
= __raw_readl(reg
);
828 if ((trigger
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
)
829 bank
->toggle_mask
|= 1 << gpio
;
830 if (trigger
& IRQ_TYPE_EDGE_RISING
)
832 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
838 #ifdef CONFIG_ARCH_OMAP16XX
839 case METHOD_GPIO_1610
:
841 reg
+= OMAP1610_GPIO_EDGE_CTRL2
;
843 reg
+= OMAP1610_GPIO_EDGE_CTRL1
;
845 l
= __raw_readl(reg
);
846 l
&= ~(3 << (gpio
<< 1));
847 if (trigger
& IRQ_TYPE_EDGE_RISING
)
848 l
|= 2 << (gpio
<< 1);
849 if (trigger
& IRQ_TYPE_EDGE_FALLING
)
850 l
|= 1 << (gpio
<< 1);
852 /* Enable wake-up during idle for dynamic tick */
853 __raw_writel(1 << gpio
, bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
);
855 __raw_writel(1 << gpio
, bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
);
858 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
859 case METHOD_GPIO_7XX
:
860 reg
+= OMAP7XX_GPIO_INT_CONTROL
;
861 l
= __raw_readl(reg
);
862 if ((trigger
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
)
863 bank
->toggle_mask
|= 1 << gpio
;
864 if (trigger
& IRQ_TYPE_EDGE_RISING
)
866 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
872 #ifdef CONFIG_ARCH_OMAP2PLUS
873 case METHOD_GPIO_24XX
:
874 case METHOD_GPIO_44XX
:
875 set_24xx_gpio_triggering(bank
, gpio
, trigger
);
881 __raw_writel(l
, reg
);
887 static int gpio_irq_type(unsigned irq
, unsigned type
)
889 struct gpio_bank
*bank
;
894 if (!cpu_class_is_omap2() && irq
> IH_MPUIO_BASE
)
895 gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
897 gpio
= irq
- IH_GPIO_BASE
;
899 if (check_gpio(gpio
) < 0)
902 if (type
& ~IRQ_TYPE_SENSE_MASK
)
905 /* OMAP1 allows only only edge triggering */
906 if (!cpu_class_is_omap2()
907 && (type
& (IRQ_TYPE_LEVEL_LOW
|IRQ_TYPE_LEVEL_HIGH
)))
910 bank
= get_irq_chip_data(irq
);
911 spin_lock_irqsave(&bank
->lock
, flags
);
912 retval
= _set_gpio_triggering(bank
, get_gpio_index(gpio
), type
);
914 irq_desc
[irq
].status
&= ~IRQ_TYPE_SENSE_MASK
;
915 irq_desc
[irq
].status
|= type
;
917 spin_unlock_irqrestore(&bank
->lock
, flags
);
919 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
))
920 __set_irq_handler_unlocked(irq
, handle_level_irq
);
921 else if (type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
922 __set_irq_handler_unlocked(irq
, handle_edge_irq
);
927 static void _clear_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
929 void __iomem
*reg
= bank
->base
;
931 switch (bank
->method
) {
932 #ifdef CONFIG_ARCH_OMAP1
934 /* MPUIO irqstatus is reset by reading the status register,
935 * so do nothing here */
938 #ifdef CONFIG_ARCH_OMAP15XX
939 case METHOD_GPIO_1510
:
940 reg
+= OMAP1510_GPIO_INT_STATUS
;
943 #ifdef CONFIG_ARCH_OMAP16XX
944 case METHOD_GPIO_1610
:
945 reg
+= OMAP1610_GPIO_IRQSTATUS1
;
948 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
949 case METHOD_GPIO_7XX
:
950 reg
+= OMAP7XX_GPIO_INT_STATUS
;
953 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
954 case METHOD_GPIO_24XX
:
955 reg
+= OMAP24XX_GPIO_IRQSTATUS1
;
958 #if defined(CONFIG_ARCH_OMAP4)
959 case METHOD_GPIO_44XX
:
960 reg
+= OMAP4_GPIO_IRQSTATUS0
;
967 __raw_writel(gpio_mask
, reg
);
969 /* Workaround for clearing DSP GPIO interrupts to allow retention */
970 if (cpu_is_omap24xx() || cpu_is_omap34xx())
971 reg
= bank
->base
+ OMAP24XX_GPIO_IRQSTATUS2
;
972 else if (cpu_is_omap44xx())
973 reg
= bank
->base
+ OMAP4_GPIO_IRQSTATUS1
;
975 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
976 __raw_writel(gpio_mask
, reg
);
978 /* Flush posted write for the irq status to avoid spurious interrupts */
983 static inline void _clear_gpio_irqstatus(struct gpio_bank
*bank
, int gpio
)
985 _clear_gpio_irqbank(bank
, 1 << get_gpio_index(gpio
));
988 static u32
_get_gpio_irqbank_mask(struct gpio_bank
*bank
)
990 void __iomem
*reg
= bank
->base
;
995 switch (bank
->method
) {
996 #ifdef CONFIG_ARCH_OMAP1
998 reg
+= OMAP_MPUIO_GPIO_MASKIT
;
1003 #ifdef CONFIG_ARCH_OMAP15XX
1004 case METHOD_GPIO_1510
:
1005 reg
+= OMAP1510_GPIO_INT_MASK
;
1010 #ifdef CONFIG_ARCH_OMAP16XX
1011 case METHOD_GPIO_1610
:
1012 reg
+= OMAP1610_GPIO_IRQENABLE1
;
1016 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1017 case METHOD_GPIO_7XX
:
1018 reg
+= OMAP7XX_GPIO_INT_MASK
;
1023 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1024 case METHOD_GPIO_24XX
:
1025 reg
+= OMAP24XX_GPIO_IRQENABLE1
;
1029 #if defined(CONFIG_ARCH_OMAP4)
1030 case METHOD_GPIO_44XX
:
1031 reg
+= OMAP4_GPIO_IRQSTATUSSET0
;
1040 l
= __raw_readl(reg
);
1047 static void _enable_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
, int enable
)
1049 void __iomem
*reg
= bank
->base
;
1052 switch (bank
->method
) {
1053 #ifdef CONFIG_ARCH_OMAP1
1055 reg
+= OMAP_MPUIO_GPIO_MASKIT
;
1056 l
= __raw_readl(reg
);
1063 #ifdef CONFIG_ARCH_OMAP15XX
1064 case METHOD_GPIO_1510
:
1065 reg
+= OMAP1510_GPIO_INT_MASK
;
1066 l
= __raw_readl(reg
);
1073 #ifdef CONFIG_ARCH_OMAP16XX
1074 case METHOD_GPIO_1610
:
1076 reg
+= OMAP1610_GPIO_SET_IRQENABLE1
;
1078 reg
+= OMAP1610_GPIO_CLEAR_IRQENABLE1
;
1082 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1083 case METHOD_GPIO_7XX
:
1084 reg
+= OMAP7XX_GPIO_INT_MASK
;
1085 l
= __raw_readl(reg
);
1092 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1093 case METHOD_GPIO_24XX
:
1095 reg
+= OMAP24XX_GPIO_SETIRQENABLE1
;
1097 reg
+= OMAP24XX_GPIO_CLEARIRQENABLE1
;
1101 #ifdef CONFIG_ARCH_OMAP4
1102 case METHOD_GPIO_44XX
:
1104 reg
+= OMAP4_GPIO_IRQSTATUSSET0
;
1106 reg
+= OMAP4_GPIO_IRQSTATUSCLR0
;
1114 __raw_writel(l
, reg
);
1117 static inline void _set_gpio_irqenable(struct gpio_bank
*bank
, int gpio
, int enable
)
1119 _enable_gpio_irqbank(bank
, 1 << get_gpio_index(gpio
), enable
);
1123 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1124 * 1510 does not seem to have a wake-up register. If JTAG is connected
1125 * to the target, system will wake up always on GPIO events. While
1126 * system is running all registered GPIO interrupts need to have wake-up
1127 * enabled. When system is suspended, only selected GPIO interrupts need
1128 * to have wake-up enabled.
1130 static int _set_gpio_wakeup(struct gpio_bank
*bank
, int gpio
, int enable
)
1132 unsigned long uninitialized_var(flags
);
1134 switch (bank
->method
) {
1135 #ifdef CONFIG_ARCH_OMAP16XX
1137 case METHOD_GPIO_1610
:
1138 spin_lock_irqsave(&bank
->lock
, flags
);
1140 bank
->suspend_wakeup
|= (1 << gpio
);
1142 bank
->suspend_wakeup
&= ~(1 << gpio
);
1143 spin_unlock_irqrestore(&bank
->lock
, flags
);
1146 #ifdef CONFIG_ARCH_OMAP2PLUS
1147 case METHOD_GPIO_24XX
:
1148 case METHOD_GPIO_44XX
:
1149 if (bank
->non_wakeup_gpios
& (1 << gpio
)) {
1150 printk(KERN_ERR
"Unable to modify wakeup on "
1151 "non-wakeup GPIO%d\n",
1152 (bank
- gpio_bank
) * 32 + gpio
);
1155 spin_lock_irqsave(&bank
->lock
, flags
);
1157 bank
->suspend_wakeup
|= (1 << gpio
);
1159 bank
->suspend_wakeup
&= ~(1 << gpio
);
1160 spin_unlock_irqrestore(&bank
->lock
, flags
);
1164 printk(KERN_ERR
"Can't enable GPIO wakeup for method %i\n",
1170 static void _reset_gpio(struct gpio_bank
*bank
, int gpio
)
1172 _set_gpio_direction(bank
, get_gpio_index(gpio
), 1);
1173 _set_gpio_irqenable(bank
, gpio
, 0);
1174 _clear_gpio_irqstatus(bank
, gpio
);
1175 _set_gpio_triggering(bank
, get_gpio_index(gpio
), IRQ_TYPE_NONE
);
1178 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1179 static int gpio_wake_enable(unsigned int irq
, unsigned int enable
)
1181 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1182 struct gpio_bank
*bank
;
1185 if (check_gpio(gpio
) < 0)
1187 bank
= get_irq_chip_data(irq
);
1188 retval
= _set_gpio_wakeup(bank
, get_gpio_index(gpio
), enable
);
1193 static int omap_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1195 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
1196 unsigned long flags
;
1198 spin_lock_irqsave(&bank
->lock
, flags
);
1200 /* Set trigger to none. You need to enable the desired trigger with
1201 * request_irq() or set_irq_type().
1203 _set_gpio_triggering(bank
, offset
, IRQ_TYPE_NONE
);
1205 #ifdef CONFIG_ARCH_OMAP15XX
1206 if (bank
->method
== METHOD_GPIO_1510
) {
1209 /* Claim the pin for MPU */
1210 reg
= bank
->base
+ OMAP1510_GPIO_PIN_CONTROL
;
1211 __raw_writel(__raw_readl(reg
) | (1 << offset
), reg
);
1214 if (!cpu_class_is_omap1()) {
1215 if (!bank
->mod_usage
) {
1217 ctrl
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_CTRL
);
1219 /* Module is enabled, clocks are not gated */
1220 __raw_writel(ctrl
, bank
->base
+ OMAP24XX_GPIO_CTRL
);
1222 bank
->mod_usage
|= 1 << offset
;
1224 spin_unlock_irqrestore(&bank
->lock
, flags
);
1229 static void omap_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
1231 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
1232 unsigned long flags
;
1234 spin_lock_irqsave(&bank
->lock
, flags
);
1235 #ifdef CONFIG_ARCH_OMAP16XX
1236 if (bank
->method
== METHOD_GPIO_1610
) {
1237 /* Disable wake-up during idle for dynamic tick */
1238 void __iomem
*reg
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1239 __raw_writel(1 << offset
, reg
);
1242 #ifdef CONFIG_ARCH_OMAP2PLUS
1243 if ((bank
->method
== METHOD_GPIO_24XX
) ||
1244 (bank
->method
== METHOD_GPIO_44XX
)) {
1245 /* Disable wake-up during idle for dynamic tick */
1246 void __iomem
*reg
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1247 __raw_writel(1 << offset
, reg
);
1250 if (!cpu_class_is_omap1()) {
1251 bank
->mod_usage
&= ~(1 << offset
);
1252 if (!bank
->mod_usage
) {
1254 ctrl
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_CTRL
);
1255 /* Module is disabled, clocks are gated */
1257 __raw_writel(ctrl
, bank
->base
+ OMAP24XX_GPIO_CTRL
);
1260 _reset_gpio(bank
, bank
->chip
.base
+ offset
);
1261 spin_unlock_irqrestore(&bank
->lock
, flags
);
1265 * We need to unmask the GPIO bank interrupt as soon as possible to
1266 * avoid missing GPIO interrupts for other lines in the bank.
1267 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1268 * in the bank to avoid missing nested interrupts for a GPIO line.
1269 * If we wait to unmask individual GPIO lines in the bank after the
1270 * line's interrupt handler has been run, we may miss some nested
1273 static void gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
1275 void __iomem
*isr_reg
= NULL
;
1277 unsigned int gpio_irq
, gpio_index
;
1278 struct gpio_bank
*bank
;
1282 desc
->chip
->ack(irq
);
1284 bank
= get_irq_data(irq
);
1285 #ifdef CONFIG_ARCH_OMAP1
1286 if (bank
->method
== METHOD_MPUIO
)
1287 isr_reg
= bank
->base
+ OMAP_MPUIO_GPIO_INT
;
1289 #ifdef CONFIG_ARCH_OMAP15XX
1290 if (bank
->method
== METHOD_GPIO_1510
)
1291 isr_reg
= bank
->base
+ OMAP1510_GPIO_INT_STATUS
;
1293 #if defined(CONFIG_ARCH_OMAP16XX)
1294 if (bank
->method
== METHOD_GPIO_1610
)
1295 isr_reg
= bank
->base
+ OMAP1610_GPIO_IRQSTATUS1
;
1297 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1298 if (bank
->method
== METHOD_GPIO_7XX
)
1299 isr_reg
= bank
->base
+ OMAP7XX_GPIO_INT_STATUS
;
1301 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1302 if (bank
->method
== METHOD_GPIO_24XX
)
1303 isr_reg
= bank
->base
+ OMAP24XX_GPIO_IRQSTATUS1
;
1305 #if defined(CONFIG_ARCH_OMAP4)
1306 if (bank
->method
== METHOD_GPIO_44XX
)
1307 isr_reg
= bank
->base
+ OMAP4_GPIO_IRQSTATUS0
;
1310 u32 isr_saved
, level_mask
= 0;
1313 enabled
= _get_gpio_irqbank_mask(bank
);
1314 isr_saved
= isr
= __raw_readl(isr_reg
) & enabled
;
1316 if (cpu_is_omap15xx() && (bank
->method
== METHOD_MPUIO
))
1319 if (cpu_class_is_omap2()) {
1320 level_mask
= bank
->level_mask
& enabled
;
1323 /* clear edge sensitive interrupts before handler(s) are
1324 called so that we don't miss any interrupt occurred while
1326 _enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
, 0);
1327 _clear_gpio_irqbank(bank
, isr_saved
& ~level_mask
);
1328 _enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
, 1);
1330 /* if there is only edge sensitive GPIO pin interrupts
1331 configured, we could unmask GPIO bank interrupt immediately */
1332 if (!level_mask
&& !unmasked
) {
1334 desc
->chip
->unmask(irq
);
1342 gpio_irq
= bank
->virtual_irq_start
;
1343 for (; isr
!= 0; isr
>>= 1, gpio_irq
++) {
1344 gpio_index
= get_gpio_index(irq_to_gpio(gpio_irq
));
1349 #ifdef CONFIG_ARCH_OMAP1
1351 * Some chips can't respond to both rising and falling
1352 * at the same time. If this irq was requested with
1353 * both flags, we need to flip the ICR data for the IRQ
1354 * to respond to the IRQ for the opposite direction.
1355 * This will be indicated in the bank toggle_mask.
1357 if (bank
->toggle_mask
& (1 << gpio_index
))
1358 _toggle_gpio_edge_triggering(bank
, gpio_index
);
1361 generic_handle_irq(gpio_irq
);
1364 /* if bank has any level sensitive GPIO pin interrupt
1365 configured, we must unmask the bank interrupt only after
1366 handler(s) are executed in order to avoid spurious bank
1369 desc
->chip
->unmask(irq
);
1373 static void gpio_irq_shutdown(unsigned int irq
)
1375 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1376 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1378 _reset_gpio(bank
, gpio
);
1381 static void gpio_ack_irq(unsigned int irq
)
1383 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1384 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1386 _clear_gpio_irqstatus(bank
, gpio
);
1389 static void gpio_mask_irq(unsigned int irq
)
1391 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1392 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1394 _set_gpio_irqenable(bank
, gpio
, 0);
1395 _set_gpio_triggering(bank
, get_gpio_index(gpio
), IRQ_TYPE_NONE
);
1398 static void gpio_unmask_irq(unsigned int irq
)
1400 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1401 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1402 unsigned int irq_mask
= 1 << get_gpio_index(gpio
);
1403 struct irq_desc
*desc
= irq_to_desc(irq
);
1404 u32 trigger
= desc
->status
& IRQ_TYPE_SENSE_MASK
;
1407 _set_gpio_triggering(bank
, get_gpio_index(gpio
), trigger
);
1409 /* For level-triggered GPIOs, the clearing must be done after
1410 * the HW source is cleared, thus after the handler has run */
1411 if (bank
->level_mask
& irq_mask
) {
1412 _set_gpio_irqenable(bank
, gpio
, 0);
1413 _clear_gpio_irqstatus(bank
, gpio
);
1416 _set_gpio_irqenable(bank
, gpio
, 1);
1419 static struct irq_chip gpio_irq_chip
= {
1421 .shutdown
= gpio_irq_shutdown
,
1422 .ack
= gpio_ack_irq
,
1423 .mask
= gpio_mask_irq
,
1424 .unmask
= gpio_unmask_irq
,
1425 .set_type
= gpio_irq_type
,
1426 .set_wake
= gpio_wake_enable
,
1429 /*---------------------------------------------------------------------*/
1431 #ifdef CONFIG_ARCH_OMAP1
1433 /* MPUIO uses the always-on 32k clock */
1435 static void mpuio_ack_irq(unsigned int irq
)
1437 /* The ISR is reset automatically, so do nothing here. */
1440 static void mpuio_mask_irq(unsigned int irq
)
1442 unsigned int gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
1443 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1445 _set_gpio_irqenable(bank
, gpio
, 0);
1448 static void mpuio_unmask_irq(unsigned int irq
)
1450 unsigned int gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
1451 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1453 _set_gpio_irqenable(bank
, gpio
, 1);
1456 static struct irq_chip mpuio_irq_chip
= {
1458 .ack
= mpuio_ack_irq
,
1459 .mask
= mpuio_mask_irq
,
1460 .unmask
= mpuio_unmask_irq
,
1461 .set_type
= gpio_irq_type
,
1462 #ifdef CONFIG_ARCH_OMAP16XX
1463 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1464 .set_wake
= gpio_wake_enable
,
1469 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1472 #ifdef CONFIG_ARCH_OMAP16XX
1474 #include <linux/platform_device.h>
1476 static int omap_mpuio_suspend_noirq(struct device
*dev
)
1478 struct platform_device
*pdev
= to_platform_device(dev
);
1479 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1480 void __iomem
*mask_reg
= bank
->base
+ OMAP_MPUIO_GPIO_MASKIT
;
1481 unsigned long flags
;
1483 spin_lock_irqsave(&bank
->lock
, flags
);
1484 bank
->saved_wakeup
= __raw_readl(mask_reg
);
1485 __raw_writel(0xffff & ~bank
->suspend_wakeup
, mask_reg
);
1486 spin_unlock_irqrestore(&bank
->lock
, flags
);
1491 static int omap_mpuio_resume_noirq(struct device
*dev
)
1493 struct platform_device
*pdev
= to_platform_device(dev
);
1494 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1495 void __iomem
*mask_reg
= bank
->base
+ OMAP_MPUIO_GPIO_MASKIT
;
1496 unsigned long flags
;
1498 spin_lock_irqsave(&bank
->lock
, flags
);
1499 __raw_writel(bank
->saved_wakeup
, mask_reg
);
1500 spin_unlock_irqrestore(&bank
->lock
, flags
);
1505 static const struct dev_pm_ops omap_mpuio_dev_pm_ops
= {
1506 .suspend_noirq
= omap_mpuio_suspend_noirq
,
1507 .resume_noirq
= omap_mpuio_resume_noirq
,
1510 /* use platform_driver for this, now that there's no longer any
1511 * point to sys_device (other than not disturbing old code).
1513 static struct platform_driver omap_mpuio_driver
= {
1516 .pm
= &omap_mpuio_dev_pm_ops
,
1520 static struct platform_device omap_mpuio_device
= {
1524 .driver
= &omap_mpuio_driver
.driver
,
1526 /* could list the /proc/iomem resources */
1529 static inline void mpuio_init(void)
1531 platform_set_drvdata(&omap_mpuio_device
, &gpio_bank_1610
[0]);
1533 if (platform_driver_register(&omap_mpuio_driver
) == 0)
1534 (void) platform_device_register(&omap_mpuio_device
);
1538 static inline void mpuio_init(void) {}
1543 extern struct irq_chip mpuio_irq_chip
;
1545 #define bank_is_mpuio(bank) 0
1546 static inline void mpuio_init(void) {}
1550 /*---------------------------------------------------------------------*/
1552 /* REVISIT these are stupid implementations! replace by ones that
1553 * don't switch on METHOD_* and which mostly avoid spinlocks
1556 static int gpio_input(struct gpio_chip
*chip
, unsigned offset
)
1558 struct gpio_bank
*bank
;
1559 unsigned long flags
;
1561 bank
= container_of(chip
, struct gpio_bank
, chip
);
1562 spin_lock_irqsave(&bank
->lock
, flags
);
1563 _set_gpio_direction(bank
, offset
, 1);
1564 spin_unlock_irqrestore(&bank
->lock
, flags
);
1568 static int gpio_is_input(struct gpio_bank
*bank
, int mask
)
1570 void __iomem
*reg
= bank
->base
;
1572 switch (bank
->method
) {
1574 reg
+= OMAP_MPUIO_IO_CNTL
;
1576 case METHOD_GPIO_1510
:
1577 reg
+= OMAP1510_GPIO_DIR_CONTROL
;
1579 case METHOD_GPIO_1610
:
1580 reg
+= OMAP1610_GPIO_DIRECTION
;
1582 case METHOD_GPIO_7XX
:
1583 reg
+= OMAP7XX_GPIO_DIR_CONTROL
;
1585 case METHOD_GPIO_24XX
:
1586 case METHOD_GPIO_44XX
:
1587 reg
+= OMAP24XX_GPIO_OE
;
1590 return __raw_readl(reg
) & mask
;
1593 static int gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1595 struct gpio_bank
*bank
;
1600 gpio
= chip
->base
+ offset
;
1601 bank
= get_gpio_bank(gpio
);
1603 mask
= 1 << get_gpio_index(gpio
);
1605 if (gpio_is_input(bank
, mask
))
1606 return _get_gpio_datain(bank
, gpio
);
1608 return _get_gpio_dataout(bank
, gpio
);
1611 static int gpio_output(struct gpio_chip
*chip
, unsigned offset
, int value
)
1613 struct gpio_bank
*bank
;
1614 unsigned long flags
;
1616 bank
= container_of(chip
, struct gpio_bank
, chip
);
1617 spin_lock_irqsave(&bank
->lock
, flags
);
1618 _set_gpio_dataout(bank
, offset
, value
);
1619 _set_gpio_direction(bank
, offset
, 0);
1620 spin_unlock_irqrestore(&bank
->lock
, flags
);
1624 static void gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1626 struct gpio_bank
*bank
;
1627 unsigned long flags
;
1629 bank
= container_of(chip
, struct gpio_bank
, chip
);
1630 spin_lock_irqsave(&bank
->lock
, flags
);
1631 _set_gpio_dataout(bank
, offset
, value
);
1632 spin_unlock_irqrestore(&bank
->lock
, flags
);
1635 static int gpio_2irq(struct gpio_chip
*chip
, unsigned offset
)
1637 struct gpio_bank
*bank
;
1639 bank
= container_of(chip
, struct gpio_bank
, chip
);
1640 return bank
->virtual_irq_start
+ offset
;
1643 /*---------------------------------------------------------------------*/
1645 static int initialized
;
1646 #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
1647 static struct clk
* gpio_ick
;
1650 #if defined(CONFIG_ARCH_OMAP2)
1651 static struct clk
* gpio_fck
;
1654 #if defined(CONFIG_ARCH_OMAP2430)
1655 static struct clk
* gpio5_ick
;
1656 static struct clk
* gpio5_fck
;
1659 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1660 static struct clk
*gpio_iclks
[OMAP34XX_NR_GPIOS
];
1663 static void __init
omap_gpio_show_rev(void)
1667 if (cpu_is_omap16xx())
1668 rev
= __raw_readw(gpio_bank
[1].base
+ OMAP1610_GPIO_REVISION
);
1669 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1670 rev
= __raw_readl(gpio_bank
[0].base
+ OMAP24XX_GPIO_REVISION
);
1671 else if (cpu_is_omap44xx())
1672 rev
= __raw_readl(gpio_bank
[0].base
+ OMAP4_GPIO_REVISION
);
1676 printk(KERN_INFO
"OMAP GPIO hardware version %d.%d\n",
1677 (rev
>> 4) & 0x0f, rev
& 0x0f);
1680 /* This lock class tells lockdep that GPIO irqs are in a different
1681 * category than their parents, so it won't report false recursion.
1683 static struct lock_class_key gpio_lock_class
;
1685 static int __init
_omap_gpio_init(void)
1689 struct gpio_bank
*bank
;
1690 int bank_size
= SZ_8K
; /* Module 4KB + L4 4KB except on omap1 */
1695 #if defined(CONFIG_ARCH_OMAP1)
1696 if (cpu_is_omap15xx()) {
1697 gpio_ick
= clk_get(NULL
, "arm_gpio_ck");
1698 if (IS_ERR(gpio_ick
))
1699 printk("Could not get arm_gpio_ck\n");
1701 clk_enable(gpio_ick
);
1704 #if defined(CONFIG_ARCH_OMAP2)
1705 if (cpu_class_is_omap2()) {
1706 gpio_ick
= clk_get(NULL
, "gpios_ick");
1707 if (IS_ERR(gpio_ick
))
1708 printk("Could not get gpios_ick\n");
1710 clk_enable(gpio_ick
);
1711 gpio_fck
= clk_get(NULL
, "gpios_fck");
1712 if (IS_ERR(gpio_fck
))
1713 printk("Could not get gpios_fck\n");
1715 clk_enable(gpio_fck
);
1718 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1720 #if defined(CONFIG_ARCH_OMAP2430)
1721 if (cpu_is_omap2430()) {
1722 gpio5_ick
= clk_get(NULL
, "gpio5_ick");
1723 if (IS_ERR(gpio5_ick
))
1724 printk("Could not get gpio5_ick\n");
1726 clk_enable(gpio5_ick
);
1727 gpio5_fck
= clk_get(NULL
, "gpio5_fck");
1728 if (IS_ERR(gpio5_fck
))
1729 printk("Could not get gpio5_fck\n");
1731 clk_enable(gpio5_fck
);
1737 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1738 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1739 for (i
= 0; i
< OMAP34XX_NR_GPIOS
; i
++) {
1740 sprintf(clk_name
, "gpio%d_ick", i
+ 1);
1741 gpio_iclks
[i
] = clk_get(NULL
, clk_name
);
1742 if (IS_ERR(gpio_iclks
[i
]))
1743 printk(KERN_ERR
"Could not get %s\n", clk_name
);
1745 clk_enable(gpio_iclks
[i
]);
1751 #ifdef CONFIG_ARCH_OMAP15XX
1752 if (cpu_is_omap15xx()) {
1753 gpio_bank_count
= 2;
1754 gpio_bank
= gpio_bank_1510
;
1758 #if defined(CONFIG_ARCH_OMAP16XX)
1759 if (cpu_is_omap16xx()) {
1760 gpio_bank_count
= 5;
1761 gpio_bank
= gpio_bank_1610
;
1765 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1766 if (cpu_is_omap7xx()) {
1767 gpio_bank_count
= 7;
1768 gpio_bank
= gpio_bank_7xx
;
1772 #ifdef CONFIG_ARCH_OMAP2
1773 if (cpu_is_omap242x()) {
1774 gpio_bank_count
= 4;
1775 gpio_bank
= gpio_bank_242x
;
1777 if (cpu_is_omap243x()) {
1778 gpio_bank_count
= 5;
1779 gpio_bank
= gpio_bank_243x
;
1782 #ifdef CONFIG_ARCH_OMAP3
1783 if (cpu_is_omap34xx()) {
1784 gpio_bank_count
= OMAP34XX_NR_GPIOS
;
1785 gpio_bank
= gpio_bank_34xx
;
1788 #ifdef CONFIG_ARCH_OMAP4
1789 if (cpu_is_omap44xx()) {
1790 gpio_bank_count
= OMAP34XX_NR_GPIOS
;
1791 gpio_bank
= gpio_bank_44xx
;
1794 for (i
= 0; i
< gpio_bank_count
; i
++) {
1795 int j
, gpio_count
= 16;
1797 bank
= &gpio_bank
[i
];
1798 spin_lock_init(&bank
->lock
);
1800 /* Static mapping, never released */
1801 bank
->base
= ioremap(bank
->pbase
, bank_size
);
1803 printk(KERN_ERR
"Could not ioremap gpio bank%i\n", i
);
1807 if (bank_is_mpuio(bank
))
1808 __raw_writew(0xffff, bank
->base
+ OMAP_MPUIO_GPIO_MASKIT
);
1809 if (cpu_is_omap15xx() && bank
->method
== METHOD_GPIO_1510
) {
1810 __raw_writew(0xffff, bank
->base
+ OMAP1510_GPIO_INT_MASK
);
1811 __raw_writew(0x0000, bank
->base
+ OMAP1510_GPIO_INT_STATUS
);
1813 if (cpu_is_omap16xx() && bank
->method
== METHOD_GPIO_1610
) {
1814 __raw_writew(0x0000, bank
->base
+ OMAP1610_GPIO_IRQENABLE1
);
1815 __raw_writew(0xffff, bank
->base
+ OMAP1610_GPIO_IRQSTATUS1
);
1816 __raw_writew(0x0014, bank
->base
+ OMAP1610_GPIO_SYSCONFIG
);
1818 if (cpu_is_omap7xx() && bank
->method
== METHOD_GPIO_7XX
) {
1819 __raw_writel(0xffffffff, bank
->base
+ OMAP7XX_GPIO_INT_MASK
);
1820 __raw_writel(0x00000000, bank
->base
+ OMAP7XX_GPIO_INT_STATUS
);
1822 gpio_count
= 32; /* 7xx has 32-bit GPIOs */
1825 #ifdef CONFIG_ARCH_OMAP2PLUS
1826 if ((bank
->method
== METHOD_GPIO_24XX
) ||
1827 (bank
->method
== METHOD_GPIO_44XX
)) {
1828 static const u32 non_wakeup_gpios
[] = {
1829 0xe203ffc0, 0x08700040
1832 if (cpu_is_omap44xx()) {
1833 __raw_writel(0xffffffff, bank
->base
+
1834 OMAP4_GPIO_IRQSTATUSCLR0
);
1835 __raw_writew(0x0015, bank
->base
+
1836 OMAP4_GPIO_SYSCONFIG
);
1837 __raw_writel(0x00000000, bank
->base
+
1838 OMAP4_GPIO_DEBOUNCENABLE
);
1840 * Initialize interface clock ungated,
1843 __raw_writel(0, bank
->base
+ OMAP4_GPIO_CTRL
);
1845 __raw_writel(0x00000000, bank
->base
+
1846 OMAP24XX_GPIO_IRQENABLE1
);
1847 __raw_writel(0xffffffff, bank
->base
+
1848 OMAP24XX_GPIO_IRQSTATUS1
);
1849 __raw_writew(0x0015, bank
->base
+
1850 OMAP24XX_GPIO_SYSCONFIG
);
1851 __raw_writel(0x00000000, bank
->base
+
1852 OMAP24XX_GPIO_DEBOUNCE_EN
);
1855 * Initialize interface clock ungated,
1858 __raw_writel(0, bank
->base
+
1859 OMAP24XX_GPIO_CTRL
);
1861 if (cpu_is_omap24xx() &&
1862 i
< ARRAY_SIZE(non_wakeup_gpios
))
1863 bank
->non_wakeup_gpios
= non_wakeup_gpios
[i
];
1868 bank
->mod_usage
= 0;
1869 /* REVISIT eventually switch from OMAP-specific gpio structs
1870 * over to the generic ones
1872 bank
->chip
.request
= omap_gpio_request
;
1873 bank
->chip
.free
= omap_gpio_free
;
1874 bank
->chip
.direction_input
= gpio_input
;
1875 bank
->chip
.get
= gpio_get
;
1876 bank
->chip
.direction_output
= gpio_output
;
1877 bank
->chip
.set
= gpio_set
;
1878 bank
->chip
.to_irq
= gpio_2irq
;
1879 if (bank_is_mpuio(bank
)) {
1880 bank
->chip
.label
= "mpuio";
1881 #ifdef CONFIG_ARCH_OMAP16XX
1882 bank
->chip
.dev
= &omap_mpuio_device
.dev
;
1884 bank
->chip
.base
= OMAP_MPUIO(0);
1886 bank
->chip
.label
= "gpio";
1887 bank
->chip
.base
= gpio
;
1890 bank
->chip
.ngpio
= gpio_count
;
1892 gpiochip_add(&bank
->chip
);
1894 for (j
= bank
->virtual_irq_start
;
1895 j
< bank
->virtual_irq_start
+ gpio_count
; j
++) {
1896 lockdep_set_class(&irq_desc
[j
].lock
, &gpio_lock_class
);
1897 set_irq_chip_data(j
, bank
);
1898 if (bank_is_mpuio(bank
))
1899 set_irq_chip(j
, &mpuio_irq_chip
);
1901 set_irq_chip(j
, &gpio_irq_chip
);
1902 set_irq_handler(j
, handle_simple_irq
);
1903 set_irq_flags(j
, IRQF_VALID
);
1905 set_irq_chained_handler(bank
->irq
, gpio_irq_handler
);
1906 set_irq_data(bank
->irq
, bank
);
1908 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1909 sprintf(clk_name
, "gpio%d_dbck", i
+ 1);
1910 bank
->dbck
= clk_get(NULL
, clk_name
);
1911 if (IS_ERR(bank
->dbck
))
1912 printk(KERN_ERR
"Could not get %s\n", clk_name
);
1916 /* Enable system clock for GPIO module.
1917 * The CAM_CLK_CTRL *is* really the right place. */
1918 if (cpu_is_omap16xx())
1919 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL
) | 0x04, ULPD_CAM_CLK_CTRL
);
1921 /* Enable autoidle for the OCP interface */
1922 if (cpu_is_omap24xx())
1923 omap_writel(1 << 0, 0x48019010);
1924 if (cpu_is_omap34xx())
1925 omap_writel(1 << 0, 0x48306814);
1927 omap_gpio_show_rev();
1932 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1933 static int omap_gpio_suspend(struct sys_device
*dev
, pm_message_t mesg
)
1937 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1940 for (i
= 0; i
< gpio_bank_count
; i
++) {
1941 struct gpio_bank
*bank
= &gpio_bank
[i
];
1942 void __iomem
*wake_status
;
1943 void __iomem
*wake_clear
;
1944 void __iomem
*wake_set
;
1945 unsigned long flags
;
1947 switch (bank
->method
) {
1948 #ifdef CONFIG_ARCH_OMAP16XX
1949 case METHOD_GPIO_1610
:
1950 wake_status
= bank
->base
+ OMAP1610_GPIO_WAKEUPENABLE
;
1951 wake_clear
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1952 wake_set
= bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
;
1955 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1956 case METHOD_GPIO_24XX
:
1957 wake_status
= bank
->base
+ OMAP24XX_GPIO_WAKE_EN
;
1958 wake_clear
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1959 wake_set
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
1962 #ifdef CONFIG_ARCH_OMAP4
1963 case METHOD_GPIO_44XX
:
1964 wake_status
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1965 wake_clear
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1966 wake_set
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1973 spin_lock_irqsave(&bank
->lock
, flags
);
1974 bank
->saved_wakeup
= __raw_readl(wake_status
);
1975 __raw_writel(0xffffffff, wake_clear
);
1976 __raw_writel(bank
->suspend_wakeup
, wake_set
);
1977 spin_unlock_irqrestore(&bank
->lock
, flags
);
1983 static int omap_gpio_resume(struct sys_device
*dev
)
1987 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1990 for (i
= 0; i
< gpio_bank_count
; i
++) {
1991 struct gpio_bank
*bank
= &gpio_bank
[i
];
1992 void __iomem
*wake_clear
;
1993 void __iomem
*wake_set
;
1994 unsigned long flags
;
1996 switch (bank
->method
) {
1997 #ifdef CONFIG_ARCH_OMAP16XX
1998 case METHOD_GPIO_1610
:
1999 wake_clear
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
2000 wake_set
= bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
;
2003 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
2004 case METHOD_GPIO_24XX
:
2005 wake_clear
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
2006 wake_set
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
2009 #ifdef CONFIG_ARCH_OMAP4
2010 case METHOD_GPIO_44XX
:
2011 wake_clear
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
2012 wake_set
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
2019 spin_lock_irqsave(&bank
->lock
, flags
);
2020 __raw_writel(0xffffffff, wake_clear
);
2021 __raw_writel(bank
->saved_wakeup
, wake_set
);
2022 spin_unlock_irqrestore(&bank
->lock
, flags
);
2028 static struct sysdev_class omap_gpio_sysclass
= {
2030 .suspend
= omap_gpio_suspend
,
2031 .resume
= omap_gpio_resume
,
2034 static struct sys_device omap_gpio_device
= {
2036 .cls
= &omap_gpio_sysclass
,
2041 #ifdef CONFIG_ARCH_OMAP2PLUS
2043 static int workaround_enabled
;
2045 void omap2_gpio_prepare_for_idle(int power_state
)
2050 if (cpu_is_omap34xx())
2053 for (i
= min
; i
< gpio_bank_count
; i
++) {
2054 struct gpio_bank
*bank
= &gpio_bank
[i
];
2057 if (power_state
> PWRDM_POWER_OFF
)
2060 /* If going to OFF, remove triggering for all
2061 * non-wakeup GPIOs. Otherwise spurious IRQs will be
2062 * generated. See OMAP2420 Errata item 1.101. */
2063 if (!(bank
->enabled_non_wakeup_gpios
))
2066 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2067 bank
->saved_datain
= __raw_readl(bank
->base
+
2068 OMAP24XX_GPIO_DATAIN
);
2069 l1
= __raw_readl(bank
->base
+
2070 OMAP24XX_GPIO_FALLINGDETECT
);
2071 l2
= __raw_readl(bank
->base
+
2072 OMAP24XX_GPIO_RISINGDETECT
);
2075 if (cpu_is_omap44xx()) {
2076 bank
->saved_datain
= __raw_readl(bank
->base
+
2078 l1
= __raw_readl(bank
->base
+
2079 OMAP4_GPIO_FALLINGDETECT
);
2080 l2
= __raw_readl(bank
->base
+
2081 OMAP4_GPIO_RISINGDETECT
);
2084 bank
->saved_fallingdetect
= l1
;
2085 bank
->saved_risingdetect
= l2
;
2086 l1
&= ~bank
->enabled_non_wakeup_gpios
;
2087 l2
&= ~bank
->enabled_non_wakeup_gpios
;
2089 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2090 __raw_writel(l1
, bank
->base
+
2091 OMAP24XX_GPIO_FALLINGDETECT
);
2092 __raw_writel(l2
, bank
->base
+
2093 OMAP24XX_GPIO_RISINGDETECT
);
2096 if (cpu_is_omap44xx()) {
2097 __raw_writel(l1
, bank
->base
+ OMAP4_GPIO_FALLINGDETECT
);
2098 __raw_writel(l2
, bank
->base
+ OMAP4_GPIO_RISINGDETECT
);
2104 workaround_enabled
= 0;
2107 workaround_enabled
= 1;
2110 void omap2_gpio_resume_after_idle(void)
2115 if (cpu_is_omap34xx())
2117 for (i
= min
; i
< gpio_bank_count
; i
++) {
2118 struct gpio_bank
*bank
= &gpio_bank
[i
];
2119 u32 l
, gen
, gen0
, gen1
;
2121 if (!workaround_enabled
)
2124 if (!(bank
->enabled_non_wakeup_gpios
))
2127 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2128 __raw_writel(bank
->saved_fallingdetect
,
2129 bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
2130 __raw_writel(bank
->saved_risingdetect
,
2131 bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
2132 l
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_DATAIN
);
2135 if (cpu_is_omap44xx()) {
2136 __raw_writel(bank
->saved_fallingdetect
,
2137 bank
->base
+ OMAP4_GPIO_FALLINGDETECT
);
2138 __raw_writel(bank
->saved_risingdetect
,
2139 bank
->base
+ OMAP4_GPIO_RISINGDETECT
);
2140 l
= __raw_readl(bank
->base
+ OMAP4_GPIO_DATAIN
);
2143 /* Check if any of the non-wakeup interrupt GPIOs have changed
2144 * state. If so, generate an IRQ by software. This is
2145 * horribly racy, but it's the best we can do to work around
2146 * this silicon bug. */
2147 l
^= bank
->saved_datain
;
2148 l
&= bank
->enabled_non_wakeup_gpios
;
2151 * No need to generate IRQs for the rising edge for gpio IRQs
2152 * configured with falling edge only; and vice versa.
2154 gen0
= l
& bank
->saved_fallingdetect
;
2155 gen0
&= bank
->saved_datain
;
2157 gen1
= l
& bank
->saved_risingdetect
;
2158 gen1
&= ~(bank
->saved_datain
);
2160 /* FIXME: Consider GPIO IRQs with level detections properly! */
2161 gen
= l
& (~(bank
->saved_fallingdetect
) &
2162 ~(bank
->saved_risingdetect
));
2163 /* Consider all GPIO IRQs needed to be updated */
2169 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2170 old0
= __raw_readl(bank
->base
+
2171 OMAP24XX_GPIO_LEVELDETECT0
);
2172 old1
= __raw_readl(bank
->base
+
2173 OMAP24XX_GPIO_LEVELDETECT1
);
2174 __raw_writel(old0
| gen
, bank
->base
+
2175 OMAP24XX_GPIO_LEVELDETECT0
);
2176 __raw_writel(old1
| gen
, bank
->base
+
2177 OMAP24XX_GPIO_LEVELDETECT1
);
2178 __raw_writel(old0
, bank
->base
+
2179 OMAP24XX_GPIO_LEVELDETECT0
);
2180 __raw_writel(old1
, bank
->base
+
2181 OMAP24XX_GPIO_LEVELDETECT1
);
2184 if (cpu_is_omap44xx()) {
2185 old0
= __raw_readl(bank
->base
+
2186 OMAP4_GPIO_LEVELDETECT0
);
2187 old1
= __raw_readl(bank
->base
+
2188 OMAP4_GPIO_LEVELDETECT1
);
2189 __raw_writel(old0
| l
, bank
->base
+
2190 OMAP4_GPIO_LEVELDETECT0
);
2191 __raw_writel(old1
| l
, bank
->base
+
2192 OMAP4_GPIO_LEVELDETECT1
);
2193 __raw_writel(old0
, bank
->base
+
2194 OMAP4_GPIO_LEVELDETECT0
);
2195 __raw_writel(old1
, bank
->base
+
2196 OMAP4_GPIO_LEVELDETECT1
);
2205 #ifdef CONFIG_ARCH_OMAP3
2206 /* save the registers of bank 2-6 */
2207 void omap_gpio_save_context(void)
2211 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2212 for (i
= 1; i
< gpio_bank_count
; i
++) {
2213 struct gpio_bank
*bank
= &gpio_bank
[i
];
2214 gpio_context
[i
].sysconfig
=
2215 __raw_readl(bank
->base
+ OMAP24XX_GPIO_SYSCONFIG
);
2216 gpio_context
[i
].irqenable1
=
2217 __raw_readl(bank
->base
+ OMAP24XX_GPIO_IRQENABLE1
);
2218 gpio_context
[i
].irqenable2
=
2219 __raw_readl(bank
->base
+ OMAP24XX_GPIO_IRQENABLE2
);
2220 gpio_context
[i
].wake_en
=
2221 __raw_readl(bank
->base
+ OMAP24XX_GPIO_WAKE_EN
);
2222 gpio_context
[i
].ctrl
=
2223 __raw_readl(bank
->base
+ OMAP24XX_GPIO_CTRL
);
2224 gpio_context
[i
].oe
=
2225 __raw_readl(bank
->base
+ OMAP24XX_GPIO_OE
);
2226 gpio_context
[i
].leveldetect0
=
2227 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
2228 gpio_context
[i
].leveldetect1
=
2229 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
2230 gpio_context
[i
].risingdetect
=
2231 __raw_readl(bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
2232 gpio_context
[i
].fallingdetect
=
2233 __raw_readl(bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
2234 gpio_context
[i
].dataout
=
2235 __raw_readl(bank
->base
+ OMAP24XX_GPIO_DATAOUT
);
2236 gpio_context
[i
].setwkuena
=
2237 __raw_readl(bank
->base
+ OMAP24XX_GPIO_SETWKUENA
);
2238 gpio_context
[i
].setdataout
=
2239 __raw_readl(bank
->base
+ OMAP24XX_GPIO_SETDATAOUT
);
2243 /* restore the required registers of bank 2-6 */
2244 void omap_gpio_restore_context(void)
2248 for (i
= 1; i
< gpio_bank_count
; i
++) {
2249 struct gpio_bank
*bank
= &gpio_bank
[i
];
2250 __raw_writel(gpio_context
[i
].sysconfig
,
2251 bank
->base
+ OMAP24XX_GPIO_SYSCONFIG
);
2252 __raw_writel(gpio_context
[i
].irqenable1
,
2253 bank
->base
+ OMAP24XX_GPIO_IRQENABLE1
);
2254 __raw_writel(gpio_context
[i
].irqenable2
,
2255 bank
->base
+ OMAP24XX_GPIO_IRQENABLE2
);
2256 __raw_writel(gpio_context
[i
].wake_en
,
2257 bank
->base
+ OMAP24XX_GPIO_WAKE_EN
);
2258 __raw_writel(gpio_context
[i
].ctrl
,
2259 bank
->base
+ OMAP24XX_GPIO_CTRL
);
2260 __raw_writel(gpio_context
[i
].oe
,
2261 bank
->base
+ OMAP24XX_GPIO_OE
);
2262 __raw_writel(gpio_context
[i
].leveldetect0
,
2263 bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
2264 __raw_writel(gpio_context
[i
].leveldetect1
,
2265 bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
2266 __raw_writel(gpio_context
[i
].risingdetect
,
2267 bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
2268 __raw_writel(gpio_context
[i
].fallingdetect
,
2269 bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
2270 __raw_writel(gpio_context
[i
].dataout
,
2271 bank
->base
+ OMAP24XX_GPIO_DATAOUT
);
2272 __raw_writel(gpio_context
[i
].setwkuena
,
2273 bank
->base
+ OMAP24XX_GPIO_SETWKUENA
);
2274 __raw_writel(gpio_context
[i
].setdataout
,
2275 bank
->base
+ OMAP24XX_GPIO_SETDATAOUT
);
2281 * This may get called early from board specific init
2282 * for boards that have interrupts routed via FPGA.
2284 int __init
omap_gpio_init(void)
2287 return _omap_gpio_init();
2292 static int __init
omap_gpio_sysinit(void)
2297 ret
= _omap_gpio_init();
2301 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2302 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2304 ret
= sysdev_class_register(&omap_gpio_sysclass
);
2306 ret
= sysdev_register(&omap_gpio_device
);
2314 arch_initcall(omap_gpio_sysinit
);
2317 #ifdef CONFIG_DEBUG_FS
2319 #include <linux/debugfs.h>
2320 #include <linux/seq_file.h>
2322 static int dbg_gpio_show(struct seq_file
*s
, void *unused
)
2324 unsigned i
, j
, gpio
;
2326 for (i
= 0, gpio
= 0; i
< gpio_bank_count
; i
++) {
2327 struct gpio_bank
*bank
= gpio_bank
+ i
;
2328 unsigned bankwidth
= 16;
2331 if (bank_is_mpuio(bank
))
2332 gpio
= OMAP_MPUIO(0);
2333 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
2336 for (j
= 0; j
< bankwidth
; j
++, gpio
++, mask
<<= 1) {
2337 unsigned irq
, value
, is_in
, irqstat
;
2340 label
= gpiochip_is_requested(&bank
->chip
, j
);
2344 irq
= bank
->virtual_irq_start
+ j
;
2345 value
= gpio_get_value(gpio
);
2346 is_in
= gpio_is_input(bank
, mask
);
2348 if (bank_is_mpuio(bank
))
2349 seq_printf(s
, "MPUIO %2d ", j
);
2351 seq_printf(s
, "GPIO %3d ", gpio
);
2352 seq_printf(s
, "(%-20.20s): %s %s",
2354 is_in
? "in " : "out",
2355 value
? "hi" : "lo");
2357 /* FIXME for at least omap2, show pullup/pulldown state */
2359 irqstat
= irq_desc
[irq
].status
;
2360 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2361 if (is_in
&& ((bank
->suspend_wakeup
& mask
)
2362 || irqstat
& IRQ_TYPE_SENSE_MASK
)) {
2363 char *trigger
= NULL
;
2365 switch (irqstat
& IRQ_TYPE_SENSE_MASK
) {
2366 case IRQ_TYPE_EDGE_FALLING
:
2367 trigger
= "falling";
2369 case IRQ_TYPE_EDGE_RISING
:
2372 case IRQ_TYPE_EDGE_BOTH
:
2373 trigger
= "bothedge";
2375 case IRQ_TYPE_LEVEL_LOW
:
2378 case IRQ_TYPE_LEVEL_HIGH
:
2385 seq_printf(s
, ", irq-%d %-8s%s",
2387 (bank
->suspend_wakeup
& mask
)
2391 seq_printf(s
, "\n");
2394 if (bank_is_mpuio(bank
)) {
2395 seq_printf(s
, "\n");
2402 static int dbg_gpio_open(struct inode
*inode
, struct file
*file
)
2404 return single_open(file
, dbg_gpio_show
, &inode
->i_private
);
2407 static const struct file_operations debug_fops
= {
2408 .open
= dbg_gpio_open
,
2410 .llseek
= seq_lseek
,
2411 .release
= single_release
,
2414 static int __init
omap_gpio_debuginit(void)
2416 (void) debugfs_create_file("omap_gpio", S_IRUGO
,
2417 NULL
, NULL
, &debug_fops
);
2420 late_initcall(omap_gpio_debuginit
);