2 * pata_cmd64x.c - CMD64x PATA for new ATA layer
4 * Alan Cox <alan@lxorguk.ukuu.org.uk>
7 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
9 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
10 * Note, this driver is not used at all on other systems because
11 * there the "BIOS" has done all of the following already.
12 * Due to massive hardware bugs, UltraDMA is only supported
13 * on the 646U2 and not on the 646U.
15 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
16 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
18 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <scsi/scsi_host.h>
31 #include <linux/libata.h>
33 #define DRV_NAME "pata_cmd64x"
34 #define DRV_VERSION "0.3.1"
37 * CMD64x specific registers definition.
53 ARTTIM23_DIS_RA2
= 0x04,
54 ARTTIM23_DIS_RA3
= 0x08,
55 ARTTIM23_INTR_CH1
= 0x10,
64 MRDMODE_INTR_CH0
= 0x04,
65 MRDMODE_INTR_CH1
= 0x08,
66 MRDMODE_BLK_CH0
= 0x10,
67 MRDMODE_BLK_CH1
= 0x20,
78 static int cmd648_cable_detect(struct ata_port
*ap
)
80 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
83 /* Check cable detect bits */
84 pci_read_config_byte(pdev
, BMIDECSR
, &r
);
85 if (r
& (1 << ap
->port_no
))
86 return ATA_CBL_PATA80
;
87 return ATA_CBL_PATA40
;
91 * cmd64x_set_piomode - set PIO and MWDMA timing
96 * Called to do the PIO and MWDMA mode setup.
99 static void cmd64x_set_timing(struct ata_port
*ap
, struct ata_device
*adev
, u8 mode
)
101 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
103 const unsigned long T
= 1000000 / 33;
104 const u8 setup_data
[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
108 /* Port layout is not logical so use a table */
109 const u8 arttim_port
[2][2] = {
110 { ARTTIM0
, ARTTIM1
},
111 { ARTTIM23
, ARTTIM23
}
113 const u8 drwtim_port
[2][2] = {
114 { DRWTIM0
, DRWTIM1
},
118 int arttim
= arttim_port
[ap
->port_no
][adev
->devno
];
119 int drwtim
= drwtim_port
[ap
->port_no
][adev
->devno
];
121 /* ata_timing_compute is smart and will produce timings for MWDMA
122 that don't violate the drives PIO capabilities. */
123 if (ata_timing_compute(adev
, mode
, &t
, T
, 0) < 0) {
124 printk(KERN_ERR DRV_NAME
": mode computation failed.\n");
128 /* Slave has shared address setup */
129 struct ata_device
*pair
= ata_dev_pair(adev
);
132 struct ata_timing tp
;
133 ata_timing_compute(pair
, pair
->pio_mode
, &tp
, T
, 0);
134 ata_timing_merge(&t
, &tp
, &t
, ATA_TIMING_SETUP
);
138 printk(KERN_DEBUG DRV_NAME
": active %d recovery %d setup %d.\n",
139 t
.active
, t
.recover
, t
.setup
);
140 if (t
.recover
> 16) {
141 t
.active
+= t
.recover
- 16;
147 /* Now convert the clocks into values we can actually stuff into
158 t
.setup
= setup_data
[t
.setup
];
160 t
.active
&= 0x0F; /* 0 = 16 */
162 /* Load setup timing */
163 pci_read_config_byte(pdev
, arttim
, ®
);
166 pci_write_config_byte(pdev
, arttim
, reg
);
168 /* Load active/recovery */
169 pci_write_config_byte(pdev
, drwtim
, (t
.active
<< 4) | t
.recover
);
173 * cmd64x_set_piomode - set initial PIO mode data
177 * Used when configuring the devices ot set the PIO timings. All the
178 * actual work is done by the PIO/MWDMA setting helper
181 static void cmd64x_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
183 cmd64x_set_timing(ap
, adev
, adev
->pio_mode
);
187 * cmd64x_set_dmamode - set initial DMA mode data
191 * Called to do the DMA mode setup.
194 static void cmd64x_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
196 static const u8 udma_data
[] = {
197 0x30, 0x20, 0x10, 0x20, 0x10, 0x00
200 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
203 int pciU
= UDIDETCR0
+ 8 * ap
->port_no
;
204 int pciD
= BMIDESR0
+ 8 * ap
->port_no
;
205 int shift
= 2 * adev
->devno
;
207 pci_read_config_byte(pdev
, pciD
, ®D
);
208 pci_read_config_byte(pdev
, pciU
, ®U
);
211 regD
&= ~(0x20 << adev
->devno
);
212 /* DMA control bits */
213 regU
&= ~(0x30 << shift
);
214 /* DMA timing bits */
215 regU
&= ~(0x05 << adev
->devno
);
217 if (adev
->dma_mode
>= XFER_UDMA_0
) {
218 /* Merge the timing value */
219 regU
|= udma_data
[adev
->dma_mode
- XFER_UDMA_0
] << shift
;
220 /* Merge the control bits */
221 regU
|= 1 << adev
->devno
; /* UDMA on */
222 if (adev
->dma_mode
> 2) /* 15nS timing */
223 regU
|= 4 << adev
->devno
;
225 regU
&= ~ (1 << adev
->devno
); /* UDMA off */
226 cmd64x_set_timing(ap
, adev
, adev
->dma_mode
);
229 regD
|= 0x20 << adev
->devno
;
231 pci_write_config_byte(pdev
, pciU
, regU
);
232 pci_write_config_byte(pdev
, pciD
, regD
);
236 * cmd648_dma_stop - DMA stop callback
237 * @qc: Command in progress
242 static void cmd648_bmdma_stop(struct ata_queued_cmd
*qc
)
244 struct ata_port
*ap
= qc
->ap
;
245 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
247 int dma_mask
= ap
->port_no
? ARTTIM23_INTR_CH1
: CFR_INTR_CH0
;
248 int dma_reg
= ap
->port_no
? ARTTIM2
: CFR
;
252 pci_read_config_byte(pdev
, dma_reg
, &dma_intr
);
253 pci_write_config_byte(pdev
, dma_reg
, dma_intr
| dma_mask
);
257 * cmd64x_bmdma_stop - DMA stop callback
258 * @qc: Command in progress
260 * Track the completion of live DMA commands and clear the
261 * host->private_data DMA tracking flag as we do.
264 static void cmd64x_bmdma_stop(struct ata_queued_cmd
*qc
)
266 struct ata_port
*ap
= qc
->ap
;
268 WARN_ON(ap
->host
->private_data
!= ap
);
269 ap
->host
->private_data
= NULL
;
273 * cmd64x_qc_defer - Defer logic for chip limits
274 * @qc: queued command
276 * Decide whether we can issue the command. Called under the host lock.
279 static int cmd64x_qc_defer(struct ata_queued_cmd
*qc
)
281 struct ata_host
*host
= qc
->ap
->host
;
282 struct ata_port
*alt
= host
->ports
[1 ^ qc
->ap
->port_no
];
286 /* Apply the ATA rules first */
287 rc
= ata_std_qc_defer(qc
);
291 if (qc
->tf
.protocol
== ATAPI_PROT_DMA
||
292 qc
->tf
.protocol
== ATA_PROT_DMA
)
295 /* If the other port is not live then issue the command */
296 if (alt
== NULL
|| !alt
->qc_active
) {
298 host
->private_data
= qc
->ap
;
301 /* If there is a live DMA command then wait */
302 if (host
->private_data
!= NULL
)
303 return ATA_DEFER_PORT
;
305 /* Cannot overlap our DMA command */
306 return ATA_DEFER_PORT
;
311 * cmd64x_interrupt - ATA host interrupt handler
312 * @irq: irq line (unused)
313 * @dev_instance: pointer to our ata_host information structure
315 * Our interrupt handler for PCI IDE devices. Calls
316 * ata_sff_host_intr() for each port that is flagging an IRQ. We cannot
317 * use the defaults as we need to avoid touching status/altstatus during
321 * Obtains host lock during operation.
324 * IRQ_NONE or IRQ_HANDLED.
326 irqreturn_t
cmd64x_interrupt(int irq
, void *dev_instance
)
328 struct ata_host
*host
= dev_instance
;
329 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
331 unsigned int handled
= 0;
333 static const u8 irq_reg
[2] = { CFR
, ARTTIM23
};
334 static const u8 irq_mask
[2] = { 1 << 2, 1 << 4 };
336 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
337 spin_lock_irqsave(&host
->lock
, flags
);
339 for (i
= 0; i
< host
->n_ports
; i
++) {
343 pci_read_config_byte(pdev
, irq_reg
[i
], ®
);
345 if (ap
&& (reg
& irq_mask
[i
]) &&
346 !(ap
->flags
& ATA_FLAG_DISABLED
)) {
347 struct ata_queued_cmd
*qc
;
349 qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
350 if (qc
&& (!(qc
->tf
.flags
& ATA_TFLAG_POLLING
)) &&
351 (qc
->flags
& ATA_QCFLAG_ACTIVE
))
352 handled
|= ata_sff_host_intr(ap
, qc
);
356 spin_unlock_irqrestore(&host
->lock
, flags
);
358 return IRQ_RETVAL(handled
);
360 static struct scsi_host_template cmd64x_sht
= {
361 ATA_BMDMA_SHT(DRV_NAME
),
364 static const struct ata_port_operations cmd64x_base_ops
= {
365 .inherits
= &ata_bmdma_port_ops
,
366 .set_piomode
= cmd64x_set_piomode
,
367 .set_dmamode
= cmd64x_set_dmamode
,
368 .bmdma_stop
= cmd64x_bmdma_stop
,
369 .qc_defer
= cmd64x_qc_defer
,
372 static struct ata_port_operations cmd64x_port_ops
= {
373 .inherits
= &cmd64x_base_ops
,
374 .cable_detect
= ata_cable_40wire
,
377 static struct ata_port_operations cmd646r1_port_ops
= {
378 .inherits
= &cmd64x_base_ops
,
379 .cable_detect
= ata_cable_40wire
,
382 static struct ata_port_operations cmd648_port_ops
= {
383 .inherits
= &cmd64x_base_ops
,
384 .bmdma_stop
= cmd648_bmdma_stop
,
385 .cable_detect
= cmd648_cable_detect
,
386 .qc_defer
= ata_std_qc_defer
389 static int cmd64x_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
391 static const struct ata_port_info cmd_info
[6] = {
392 { /* CMD 643 - no UDMA */
393 .flags
= ATA_FLAG_SLAVE_POSS
,
394 .pio_mask
= ATA_PIO4
,
395 .mwdma_mask
= ATA_MWDMA2
,
396 .port_ops
= &cmd64x_port_ops
398 { /* CMD 646 with broken UDMA */
399 .flags
= ATA_FLAG_SLAVE_POSS
,
400 .pio_mask
= ATA_PIO4
,
401 .mwdma_mask
= ATA_MWDMA2
,
402 .port_ops
= &cmd64x_port_ops
404 { /* CMD 646 with working UDMA */
405 .flags
= ATA_FLAG_SLAVE_POSS
,
406 .pio_mask
= ATA_PIO4
,
407 .mwdma_mask
= ATA_MWDMA2
,
408 .udma_mask
= ATA_UDMA2
,
409 .port_ops
= &cmd64x_port_ops
411 { /* CMD 646 rev 1 */
412 .flags
= ATA_FLAG_SLAVE_POSS
,
413 .pio_mask
= ATA_PIO4
,
414 .mwdma_mask
= ATA_MWDMA2
,
415 .port_ops
= &cmd646r1_port_ops
418 .flags
= ATA_FLAG_SLAVE_POSS
,
419 .pio_mask
= ATA_PIO4
,
420 .mwdma_mask
= ATA_MWDMA2
,
421 .udma_mask
= ATA_UDMA4
,
422 .port_ops
= &cmd648_port_ops
425 .flags
= ATA_FLAG_SLAVE_POSS
,
426 .pio_mask
= ATA_PIO4
,
427 .mwdma_mask
= ATA_MWDMA2
,
428 .udma_mask
= ATA_UDMA5
,
429 .port_ops
= &cmd648_port_ops
432 const struct ata_port_info
*ppi
[] = { &cmd_info
[id
->driver_data
], NULL
};
435 struct ata_host
*host
;
437 rc
= pcim_enable_device(pdev
);
441 if (id
->driver_data
== 0) /* 643 */
442 ata_pci_bmdma_clear_simplex(pdev
);
444 if (pdev
->device
== PCI_DEVICE_ID_CMD_646
) {
445 /* Does UDMA work ? */
446 if (pdev
->revision
> 4)
447 ppi
[0] = &cmd_info
[2];
448 /* Early rev with other problems ? */
449 else if (pdev
->revision
== 1)
450 ppi
[0] = &cmd_info
[3];
454 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 64);
455 pci_read_config_byte(pdev
, MRDMODE
, &mrdmode
);
456 mrdmode
&= ~ 0x30; /* IRQ set up */
457 mrdmode
|= 0x02; /* Memory read line enable */
458 pci_write_config_byte(pdev
, MRDMODE
, mrdmode
);
460 /* PPC specific fixup copied from old driver */
462 pci_write_config_byte(pdev
, UDIDETCR0
, 0xF0);
464 rc
= ata_pci_sff_prepare_host(pdev
, ppi
, &host
);
467 /* We use this pointer to track the AP which has DMA running */
468 host
->private_data
= NULL
;
470 pci_set_master(pdev
);
471 return ata_pci_sff_activate_host(host
, cmd64x_interrupt
, &cmd64x_sht
);
475 static int cmd64x_reinit_one(struct pci_dev
*pdev
)
477 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
481 rc
= ata_pci_device_do_resume(pdev
);
485 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 64);
486 pci_read_config_byte(pdev
, MRDMODE
, &mrdmode
);
487 mrdmode
&= ~ 0x30; /* IRQ set up */
488 mrdmode
|= 0x02; /* Memory read line enable */
489 pci_write_config_byte(pdev
, MRDMODE
, mrdmode
);
491 pci_write_config_byte(pdev
, UDIDETCR0
, 0xF0);
493 ata_host_resume(host
);
498 static const struct pci_device_id cmd64x
[] = {
499 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_CMD_643
), 0 },
500 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_CMD_646
), 1 },
501 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_CMD_648
), 4 },
502 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_CMD_649
), 5 },
507 static struct pci_driver cmd64x_pci_driver
= {
510 .probe
= cmd64x_init_one
,
511 .remove
= ata_pci_remove_one
,
513 .suspend
= ata_pci_device_suspend
,
514 .resume
= cmd64x_reinit_one
,
518 static int __init
cmd64x_init(void)
520 return pci_register_driver(&cmd64x_pci_driver
);
523 static void __exit
cmd64x_exit(void)
525 pci_unregister_driver(&cmd64x_pci_driver
);
528 MODULE_AUTHOR("Alan Cox");
529 MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
530 MODULE_LICENSE("GPL");
531 MODULE_DEVICE_TABLE(pci
, cmd64x
);
532 MODULE_VERSION(DRV_VERSION
);
534 module_init(cmd64x_init
);
535 module_exit(cmd64x_exit
);