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ath9k: clean up enums and unused macros
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / xmit.c
blob6fcf1d708843f62978f047a71daed7f6abde6c4f
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "ath9k.h"
18 #include "ar9003_mac.h"
19
20 #define BITS_PER_BYTE 8
21 #define OFDM_PLCP_BITS 22
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
23 #define L_STF 8
24 #define L_LTF 8
25 #define L_SIG 4
26 #define HT_SIG 8
27 #define HT_STF 4
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
33
34
35 static u16 bits_per_symbol[][2] = {
36 /* 20MHz 40MHz */
37 { 26, 54 }, /* 0: BPSK */
38 { 52, 108 }, /* 1: QPSK 1/2 */
39 { 78, 162 }, /* 2: QPSK 3/4 */
40 { 104, 216 }, /* 3: 16-QAM 1/2 */
41 { 156, 324 }, /* 4: 16-QAM 3/4 */
42 { 208, 432 }, /* 5: 64-QAM 2/3 */
43 { 234, 486 }, /* 6: 64-QAM 3/4 */
44 { 260, 540 }, /* 7: 64-QAM 5/6 */
45 };
46
47 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
48
49 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
50 struct ath_atx_tid *tid,
51 struct list_head *bf_head);
52 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
53 struct ath_txq *txq, struct list_head *bf_q,
54 struct ath_tx_status *ts, int txok, int sendbar);
55 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
56 struct list_head *head);
57 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
58 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
59 int nframes, int nbad, int txok, bool update_rc);
60 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
61 int seqno);
62
63 enum {
64 MCS_HT20,
65 MCS_HT20_SGI,
66 MCS_HT40,
67 MCS_HT40_SGI,
68 };
69
70 static int ath_max_4ms_framelen[4][32] = {
71 [MCS_HT20] = {
72 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
73 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
74 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
75 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
76 },
77 [MCS_HT20_SGI] = {
78 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
79 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
80 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
81 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
82 },
83 [MCS_HT40] = {
84 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
85 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
86 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
87 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
88 },
89 [MCS_HT40_SGI] = {
90 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
91 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
92 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
93 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
94 }
95 };
96
97 /*********************/
98 /* Aggregation logic */
99 /*********************/
100
101 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
102 {
103 struct ath_atx_ac *ac = tid->ac;
104
105 if (tid->paused)
106 return;
107
108 if (tid->sched)
109 return;
110
111 tid->sched = true;
112 list_add_tail(&tid->list, &ac->tid_q);
113
114 if (ac->sched)
115 return;
116
117 ac->sched = true;
118 list_add_tail(&ac->list, &txq->axq_acq);
119 }
120
121 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
122 {
123 struct ath_txq *txq = tid->ac->txq;
124
125 WARN_ON(!tid->paused);
126
127 spin_lock_bh(&txq->axq_lock);
128 tid->paused = false;
129
130 if (list_empty(&tid->buf_q))
131 goto unlock;
132
133 ath_tx_queue_tid(txq, tid);
134 ath_txq_schedule(sc, txq);
135 unlock:
136 spin_unlock_bh(&txq->axq_lock);
137 }
138
139 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
140 {
141 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
142 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
143 sizeof(tx_info->rate_driver_data));
144 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
145 }
146
147 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
148 {
149 struct ath_txq *txq = tid->ac->txq;
150 struct ath_buf *bf;
151 struct list_head bf_head;
152 struct ath_tx_status ts;
153 struct ath_frame_info *fi;
154
155 INIT_LIST_HEAD(&bf_head);
156
157 memset(&ts, 0, sizeof(ts));
158 spin_lock_bh(&txq->axq_lock);
159
160 while (!list_empty(&tid->buf_q)) {
161 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
162 list_move_tail(&bf->list, &bf_head);
163
164 spin_unlock_bh(&txq->axq_lock);
165 fi = get_frame_info(bf->bf_mpdu);
166 if (fi->retries) {
167 ath_tx_update_baw(sc, tid, fi->seqno);
168 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
169 } else {
170 ath_tx_send_normal(sc, txq, NULL, &bf_head);
171 }
172 spin_lock_bh(&txq->axq_lock);
173 }
174
175 spin_unlock_bh(&txq->axq_lock);
176 }
177
178 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
179 int seqno)
180 {
181 int index, cindex;
182
183 index = ATH_BA_INDEX(tid->seq_start, seqno);
184 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
185
186 __clear_bit(cindex, tid->tx_buf);
187
188 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
189 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
190 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
191 }
192 }
193
194 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
195 u16 seqno)
196 {
197 int index, cindex;
198
199 index = ATH_BA_INDEX(tid->seq_start, seqno);
200 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
201 __set_bit(cindex, tid->tx_buf);
202
203 if (index >= ((tid->baw_tail - tid->baw_head) &
204 (ATH_TID_MAX_BUFS - 1))) {
205 tid->baw_tail = cindex;
206 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
207 }
208 }
209
210 /*
211 * TODO: For frame(s) that are in the retry state, we will reuse the
212 * sequence number(s) without setting the retry bit. The
213 * alternative is to give up on these and BAR the receiver's window
214 * forward.
215 */
216 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
217 struct ath_atx_tid *tid)
218
219 {
220 struct ath_buf *bf;
221 struct list_head bf_head;
222 struct ath_tx_status ts;
223 struct ath_frame_info *fi;
224
225 memset(&ts, 0, sizeof(ts));
226 INIT_LIST_HEAD(&bf_head);
227
228 for (;;) {
229 if (list_empty(&tid->buf_q))
230 break;
231
232 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
233 list_move_tail(&bf->list, &bf_head);
234
235 fi = get_frame_info(bf->bf_mpdu);
236 if (fi->retries)
237 ath_tx_update_baw(sc, tid, fi->seqno);
238
239 spin_unlock(&txq->axq_lock);
240 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
241 spin_lock(&txq->axq_lock);
242 }
243
244 tid->seq_next = tid->seq_start;
245 tid->baw_tail = tid->baw_head;
246 }
247
248 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
249 struct sk_buff *skb)
250 {
251 struct ath_frame_info *fi = get_frame_info(skb);
252 struct ieee80211_hdr *hdr;
253
254 TX_STAT_INC(txq->axq_qnum, a_retries);
255 if (fi->retries++ > 0)
256 return;
257
258 hdr = (struct ieee80211_hdr *)skb->data;
259 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
260 }
261
262 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
263 {
264 struct ath_buf *bf = NULL;
265
266 spin_lock_bh(&sc->tx.txbuflock);
267
268 if (unlikely(list_empty(&sc->tx.txbuf))) {
269 spin_unlock_bh(&sc->tx.txbuflock);
270 return NULL;
271 }
272
273 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
274 list_del(&bf->list);
275
276 spin_unlock_bh(&sc->tx.txbuflock);
277
278 return bf;
279 }
280
281 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
282 {
283 spin_lock_bh(&sc->tx.txbuflock);
284 list_add_tail(&bf->list, &sc->tx.txbuf);
285 spin_unlock_bh(&sc->tx.txbuflock);
286 }
287
288 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
289 {
290 struct ath_buf *tbf;
291
292 tbf = ath_tx_get_buffer(sc);
293 if (WARN_ON(!tbf))
294 return NULL;
295
296 ATH_TXBUF_RESET(tbf);
297
298 tbf->aphy = bf->aphy;
299 tbf->bf_mpdu = bf->bf_mpdu;
300 tbf->bf_buf_addr = bf->bf_buf_addr;
301 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
302 tbf->bf_state = bf->bf_state;
303
304 return tbf;
305 }
306
307 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
308 struct ath_tx_status *ts, int txok,
309 int *nframes, int *nbad)
310 {
311 struct ath_frame_info *fi;
312 u16 seq_st = 0;
313 u32 ba[WME_BA_BMP_SIZE >> 5];
314 int ba_index;
315 int isaggr = 0;
316
317 *nbad = 0;
318 *nframes = 0;
319
320 isaggr = bf_isaggr(bf);
321 if (isaggr) {
322 seq_st = ts->ts_seqnum;
323 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
324 }
325
326 while (bf) {
327 fi = get_frame_info(bf->bf_mpdu);
328 ba_index = ATH_BA_INDEX(seq_st, fi->seqno);
329
330 (*nframes)++;
331 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
332 (*nbad)++;
333
334 bf = bf->bf_next;
335 }
336 }
337
338
339 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
340 struct ath_buf *bf, struct list_head *bf_q,
341 struct ath_tx_status *ts, int txok, bool retry)
342 {
343 struct ath_node *an = NULL;
344 struct sk_buff *skb;
345 struct ieee80211_sta *sta;
346 struct ieee80211_hw *hw;
347 struct ieee80211_hdr *hdr;
348 struct ieee80211_tx_info *tx_info;
349 struct ath_atx_tid *tid = NULL;
350 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
351 struct list_head bf_head, bf_pending;
352 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
353 u32 ba[WME_BA_BMP_SIZE >> 5];
354 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
355 bool rc_update = true;
356 struct ieee80211_tx_rate rates[4];
357 struct ath_frame_info *fi;
358 int nframes;
359 u8 tidno;
360
361 skb = bf->bf_mpdu;
362 hdr = (struct ieee80211_hdr *)skb->data;
363
364 tx_info = IEEE80211_SKB_CB(skb);
365 hw = bf->aphy->hw;
366
367 memcpy(rates, tx_info->control.rates, sizeof(rates));
368
369 rcu_read_lock();
370
371 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
372 if (!sta) {
373 rcu_read_unlock();
374
375 INIT_LIST_HEAD(&bf_head);
376 while (bf) {
377 bf_next = bf->bf_next;
378
379 bf->bf_state.bf_type |= BUF_XRETRY;
380 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
381 !bf->bf_stale || bf_next != NULL)
382 list_move_tail(&bf->list, &bf_head);
383
384 ath_tx_rc_status(bf, ts, 1, 1, 0, false);
385 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
386 0, 0);
387
388 bf = bf_next;
389 }
390 return;
391 }
392
393 an = (struct ath_node *)sta->drv_priv;
394 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
395 tid = ATH_AN_2_TID(an, tidno);
396
397 /*
398 * The hardware occasionally sends a tx status for the wrong TID.
399 * In this case, the BA status cannot be considered valid and all
400 * subframes need to be retransmitted
401 */
402 if (tidno != ts->tid)
403 txok = false;
404
405 isaggr = bf_isaggr(bf);
406 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
407
408 if (isaggr && txok) {
409 if (ts->ts_flags & ATH9K_TX_BA) {
410 seq_st = ts->ts_seqnum;
411 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
412 } else {
413 /*
414 * AR5416 can become deaf/mute when BA
415 * issue happens. Chip needs to be reset.
416 * But AP code may have sychronization issues
417 * when perform internal reset in this routine.
418 * Only enable reset in STA mode for now.
419 */
420 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
421 needreset = 1;
422 }
423 }
424
425 INIT_LIST_HEAD(&bf_pending);
426 INIT_LIST_HEAD(&bf_head);
427
428 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
429 while (bf) {
430 txfail = txpending = sendbar = 0;
431 bf_next = bf->bf_next;
432
433 skb = bf->bf_mpdu;
434 tx_info = IEEE80211_SKB_CB(skb);
435 fi = get_frame_info(skb);
436
437 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, fi->seqno))) {
438 /* transmit completion, subframe is
439 * acked by block ack */
440 acked_cnt++;
441 } else if (!isaggr && txok) {
442 /* transmit completion */
443 acked_cnt++;
444 } else {
445 if (!(tid->state & AGGR_CLEANUP) && retry) {
446 if (fi->retries < ATH_MAX_SW_RETRIES) {
447 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
448 txpending = 1;
449 } else {
450 bf->bf_state.bf_type |= BUF_XRETRY;
451 txfail = 1;
452 sendbar = 1;
453 txfail_cnt++;
454 }
455 } else {
456 /*
457 * cleanup in progress, just fail
458 * the un-acked sub-frames
459 */
460 txfail = 1;
461 }
462 }
463
464 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
465 bf_next == NULL) {
466 /*
467 * Make sure the last desc is reclaimed if it
468 * not a holding desc.
469 */
470 if (!bf_last->bf_stale)
471 list_move_tail(&bf->list, &bf_head);
472 else
473 INIT_LIST_HEAD(&bf_head);
474 } else {
475 BUG_ON(list_empty(bf_q));
476 list_move_tail(&bf->list, &bf_head);
477 }
478
479 if (!txpending || (tid->state & AGGR_CLEANUP)) {
480 /*
481 * complete the acked-ones/xretried ones; update
482 * block-ack window
483 */
484 spin_lock_bh(&txq->axq_lock);
485 ath_tx_update_baw(sc, tid, fi->seqno);
486 spin_unlock_bh(&txq->axq_lock);
487
488 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
489 memcpy(tx_info->control.rates, rates, sizeof(rates));
490 ath_tx_rc_status(bf, ts, nframes, nbad, txok, true);
491 rc_update = false;
492 } else {
493 ath_tx_rc_status(bf, ts, nframes, nbad, txok, false);
494 }
495
496 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
497 !txfail, sendbar);
498 } else {
499 /* retry the un-acked ones */
500 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
501 if (bf->bf_next == NULL && bf_last->bf_stale) {
502 struct ath_buf *tbf;
503
504 tbf = ath_clone_txbuf(sc, bf_last);
505 /*
506 * Update tx baw and complete the
507 * frame with failed status if we
508 * run out of tx buf.
509 */
510 if (!tbf) {
511 spin_lock_bh(&txq->axq_lock);
512 ath_tx_update_baw(sc, tid, fi->seqno);
513 spin_unlock_bh(&txq->axq_lock);
514
515 bf->bf_state.bf_type |=
516 BUF_XRETRY;
517 ath_tx_rc_status(bf, ts, nframes,
518 nbad, 0, false);
519 ath_tx_complete_buf(sc, bf, txq,
520 &bf_head,
521 ts, 0, 0);
522 break;
523 }
524
525 ath9k_hw_cleartxdesc(sc->sc_ah,
526 tbf->bf_desc);
527 list_add_tail(&tbf->list, &bf_head);
528 } else {
529 /*
530 * Clear descriptor status words for
531 * software retry
532 */
533 ath9k_hw_cleartxdesc(sc->sc_ah,
534 bf->bf_desc);
535 }
536 }
537
538 /*
539 * Put this buffer to the temporary pending
540 * queue to retain ordering
541 */
542 list_splice_tail_init(&bf_head, &bf_pending);
543 }
544
545 bf = bf_next;
546 }
547
548 /* prepend un-acked frames to the beginning of the pending frame queue */
549 if (!list_empty(&bf_pending)) {
550 spin_lock_bh(&txq->axq_lock);
551 list_splice(&bf_pending, &tid->buf_q);
552 ath_tx_queue_tid(txq, tid);
553 spin_unlock_bh(&txq->axq_lock);
554 }
555
556 if (tid->state & AGGR_CLEANUP) {
557 ath_tx_flush_tid(sc, tid);
558
559 if (tid->baw_head == tid->baw_tail) {
560 tid->state &= ~AGGR_ADDBA_COMPLETE;
561 tid->state &= ~AGGR_CLEANUP;
562 }
563 }
564
565 rcu_read_unlock();
566
567 if (needreset)
568 ath_reset(sc, false);
569 }
570
571 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
572 struct ath_atx_tid *tid)
573 {
574 struct sk_buff *skb;
575 struct ieee80211_tx_info *tx_info;
576 struct ieee80211_tx_rate *rates;
577 u32 max_4ms_framelen, frmlen;
578 u16 aggr_limit, legacy = 0;
579 int i;
580
581 skb = bf->bf_mpdu;
582 tx_info = IEEE80211_SKB_CB(skb);
583 rates = tx_info->control.rates;
584
585 /*
586 * Find the lowest frame length among the rate series that will have a
587 * 4ms transmit duration.
588 * TODO - TXOP limit needs to be considered.
589 */
590 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
591
592 for (i = 0; i < 4; i++) {
593 if (rates[i].count) {
594 int modeidx;
595 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
596 legacy = 1;
597 break;
598 }
599
600 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
601 modeidx = MCS_HT40;
602 else
603 modeidx = MCS_HT20;
604
605 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
606 modeidx++;
607
608 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
609 max_4ms_framelen = min(max_4ms_framelen, frmlen);
610 }
611 }
612
613 /*
614 * limit aggregate size by the minimum rate if rate selected is
615 * not a probe rate, if rate selected is a probe rate then
616 * avoid aggregation of this packet.
617 */
618 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
619 return 0;
620
621 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
622 aggr_limit = min((max_4ms_framelen * 3) / 8,
623 (u32)ATH_AMPDU_LIMIT_MAX);
624 else
625 aggr_limit = min(max_4ms_framelen,
626 (u32)ATH_AMPDU_LIMIT_MAX);
627
628 /*
629 * h/w can accept aggregates upto 16 bit lengths (65535).
630 * The IE, however can hold upto 65536, which shows up here
631 * as zero. Ignore 65536 since we are constrained by hw.
632 */
633 if (tid->an->maxampdu)
634 aggr_limit = min(aggr_limit, tid->an->maxampdu);
635
636 return aggr_limit;
637 }
638
639 /*
640 * Returns the number of delimiters to be added to
641 * meet the minimum required mpdudensity.
642 */
643 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
644 struct ath_buf *bf, u16 frmlen)
645 {
646 struct sk_buff *skb = bf->bf_mpdu;
647 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
648 u32 nsymbits, nsymbols;
649 u16 minlen;
650 u8 flags, rix;
651 int width, streams, half_gi, ndelim, mindelim;
652 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
653
654 /* Select standard number of delimiters based on frame length alone */
655 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
656
657 /*
658 * If encryption enabled, hardware requires some more padding between
659 * subframes.
660 * TODO - this could be improved to be dependent on the rate.
661 * The hardware can keep up at lower rates, but not higher rates
662 */
663 if (fi->keyix != ATH9K_TXKEYIX_INVALID)
664 ndelim += ATH_AGGR_ENCRYPTDELIM;
665
666 /*
667 * Convert desired mpdu density from microeconds to bytes based
668 * on highest rate in rate series (i.e. first rate) to determine
669 * required minimum length for subframe. Take into account
670 * whether high rate is 20 or 40Mhz and half or full GI.
671 *
672 * If there is no mpdu density restriction, no further calculation
673 * is needed.
674 */
675
676 if (tid->an->mpdudensity == 0)
677 return ndelim;
678
679 rix = tx_info->control.rates[0].idx;
680 flags = tx_info->control.rates[0].flags;
681 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
682 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
683
684 if (half_gi)
685 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
686 else
687 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
688
689 if (nsymbols == 0)
690 nsymbols = 1;
691
692 streams = HT_RC_2_STREAMS(rix);
693 nsymbits = bits_per_symbol[rix % 8][width] * streams;
694 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
695
696 if (frmlen < minlen) {
697 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
698 ndelim = max(mindelim, ndelim);
699 }
700
701 return ndelim;
702 }
703
704 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
705 struct ath_txq *txq,
706 struct ath_atx_tid *tid,
707 struct list_head *bf_q,
708 int *aggr_len)
709 {
710 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
711 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
712 int rl = 0, nframes = 0, ndelim, prev_al = 0;
713 u16 aggr_limit = 0, al = 0, bpad = 0,
714 al_delta, h_baw = tid->baw_size / 2;
715 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
716 struct ieee80211_tx_info *tx_info;
717 struct ath_frame_info *fi;
718
719 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
720
721 do {
722 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
723 fi = get_frame_info(bf->bf_mpdu);
724
725 /* do not step over block-ack window */
726 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno)) {
727 status = ATH_AGGR_BAW_CLOSED;
728 break;
729 }
730
731 if (!rl) {
732 aggr_limit = ath_lookup_rate(sc, bf, tid);
733 rl = 1;
734 }
735
736 /* do not exceed aggregation limit */
737 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
738
739 if (nframes &&
740 (aggr_limit < (al + bpad + al_delta + prev_al))) {
741 status = ATH_AGGR_LIMITED;
742 break;
743 }
744
745 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
746 if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
747 !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
748 break;
749
750 /* do not exceed subframe limit */
751 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
752 status = ATH_AGGR_LIMITED;
753 break;
754 }
755 nframes++;
756
757 /* add padding for previous frame to aggregation length */
758 al += bpad + al_delta;
759
760 /*
761 * Get the delimiters needed to meet the MPDU
762 * density for this node.
763 */
764 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen);
765 bpad = PADBYTES(al_delta) + (ndelim << 2);
766
767 bf->bf_next = NULL;
768 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
769
770 /* link buffers of this frame to the aggregate */
771 if (!fi->retries)
772 ath_tx_addto_baw(sc, tid, fi->seqno);
773 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
774 list_move_tail(&bf->list, bf_q);
775 if (bf_prev) {
776 bf_prev->bf_next = bf;
777 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
778 bf->bf_daddr);
779 }
780 bf_prev = bf;
781
782 } while (!list_empty(&tid->buf_q));
783
784 *aggr_len = al;
785
786 return status;
787 #undef PADBYTES
788 }
789
790 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
791 struct ath_atx_tid *tid)
792 {
793 struct ath_buf *bf;
794 enum ATH_AGGR_STATUS status;
795 struct ath_frame_info *fi;
796 struct list_head bf_q;
797 int aggr_len;
798
799 do {
800 if (list_empty(&tid->buf_q))
801 return;
802
803 INIT_LIST_HEAD(&bf_q);
804
805 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
806
807 /*
808 * no frames picked up to be aggregated;
809 * block-ack window is not open.
810 */
811 if (list_empty(&bf_q))
812 break;
813
814 bf = list_first_entry(&bf_q, struct ath_buf, list);
815 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
816
817 /* if only one frame, send as non-aggregate */
818 if (bf == bf->bf_lastbf) {
819 fi = get_frame_info(bf->bf_mpdu);
820
821 bf->bf_state.bf_type &= ~BUF_AGGR;
822 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
823 ath_buf_set_rate(sc, bf, fi->framelen);
824 ath_tx_txqaddbuf(sc, txq, &bf_q);
825 continue;
826 }
827
828 /* setup first desc of aggregate */
829 bf->bf_state.bf_type |= BUF_AGGR;
830 ath_buf_set_rate(sc, bf, aggr_len);
831 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
832
833 /* anchor last desc of aggregate */
834 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
835
836 ath_tx_txqaddbuf(sc, txq, &bf_q);
837 TX_STAT_INC(txq->axq_qnum, a_aggr);
838
839 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
840 status != ATH_AGGR_BAW_CLOSED);
841 }
842
843 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
844 u16 tid, u16 *ssn)
845 {
846 struct ath_atx_tid *txtid;
847 struct ath_node *an;
848
849 an = (struct ath_node *)sta->drv_priv;
850 txtid = ATH_AN_2_TID(an, tid);
851
852 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
853 return -EAGAIN;
854
855 txtid->state |= AGGR_ADDBA_PROGRESS;
856 txtid->paused = true;
857 *ssn = txtid->seq_start = txtid->seq_next;
858
859 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
860 txtid->baw_head = txtid->baw_tail = 0;
861
862 return 0;
863 }
864
865 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
866 {
867 struct ath_node *an = (struct ath_node *)sta->drv_priv;
868 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
869 struct ath_txq *txq = txtid->ac->txq;
870
871 if (txtid->state & AGGR_CLEANUP)
872 return;
873
874 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
875 txtid->state &= ~AGGR_ADDBA_PROGRESS;
876 return;
877 }
878
879 spin_lock_bh(&txq->axq_lock);
880 txtid->paused = true;
881
882 /*
883 * If frames are still being transmitted for this TID, they will be
884 * cleaned up during tx completion. To prevent race conditions, this
885 * TID can only be reused after all in-progress subframes have been
886 * completed.
887 */
888 if (txtid->baw_head != txtid->baw_tail)
889 txtid->state |= AGGR_CLEANUP;
890 else
891 txtid->state &= ~AGGR_ADDBA_COMPLETE;
892 spin_unlock_bh(&txq->axq_lock);
893
894 ath_tx_flush_tid(sc, txtid);
895 }
896
897 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
898 {
899 struct ath_atx_tid *txtid;
900 struct ath_node *an;
901
902 an = (struct ath_node *)sta->drv_priv;
903
904 if (sc->sc_flags & SC_OP_TXAGGR) {
905 txtid = ATH_AN_2_TID(an, tid);
906 txtid->baw_size =
907 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
908 txtid->state |= AGGR_ADDBA_COMPLETE;
909 txtid->state &= ~AGGR_ADDBA_PROGRESS;
910 ath_tx_resume_tid(sc, txtid);
911 }
912 }
913
914 /********************/
915 /* Queue Management */
916 /********************/
917
918 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
919 struct ath_txq *txq)
920 {
921 struct ath_atx_ac *ac, *ac_tmp;
922 struct ath_atx_tid *tid, *tid_tmp;
923
924 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
925 list_del(&ac->list);
926 ac->sched = false;
927 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
928 list_del(&tid->list);
929 tid->sched = false;
930 ath_tid_drain(sc, txq, tid);
931 }
932 }
933 }
934
935 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
936 {
937 struct ath_hw *ah = sc->sc_ah;
938 struct ath_common *common = ath9k_hw_common(ah);
939 struct ath9k_tx_queue_info qi;
940 static const int subtype_txq_to_hwq[] = {
941 [WME_AC_BE] = ATH_TXQ_AC_BE,
942 [WME_AC_BK] = ATH_TXQ_AC_BK,
943 [WME_AC_VI] = ATH_TXQ_AC_VI,
944 [WME_AC_VO] = ATH_TXQ_AC_VO,
945 };
946 int axq_qnum, i;
947
948 memset(&qi, 0, sizeof(qi));
949 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
950 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
951 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
952 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
953 qi.tqi_physCompBuf = 0;
954
955 /*
956 * Enable interrupts only for EOL and DESC conditions.
957 * We mark tx descriptors to receive a DESC interrupt
958 * when a tx queue gets deep; otherwise waiting for the
959 * EOL to reap descriptors. Note that this is done to
960 * reduce interrupt load and this only defers reaping
961 * descriptors, never transmitting frames. Aside from
962 * reducing interrupts this also permits more concurrency.
963 * The only potential downside is if the tx queue backs
964 * up in which case the top half of the kernel may backup
965 * due to a lack of tx descriptors.
966 *
967 * The UAPSD queue is an exception, since we take a desc-
968 * based intr on the EOSP frames.
969 */
970 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
971 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
972 TXQ_FLAG_TXERRINT_ENABLE;
973 } else {
974 if (qtype == ATH9K_TX_QUEUE_UAPSD)
975 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
976 else
977 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
978 TXQ_FLAG_TXDESCINT_ENABLE;
979 }
980 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
981 if (axq_qnum == -1) {
982 /*
983 * NB: don't print a message, this happens
984 * normally on parts with too few tx queues
985 */
986 return NULL;
987 }
988 if (axq_qnum >= ARRAY_SIZE(sc->tx.txq)) {
989 ath_err(common, "qnum %u out of range, max %zu!\n",
990 axq_qnum, ARRAY_SIZE(sc->tx.txq));
991 ath9k_hw_releasetxqueue(ah, axq_qnum);
992 return NULL;
993 }
994 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
995 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
996
997 txq->axq_qnum = axq_qnum;
998 txq->mac80211_qnum = -1;
999 txq->axq_link = NULL;
1000 INIT_LIST_HEAD(&txq->axq_q);
1001 INIT_LIST_HEAD(&txq->axq_acq);
1002 spin_lock_init(&txq->axq_lock);
1003 txq->axq_depth = 0;
1004 txq->axq_ampdu_depth = 0;
1005 txq->axq_tx_inprogress = false;
1006 sc->tx.txqsetup |= 1<<axq_qnum;
1007
1008 txq->txq_headidx = txq->txq_tailidx = 0;
1009 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1010 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1011 INIT_LIST_HEAD(&txq->txq_fifo_pending);
1012 }
1013 return &sc->tx.txq[axq_qnum];
1014 }
1015
1016 int ath_txq_update(struct ath_softc *sc, int qnum,
1017 struct ath9k_tx_queue_info *qinfo)
1018 {
1019 struct ath_hw *ah = sc->sc_ah;
1020 int error = 0;
1021 struct ath9k_tx_queue_info qi;
1022
1023 if (qnum == sc->beacon.beaconq) {
1024 /*
1025 * XXX: for beacon queue, we just save the parameter.
1026 * It will be picked up by ath_beaconq_config when
1027 * it's necessary.
1028 */
1029 sc->beacon.beacon_qi = *qinfo;
1030 return 0;
1031 }
1032
1033 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1034
1035 ath9k_hw_get_txq_props(ah, qnum, &qi);
1036 qi.tqi_aifs = qinfo->tqi_aifs;
1037 qi.tqi_cwmin = qinfo->tqi_cwmin;
1038 qi.tqi_cwmax = qinfo->tqi_cwmax;
1039 qi.tqi_burstTime = qinfo->tqi_burstTime;
1040 qi.tqi_readyTime = qinfo->tqi_readyTime;
1041
1042 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1043 ath_err(ath9k_hw_common(sc->sc_ah),
1044 "Unable to update hardware queue %u!\n", qnum);
1045 error = -EIO;
1046 } else {
1047 ath9k_hw_resettxqueue(ah, qnum);
1048 }
1049
1050 return error;
1051 }
1052
1053 int ath_cabq_update(struct ath_softc *sc)
1054 {
1055 struct ath9k_tx_queue_info qi;
1056 int qnum = sc->beacon.cabq->axq_qnum;
1057
1058 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1059 /*
1060 * Ensure the readytime % is within the bounds.
1061 */
1062 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1063 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1064 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1065 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1066
1067 qi.tqi_readyTime = (sc->beacon_interval *
1068 sc->config.cabqReadytime) / 100;
1069 ath_txq_update(sc, qnum, &qi);
1070
1071 return 0;
1072 }
1073
1074 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1075 {
1076 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1077 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1078 }
1079
1080 /*
1081 * Drain a given TX queue (could be Beacon or Data)
1082 *
1083 * This assumes output has been stopped and
1084 * we do not need to block ath_tx_tasklet.
1085 */
1086 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1087 {
1088 struct ath_buf *bf, *lastbf;
1089 struct list_head bf_head;
1090 struct ath_tx_status ts;
1091
1092 memset(&ts, 0, sizeof(ts));
1093 INIT_LIST_HEAD(&bf_head);
1094
1095 for (;;) {
1096 spin_lock_bh(&txq->axq_lock);
1097
1098 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1099 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
1100 txq->txq_headidx = txq->txq_tailidx = 0;
1101 spin_unlock_bh(&txq->axq_lock);
1102 break;
1103 } else {
1104 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
1105 struct ath_buf, list);
1106 }
1107 } else {
1108 if (list_empty(&txq->axq_q)) {
1109 txq->axq_link = NULL;
1110 spin_unlock_bh(&txq->axq_lock);
1111 break;
1112 }
1113 bf = list_first_entry(&txq->axq_q, struct ath_buf,
1114 list);
1115
1116 if (bf->bf_stale) {
1117 list_del(&bf->list);
1118 spin_unlock_bh(&txq->axq_lock);
1119
1120 ath_tx_return_buffer(sc, bf);
1121 continue;
1122 }
1123 }
1124
1125 lastbf = bf->bf_lastbf;
1126
1127 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1128 list_cut_position(&bf_head,
1129 &txq->txq_fifo[txq->txq_tailidx],
1130 &lastbf->list);
1131 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
1132 } else {
1133 /* remove ath_buf's of the same mpdu from txq */
1134 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1135 }
1136
1137 txq->axq_depth--;
1138 if (bf_is_ampdu_not_probing(bf))
1139 txq->axq_ampdu_depth--;
1140 spin_unlock_bh(&txq->axq_lock);
1141
1142 if (bf_isampdu(bf))
1143 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1144 retry_tx);
1145 else
1146 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1147 }
1148
1149 spin_lock_bh(&txq->axq_lock);
1150 txq->axq_tx_inprogress = false;
1151 spin_unlock_bh(&txq->axq_lock);
1152
1153 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1154 spin_lock_bh(&txq->axq_lock);
1155 while (!list_empty(&txq->txq_fifo_pending)) {
1156 bf = list_first_entry(&txq->txq_fifo_pending,
1157 struct ath_buf, list);
1158 list_cut_position(&bf_head,
1159 &txq->txq_fifo_pending,
1160 &bf->bf_lastbf->list);
1161 spin_unlock_bh(&txq->axq_lock);
1162
1163 if (bf_isampdu(bf))
1164 ath_tx_complete_aggr(sc, txq, bf, &bf_head,
1165 &ts, 0, retry_tx);
1166 else
1167 ath_tx_complete_buf(sc, bf, txq, &bf_head,
1168 &ts, 0, 0);
1169 spin_lock_bh(&txq->axq_lock);
1170 }
1171 spin_unlock_bh(&txq->axq_lock);
1172 }
1173
1174 /* flush any pending frames if aggregation is enabled */
1175 if (sc->sc_flags & SC_OP_TXAGGR) {
1176 if (!retry_tx) {
1177 spin_lock_bh(&txq->axq_lock);
1178 ath_txq_drain_pending_buffers(sc, txq);
1179 spin_unlock_bh(&txq->axq_lock);
1180 }
1181 }
1182 }
1183
1184 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1185 {
1186 struct ath_hw *ah = sc->sc_ah;
1187 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1188 struct ath_txq *txq;
1189 int i, npend = 0;
1190
1191 if (sc->sc_flags & SC_OP_INVALID)
1192 return true;
1193
1194 /* Stop beacon queue */
1195 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1196
1197 /* Stop data queues */
1198 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1199 if (ATH_TXQ_SETUP(sc, i)) {
1200 txq = &sc->tx.txq[i];
1201 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1202 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1203 }
1204 }
1205
1206 if (npend)
1207 ath_err(common, "Failed to stop TX DMA!\n");
1208
1209 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1210 if (ATH_TXQ_SETUP(sc, i))
1211 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1212 }
1213
1214 return !npend;
1215 }
1216
1217 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1218 {
1219 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1220 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1221 }
1222
1223 /* For each axq_acq entry, for each tid, try to schedule packets
1224 * for transmit until ampdu_depth has reached min Q depth.
1225 */
1226 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1227 {
1228 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1229 struct ath_atx_tid *tid, *last_tid;
1230
1231 if (list_empty(&txq->axq_acq) ||
1232 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1233 return;
1234
1235 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1236 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1237
1238 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1239 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1240 list_del(&ac->list);
1241 ac->sched = false;
1242
1243 while (!list_empty(&ac->tid_q)) {
1244 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1245 list);
1246 list_del(&tid->list);
1247 tid->sched = false;
1248
1249 if (tid->paused)
1250 continue;
1251
1252 ath_tx_sched_aggr(sc, txq, tid);
1253
1254 /*
1255 * add tid to round-robin queue if more frames
1256 * are pending for the tid
1257 */
1258 if (!list_empty(&tid->buf_q))
1259 ath_tx_queue_tid(txq, tid);
1260
1261 if (tid == last_tid ||
1262 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1263 break;
1264 }
1265
1266 if (!list_empty(&ac->tid_q)) {
1267 if (!ac->sched) {
1268 ac->sched = true;
1269 list_add_tail(&ac->list, &txq->axq_acq);
1270 }
1271 }
1272
1273 if (ac == last_ac ||
1274 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1275 return;
1276 }
1277 }
1278
1279 /***********/
1280 /* TX, DMA */
1281 /***********/
1282
1283 /*
1284 * Insert a chain of ath_buf (descriptors) on a txq and
1285 * assume the descriptors are already chained together by caller.
1286 */
1287 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1288 struct list_head *head)
1289 {
1290 struct ath_hw *ah = sc->sc_ah;
1291 struct ath_common *common = ath9k_hw_common(ah);
1292 struct ath_buf *bf;
1293
1294 /*
1295 * Insert the frame on the outbound list and
1296 * pass it on to the hardware.
1297 */
1298
1299 if (list_empty(head))
1300 return;
1301
1302 bf = list_first_entry(head, struct ath_buf, list);
1303
1304 ath_dbg(common, ATH_DBG_QUEUE,
1305 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1306
1307 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1308 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
1309 list_splice_tail_init(head, &txq->txq_fifo_pending);
1310 return;
1311 }
1312 if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
1313 ath_dbg(common, ATH_DBG_XMIT,
1314 "Initializing tx fifo %d which is non-empty\n",
1315 txq->txq_headidx);
1316 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
1317 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
1318 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1319 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1320 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1321 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1322 } else {
1323 list_splice_tail_init(head, &txq->axq_q);
1324
1325 if (txq->axq_link == NULL) {
1326 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1327 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1328 txq->axq_qnum, ito64(bf->bf_daddr),
1329 bf->bf_desc);
1330 } else {
1331 *txq->axq_link = bf->bf_daddr;
1332 ath_dbg(common, ATH_DBG_XMIT,
1333 "link[%u] (%p)=%llx (%p)\n",
1334 txq->axq_qnum, txq->axq_link,
1335 ito64(bf->bf_daddr), bf->bf_desc);
1336 }
1337 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
1338 &txq->axq_link);
1339 ath9k_hw_txstart(ah, txq->axq_qnum);
1340 }
1341 txq->axq_depth++;
1342 if (bf_is_ampdu_not_probing(bf))
1343 txq->axq_ampdu_depth++;
1344 }
1345
1346 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1347 struct ath_buf *bf, struct ath_tx_control *txctl)
1348 {
1349 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1350 struct list_head bf_head;
1351
1352 bf->bf_state.bf_type |= BUF_AMPDU;
1353
1354 /*
1355 * Do not queue to h/w when any of the following conditions is true:
1356 * - there are pending frames in software queue
1357 * - the TID is currently paused for ADDBA/BAR request
1358 * - seqno is not within block-ack window
1359 * - h/w queue depth exceeds low water mark
1360 */
1361 if (!list_empty(&tid->buf_q) || tid->paused ||
1362 !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) ||
1363 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1364 /*
1365 * Add this frame to software queue for scheduling later
1366 * for aggregation.
1367 */
1368 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1369 list_add_tail(&bf->list, &tid->buf_q);
1370 ath_tx_queue_tid(txctl->txq, tid);
1371 return;
1372 }
1373
1374 INIT_LIST_HEAD(&bf_head);
1375 list_add(&bf->list, &bf_head);
1376
1377 /* Add sub-frame to BAW */
1378 if (!fi->retries)
1379 ath_tx_addto_baw(sc, tid, fi->seqno);
1380
1381 /* Queue to h/w without aggregation */
1382 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1383 bf->bf_lastbf = bf;
1384 ath_buf_set_rate(sc, bf, fi->framelen);
1385 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
1386 }
1387
1388 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1389 struct ath_atx_tid *tid,
1390 struct list_head *bf_head)
1391 {
1392 struct ath_frame_info *fi;
1393 struct ath_buf *bf;
1394
1395 bf = list_first_entry(bf_head, struct ath_buf, list);
1396 bf->bf_state.bf_type &= ~BUF_AMPDU;
1397
1398 /* update starting sequence number for subsequent ADDBA request */
1399 if (tid)
1400 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1401
1402 bf->bf_lastbf = bf;
1403 fi = get_frame_info(bf->bf_mpdu);
1404 ath_buf_set_rate(sc, bf, fi->framelen);
1405 ath_tx_txqaddbuf(sc, txq, bf_head);
1406 TX_STAT_INC(txq->axq_qnum, queued);
1407 }
1408
1409 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1410 {
1411 struct ieee80211_hdr *hdr;
1412 enum ath9k_pkt_type htype;
1413 __le16 fc;
1414
1415 hdr = (struct ieee80211_hdr *)skb->data;
1416 fc = hdr->frame_control;
1417
1418 if (ieee80211_is_beacon(fc))
1419 htype = ATH9K_PKT_TYPE_BEACON;
1420 else if (ieee80211_is_probe_resp(fc))
1421 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1422 else if (ieee80211_is_atim(fc))
1423 htype = ATH9K_PKT_TYPE_ATIM;
1424 else if (ieee80211_is_pspoll(fc))
1425 htype = ATH9K_PKT_TYPE_PSPOLL;
1426 else
1427 htype = ATH9K_PKT_TYPE_NORMAL;
1428
1429 return htype;
1430 }
1431
1432 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1433 int framelen)
1434 {
1435 struct ath_wiphy *aphy = hw->priv;
1436 struct ath_softc *sc = aphy->sc;
1437 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1438 struct ieee80211_sta *sta = tx_info->control.sta;
1439 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1440 struct ieee80211_hdr *hdr;
1441 struct ath_frame_info *fi = get_frame_info(skb);
1442 struct ath_node *an;
1443 struct ath_atx_tid *tid;
1444 enum ath9k_key_type keytype;
1445 u16 seqno = 0;
1446 u8 tidno;
1447
1448 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1449
1450 hdr = (struct ieee80211_hdr *)skb->data;
1451 if (sta && ieee80211_is_data_qos(hdr->frame_control) &&
1452 conf_is_ht(&hw->conf) && (sc->sc_flags & SC_OP_TXAGGR)) {
1453
1454 an = (struct ath_node *) sta->drv_priv;
1455 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
1456
1457 /*
1458 * Override seqno set by upper layer with the one
1459 * in tx aggregation state.
1460 */
1461 tid = ATH_AN_2_TID(an, tidno);
1462 seqno = tid->seq_next;
1463 hdr->seq_ctrl = cpu_to_le16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
1464 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1465 }
1466
1467 memset(fi, 0, sizeof(*fi));
1468 if (hw_key)
1469 fi->keyix = hw_key->hw_key_idx;
1470 else
1471 fi->keyix = ATH9K_TXKEYIX_INVALID;
1472 fi->keytype = keytype;
1473 fi->framelen = framelen;
1474 fi->seqno = seqno;
1475 }
1476
1477 static int setup_tx_flags(struct sk_buff *skb)
1478 {
1479 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1480 int flags = 0;
1481
1482 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1483 flags |= ATH9K_TXDESC_INTREQ;
1484
1485 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1486 flags |= ATH9K_TXDESC_NOACK;
1487
1488 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1489 flags |= ATH9K_TXDESC_LDPC;
1490
1491 return flags;
1492 }
1493
1494 /*
1495 * rix - rate index
1496 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1497 * width - 0 for 20 MHz, 1 for 40 MHz
1498 * half_gi - to use 4us v/s 3.6 us for symbol time
1499 */
1500 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1501 int width, int half_gi, bool shortPreamble)
1502 {
1503 u32 nbits, nsymbits, duration, nsymbols;
1504 int streams;
1505
1506 /* find number of symbols: PLCP + data */
1507 streams = HT_RC_2_STREAMS(rix);
1508 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1509 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1510 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1511
1512 if (!half_gi)
1513 duration = SYMBOL_TIME(nsymbols);
1514 else
1515 duration = SYMBOL_TIME_HALFGI(nsymbols);
1516
1517 /* addup duration for legacy/ht training and signal fields */
1518 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1519
1520 return duration;
1521 }
1522
1523 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1524 {
1525 struct ath_hw *ah = sc->sc_ah;
1526 struct ath9k_channel *curchan = ah->curchan;
1527 if ((sc->sc_flags & SC_OP_ENABLE_APM) &&
1528 (curchan->channelFlags & CHANNEL_5GHZ) &&
1529 (chainmask == 0x7) && (rate < 0x90))
1530 return 0x3;
1531 else
1532 return chainmask;
1533 }
1534
1535 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
1536 {
1537 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1538 struct ath9k_11n_rate_series series[4];
1539 struct sk_buff *skb;
1540 struct ieee80211_tx_info *tx_info;
1541 struct ieee80211_tx_rate *rates;
1542 const struct ieee80211_rate *rate;
1543 struct ieee80211_hdr *hdr;
1544 int i, flags = 0;
1545 u8 rix = 0, ctsrate = 0;
1546 bool is_pspoll;
1547
1548 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1549
1550 skb = bf->bf_mpdu;
1551 tx_info = IEEE80211_SKB_CB(skb);
1552 rates = tx_info->control.rates;
1553 hdr = (struct ieee80211_hdr *)skb->data;
1554 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1555
1556 /*
1557 * We check if Short Preamble is needed for the CTS rate by
1558 * checking the BSS's global flag.
1559 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1560 */
1561 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1562 ctsrate = rate->hw_value;
1563 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1564 ctsrate |= rate->hw_value_short;
1565
1566 for (i = 0; i < 4; i++) {
1567 bool is_40, is_sgi, is_sp;
1568 int phy;
1569
1570 if (!rates[i].count || (rates[i].idx < 0))
1571 continue;
1572
1573 rix = rates[i].idx;
1574 series[i].Tries = rates[i].count;
1575
1576 if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) ||
1577 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
1578 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1579 flags |= ATH9K_TXDESC_RTSENA;
1580 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1581 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1582 flags |= ATH9K_TXDESC_CTSENA;
1583 }
1584
1585 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1586 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1587 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1588 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1589
1590 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1591 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1592 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1593
1594 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1595 /* MCS rates */
1596 series[i].Rate = rix | 0x80;
1597 series[i].ChSel = ath_txchainmask_reduction(sc,
1598 common->tx_chainmask, series[i].Rate);
1599 series[i].PktDuration = ath_pkt_duration(sc, rix, len,
1600 is_40, is_sgi, is_sp);
1601 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1602 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1603 continue;
1604 }
1605
1606 /* legacy rates */
1607 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1608 !(rate->flags & IEEE80211_RATE_ERP_G))
1609 phy = WLAN_RC_PHY_CCK;
1610 else
1611 phy = WLAN_RC_PHY_OFDM;
1612
1613 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1614 series[i].Rate = rate->hw_value;
1615 if (rate->hw_value_short) {
1616 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1617 series[i].Rate |= rate->hw_value_short;
1618 } else {
1619 is_sp = false;
1620 }
1621
1622 if (bf->bf_state.bfs_paprd)
1623 series[i].ChSel = common->tx_chainmask;
1624 else
1625 series[i].ChSel = ath_txchainmask_reduction(sc,
1626 common->tx_chainmask, series[i].Rate);
1627
1628 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1629 phy, rate->bitrate * 100, len, rix, is_sp);
1630 }
1631
1632 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1633 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1634 flags &= ~ATH9K_TXDESC_RTSENA;
1635
1636 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1637 if (flags & ATH9K_TXDESC_RTSENA)
1638 flags &= ~ATH9K_TXDESC_CTSENA;
1639
1640 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1641 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1642 bf->bf_lastbf->bf_desc,
1643 !is_pspoll, ctsrate,
1644 0, series, 4, flags);
1645
1646 if (sc->config.ath_aggr_prot && flags)
1647 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1648 }
1649
1650 static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
1651 struct ath_txq *txq,
1652 struct sk_buff *skb)
1653 {
1654 struct ath_wiphy *aphy = hw->priv;
1655 struct ath_softc *sc = aphy->sc;
1656 struct ath_hw *ah = sc->sc_ah;
1657 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1658 struct ath_frame_info *fi = get_frame_info(skb);
1659 struct ath_buf *bf;
1660 struct ath_desc *ds;
1661 int frm_type;
1662
1663 bf = ath_tx_get_buffer(sc);
1664 if (!bf) {
1665 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1666 return NULL;
1667 }
1668
1669 ATH_TXBUF_RESET(bf);
1670
1671 bf->aphy = aphy;
1672 bf->bf_flags = setup_tx_flags(skb);
1673 bf->bf_mpdu = skb;
1674
1675 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1676 skb->len, DMA_TO_DEVICE);
1677 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1678 bf->bf_mpdu = NULL;
1679 bf->bf_buf_addr = 0;
1680 ath_err(ath9k_hw_common(sc->sc_ah),
1681 "dma_mapping_error() on TX\n");
1682 ath_tx_return_buffer(sc, bf);
1683 return NULL;
1684 }
1685
1686 frm_type = get_hw_packet_type(skb);
1687
1688 ds = bf->bf_desc;
1689 ath9k_hw_set_desc_link(ah, ds, 0);
1690
1691 ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
1692 fi->keyix, fi->keytype, bf->bf_flags);
1693
1694 ath9k_hw_filltxdesc(ah, ds,
1695 skb->len, /* segment length */
1696 true, /* first segment */
1697 true, /* last segment */
1698 ds, /* first descriptor */
1699 bf->bf_buf_addr,
1700 txq->axq_qnum);
1701
1702
1703 return bf;
1704 }
1705
1706 /* FIXME: tx power */
1707 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1708 struct ath_tx_control *txctl)
1709 {
1710 struct sk_buff *skb = bf->bf_mpdu;
1711 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1712 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1713 struct list_head bf_head;
1714 struct ath_atx_tid *tid = NULL;
1715 u8 tidno;
1716
1717 spin_lock_bh(&txctl->txq->axq_lock);
1718
1719 if (ieee80211_is_data_qos(hdr->frame_control) && txctl->an) {
1720 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1721 IEEE80211_QOS_CTL_TID_MASK;
1722 tid = ATH_AN_2_TID(txctl->an, tidno);
1723
1724 WARN_ON(tid->ac->txq != txctl->txq);
1725 }
1726
1727 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1728 /*
1729 * Try aggregation if it's a unicast data frame
1730 * and the destination is HT capable.
1731 */
1732 ath_tx_send_ampdu(sc, tid, bf, txctl);
1733 } else {
1734 INIT_LIST_HEAD(&bf_head);
1735 list_add_tail(&bf->list, &bf_head);
1736
1737 bf->bf_state.bfs_ftype = txctl->frame_type;
1738 bf->bf_state.bfs_paprd = txctl->paprd;
1739
1740 if (bf->bf_state.bfs_paprd)
1741 ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
1742 bf->bf_state.bfs_paprd);
1743
1744 ath_tx_send_normal(sc, txctl->txq, tid, &bf_head);
1745 }
1746
1747 spin_unlock_bh(&txctl->txq->axq_lock);
1748 }
1749
1750 /* Upon failure caller should free skb */
1751 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1752 struct ath_tx_control *txctl)
1753 {
1754 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1755 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1756 struct ieee80211_sta *sta = info->control.sta;
1757 struct ath_wiphy *aphy = hw->priv;
1758 struct ath_softc *sc = aphy->sc;
1759 struct ath_txq *txq = txctl->txq;
1760 struct ath_buf *bf;
1761 int padpos, padsize;
1762 int frmlen = skb->len + FCS_LEN;
1763 int q;
1764
1765 /* NOTE: sta can be NULL according to net/mac80211.h */
1766 if (sta)
1767 txctl->an = (struct ath_node *)sta->drv_priv;
1768
1769 if (info->control.hw_key)
1770 frmlen += info->control.hw_key->icv_len;
1771
1772 /*
1773 * As a temporary workaround, assign seq# here; this will likely need
1774 * to be cleaned up to work better with Beacon transmission and virtual
1775 * BSSes.
1776 */
1777 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1778 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1779 sc->tx.seq_no += 0x10;
1780 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1781 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1782 }
1783
1784 /* Add the padding after the header if this is not already done */
1785 padpos = ath9k_cmn_padpos(hdr->frame_control);
1786 padsize = padpos & 3;
1787 if (padsize && skb->len > padpos) {
1788 if (skb_headroom(skb) < padsize)
1789 return -ENOMEM;
1790
1791 skb_push(skb, padsize);
1792 memmove(skb->data, skb->data + padsize, padpos);
1793 }
1794
1795 setup_frame_info(hw, skb, frmlen);
1796
1797 /*
1798 * At this point, the vif, hw_key and sta pointers in the tx control
1799 * info are no longer valid (overwritten by the ath_frame_info data.
1800 */
1801
1802 bf = ath_tx_setup_buffer(hw, txctl->txq, skb);
1803 if (unlikely(!bf))
1804 return -ENOMEM;
1805
1806 q = skb_get_queue_mapping(skb);
1807 spin_lock_bh(&txq->axq_lock);
1808 if (txq == sc->tx.txq_map[q] &&
1809 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1810 ath_mac80211_stop_queue(sc, q);
1811 txq->stopped = 1;
1812 }
1813 spin_unlock_bh(&txq->axq_lock);
1814
1815 ath_tx_start_dma(sc, bf, txctl);
1816
1817 return 0;
1818 }
1819
1820 /*****************/
1821 /* TX Completion */
1822 /*****************/
1823
1824 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1825 struct ath_wiphy *aphy, int tx_flags, int ftype,
1826 struct ath_txq *txq)
1827 {
1828 struct ieee80211_hw *hw = sc->hw;
1829 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1830 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1831 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1832 int q, padpos, padsize;
1833
1834 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1835
1836 if (aphy)
1837 hw = aphy->hw;
1838
1839 if (tx_flags & ATH_TX_BAR)
1840 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1841
1842 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1843 /* Frame was ACKed */
1844 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1845 }
1846
1847 padpos = ath9k_cmn_padpos(hdr->frame_control);
1848 padsize = padpos & 3;
1849 if (padsize && skb->len>padpos+padsize) {
1850 /*
1851 * Remove MAC header padding before giving the frame back to
1852 * mac80211.
1853 */
1854 memmove(skb->data + padsize, skb->data, padpos);
1855 skb_pull(skb, padsize);
1856 }
1857
1858 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1859 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1860 ath_dbg(common, ATH_DBG_PS,
1861 "Going back to sleep after having received TX status (0x%lx)\n",
1862 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1863 PS_WAIT_FOR_CAB |
1864 PS_WAIT_FOR_PSPOLL_DATA |
1865 PS_WAIT_FOR_TX_ACK));
1866 }
1867
1868 if (unlikely(ftype))
1869 ath9k_tx_status(hw, skb, ftype);
1870 else {
1871 q = skb_get_queue_mapping(skb);
1872 if (txq == sc->tx.txq_map[q]) {
1873 spin_lock_bh(&txq->axq_lock);
1874 if (WARN_ON(--txq->pending_frames < 0))
1875 txq->pending_frames = 0;
1876 spin_unlock_bh(&txq->axq_lock);
1877 }
1878
1879 ieee80211_tx_status(hw, skb);
1880 }
1881 }
1882
1883 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1884 struct ath_txq *txq, struct list_head *bf_q,
1885 struct ath_tx_status *ts, int txok, int sendbar)
1886 {
1887 struct sk_buff *skb = bf->bf_mpdu;
1888 unsigned long flags;
1889 int tx_flags = 0;
1890
1891 if (sendbar)
1892 tx_flags = ATH_TX_BAR;
1893
1894 if (!txok) {
1895 tx_flags |= ATH_TX_ERROR;
1896
1897 if (bf_isxretried(bf))
1898 tx_flags |= ATH_TX_XRETRY;
1899 }
1900
1901 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
1902 bf->bf_buf_addr = 0;
1903
1904 if (bf->bf_state.bfs_paprd) {
1905 if (!sc->paprd_pending)
1906 dev_kfree_skb_any(skb);
1907 else
1908 complete(&sc->paprd_complete);
1909 } else {
1910 ath_debug_stat_tx(sc, bf, ts);
1911 ath_tx_complete(sc, skb, bf->aphy, tx_flags,
1912 bf->bf_state.bfs_ftype, txq);
1913 }
1914 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
1915 * accidentally reference it later.
1916 */
1917 bf->bf_mpdu = NULL;
1918
1919 /*
1920 * Return the list of ath_buf of this mpdu to free queue
1921 */
1922 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1923 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1924 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1925 }
1926
1927 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
1928 int nframes, int nbad, int txok, bool update_rc)
1929 {
1930 struct sk_buff *skb = bf->bf_mpdu;
1931 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1932 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1933 struct ieee80211_hw *hw = bf->aphy->hw;
1934 struct ath_softc *sc = bf->aphy->sc;
1935 struct ath_hw *ah = sc->sc_ah;
1936 u8 i, tx_rateindex;
1937
1938 if (txok)
1939 tx_info->status.ack_signal = ts->ts_rssi;
1940
1941 tx_rateindex = ts->ts_rateindex;
1942 WARN_ON(tx_rateindex >= hw->max_rates);
1943
1944 if (ts->ts_status & ATH9K_TXERR_FILT)
1945 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1946 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
1947 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
1948
1949 BUG_ON(nbad > nframes);
1950
1951 tx_info->status.ampdu_len = nframes;
1952 tx_info->status.ampdu_ack_len = nframes - nbad;
1953 }
1954
1955 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
1956 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1957 /*
1958 * If an underrun error is seen assume it as an excessive
1959 * retry only if max frame trigger level has been reached
1960 * (2 KB for single stream, and 4 KB for dual stream).
1961 * Adjust the long retry as if the frame was tried
1962 * hw->max_rate_tries times to affect how rate control updates
1963 * PER for the failed rate.
1964 * In case of congestion on the bus penalizing this type of
1965 * underruns should help hardware actually transmit new frames
1966 * successfully by eventually preferring slower rates.
1967 * This itself should also alleviate congestion on the bus.
1968 */
1969 if (ieee80211_is_data(hdr->frame_control) &&
1970 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
1971 ATH9K_TX_DELIM_UNDERRUN)) &&
1972 ah->tx_trig_level >= sc->sc_ah->caps.tx_triglevel_max)
1973 tx_info->status.rates[tx_rateindex].count =
1974 hw->max_rate_tries;
1975 }
1976
1977 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
1978 tx_info->status.rates[i].count = 0;
1979 tx_info->status.rates[i].idx = -1;
1980 }
1981
1982 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
1983 }
1984
1985 /* Has no locking. Must hold spin_lock_bh(&txq->axq_lock)
1986 * before calling this.
1987 */
1988 static void __ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1989 {
1990 if (txq->mac80211_qnum >= 0 &&
1991 txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1992 if (ath_mac80211_start_queue(sc, txq->mac80211_qnum))
1993 txq->stopped = 0;
1994 }
1995 }
1996
1997 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1998 {
1999 struct ath_hw *ah = sc->sc_ah;
2000 struct ath_common *common = ath9k_hw_common(ah);
2001 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2002 struct list_head bf_head;
2003 struct ath_desc *ds;
2004 struct ath_tx_status ts;
2005 int txok;
2006 int status;
2007 int qnum;
2008
2009 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2010 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2011 txq->axq_link);
2012
2013 for (;;) {
2014 spin_lock_bh(&txq->axq_lock);
2015 if (list_empty(&txq->axq_q)) {
2016 txq->axq_link = NULL;
2017 if (sc->sc_flags & SC_OP_TXAGGR)
2018 ath_txq_schedule(sc, txq);
2019 spin_unlock_bh(&txq->axq_lock);
2020 break;
2021 }
2022 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2023
2024 /*
2025 * There is a race condition that a BH gets scheduled
2026 * after sw writes TxE and before hw re-load the last
2027 * descriptor to get the newly chained one.
2028 * Software must keep the last DONE descriptor as a
2029 * holding descriptor - software does so by marking
2030 * it with the STALE flag.
2031 */
2032 bf_held = NULL;
2033 if (bf->bf_stale) {
2034 bf_held = bf;
2035 if (list_is_last(&bf_held->list, &txq->axq_q)) {
2036 spin_unlock_bh(&txq->axq_lock);
2037 break;
2038 } else {
2039 bf = list_entry(bf_held->list.next,
2040 struct ath_buf, list);
2041 }
2042 }
2043
2044 lastbf = bf->bf_lastbf;
2045 ds = lastbf->bf_desc;
2046
2047 memset(&ts, 0, sizeof(ts));
2048 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2049 if (status == -EINPROGRESS) {
2050 spin_unlock_bh(&txq->axq_lock);
2051 break;
2052 }
2053 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2054
2055 /*
2056 * Remove ath_buf's of the same transmit unit from txq,
2057 * however leave the last descriptor back as the holding
2058 * descriptor for hw.
2059 */
2060 lastbf->bf_stale = true;
2061 INIT_LIST_HEAD(&bf_head);
2062 if (!list_is_singular(&lastbf->list))
2063 list_cut_position(&bf_head,
2064 &txq->axq_q, lastbf->list.prev);
2065
2066 txq->axq_depth--;
2067 txok = !(ts.ts_status & ATH9K_TXERR_MASK);
2068 txq->axq_tx_inprogress = false;
2069 if (bf_held)
2070 list_del(&bf_held->list);
2071
2072 if (bf_is_ampdu_not_probing(bf))
2073 txq->axq_ampdu_depth--;
2074 spin_unlock_bh(&txq->axq_lock);
2075
2076 if (bf_held)
2077 ath_tx_return_buffer(sc, bf_held);
2078
2079 if (!bf_isampdu(bf)) {
2080 /*
2081 * This frame is sent out as a single frame.
2082 * Use hardware retry status for this frame.
2083 */
2084 if (ts.ts_status & ATH9K_TXERR_XRETRY)
2085 bf->bf_state.bf_type |= BUF_XRETRY;
2086 ath_tx_rc_status(bf, &ts, 1, txok ? 0 : 1, txok, true);
2087 }
2088
2089 qnum = skb_get_queue_mapping(bf->bf_mpdu);
2090
2091 if (bf_isampdu(bf))
2092 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok,
2093 true);
2094 else
2095 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0);
2096
2097 spin_lock_bh(&txq->axq_lock);
2098 __ath_wake_mac80211_queue(sc, txq);
2099
2100 if (sc->sc_flags & SC_OP_TXAGGR)
2101 ath_txq_schedule(sc, txq);
2102 spin_unlock_bh(&txq->axq_lock);
2103 }
2104 }
2105
2106 static void ath_tx_complete_poll_work(struct work_struct *work)
2107 {
2108 struct ath_softc *sc = container_of(work, struct ath_softc,
2109 tx_complete_work.work);
2110 struct ath_txq *txq;
2111 int i;
2112 bool needreset = false;
2113 #ifdef CONFIG_ATH9K_DEBUGFS
2114 sc->tx_complete_poll_work_seen++;
2115 #endif
2116
2117 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2118 if (ATH_TXQ_SETUP(sc, i)) {
2119 txq = &sc->tx.txq[i];
2120 spin_lock_bh(&txq->axq_lock);
2121 if (txq->axq_depth) {
2122 if (txq->axq_tx_inprogress) {
2123 needreset = true;
2124 spin_unlock_bh(&txq->axq_lock);
2125 break;
2126 } else {
2127 txq->axq_tx_inprogress = true;
2128 }
2129 } else {
2130 /* If the queue has pending buffers, then it
2131 * should be doing tx work (and have axq_depth).
2132 * Shouldn't get to this state I think..but
2133 * we do.
2134 */
2135 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) &&
2136 (txq->pending_frames > 0 ||
2137 !list_empty(&txq->axq_acq) ||
2138 txq->stopped)) {
2139 ath_err(ath9k_hw_common(sc->sc_ah),
2140 "txq: %p axq_qnum: %u,"
2141 " mac80211_qnum: %i"
2142 " axq_link: %p"
2143 " pending frames: %i"
2144 " axq_acq empty: %i"
2145 " stopped: %i"
2146 " axq_depth: 0 Attempting to"
2147 " restart tx logic.\n",
2148 txq, txq->axq_qnum,
2149 txq->mac80211_qnum,
2150 txq->axq_link,
2151 txq->pending_frames,
2152 list_empty(&txq->axq_acq),
2153 txq->stopped);
2154 __ath_wake_mac80211_queue(sc, txq);
2155 ath_txq_schedule(sc, txq);
2156 }
2157 }
2158 spin_unlock_bh(&txq->axq_lock);
2159 }
2160
2161 if (needreset) {
2162 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2163 "tx hung, resetting the chip\n");
2164 ath9k_ps_wakeup(sc);
2165 ath_reset(sc, true);
2166 ath9k_ps_restore(sc);
2167 }
2168
2169 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2170 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2171 }
2172
2173
2174
2175 void ath_tx_tasklet(struct ath_softc *sc)
2176 {
2177 int i;
2178 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2179
2180 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2181
2182 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2183 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2184 ath_tx_processq(sc, &sc->tx.txq[i]);
2185 }
2186 }
2187
2188 void ath_tx_edma_tasklet(struct ath_softc *sc)
2189 {
2190 struct ath_tx_status txs;
2191 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2192 struct ath_hw *ah = sc->sc_ah;
2193 struct ath_txq *txq;
2194 struct ath_buf *bf, *lastbf;
2195 struct list_head bf_head;
2196 int status;
2197 int txok;
2198 int qnum;
2199
2200 for (;;) {
2201 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs);
2202 if (status == -EINPROGRESS)
2203 break;
2204 if (status == -EIO) {
2205 ath_dbg(common, ATH_DBG_XMIT,
2206 "Error processing tx status\n");
2207 break;
2208 }
2209
2210 /* Skip beacon completions */
2211 if (txs.qid == sc->beacon.beaconq)
2212 continue;
2213
2214 txq = &sc->tx.txq[txs.qid];
2215
2216 spin_lock_bh(&txq->axq_lock);
2217 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2218 spin_unlock_bh(&txq->axq_lock);
2219 return;
2220 }
2221
2222 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2223 struct ath_buf, list);
2224 lastbf = bf->bf_lastbf;
2225
2226 INIT_LIST_HEAD(&bf_head);
2227 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2228 &lastbf->list);
2229 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2230 txq->axq_depth--;
2231 txq->axq_tx_inprogress = false;
2232 if (bf_is_ampdu_not_probing(bf))
2233 txq->axq_ampdu_depth--;
2234 spin_unlock_bh(&txq->axq_lock);
2235
2236 txok = !(txs.ts_status & ATH9K_TXERR_MASK);
2237
2238 if (!bf_isampdu(bf)) {
2239 if (txs.ts_status & ATH9K_TXERR_XRETRY)
2240 bf->bf_state.bf_type |= BUF_XRETRY;
2241 ath_tx_rc_status(bf, &txs, 1, txok ? 0 : 1, txok, true);
2242 }
2243
2244 qnum = skb_get_queue_mapping(bf->bf_mpdu);
2245
2246 if (bf_isampdu(bf))
2247 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs,
2248 txok, true);
2249 else
2250 ath_tx_complete_buf(sc, bf, txq, &bf_head,
2251 &txs, txok, 0);
2252
2253 spin_lock_bh(&txq->axq_lock);
2254 __ath_wake_mac80211_queue(sc, txq);
2255
2256 if (!list_empty(&txq->txq_fifo_pending)) {
2257 INIT_LIST_HEAD(&bf_head);
2258 bf = list_first_entry(&txq->txq_fifo_pending,
2259 struct ath_buf, list);
2260 list_cut_position(&bf_head, &txq->txq_fifo_pending,
2261 &bf->bf_lastbf->list);
2262 ath_tx_txqaddbuf(sc, txq, &bf_head);
2263 } else if (sc->sc_flags & SC_OP_TXAGGR)
2264 ath_txq_schedule(sc, txq);
2265 spin_unlock_bh(&txq->axq_lock);
2266 }
2267 }
2268
2269 /*****************/
2270 /* Init, Cleanup */
2271 /*****************/
2272
2273 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2274 {
2275 struct ath_descdma *dd = &sc->txsdma;
2276 u8 txs_len = sc->sc_ah->caps.txs_len;
2277
2278 dd->dd_desc_len = size * txs_len;
2279 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2280 &dd->dd_desc_paddr, GFP_KERNEL);
2281 if (!dd->dd_desc)
2282 return -ENOMEM;
2283
2284 return 0;
2285 }
2286
2287 static int ath_tx_edma_init(struct ath_softc *sc)
2288 {
2289 int err;
2290
2291 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2292 if (!err)
2293 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2294 sc->txsdma.dd_desc_paddr,
2295 ATH_TXSTATUS_RING_SIZE);
2296
2297 return err;
2298 }
2299
2300 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2301 {
2302 struct ath_descdma *dd = &sc->txsdma;
2303
2304 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2305 dd->dd_desc_paddr);
2306 }
2307
2308 int ath_tx_init(struct ath_softc *sc, int nbufs)
2309 {
2310 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2311 int error = 0;
2312
2313 spin_lock_init(&sc->tx.txbuflock);
2314
2315 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2316 "tx", nbufs, 1, 1);
2317 if (error != 0) {
2318 ath_err(common,
2319 "Failed to allocate tx descriptors: %d\n", error);
2320 goto err;
2321 }
2322
2323 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2324 "beacon", ATH_BCBUF, 1, 1);
2325 if (error != 0) {
2326 ath_err(common,
2327 "Failed to allocate beacon descriptors: %d\n", error);
2328 goto err;
2329 }
2330
2331 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2332
2333 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2334 error = ath_tx_edma_init(sc);
2335 if (error)
2336 goto err;
2337 }
2338
2339 err:
2340 if (error != 0)
2341 ath_tx_cleanup(sc);
2342
2343 return error;
2344 }
2345
2346 void ath_tx_cleanup(struct ath_softc *sc)
2347 {
2348 if (sc->beacon.bdma.dd_desc_len != 0)
2349 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2350
2351 if (sc->tx.txdma.dd_desc_len != 0)
2352 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2353
2354 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2355 ath_tx_edma_cleanup(sc);
2356 }
2357
2358 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2359 {
2360 struct ath_atx_tid *tid;
2361 struct ath_atx_ac *ac;
2362 int tidno, acno;
2363
2364 for (tidno = 0, tid = &an->tid[tidno];
2365 tidno < WME_NUM_TID;
2366 tidno++, tid++) {
2367 tid->an = an;
2368 tid->tidno = tidno;
2369 tid->seq_start = tid->seq_next = 0;
2370 tid->baw_size = WME_MAX_BA;
2371 tid->baw_head = tid->baw_tail = 0;
2372 tid->sched = false;
2373 tid->paused = false;
2374 tid->state &= ~AGGR_CLEANUP;
2375 INIT_LIST_HEAD(&tid->buf_q);
2376 acno = TID_TO_WME_AC(tidno);
2377 tid->ac = &an->ac[acno];
2378 tid->state &= ~AGGR_ADDBA_COMPLETE;
2379 tid->state &= ~AGGR_ADDBA_PROGRESS;
2380 }
2381
2382 for (acno = 0, ac = &an->ac[acno];
2383 acno < WME_NUM_AC; acno++, ac++) {
2384 ac->sched = false;
2385 ac->txq = sc->tx.txq_map[acno];
2386 INIT_LIST_HEAD(&ac->tid_q);
2387 }
2388 }
2389
2390 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2391 {
2392 struct ath_atx_ac *ac;
2393 struct ath_atx_tid *tid;
2394 struct ath_txq *txq;
2395 int tidno;
2396
2397 for (tidno = 0, tid = &an->tid[tidno];
2398 tidno < WME_NUM_TID; tidno++, tid++) {
2399
2400 ac = tid->ac;
2401 txq = ac->txq;
2402
2403 spin_lock_bh(&txq->axq_lock);
2404
2405 if (tid->sched) {
2406 list_del(&tid->list);
2407 tid->sched = false;
2408 }
2409
2410 if (ac->sched) {
2411 list_del(&ac->list);
2412 tid->ac->sched = false;
2413 }
2414
2415 ath_tid_drain(sc, txq, tid);
2416 tid->state &= ~AGGR_ADDBA_COMPLETE;
2417 tid->state &= ~AGGR_CLEANUP;
2418
2419 spin_unlock_bh(&txq->axq_lock);
2420 }
2421 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree