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drm/i915: set dither bits on eDP panels too
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
blob4b23646304df1bae6fb9ec23539b5535436e43b0
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
48
49 typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59 } intel_clock_t;
60
61 typedef struct {
62 int min, max;
63 } intel_range_t;
64
65 typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77 };
78
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
83 #define I8XX_N_MIN 3
84 #define I8XX_N_MAX 16
85 #define I8XX_M_MIN 96
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
89 #define I8XX_M2_MIN 6
90 #define I8XX_M2_MAX 16
91 #define I8XX_P_MIN 4
92 #define I8XX_P_MAX 128
93 #define I8XX_P1_MIN 2
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
102
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
109 #define I9XX_N_MIN 1
110 #define I9XX_N_MAX 6
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
162
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
181
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252
253 /* We have parameter ranges for different type of outputs. */
254
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
266
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
278
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
290
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315 /* DisplayPort */
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
327
328 /* FDI */
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
331 static bool
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
337
338 static bool
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
341 static bool
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
344
345 static const intel_limit_t intel_limits_i8xx_dvo = {
346 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
347 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
348 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
349 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
350 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
351 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
352 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
353 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
354 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
355 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
356 .find_pll = intel_find_best_PLL,
357 };
358
359 static const intel_limit_t intel_limits_i8xx_lvds = {
360 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
361 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
362 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
363 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
364 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
365 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
366 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
367 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
368 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
369 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
370 .find_pll = intel_find_best_PLL,
371 };
372
373 static const intel_limit_t intel_limits_i9xx_sdvo = {
374 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
375 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
376 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
377 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
378 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
379 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
380 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
381 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
382 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
383 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
384 .find_pll = intel_find_best_PLL,
385 };
386
387 static const intel_limit_t intel_limits_i9xx_lvds = {
388 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
389 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
390 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
391 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
392 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
393 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
394 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
395 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
396 /* The single-channel range is 25-112Mhz, and dual-channel
397 * is 80-224Mhz. Prefer single channel as much as possible.
398 */
399 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
400 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
401 .find_pll = intel_find_best_PLL,
402 };
403
404 /* below parameter and function is for G4X Chipset Family*/
405 static const intel_limit_t intel_limits_g4x_sdvo = {
406 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
407 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
408 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
409 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
410 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
411 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
412 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
413 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
414 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
415 .p2_slow = G4X_P2_SDVO_SLOW,
416 .p2_fast = G4X_P2_SDVO_FAST
417 },
418 .find_pll = intel_g4x_find_best_PLL,
419 };
420
421 static const intel_limit_t intel_limits_g4x_hdmi = {
422 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
423 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
424 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
425 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
426 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
427 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
428 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
429 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
430 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
431 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
432 .p2_fast = G4X_P2_HDMI_DAC_FAST
433 },
434 .find_pll = intel_g4x_find_best_PLL,
435 };
436
437 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
438 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
439 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
440 .vco = { .min = G4X_VCO_MIN,
441 .max = G4X_VCO_MAX },
442 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
443 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
444 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
445 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
446 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
447 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
448 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
450 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
451 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
452 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
454 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
455 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
456 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
457 },
458 .find_pll = intel_g4x_find_best_PLL,
459 };
460
461 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
462 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
463 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
464 .vco = { .min = G4X_VCO_MIN,
465 .max = G4X_VCO_MAX },
466 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
467 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
468 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
469 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
470 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
471 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
472 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
474 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
475 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
476 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
478 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
479 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
480 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
481 },
482 .find_pll = intel_g4x_find_best_PLL,
483 };
484
485 static const intel_limit_t intel_limits_g4x_display_port = {
486 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
487 .max = G4X_DOT_DISPLAY_PORT_MAX },
488 .vco = { .min = G4X_VCO_MIN,
489 .max = G4X_VCO_MAX},
490 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
491 .max = G4X_N_DISPLAY_PORT_MAX },
492 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
493 .max = G4X_M_DISPLAY_PORT_MAX },
494 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
495 .max = G4X_M1_DISPLAY_PORT_MAX },
496 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
497 .max = G4X_M2_DISPLAY_PORT_MAX },
498 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
499 .max = G4X_P_DISPLAY_PORT_MAX },
500 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
501 .max = G4X_P1_DISPLAY_PORT_MAX},
502 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
503 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
504 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
505 .find_pll = intel_find_pll_g4x_dp,
506 };
507
508 static const intel_limit_t intel_limits_pineview_sdvo = {
509 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
510 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
511 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
512 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
513 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
514 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
515 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
516 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
517 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
518 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
519 .find_pll = intel_find_best_PLL,
520 };
521
522 static const intel_limit_t intel_limits_pineview_lvds = {
523 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
524 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
525 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
526 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
527 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
528 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
529 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
530 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
531 /* Pineview only supports single-channel mode. */
532 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
533 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
534 .find_pll = intel_find_best_PLL,
535 };
536
537 static const intel_limit_t intel_limits_ironlake_dac = {
538 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
539 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
540 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
541 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
542 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
543 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
544 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
545 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
546 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
547 .p2_slow = IRONLAKE_DAC_P2_SLOW,
548 .p2_fast = IRONLAKE_DAC_P2_FAST },
549 .find_pll = intel_g4x_find_best_PLL,
550 };
551
552 static const intel_limit_t intel_limits_ironlake_single_lvds = {
553 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
554 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
555 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
556 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
557 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
558 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
559 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
560 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
561 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
562 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
563 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
564 .find_pll = intel_g4x_find_best_PLL,
565 };
566
567 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
568 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
569 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
570 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
571 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
572 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
573 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
574 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
575 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
576 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
577 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
578 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
579 .find_pll = intel_g4x_find_best_PLL,
580 };
581
582 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
583 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
584 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
585 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
586 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
587 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
588 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
589 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
590 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
591 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
592 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
593 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
594 .find_pll = intel_g4x_find_best_PLL,
595 };
596
597 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
598 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
599 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
600 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
601 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
602 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
603 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
604 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
605 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
606 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
607 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
608 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
609 .find_pll = intel_g4x_find_best_PLL,
610 };
611
612 static const intel_limit_t intel_limits_ironlake_display_port = {
613 .dot = { .min = IRONLAKE_DOT_MIN,
614 .max = IRONLAKE_DOT_MAX },
615 .vco = { .min = IRONLAKE_VCO_MIN,
616 .max = IRONLAKE_VCO_MAX},
617 .n = { .min = IRONLAKE_DP_N_MIN,
618 .max = IRONLAKE_DP_N_MAX },
619 .m = { .min = IRONLAKE_DP_M_MIN,
620 .max = IRONLAKE_DP_M_MAX },
621 .m1 = { .min = IRONLAKE_M1_MIN,
622 .max = IRONLAKE_M1_MAX },
623 .m2 = { .min = IRONLAKE_M2_MIN,
624 .max = IRONLAKE_M2_MAX },
625 .p = { .min = IRONLAKE_DP_P_MIN,
626 .max = IRONLAKE_DP_P_MAX },
627 .p1 = { .min = IRONLAKE_DP_P1_MIN,
628 .max = IRONLAKE_DP_P1_MAX},
629 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
630 .p2_slow = IRONLAKE_DP_P2_SLOW,
631 .p2_fast = IRONLAKE_DP_P2_FAST },
632 .find_pll = intel_find_pll_ironlake_dp,
633 };
634
635 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
636 {
637 struct drm_device *dev = crtc->dev;
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 const intel_limit_t *limit;
640 int refclk = 120;
641
642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
643 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
644 refclk = 100;
645
646 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
647 LVDS_CLKB_POWER_UP) {
648 /* LVDS dual channel */
649 if (refclk == 100)
650 limit = &intel_limits_ironlake_dual_lvds_100m;
651 else
652 limit = &intel_limits_ironlake_dual_lvds;
653 } else {
654 if (refclk == 100)
655 limit = &intel_limits_ironlake_single_lvds_100m;
656 else
657 limit = &intel_limits_ironlake_single_lvds;
658 }
659 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
660 HAS_eDP)
661 limit = &intel_limits_ironlake_display_port;
662 else
663 limit = &intel_limits_ironlake_dac;
664
665 return limit;
666 }
667
668 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
669 {
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 const intel_limit_t *limit;
673
674 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
675 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
676 LVDS_CLKB_POWER_UP)
677 /* LVDS with dual channel */
678 limit = &intel_limits_g4x_dual_channel_lvds;
679 else
680 /* LVDS with dual channel */
681 limit = &intel_limits_g4x_single_channel_lvds;
682 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
683 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
684 limit = &intel_limits_g4x_hdmi;
685 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
686 limit = &intel_limits_g4x_sdvo;
687 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
688 limit = &intel_limits_g4x_display_port;
689 } else /* The option is for other outputs */
690 limit = &intel_limits_i9xx_sdvo;
691
692 return limit;
693 }
694
695 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
696 {
697 struct drm_device *dev = crtc->dev;
698 const intel_limit_t *limit;
699
700 if (HAS_PCH_SPLIT(dev))
701 limit = intel_ironlake_limit(crtc);
702 else if (IS_G4X(dev)) {
703 limit = intel_g4x_limit(crtc);
704 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
705 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
706 limit = &intel_limits_i9xx_lvds;
707 else
708 limit = &intel_limits_i9xx_sdvo;
709 } else if (IS_PINEVIEW(dev)) {
710 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
711 limit = &intel_limits_pineview_lvds;
712 else
713 limit = &intel_limits_pineview_sdvo;
714 } else {
715 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
716 limit = &intel_limits_i8xx_lvds;
717 else
718 limit = &intel_limits_i8xx_dvo;
719 }
720 return limit;
721 }
722
723 /* m1 is reserved as 0 in Pineview, n is a ring counter */
724 static void pineview_clock(int refclk, intel_clock_t *clock)
725 {
726 clock->m = clock->m2 + 2;
727 clock->p = clock->p1 * clock->p2;
728 clock->vco = refclk * clock->m / clock->n;
729 clock->dot = clock->vco / clock->p;
730 }
731
732 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
733 {
734 if (IS_PINEVIEW(dev)) {
735 pineview_clock(refclk, clock);
736 return;
737 }
738 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
739 clock->p = clock->p1 * clock->p2;
740 clock->vco = refclk * clock->m / (clock->n + 2);
741 clock->dot = clock->vco / clock->p;
742 }
743
744 /**
745 * Returns whether any output on the specified pipe is of the specified type
746 */
747 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
748 {
749 struct drm_device *dev = crtc->dev;
750 struct drm_mode_config *mode_config = &dev->mode_config;
751 struct drm_encoder *l_entry;
752
753 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
754 if (l_entry && l_entry->crtc == crtc) {
755 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
756 if (intel_encoder->type == type)
757 return true;
758 }
759 }
760 return false;
761 }
762
763 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
764 /**
765 * Returns whether the given set of divisors are valid for a given refclk with
766 * the given connectors.
767 */
768
769 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
770 {
771 const intel_limit_t *limit = intel_limit (crtc);
772 struct drm_device *dev = crtc->dev;
773
774 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
775 INTELPllInvalid ("p1 out of range\n");
776 if (clock->p < limit->p.min || limit->p.max < clock->p)
777 INTELPllInvalid ("p out of range\n");
778 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
779 INTELPllInvalid ("m2 out of range\n");
780 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
781 INTELPllInvalid ("m1 out of range\n");
782 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
783 INTELPllInvalid ("m1 <= m2\n");
784 if (clock->m < limit->m.min || limit->m.max < clock->m)
785 INTELPllInvalid ("m out of range\n");
786 if (clock->n < limit->n.min || limit->n.max < clock->n)
787 INTELPllInvalid ("n out of range\n");
788 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
789 INTELPllInvalid ("vco out of range\n");
790 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
791 * connector, etc., rather than just a single range.
792 */
793 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
794 INTELPllInvalid ("dot out of range\n");
795
796 return true;
797 }
798
799 static bool
800 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
801 int target, int refclk, intel_clock_t *best_clock)
802
803 {
804 struct drm_device *dev = crtc->dev;
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 intel_clock_t clock;
807 int err = target;
808
809 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
810 (I915_READ(LVDS)) != 0) {
811 /*
812 * For LVDS, if the panel is on, just rely on its current
813 * settings for dual-channel. We haven't figured out how to
814 * reliably set up different single/dual channel state, if we
815 * even can.
816 */
817 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
818 LVDS_CLKB_POWER_UP)
819 clock.p2 = limit->p2.p2_fast;
820 else
821 clock.p2 = limit->p2.p2_slow;
822 } else {
823 if (target < limit->p2.dot_limit)
824 clock.p2 = limit->p2.p2_slow;
825 else
826 clock.p2 = limit->p2.p2_fast;
827 }
828
829 memset (best_clock, 0, sizeof (*best_clock));
830
831 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
832 clock.m1++) {
833 for (clock.m2 = limit->m2.min;
834 clock.m2 <= limit->m2.max; clock.m2++) {
835 /* m1 is always 0 in Pineview */
836 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
837 break;
838 for (clock.n = limit->n.min;
839 clock.n <= limit->n.max; clock.n++) {
840 for (clock.p1 = limit->p1.min;
841 clock.p1 <= limit->p1.max; clock.p1++) {
842 int this_err;
843
844 intel_clock(dev, refclk, &clock);
845
846 if (!intel_PLL_is_valid(crtc, &clock))
847 continue;
848
849 this_err = abs(clock.dot - target);
850 if (this_err < err) {
851 *best_clock = clock;
852 err = this_err;
853 }
854 }
855 }
856 }
857 }
858
859 return (err != target);
860 }
861
862 static bool
863 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
864 int target, int refclk, intel_clock_t *best_clock)
865 {
866 struct drm_device *dev = crtc->dev;
867 struct drm_i915_private *dev_priv = dev->dev_private;
868 intel_clock_t clock;
869 int max_n;
870 bool found;
871 /* approximately equals target * 0.00585 */
872 int err_most = (target >> 8) + (target >> 9);
873 found = false;
874
875 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
876 int lvds_reg;
877
878 if (HAS_PCH_SPLIT(dev))
879 lvds_reg = PCH_LVDS;
880 else
881 lvds_reg = LVDS;
882 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
883 LVDS_CLKB_POWER_UP)
884 clock.p2 = limit->p2.p2_fast;
885 else
886 clock.p2 = limit->p2.p2_slow;
887 } else {
888 if (target < limit->p2.dot_limit)
889 clock.p2 = limit->p2.p2_slow;
890 else
891 clock.p2 = limit->p2.p2_fast;
892 }
893
894 memset(best_clock, 0, sizeof(*best_clock));
895 max_n = limit->n.max;
896 /* based on hardware requirement, prefer smaller n to precision */
897 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
898 /* based on hardware requirement, prefere larger m1,m2 */
899 for (clock.m1 = limit->m1.max;
900 clock.m1 >= limit->m1.min; clock.m1--) {
901 for (clock.m2 = limit->m2.max;
902 clock.m2 >= limit->m2.min; clock.m2--) {
903 for (clock.p1 = limit->p1.max;
904 clock.p1 >= limit->p1.min; clock.p1--) {
905 int this_err;
906
907 intel_clock(dev, refclk, &clock);
908 if (!intel_PLL_is_valid(crtc, &clock))
909 continue;
910 this_err = abs(clock.dot - target) ;
911 if (this_err < err_most) {
912 *best_clock = clock;
913 err_most = this_err;
914 max_n = clock.n;
915 found = true;
916 }
917 }
918 }
919 }
920 }
921 return found;
922 }
923
924 static bool
925 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
926 int target, int refclk, intel_clock_t *best_clock)
927 {
928 struct drm_device *dev = crtc->dev;
929 intel_clock_t clock;
930
931 /* return directly when it is eDP */
932 if (HAS_eDP)
933 return true;
934
935 if (target < 200000) {
936 clock.n = 1;
937 clock.p1 = 2;
938 clock.p2 = 10;
939 clock.m1 = 12;
940 clock.m2 = 9;
941 } else {
942 clock.n = 2;
943 clock.p1 = 1;
944 clock.p2 = 10;
945 clock.m1 = 14;
946 clock.m2 = 8;
947 }
948 intel_clock(dev, refclk, &clock);
949 memcpy(best_clock, &clock, sizeof(intel_clock_t));
950 return true;
951 }
952
953 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
954 static bool
955 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
956 int target, int refclk, intel_clock_t *best_clock)
957 {
958 intel_clock_t clock;
959 if (target < 200000) {
960 clock.p1 = 2;
961 clock.p2 = 10;
962 clock.n = 2;
963 clock.m1 = 23;
964 clock.m2 = 8;
965 } else {
966 clock.p1 = 1;
967 clock.p2 = 10;
968 clock.n = 1;
969 clock.m1 = 14;
970 clock.m2 = 2;
971 }
972 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
973 clock.p = (clock.p1 * clock.p2);
974 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
975 clock.vco = 0;
976 memcpy(best_clock, &clock, sizeof(intel_clock_t));
977 return true;
978 }
979
980 /**
981 * intel_wait_for_vblank - wait for vblank on a given pipe
982 * @dev: drm device
983 * @pipe: pipe to wait for
984 *
985 * Wait for vblank to occur on a given pipe. Needed for various bits of
986 * mode setting code.
987 */
988 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
989 {
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
992
993 /* Clear existing vblank status. Note this will clear any other
994 * sticky status fields as well.
995 *
996 * This races with i915_driver_irq_handler() with the result
997 * that either function could miss a vblank event. Here it is not
998 * fatal, as we will either wait upon the next vblank interrupt or
999 * timeout. Generally speaking intel_wait_for_vblank() is only
1000 * called during modeset at which time the GPU should be idle and
1001 * should *not* be performing page flips and thus not waiting on
1002 * vblanks...
1003 * Currently, the result of us stealing a vblank from the irq
1004 * handler is that a single frame will be skipped during swapbuffers.
1005 */
1006 I915_WRITE(pipestat_reg,
1007 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1008
1009 /* Wait for vblank interrupt bit to set */
1010 if (wait_for(I915_READ(pipestat_reg) &
1011 PIPE_VBLANK_INTERRUPT_STATUS,
1012 50))
1013 DRM_DEBUG_KMS("vblank wait timed out\n");
1014 }
1015
1016 /**
1017 * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1018 * @dev: drm device
1019 * @pipe: pipe to wait for
1020 *
1021 * After disabling a pipe, we can't wait for vblank in the usual way,
1022 * spinning on the vblank interrupt status bit, since we won't actually
1023 * see an interrupt when the pipe is disabled.
1024 *
1025 * So this function waits for the display line value to settle (it
1026 * usually ends up stopping at the start of the next frame).
1027 */
1028 void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
1029 {
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1032 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033 u32 last_line;
1034
1035 /* Wait for the display line to settle */
1036 do {
1037 last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1038 mdelay(5);
1039 } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) &&
1040 time_after(timeout, jiffies));
1041
1042 if (time_after(jiffies, timeout))
1043 DRM_DEBUG_KMS("vblank wait timed out\n");
1044 }
1045
1046 /* Parameters have changed, update FBC info */
1047 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1048 {
1049 struct drm_device *dev = crtc->dev;
1050 struct drm_i915_private *dev_priv = dev->dev_private;
1051 struct drm_framebuffer *fb = crtc->fb;
1052 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1053 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1055 int plane, i;
1056 u32 fbc_ctl, fbc_ctl2;
1057
1058 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1059
1060 if (fb->pitch < dev_priv->cfb_pitch)
1061 dev_priv->cfb_pitch = fb->pitch;
1062
1063 /* FBC_CTL wants 64B units */
1064 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1065 dev_priv->cfb_fence = obj_priv->fence_reg;
1066 dev_priv->cfb_plane = intel_crtc->plane;
1067 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1068
1069 /* Clear old tags */
1070 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1071 I915_WRITE(FBC_TAG + (i * 4), 0);
1072
1073 /* Set it up... */
1074 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1075 if (obj_priv->tiling_mode != I915_TILING_NONE)
1076 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1077 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1078 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1079
1080 /* enable it... */
1081 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1082 if (IS_I945GM(dev))
1083 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1084 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1085 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1086 if (obj_priv->tiling_mode != I915_TILING_NONE)
1087 fbc_ctl |= dev_priv->cfb_fence;
1088 I915_WRITE(FBC_CONTROL, fbc_ctl);
1089
1090 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1091 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1092 }
1093
1094 void i8xx_disable_fbc(struct drm_device *dev)
1095 {
1096 struct drm_i915_private *dev_priv = dev->dev_private;
1097 u32 fbc_ctl;
1098
1099 if (!I915_HAS_FBC(dev))
1100 return;
1101
1102 if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1103 return; /* Already off, just return */
1104
1105 /* Disable compression */
1106 fbc_ctl = I915_READ(FBC_CONTROL);
1107 fbc_ctl &= ~FBC_CTL_EN;
1108 I915_WRITE(FBC_CONTROL, fbc_ctl);
1109
1110 /* Wait for compressing bit to clear */
1111 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1112 DRM_DEBUG_KMS("FBC idle timed out\n");
1113 return;
1114 }
1115
1116 DRM_DEBUG_KMS("disabled FBC\n");
1117 }
1118
1119 static bool i8xx_fbc_enabled(struct drm_device *dev)
1120 {
1121 struct drm_i915_private *dev_priv = dev->dev_private;
1122
1123 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1124 }
1125
1126 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1127 {
1128 struct drm_device *dev = crtc->dev;
1129 struct drm_i915_private *dev_priv = dev->dev_private;
1130 struct drm_framebuffer *fb = crtc->fb;
1131 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1132 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1134 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1135 DPFC_CTL_PLANEB);
1136 unsigned long stall_watermark = 200;
1137 u32 dpfc_ctl;
1138
1139 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1140 dev_priv->cfb_fence = obj_priv->fence_reg;
1141 dev_priv->cfb_plane = intel_crtc->plane;
1142
1143 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1144 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1145 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1146 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1147 } else {
1148 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1149 }
1150
1151 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1152 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1153 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1154 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1155 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1156
1157 /* enable it... */
1158 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1159
1160 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1161 }
1162
1163 void g4x_disable_fbc(struct drm_device *dev)
1164 {
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1166 u32 dpfc_ctl;
1167
1168 /* Disable compression */
1169 dpfc_ctl = I915_READ(DPFC_CONTROL);
1170 dpfc_ctl &= ~DPFC_CTL_EN;
1171 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1172
1173 DRM_DEBUG_KMS("disabled FBC\n");
1174 }
1175
1176 static bool g4x_fbc_enabled(struct drm_device *dev)
1177 {
1178 struct drm_i915_private *dev_priv = dev->dev_private;
1179
1180 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1181 }
1182
1183 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1184 {
1185 struct drm_device *dev = crtc->dev;
1186 struct drm_i915_private *dev_priv = dev->dev_private;
1187 struct drm_framebuffer *fb = crtc->fb;
1188 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1189 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1191 int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1192 DPFC_CTL_PLANEB;
1193 unsigned long stall_watermark = 200;
1194 u32 dpfc_ctl;
1195
1196 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1197 dev_priv->cfb_fence = obj_priv->fence_reg;
1198 dev_priv->cfb_plane = intel_crtc->plane;
1199
1200 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1201 dpfc_ctl &= DPFC_RESERVED;
1202 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1203 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1204 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1205 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1206 } else {
1207 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1208 }
1209
1210 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1211 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1212 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1213 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1214 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1215 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1216 /* enable it... */
1217 I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1218 DPFC_CTL_EN);
1219
1220 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1221 }
1222
1223 void ironlake_disable_fbc(struct drm_device *dev)
1224 {
1225 struct drm_i915_private *dev_priv = dev->dev_private;
1226 u32 dpfc_ctl;
1227
1228 /* Disable compression */
1229 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1230 dpfc_ctl &= ~DPFC_CTL_EN;
1231 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1232
1233 DRM_DEBUG_KMS("disabled FBC\n");
1234 }
1235
1236 static bool ironlake_fbc_enabled(struct drm_device *dev)
1237 {
1238 struct drm_i915_private *dev_priv = dev->dev_private;
1239
1240 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1241 }
1242
1243 bool intel_fbc_enabled(struct drm_device *dev)
1244 {
1245 struct drm_i915_private *dev_priv = dev->dev_private;
1246
1247 if (!dev_priv->display.fbc_enabled)
1248 return false;
1249
1250 return dev_priv->display.fbc_enabled(dev);
1251 }
1252
1253 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1254 {
1255 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1256
1257 if (!dev_priv->display.enable_fbc)
1258 return;
1259
1260 dev_priv->display.enable_fbc(crtc, interval);
1261 }
1262
1263 void intel_disable_fbc(struct drm_device *dev)
1264 {
1265 struct drm_i915_private *dev_priv = dev->dev_private;
1266
1267 if (!dev_priv->display.disable_fbc)
1268 return;
1269
1270 dev_priv->display.disable_fbc(dev);
1271 }
1272
1273 /**
1274 * intel_update_fbc - enable/disable FBC as needed
1275 * @crtc: CRTC to point the compressor at
1276 * @mode: mode in use
1277 *
1278 * Set up the framebuffer compression hardware at mode set time. We
1279 * enable it if possible:
1280 * - plane A only (on pre-965)
1281 * - no pixel mulitply/line duplication
1282 * - no alpha buffer discard
1283 * - no dual wide
1284 * - framebuffer <= 2048 in width, 1536 in height
1285 *
1286 * We can't assume that any compression will take place (worst case),
1287 * so the compressed buffer has to be the same size as the uncompressed
1288 * one. It also must reside (along with the line length buffer) in
1289 * stolen memory.
1290 *
1291 * We need to enable/disable FBC on a global basis.
1292 */
1293 static void intel_update_fbc(struct drm_crtc *crtc,
1294 struct drm_display_mode *mode)
1295 {
1296 struct drm_device *dev = crtc->dev;
1297 struct drm_i915_private *dev_priv = dev->dev_private;
1298 struct drm_framebuffer *fb = crtc->fb;
1299 struct intel_framebuffer *intel_fb;
1300 struct drm_i915_gem_object *obj_priv;
1301 struct drm_crtc *tmp_crtc;
1302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1303 int plane = intel_crtc->plane;
1304 int crtcs_enabled = 0;
1305
1306 DRM_DEBUG_KMS("\n");
1307
1308 if (!i915_powersave)
1309 return;
1310
1311 if (!I915_HAS_FBC(dev))
1312 return;
1313
1314 if (!crtc->fb)
1315 return;
1316
1317 intel_fb = to_intel_framebuffer(fb);
1318 obj_priv = to_intel_bo(intel_fb->obj);
1319
1320 /*
1321 * If FBC is already on, we just have to verify that we can
1322 * keep it that way...
1323 * Need to disable if:
1324 * - more than one pipe is active
1325 * - changing FBC params (stride, fence, mode)
1326 * - new fb is too large to fit in compressed buffer
1327 * - going to an unsupported config (interlace, pixel multiply, etc.)
1328 */
1329 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1330 if (tmp_crtc->enabled)
1331 crtcs_enabled++;
1332 }
1333 DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1334 if (crtcs_enabled > 1) {
1335 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1336 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1337 goto out_disable;
1338 }
1339 if (intel_fb->obj->size > dev_priv->cfb_size) {
1340 DRM_DEBUG_KMS("framebuffer too large, disabling "
1341 "compression\n");
1342 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1343 goto out_disable;
1344 }
1345 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1346 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1347 DRM_DEBUG_KMS("mode incompatible with compression, "
1348 "disabling\n");
1349 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1350 goto out_disable;
1351 }
1352 if ((mode->hdisplay > 2048) ||
1353 (mode->vdisplay > 1536)) {
1354 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1355 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1356 goto out_disable;
1357 }
1358 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1359 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1360 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1361 goto out_disable;
1362 }
1363 if (obj_priv->tiling_mode != I915_TILING_X) {
1364 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1365 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1366 goto out_disable;
1367 }
1368
1369 /* If the kernel debugger is active, always disable compression */
1370 if (in_dbg_master())
1371 goto out_disable;
1372
1373 if (intel_fbc_enabled(dev)) {
1374 /* We can re-enable it in this case, but need to update pitch */
1375 if ((fb->pitch > dev_priv->cfb_pitch) ||
1376 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1377 (plane != dev_priv->cfb_plane))
1378 intel_disable_fbc(dev);
1379 }
1380
1381 /* Now try to turn it back on if possible */
1382 if (!intel_fbc_enabled(dev))
1383 intel_enable_fbc(crtc, 500);
1384
1385 return;
1386
1387 out_disable:
1388 /* Multiple disables should be harmless */
1389 if (intel_fbc_enabled(dev)) {
1390 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1391 intel_disable_fbc(dev);
1392 }
1393 }
1394
1395 int
1396 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1397 {
1398 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1399 u32 alignment;
1400 int ret;
1401
1402 switch (obj_priv->tiling_mode) {
1403 case I915_TILING_NONE:
1404 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1405 alignment = 128 * 1024;
1406 else if (IS_I965G(dev))
1407 alignment = 4 * 1024;
1408 else
1409 alignment = 64 * 1024;
1410 break;
1411 case I915_TILING_X:
1412 /* pin() will align the object as required by fence */
1413 alignment = 0;
1414 break;
1415 case I915_TILING_Y:
1416 /* FIXME: Is this true? */
1417 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1418 return -EINVAL;
1419 default:
1420 BUG();
1421 }
1422
1423 ret = i915_gem_object_pin(obj, alignment);
1424 if (ret != 0)
1425 return ret;
1426
1427 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1428 * fence, whereas 965+ only requires a fence if using
1429 * framebuffer compression. For simplicity, we always install
1430 * a fence as the cost is not that onerous.
1431 */
1432 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1433 obj_priv->tiling_mode != I915_TILING_NONE) {
1434 ret = i915_gem_object_get_fence_reg(obj);
1435 if (ret != 0) {
1436 i915_gem_object_unpin(obj);
1437 return ret;
1438 }
1439 }
1440
1441 return 0;
1442 }
1443
1444 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1445 static int
1446 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1447 int x, int y)
1448 {
1449 struct drm_device *dev = crtc->dev;
1450 struct drm_i915_private *dev_priv = dev->dev_private;
1451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1452 struct intel_framebuffer *intel_fb;
1453 struct drm_i915_gem_object *obj_priv;
1454 struct drm_gem_object *obj;
1455 int plane = intel_crtc->plane;
1456 unsigned long Start, Offset;
1457 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1458 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1459 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1460 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1461 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1462 u32 dspcntr;
1463
1464 switch (plane) {
1465 case 0:
1466 case 1:
1467 break;
1468 default:
1469 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1470 return -EINVAL;
1471 }
1472
1473 intel_fb = to_intel_framebuffer(fb);
1474 obj = intel_fb->obj;
1475 obj_priv = to_intel_bo(obj);
1476
1477 dspcntr = I915_READ(dspcntr_reg);
1478 /* Mask out pixel format bits in case we change it */
1479 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1480 switch (fb->bits_per_pixel) {
1481 case 8:
1482 dspcntr |= DISPPLANE_8BPP;
1483 break;
1484 case 16:
1485 if (fb->depth == 15)
1486 dspcntr |= DISPPLANE_15_16BPP;
1487 else
1488 dspcntr |= DISPPLANE_16BPP;
1489 break;
1490 case 24:
1491 case 32:
1492 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1493 break;
1494 default:
1495 DRM_ERROR("Unknown color depth\n");
1496 return -EINVAL;
1497 }
1498 if (IS_I965G(dev)) {
1499 if (obj_priv->tiling_mode != I915_TILING_NONE)
1500 dspcntr |= DISPPLANE_TILED;
1501 else
1502 dspcntr &= ~DISPPLANE_TILED;
1503 }
1504
1505 if (HAS_PCH_SPLIT(dev))
1506 /* must disable */
1507 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1508
1509 I915_WRITE(dspcntr_reg, dspcntr);
1510
1511 Start = obj_priv->gtt_offset;
1512 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1513
1514 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1515 Start, Offset, x, y, fb->pitch);
1516 I915_WRITE(dspstride, fb->pitch);
1517 if (IS_I965G(dev)) {
1518 I915_WRITE(dspsurf, Start);
1519 I915_WRITE(dsptileoff, (y << 16) | x);
1520 I915_WRITE(dspbase, Offset);
1521 } else {
1522 I915_WRITE(dspbase, Start + Offset);
1523 }
1524 POSTING_READ(dspbase);
1525
1526 if (IS_I965G(dev) || plane == 0)
1527 intel_update_fbc(crtc, &crtc->mode);
1528
1529 intel_wait_for_vblank(dev, intel_crtc->pipe);
1530 intel_increase_pllclock(crtc);
1531
1532 return 0;
1533 }
1534
1535 static int
1536 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1537 struct drm_framebuffer *old_fb)
1538 {
1539 struct drm_device *dev = crtc->dev;
1540 struct drm_i915_master_private *master_priv;
1541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1542 struct intel_framebuffer *intel_fb;
1543 struct drm_i915_gem_object *obj_priv;
1544 struct drm_gem_object *obj;
1545 int pipe = intel_crtc->pipe;
1546 int plane = intel_crtc->plane;
1547 int ret;
1548
1549 /* no fb bound */
1550 if (!crtc->fb) {
1551 DRM_DEBUG_KMS("No FB bound\n");
1552 return 0;
1553 }
1554
1555 switch (plane) {
1556 case 0:
1557 case 1:
1558 break;
1559 default:
1560 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1561 return -EINVAL;
1562 }
1563
1564 intel_fb = to_intel_framebuffer(crtc->fb);
1565 obj = intel_fb->obj;
1566 obj_priv = to_intel_bo(obj);
1567
1568 mutex_lock(&dev->struct_mutex);
1569 ret = intel_pin_and_fence_fb_obj(dev, obj);
1570 if (ret != 0) {
1571 mutex_unlock(&dev->struct_mutex);
1572 return ret;
1573 }
1574
1575 ret = i915_gem_object_set_to_display_plane(obj);
1576 if (ret != 0) {
1577 i915_gem_object_unpin(obj);
1578 mutex_unlock(&dev->struct_mutex);
1579 return ret;
1580 }
1581
1582 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1583 if (ret) {
1584 i915_gem_object_unpin(obj);
1585 mutex_unlock(&dev->struct_mutex);
1586 return ret;
1587 }
1588
1589 if (old_fb) {
1590 intel_fb = to_intel_framebuffer(old_fb);
1591 obj_priv = to_intel_bo(intel_fb->obj);
1592 i915_gem_object_unpin(intel_fb->obj);
1593 }
1594
1595 mutex_unlock(&dev->struct_mutex);
1596
1597 if (!dev->primary->master)
1598 return 0;
1599
1600 master_priv = dev->primary->master->driver_priv;
1601 if (!master_priv->sarea_priv)
1602 return 0;
1603
1604 if (pipe) {
1605 master_priv->sarea_priv->pipeB_x = x;
1606 master_priv->sarea_priv->pipeB_y = y;
1607 } else {
1608 master_priv->sarea_priv->pipeA_x = x;
1609 master_priv->sarea_priv->pipeA_y = y;
1610 }
1611
1612 return 0;
1613 }
1614
1615 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1616 {
1617 struct drm_device *dev = crtc->dev;
1618 struct drm_i915_private *dev_priv = dev->dev_private;
1619 u32 dpa_ctl;
1620
1621 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1622 dpa_ctl = I915_READ(DP_A);
1623 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1624
1625 if (clock < 200000) {
1626 u32 temp;
1627 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1628 /* workaround for 160Mhz:
1629 1) program 0x4600c bits 15:0 = 0x8124
1630 2) program 0x46010 bit 0 = 1
1631 3) program 0x46034 bit 24 = 1
1632 4) program 0x64000 bit 14 = 1
1633 */
1634 temp = I915_READ(0x4600c);
1635 temp &= 0xffff0000;
1636 I915_WRITE(0x4600c, temp | 0x8124);
1637
1638 temp = I915_READ(0x46010);
1639 I915_WRITE(0x46010, temp | 1);
1640
1641 temp = I915_READ(0x46034);
1642 I915_WRITE(0x46034, temp | (1 << 24));
1643 } else {
1644 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1645 }
1646 I915_WRITE(DP_A, dpa_ctl);
1647
1648 udelay(500);
1649 }
1650
1651 /* The FDI link training functions for ILK/Ibexpeak. */
1652 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1653 {
1654 struct drm_device *dev = crtc->dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1657 int pipe = intel_crtc->pipe;
1658 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1659 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1660 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1661 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1662 u32 temp, tries = 0;
1663
1664 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1665 for train result */
1666 temp = I915_READ(fdi_rx_imr_reg);
1667 temp &= ~FDI_RX_SYMBOL_LOCK;
1668 temp &= ~FDI_RX_BIT_LOCK;
1669 I915_WRITE(fdi_rx_imr_reg, temp);
1670 I915_READ(fdi_rx_imr_reg);
1671 udelay(150);
1672
1673 /* enable CPU FDI TX and PCH FDI RX */
1674 temp = I915_READ(fdi_tx_reg);
1675 temp |= FDI_TX_ENABLE;
1676 temp &= ~(7 << 19);
1677 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1678 temp &= ~FDI_LINK_TRAIN_NONE;
1679 temp |= FDI_LINK_TRAIN_PATTERN_1;
1680 I915_WRITE(fdi_tx_reg, temp);
1681 I915_READ(fdi_tx_reg);
1682
1683 temp = I915_READ(fdi_rx_reg);
1684 temp &= ~FDI_LINK_TRAIN_NONE;
1685 temp |= FDI_LINK_TRAIN_PATTERN_1;
1686 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1687 I915_READ(fdi_rx_reg);
1688 udelay(150);
1689
1690 for (tries = 0; tries < 5; tries++) {
1691 temp = I915_READ(fdi_rx_iir_reg);
1692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1693
1694 if ((temp & FDI_RX_BIT_LOCK)) {
1695 DRM_DEBUG_KMS("FDI train 1 done.\n");
1696 I915_WRITE(fdi_rx_iir_reg,
1697 temp | FDI_RX_BIT_LOCK);
1698 break;
1699 }
1700 }
1701 if (tries == 5)
1702 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1703
1704 /* Train 2 */
1705 temp = I915_READ(fdi_tx_reg);
1706 temp &= ~FDI_LINK_TRAIN_NONE;
1707 temp |= FDI_LINK_TRAIN_PATTERN_2;
1708 I915_WRITE(fdi_tx_reg, temp);
1709
1710 temp = I915_READ(fdi_rx_reg);
1711 temp &= ~FDI_LINK_TRAIN_NONE;
1712 temp |= FDI_LINK_TRAIN_PATTERN_2;
1713 I915_WRITE(fdi_rx_reg, temp);
1714 udelay(150);
1715
1716 tries = 0;
1717
1718 for (tries = 0; tries < 5; tries++) {
1719 temp = I915_READ(fdi_rx_iir_reg);
1720 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1721
1722 if (temp & FDI_RX_SYMBOL_LOCK) {
1723 I915_WRITE(fdi_rx_iir_reg,
1724 temp | FDI_RX_SYMBOL_LOCK);
1725 DRM_DEBUG_KMS("FDI train 2 done.\n");
1726 break;
1727 }
1728 }
1729 if (tries == 5)
1730 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1731
1732 DRM_DEBUG_KMS("FDI train done\n");
1733 }
1734
1735 static int snb_b_fdi_train_param [] = {
1736 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1737 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1738 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1739 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1740 };
1741
1742 /* The FDI link training functions for SNB/Cougarpoint. */
1743 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1744 {
1745 struct drm_device *dev = crtc->dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1748 int pipe = intel_crtc->pipe;
1749 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1750 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1751 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1752 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1753 u32 temp, i;
1754
1755 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1756 for train result */
1757 temp = I915_READ(fdi_rx_imr_reg);
1758 temp &= ~FDI_RX_SYMBOL_LOCK;
1759 temp &= ~FDI_RX_BIT_LOCK;
1760 I915_WRITE(fdi_rx_imr_reg, temp);
1761 I915_READ(fdi_rx_imr_reg);
1762 udelay(150);
1763
1764 /* enable CPU FDI TX and PCH FDI RX */
1765 temp = I915_READ(fdi_tx_reg);
1766 temp |= FDI_TX_ENABLE;
1767 temp &= ~(7 << 19);
1768 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1769 temp &= ~FDI_LINK_TRAIN_NONE;
1770 temp |= FDI_LINK_TRAIN_PATTERN_1;
1771 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1772 /* SNB-B */
1773 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1774 I915_WRITE(fdi_tx_reg, temp);
1775 I915_READ(fdi_tx_reg);
1776
1777 temp = I915_READ(fdi_rx_reg);
1778 if (HAS_PCH_CPT(dev)) {
1779 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1780 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1781 } else {
1782 temp &= ~FDI_LINK_TRAIN_NONE;
1783 temp |= FDI_LINK_TRAIN_PATTERN_1;
1784 }
1785 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1786 I915_READ(fdi_rx_reg);
1787 udelay(150);
1788
1789 for (i = 0; i < 4; i++ ) {
1790 temp = I915_READ(fdi_tx_reg);
1791 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1792 temp |= snb_b_fdi_train_param[i];
1793 I915_WRITE(fdi_tx_reg, temp);
1794 udelay(500);
1795
1796 temp = I915_READ(fdi_rx_iir_reg);
1797 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1798
1799 if (temp & FDI_RX_BIT_LOCK) {
1800 I915_WRITE(fdi_rx_iir_reg,
1801 temp | FDI_RX_BIT_LOCK);
1802 DRM_DEBUG_KMS("FDI train 1 done.\n");
1803 break;
1804 }
1805 }
1806 if (i == 4)
1807 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1808
1809 /* Train 2 */
1810 temp = I915_READ(fdi_tx_reg);
1811 temp &= ~FDI_LINK_TRAIN_NONE;
1812 temp |= FDI_LINK_TRAIN_PATTERN_2;
1813 if (IS_GEN6(dev)) {
1814 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1815 /* SNB-B */
1816 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1817 }
1818 I915_WRITE(fdi_tx_reg, temp);
1819
1820 temp = I915_READ(fdi_rx_reg);
1821 if (HAS_PCH_CPT(dev)) {
1822 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1823 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1824 } else {
1825 temp &= ~FDI_LINK_TRAIN_NONE;
1826 temp |= FDI_LINK_TRAIN_PATTERN_2;
1827 }
1828 I915_WRITE(fdi_rx_reg, temp);
1829 udelay(150);
1830
1831 for (i = 0; i < 4; i++ ) {
1832 temp = I915_READ(fdi_tx_reg);
1833 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1834 temp |= snb_b_fdi_train_param[i];
1835 I915_WRITE(fdi_tx_reg, temp);
1836 udelay(500);
1837
1838 temp = I915_READ(fdi_rx_iir_reg);
1839 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1840
1841 if (temp & FDI_RX_SYMBOL_LOCK) {
1842 I915_WRITE(fdi_rx_iir_reg,
1843 temp | FDI_RX_SYMBOL_LOCK);
1844 DRM_DEBUG_KMS("FDI train 2 done.\n");
1845 break;
1846 }
1847 }
1848 if (i == 4)
1849 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1850
1851 DRM_DEBUG_KMS("FDI train done.\n");
1852 }
1853
1854 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1855 {
1856 struct drm_device *dev = crtc->dev;
1857 struct drm_i915_private *dev_priv = dev->dev_private;
1858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1859 int pipe = intel_crtc->pipe;
1860 int plane = intel_crtc->plane;
1861 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1862 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1863 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1864 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1865 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1866 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1867 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1868 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1869 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1870 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1871 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1872 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1873 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1874 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1875 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1876 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1877 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1878 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1879 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1880 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1881 u32 temp;
1882 u32 pipe_bpc;
1883
1884 temp = I915_READ(pipeconf_reg);
1885 pipe_bpc = temp & PIPE_BPC_MASK;
1886
1887 /* XXX: When our outputs are all unaware of DPMS modes other than off
1888 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1889 */
1890 switch (mode) {
1891 case DRM_MODE_DPMS_ON:
1892 case DRM_MODE_DPMS_STANDBY:
1893 case DRM_MODE_DPMS_SUSPEND:
1894 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1895
1896 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1897 temp = I915_READ(PCH_LVDS);
1898 if ((temp & LVDS_PORT_EN) == 0) {
1899 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1900 POSTING_READ(PCH_LVDS);
1901 }
1902 }
1903
1904 if (!HAS_eDP) {
1905
1906 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1907 temp = I915_READ(fdi_rx_reg);
1908 /*
1909 * make the BPC in FDI Rx be consistent with that in
1910 * pipeconf reg.
1911 */
1912 temp &= ~(0x7 << 16);
1913 temp |= (pipe_bpc << 11);
1914 temp &= ~(7 << 19);
1915 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1916 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1917 I915_READ(fdi_rx_reg);
1918 udelay(200);
1919
1920 /* Switch from Rawclk to PCDclk */
1921 temp = I915_READ(fdi_rx_reg);
1922 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1923 I915_READ(fdi_rx_reg);
1924 udelay(200);
1925
1926 /* Enable CPU FDI TX PLL, always on for Ironlake */
1927 temp = I915_READ(fdi_tx_reg);
1928 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1929 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1930 I915_READ(fdi_tx_reg);
1931 udelay(100);
1932 }
1933 }
1934
1935 /* Enable panel fitting for LVDS */
1936 if (dev_priv->pch_pf_size &&
1937 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1938 || HAS_eDP || intel_pch_has_edp(crtc))) {
1939 /* Force use of hard-coded filter coefficients
1940 * as some pre-programmed values are broken,
1941 * e.g. x201.
1942 */
1943 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
1944 PF_ENABLE | PF_FILTER_MED_3x3);
1945 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
1946 dev_priv->pch_pf_pos);
1947 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
1948 dev_priv->pch_pf_size);
1949 }
1950
1951 /* Enable CPU pipe */
1952 temp = I915_READ(pipeconf_reg);
1953 if ((temp & PIPEACONF_ENABLE) == 0) {
1954 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1955 I915_READ(pipeconf_reg);
1956 udelay(100);
1957 }
1958
1959 /* configure and enable CPU plane */
1960 temp = I915_READ(dspcntr_reg);
1961 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1962 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1963 /* Flush the plane changes */
1964 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1965 }
1966
1967 if (!HAS_eDP) {
1968 /* For PCH output, training FDI link */
1969 if (IS_GEN6(dev))
1970 gen6_fdi_link_train(crtc);
1971 else
1972 ironlake_fdi_link_train(crtc);
1973
1974 /* enable PCH DPLL */
1975 temp = I915_READ(pch_dpll_reg);
1976 if ((temp & DPLL_VCO_ENABLE) == 0) {
1977 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1978 I915_READ(pch_dpll_reg);
1979 }
1980 udelay(200);
1981
1982 if (HAS_PCH_CPT(dev)) {
1983 /* Be sure PCH DPLL SEL is set */
1984 temp = I915_READ(PCH_DPLL_SEL);
1985 if (trans_dpll_sel == 0 &&
1986 (temp & TRANSA_DPLL_ENABLE) == 0)
1987 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1988 else if (trans_dpll_sel == 1 &&
1989 (temp & TRANSB_DPLL_ENABLE) == 0)
1990 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1991 I915_WRITE(PCH_DPLL_SEL, temp);
1992 I915_READ(PCH_DPLL_SEL);
1993 }
1994
1995 /* set transcoder timing */
1996 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1997 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1998 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1999
2000 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2001 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2002 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2003
2004 /* enable normal train */
2005 temp = I915_READ(fdi_tx_reg);
2006 temp &= ~FDI_LINK_TRAIN_NONE;
2007 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2008 FDI_TX_ENHANCE_FRAME_ENABLE);
2009 I915_READ(fdi_tx_reg);
2010
2011 temp = I915_READ(fdi_rx_reg);
2012 if (HAS_PCH_CPT(dev)) {
2013 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2014 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2015 } else {
2016 temp &= ~FDI_LINK_TRAIN_NONE;
2017 temp |= FDI_LINK_TRAIN_NONE;
2018 }
2019 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2020 I915_READ(fdi_rx_reg);
2021
2022 /* wait one idle pattern time */
2023 udelay(100);
2024
2025 /* For PCH DP, enable TRANS_DP_CTL */
2026 if (HAS_PCH_CPT(dev) &&
2027 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2028 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2029 int reg;
2030
2031 reg = I915_READ(trans_dp_ctl);
2032 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2033 TRANS_DP_SYNC_MASK);
2034 reg |= (TRANS_DP_OUTPUT_ENABLE |
2035 TRANS_DP_ENH_FRAMING);
2036
2037 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2038 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2039 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2040 reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2041
2042 switch (intel_trans_dp_port_sel(crtc)) {
2043 case PCH_DP_B:
2044 reg |= TRANS_DP_PORT_SEL_B;
2045 break;
2046 case PCH_DP_C:
2047 reg |= TRANS_DP_PORT_SEL_C;
2048 break;
2049 case PCH_DP_D:
2050 reg |= TRANS_DP_PORT_SEL_D;
2051 break;
2052 default:
2053 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2054 reg |= TRANS_DP_PORT_SEL_B;
2055 break;
2056 }
2057
2058 I915_WRITE(trans_dp_ctl, reg);
2059 POSTING_READ(trans_dp_ctl);
2060 }
2061
2062 /* enable PCH transcoder */
2063 temp = I915_READ(transconf_reg);
2064 /*
2065 * make the BPC in transcoder be consistent with
2066 * that in pipeconf reg.
2067 */
2068 temp &= ~PIPE_BPC_MASK;
2069 temp |= pipe_bpc;
2070 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2071 I915_READ(transconf_reg);
2072
2073 if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100))
2074 DRM_ERROR("failed to enable transcoder\n");
2075 }
2076
2077 intel_crtc_load_lut(crtc);
2078
2079 intel_update_fbc(crtc, &crtc->mode);
2080 break;
2081
2082 case DRM_MODE_DPMS_OFF:
2083 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2084
2085 drm_vblank_off(dev, pipe);
2086 /* Disable display plane */
2087 temp = I915_READ(dspcntr_reg);
2088 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2089 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2090 /* Flush the plane changes */
2091 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2092 I915_READ(dspbase_reg);
2093 }
2094
2095 if (dev_priv->cfb_plane == plane &&
2096 dev_priv->display.disable_fbc)
2097 dev_priv->display.disable_fbc(dev);
2098
2099 /* disable cpu pipe, disable after all planes disabled */
2100 temp = I915_READ(pipeconf_reg);
2101 if ((temp & PIPEACONF_ENABLE) != 0) {
2102 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2103
2104 /* wait for cpu pipe off, pipe state */
2105 if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50))
2106 DRM_ERROR("failed to turn off cpu pipe\n");
2107 } else
2108 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2109
2110 udelay(100);
2111
2112 /* Disable PF */
2113 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2114 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2115
2116 /* disable CPU FDI tx and PCH FDI rx */
2117 temp = I915_READ(fdi_tx_reg);
2118 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2119 I915_READ(fdi_tx_reg);
2120
2121 temp = I915_READ(fdi_rx_reg);
2122 /* BPC in FDI rx is consistent with that in pipeconf */
2123 temp &= ~(0x07 << 16);
2124 temp |= (pipe_bpc << 11);
2125 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2126 I915_READ(fdi_rx_reg);
2127
2128 udelay(100);
2129
2130 /* still set train pattern 1 */
2131 temp = I915_READ(fdi_tx_reg);
2132 temp &= ~FDI_LINK_TRAIN_NONE;
2133 temp |= FDI_LINK_TRAIN_PATTERN_1;
2134 I915_WRITE(fdi_tx_reg, temp);
2135 POSTING_READ(fdi_tx_reg);
2136
2137 temp = I915_READ(fdi_rx_reg);
2138 if (HAS_PCH_CPT(dev)) {
2139 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2140 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2141 } else {
2142 temp &= ~FDI_LINK_TRAIN_NONE;
2143 temp |= FDI_LINK_TRAIN_PATTERN_1;
2144 }
2145 I915_WRITE(fdi_rx_reg, temp);
2146 POSTING_READ(fdi_rx_reg);
2147
2148 udelay(100);
2149
2150 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2151 temp = I915_READ(PCH_LVDS);
2152 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2153 I915_READ(PCH_LVDS);
2154 udelay(100);
2155 }
2156
2157 /* disable PCH transcoder */
2158 temp = I915_READ(transconf_reg);
2159 if ((temp & TRANS_ENABLE) != 0) {
2160 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2161
2162 /* wait for PCH transcoder off, transcoder state */
2163 if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50))
2164 DRM_ERROR("failed to disable transcoder\n");
2165 }
2166
2167 temp = I915_READ(transconf_reg);
2168 /* BPC in transcoder is consistent with that in pipeconf */
2169 temp &= ~PIPE_BPC_MASK;
2170 temp |= pipe_bpc;
2171 I915_WRITE(transconf_reg, temp);
2172 I915_READ(transconf_reg);
2173 udelay(100);
2174
2175 if (HAS_PCH_CPT(dev)) {
2176 /* disable TRANS_DP_CTL */
2177 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2178 int reg;
2179
2180 reg = I915_READ(trans_dp_ctl);
2181 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2182 I915_WRITE(trans_dp_ctl, reg);
2183 POSTING_READ(trans_dp_ctl);
2184
2185 /* disable DPLL_SEL */
2186 temp = I915_READ(PCH_DPLL_SEL);
2187 if (trans_dpll_sel == 0)
2188 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2189 else
2190 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2191 I915_WRITE(PCH_DPLL_SEL, temp);
2192 I915_READ(PCH_DPLL_SEL);
2193
2194 }
2195
2196 /* disable PCH DPLL */
2197 temp = I915_READ(pch_dpll_reg);
2198 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2199 I915_READ(pch_dpll_reg);
2200
2201 /* Switch from PCDclk to Rawclk */
2202 temp = I915_READ(fdi_rx_reg);
2203 temp &= ~FDI_SEL_PCDCLK;
2204 I915_WRITE(fdi_rx_reg, temp);
2205 I915_READ(fdi_rx_reg);
2206
2207 /* Disable CPU FDI TX PLL */
2208 temp = I915_READ(fdi_tx_reg);
2209 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2210 I915_READ(fdi_tx_reg);
2211 udelay(100);
2212
2213 temp = I915_READ(fdi_rx_reg);
2214 temp &= ~FDI_RX_PLL_ENABLE;
2215 I915_WRITE(fdi_rx_reg, temp);
2216 I915_READ(fdi_rx_reg);
2217
2218 /* Wait for the clocks to turn off. */
2219 udelay(100);
2220 break;
2221 }
2222 }
2223
2224 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2225 {
2226 if (!enable && intel_crtc->overlay) {
2227 struct drm_device *dev = intel_crtc->base.dev;
2228
2229 mutex_lock(&dev->struct_mutex);
2230 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2231 mutex_unlock(&dev->struct_mutex);
2232 }
2233
2234 /* Let userspace switch the overlay on again. In most cases userspace
2235 * has to recompute where to put it anyway.
2236 */
2237 }
2238
2239 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2240 {
2241 struct drm_device *dev = crtc->dev;
2242 struct drm_i915_private *dev_priv = dev->dev_private;
2243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2244 int pipe = intel_crtc->pipe;
2245 int plane = intel_crtc->plane;
2246 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2247 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2248 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2249 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2250 u32 temp;
2251
2252 /* XXX: When our outputs are all unaware of DPMS modes other than off
2253 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2254 */
2255 switch (mode) {
2256 case DRM_MODE_DPMS_ON:
2257 case DRM_MODE_DPMS_STANDBY:
2258 case DRM_MODE_DPMS_SUSPEND:
2259 /* Enable the DPLL */
2260 temp = I915_READ(dpll_reg);
2261 if ((temp & DPLL_VCO_ENABLE) == 0) {
2262 I915_WRITE(dpll_reg, temp);
2263 I915_READ(dpll_reg);
2264 /* Wait for the clocks to stabilize. */
2265 udelay(150);
2266 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2267 I915_READ(dpll_reg);
2268 /* Wait for the clocks to stabilize. */
2269 udelay(150);
2270 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2271 I915_READ(dpll_reg);
2272 /* Wait for the clocks to stabilize. */
2273 udelay(150);
2274 }
2275
2276 /* Enable the pipe */
2277 temp = I915_READ(pipeconf_reg);
2278 if ((temp & PIPEACONF_ENABLE) == 0)
2279 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2280
2281 /* Enable the plane */
2282 temp = I915_READ(dspcntr_reg);
2283 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2284 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2285 /* Flush the plane changes */
2286 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2287 }
2288
2289 intel_crtc_load_lut(crtc);
2290
2291 if ((IS_I965G(dev) || plane == 0))
2292 intel_update_fbc(crtc, &crtc->mode);
2293
2294 /* Give the overlay scaler a chance to enable if it's on this pipe */
2295 intel_crtc_dpms_overlay(intel_crtc, true);
2296 break;
2297 case DRM_MODE_DPMS_OFF:
2298 /* Give the overlay scaler a chance to disable if it's on this pipe */
2299 intel_crtc_dpms_overlay(intel_crtc, false);
2300 drm_vblank_off(dev, pipe);
2301
2302 if (dev_priv->cfb_plane == plane &&
2303 dev_priv->display.disable_fbc)
2304 dev_priv->display.disable_fbc(dev);
2305
2306 /* Disable display plane */
2307 temp = I915_READ(dspcntr_reg);
2308 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2309 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2310 /* Flush the plane changes */
2311 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2312 I915_READ(dspbase_reg);
2313 }
2314
2315 if (!IS_I9XX(dev)) {
2316 /* Wait for vblank for the disable to take effect */
2317 intel_wait_for_vblank_off(dev, pipe);
2318 }
2319
2320 /* Don't disable pipe A or pipe A PLLs if needed */
2321 if (pipeconf_reg == PIPEACONF &&
2322 (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2323 goto skip_pipe_off;
2324
2325 /* Next, disable display pipes */
2326 temp = I915_READ(pipeconf_reg);
2327 if ((temp & PIPEACONF_ENABLE) != 0) {
2328 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2329 I915_READ(pipeconf_reg);
2330 }
2331
2332 /* Wait for vblank for the disable to take effect. */
2333 intel_wait_for_vblank_off(dev, pipe);
2334
2335 temp = I915_READ(dpll_reg);
2336 if ((temp & DPLL_VCO_ENABLE) != 0) {
2337 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2338 I915_READ(dpll_reg);
2339 }
2340 skip_pipe_off:
2341 /* Wait for the clocks to turn off. */
2342 udelay(150);
2343 break;
2344 }
2345 }
2346
2347 /*
2348 * When we disable a pipe, we need to clear any pending scanline wait events
2349 * to avoid hanging the ring, which we assume we are waiting on.
2350 */
2351 static void intel_clear_scanline_wait(struct drm_device *dev)
2352 {
2353 struct drm_i915_private *dev_priv = dev->dev_private;
2354 u32 tmp;
2355
2356 if (IS_GEN2(dev))
2357 /* Can't break the hang on i8xx */
2358 return;
2359
2360 tmp = I915_READ(PRB0_CTL);
2361 if (tmp & RING_WAIT) {
2362 I915_WRITE(PRB0_CTL, tmp);
2363 POSTING_READ(PRB0_CTL);
2364 }
2365 }
2366
2367 /**
2368 * Sets the power management mode of the pipe and plane.
2369 */
2370 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2371 {
2372 struct drm_device *dev = crtc->dev;
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374 struct drm_i915_master_private *master_priv;
2375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2376 int pipe = intel_crtc->pipe;
2377 bool enabled;
2378
2379 if (intel_crtc->dpms_mode == mode)
2380 return;
2381
2382 intel_crtc->dpms_mode = mode;
2383 intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2384
2385 /* When switching on the display, ensure that SR is disabled
2386 * with multiple pipes prior to enabling to new pipe.
2387 *
2388 * When switching off the display, make sure the cursor is
2389 * properly hidden and there are no pending waits prior to
2390 * disabling the pipe.
2391 */
2392 if (mode == DRM_MODE_DPMS_ON)
2393 intel_update_watermarks(dev);
2394 else
2395 intel_crtc_update_cursor(crtc);
2396
2397 dev_priv->display.dpms(crtc, mode);
2398
2399 if (mode == DRM_MODE_DPMS_ON)
2400 intel_crtc_update_cursor(crtc);
2401 else {
2402 /* XXX Note that this is not a complete solution, but a hack
2403 * to avoid the most frequently hit hang.
2404 */
2405 intel_clear_scanline_wait(dev);
2406
2407 intel_update_watermarks(dev);
2408 }
2409
2410 if (!dev->primary->master)
2411 return;
2412
2413 master_priv = dev->primary->master->driver_priv;
2414 if (!master_priv->sarea_priv)
2415 return;
2416
2417 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2418
2419 switch (pipe) {
2420 case 0:
2421 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2422 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2423 break;
2424 case 1:
2425 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2426 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2427 break;
2428 default:
2429 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2430 break;
2431 }
2432 }
2433
2434 static void intel_crtc_prepare (struct drm_crtc *crtc)
2435 {
2436 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2437 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2438 }
2439
2440 static void intel_crtc_commit (struct drm_crtc *crtc)
2441 {
2442 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2443 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2444 }
2445
2446 void intel_encoder_prepare (struct drm_encoder *encoder)
2447 {
2448 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2449 /* lvds has its own version of prepare see intel_lvds_prepare */
2450 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2451 }
2452
2453 void intel_encoder_commit (struct drm_encoder *encoder)
2454 {
2455 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2456 /* lvds has its own version of commit see intel_lvds_commit */
2457 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2458 }
2459
2460 void intel_encoder_destroy(struct drm_encoder *encoder)
2461 {
2462 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2463
2464 if (intel_encoder->ddc_bus)
2465 intel_i2c_destroy(intel_encoder->ddc_bus);
2466
2467 if (intel_encoder->i2c_bus)
2468 intel_i2c_destroy(intel_encoder->i2c_bus);
2469
2470 drm_encoder_cleanup(encoder);
2471 kfree(intel_encoder);
2472 }
2473
2474 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2475 struct drm_display_mode *mode,
2476 struct drm_display_mode *adjusted_mode)
2477 {
2478 struct drm_device *dev = crtc->dev;
2479 if (HAS_PCH_SPLIT(dev)) {
2480 /* FDI link clock is fixed at 2.7G */
2481 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2482 return false;
2483 }
2484 return true;
2485 }
2486
2487 static int i945_get_display_clock_speed(struct drm_device *dev)
2488 {
2489 return 400000;
2490 }
2491
2492 static int i915_get_display_clock_speed(struct drm_device *dev)
2493 {
2494 return 333000;
2495 }
2496
2497 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2498 {
2499 return 200000;
2500 }
2501
2502 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2503 {
2504 u16 gcfgc = 0;
2505
2506 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2507
2508 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2509 return 133000;
2510 else {
2511 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2512 case GC_DISPLAY_CLOCK_333_MHZ:
2513 return 333000;
2514 default:
2515 case GC_DISPLAY_CLOCK_190_200_MHZ:
2516 return 190000;
2517 }
2518 }
2519 }
2520
2521 static int i865_get_display_clock_speed(struct drm_device *dev)
2522 {
2523 return 266000;
2524 }
2525
2526 static int i855_get_display_clock_speed(struct drm_device *dev)
2527 {
2528 u16 hpllcc = 0;
2529 /* Assume that the hardware is in the high speed state. This
2530 * should be the default.
2531 */
2532 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2533 case GC_CLOCK_133_200:
2534 case GC_CLOCK_100_200:
2535 return 200000;
2536 case GC_CLOCK_166_250:
2537 return 250000;
2538 case GC_CLOCK_100_133:
2539 return 133000;
2540 }
2541
2542 /* Shouldn't happen */
2543 return 0;
2544 }
2545
2546 static int i830_get_display_clock_speed(struct drm_device *dev)
2547 {
2548 return 133000;
2549 }
2550
2551 /**
2552 * Return the pipe currently connected to the panel fitter,
2553 * or -1 if the panel fitter is not present or not in use
2554 */
2555 int intel_panel_fitter_pipe (struct drm_device *dev)
2556 {
2557 struct drm_i915_private *dev_priv = dev->dev_private;
2558 u32 pfit_control;
2559
2560 /* i830 doesn't have a panel fitter */
2561 if (IS_I830(dev))
2562 return -1;
2563
2564 pfit_control = I915_READ(PFIT_CONTROL);
2565
2566 /* See if the panel fitter is in use */
2567 if ((pfit_control & PFIT_ENABLE) == 0)
2568 return -1;
2569
2570 /* 965 can place panel fitter on either pipe */
2571 if (IS_I965G(dev))
2572 return (pfit_control >> 29) & 0x3;
2573
2574 /* older chips can only use pipe 1 */
2575 return 1;
2576 }
2577
2578 struct fdi_m_n {
2579 u32 tu;
2580 u32 gmch_m;
2581 u32 gmch_n;
2582 u32 link_m;
2583 u32 link_n;
2584 };
2585
2586 static void
2587 fdi_reduce_ratio(u32 *num, u32 *den)
2588 {
2589 while (*num > 0xffffff || *den > 0xffffff) {
2590 *num >>= 1;
2591 *den >>= 1;
2592 }
2593 }
2594
2595 #define DATA_N 0x800000
2596 #define LINK_N 0x80000
2597
2598 static void
2599 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2600 int link_clock, struct fdi_m_n *m_n)
2601 {
2602 u64 temp;
2603
2604 m_n->tu = 64; /* default size */
2605
2606 temp = (u64) DATA_N * pixel_clock;
2607 temp = div_u64(temp, link_clock);
2608 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2609 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2610 m_n->gmch_n = DATA_N;
2611 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2612
2613 temp = (u64) LINK_N * pixel_clock;
2614 m_n->link_m = div_u64(temp, link_clock);
2615 m_n->link_n = LINK_N;
2616 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2617 }
2618
2619
2620 struct intel_watermark_params {
2621 unsigned long fifo_size;
2622 unsigned long max_wm;
2623 unsigned long default_wm;
2624 unsigned long guard_size;
2625 unsigned long cacheline_size;
2626 };
2627
2628 /* Pineview has different values for various configs */
2629 static struct intel_watermark_params pineview_display_wm = {
2630 PINEVIEW_DISPLAY_FIFO,
2631 PINEVIEW_MAX_WM,
2632 PINEVIEW_DFT_WM,
2633 PINEVIEW_GUARD_WM,
2634 PINEVIEW_FIFO_LINE_SIZE
2635 };
2636 static struct intel_watermark_params pineview_display_hplloff_wm = {
2637 PINEVIEW_DISPLAY_FIFO,
2638 PINEVIEW_MAX_WM,
2639 PINEVIEW_DFT_HPLLOFF_WM,
2640 PINEVIEW_GUARD_WM,
2641 PINEVIEW_FIFO_LINE_SIZE
2642 };
2643 static struct intel_watermark_params pineview_cursor_wm = {
2644 PINEVIEW_CURSOR_FIFO,
2645 PINEVIEW_CURSOR_MAX_WM,
2646 PINEVIEW_CURSOR_DFT_WM,
2647 PINEVIEW_CURSOR_GUARD_WM,
2648 PINEVIEW_FIFO_LINE_SIZE,
2649 };
2650 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2651 PINEVIEW_CURSOR_FIFO,
2652 PINEVIEW_CURSOR_MAX_WM,
2653 PINEVIEW_CURSOR_DFT_WM,
2654 PINEVIEW_CURSOR_GUARD_WM,
2655 PINEVIEW_FIFO_LINE_SIZE
2656 };
2657 static struct intel_watermark_params g4x_wm_info = {
2658 G4X_FIFO_SIZE,
2659 G4X_MAX_WM,
2660 G4X_MAX_WM,
2661 2,
2662 G4X_FIFO_LINE_SIZE,
2663 };
2664 static struct intel_watermark_params g4x_cursor_wm_info = {
2665 I965_CURSOR_FIFO,
2666 I965_CURSOR_MAX_WM,
2667 I965_CURSOR_DFT_WM,
2668 2,
2669 G4X_FIFO_LINE_SIZE,
2670 };
2671 static struct intel_watermark_params i965_cursor_wm_info = {
2672 I965_CURSOR_FIFO,
2673 I965_CURSOR_MAX_WM,
2674 I965_CURSOR_DFT_WM,
2675 2,
2676 I915_FIFO_LINE_SIZE,
2677 };
2678 static struct intel_watermark_params i945_wm_info = {
2679 I945_FIFO_SIZE,
2680 I915_MAX_WM,
2681 1,
2682 2,
2683 I915_FIFO_LINE_SIZE
2684 };
2685 static struct intel_watermark_params i915_wm_info = {
2686 I915_FIFO_SIZE,
2687 I915_MAX_WM,
2688 1,
2689 2,
2690 I915_FIFO_LINE_SIZE
2691 };
2692 static struct intel_watermark_params i855_wm_info = {
2693 I855GM_FIFO_SIZE,
2694 I915_MAX_WM,
2695 1,
2696 2,
2697 I830_FIFO_LINE_SIZE
2698 };
2699 static struct intel_watermark_params i830_wm_info = {
2700 I830_FIFO_SIZE,
2701 I915_MAX_WM,
2702 1,
2703 2,
2704 I830_FIFO_LINE_SIZE
2705 };
2706
2707 static struct intel_watermark_params ironlake_display_wm_info = {
2708 ILK_DISPLAY_FIFO,
2709 ILK_DISPLAY_MAXWM,
2710 ILK_DISPLAY_DFTWM,
2711 2,
2712 ILK_FIFO_LINE_SIZE
2713 };
2714
2715 static struct intel_watermark_params ironlake_cursor_wm_info = {
2716 ILK_CURSOR_FIFO,
2717 ILK_CURSOR_MAXWM,
2718 ILK_CURSOR_DFTWM,
2719 2,
2720 ILK_FIFO_LINE_SIZE
2721 };
2722
2723 static struct intel_watermark_params ironlake_display_srwm_info = {
2724 ILK_DISPLAY_SR_FIFO,
2725 ILK_DISPLAY_MAX_SRWM,
2726 ILK_DISPLAY_DFT_SRWM,
2727 2,
2728 ILK_FIFO_LINE_SIZE
2729 };
2730
2731 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2732 ILK_CURSOR_SR_FIFO,
2733 ILK_CURSOR_MAX_SRWM,
2734 ILK_CURSOR_DFT_SRWM,
2735 2,
2736 ILK_FIFO_LINE_SIZE
2737 };
2738
2739 /**
2740 * intel_calculate_wm - calculate watermark level
2741 * @clock_in_khz: pixel clock
2742 * @wm: chip FIFO params
2743 * @pixel_size: display pixel size
2744 * @latency_ns: memory latency for the platform
2745 *
2746 * Calculate the watermark level (the level at which the display plane will
2747 * start fetching from memory again). Each chip has a different display
2748 * FIFO size and allocation, so the caller needs to figure that out and pass
2749 * in the correct intel_watermark_params structure.
2750 *
2751 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2752 * on the pixel size. When it reaches the watermark level, it'll start
2753 * fetching FIFO line sized based chunks from memory until the FIFO fills
2754 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2755 * will occur, and a display engine hang could result.
2756 */
2757 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2758 struct intel_watermark_params *wm,
2759 int pixel_size,
2760 unsigned long latency_ns)
2761 {
2762 long entries_required, wm_size;
2763
2764 /*
2765 * Note: we need to make sure we don't overflow for various clock &
2766 * latency values.
2767 * clocks go from a few thousand to several hundred thousand.
2768 * latency is usually a few thousand
2769 */
2770 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2771 1000;
2772 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2773
2774 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2775
2776 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2777
2778 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2779
2780 /* Don't promote wm_size to unsigned... */
2781 if (wm_size > (long)wm->max_wm)
2782 wm_size = wm->max_wm;
2783 if (wm_size <= 0)
2784 wm_size = wm->default_wm;
2785 return wm_size;
2786 }
2787
2788 struct cxsr_latency {
2789 int is_desktop;
2790 int is_ddr3;
2791 unsigned long fsb_freq;
2792 unsigned long mem_freq;
2793 unsigned long display_sr;
2794 unsigned long display_hpll_disable;
2795 unsigned long cursor_sr;
2796 unsigned long cursor_hpll_disable;
2797 };
2798
2799 static const struct cxsr_latency cxsr_latency_table[] = {
2800 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2801 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2802 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2803 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2804 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2805
2806 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2807 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2808 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2809 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2810 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2811
2812 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2813 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2814 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2815 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2816 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2817
2818 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2819 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2820 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2821 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2822 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2823
2824 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2825 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2826 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2827 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2828 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2829
2830 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2831 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2832 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2833 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2834 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2835 };
2836
2837 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2838 int is_ddr3,
2839 int fsb,
2840 int mem)
2841 {
2842 const struct cxsr_latency *latency;
2843 int i;
2844
2845 if (fsb == 0 || mem == 0)
2846 return NULL;
2847
2848 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2849 latency = &cxsr_latency_table[i];
2850 if (is_desktop == latency->is_desktop &&
2851 is_ddr3 == latency->is_ddr3 &&
2852 fsb == latency->fsb_freq && mem == latency->mem_freq)
2853 return latency;
2854 }
2855
2856 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2857
2858 return NULL;
2859 }
2860
2861 static void pineview_disable_cxsr(struct drm_device *dev)
2862 {
2863 struct drm_i915_private *dev_priv = dev->dev_private;
2864
2865 /* deactivate cxsr */
2866 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2867 }
2868
2869 /*
2870 * Latency for FIFO fetches is dependent on several factors:
2871 * - memory configuration (speed, channels)
2872 * - chipset
2873 * - current MCH state
2874 * It can be fairly high in some situations, so here we assume a fairly
2875 * pessimal value. It's a tradeoff between extra memory fetches (if we
2876 * set this value too high, the FIFO will fetch frequently to stay full)
2877 * and power consumption (set it too low to save power and we might see
2878 * FIFO underruns and display "flicker").
2879 *
2880 * A value of 5us seems to be a good balance; safe for very low end
2881 * platforms but not overly aggressive on lower latency configs.
2882 */
2883 static const int latency_ns = 5000;
2884
2885 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2886 {
2887 struct drm_i915_private *dev_priv = dev->dev_private;
2888 uint32_t dsparb = I915_READ(DSPARB);
2889 int size;
2890
2891 size = dsparb & 0x7f;
2892 if (plane)
2893 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2894
2895 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2896 plane ? "B" : "A", size);
2897
2898 return size;
2899 }
2900
2901 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2902 {
2903 struct drm_i915_private *dev_priv = dev->dev_private;
2904 uint32_t dsparb = I915_READ(DSPARB);
2905 int size;
2906
2907 size = dsparb & 0x1ff;
2908 if (plane)
2909 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2910 size >>= 1; /* Convert to cachelines */
2911
2912 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2913 plane ? "B" : "A", size);
2914
2915 return size;
2916 }
2917
2918 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2919 {
2920 struct drm_i915_private *dev_priv = dev->dev_private;
2921 uint32_t dsparb = I915_READ(DSPARB);
2922 int size;
2923
2924 size = dsparb & 0x7f;
2925 size >>= 2; /* Convert to cachelines */
2926
2927 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2928 plane ? "B" : "A",
2929 size);
2930
2931 return size;
2932 }
2933
2934 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2935 {
2936 struct drm_i915_private *dev_priv = dev->dev_private;
2937 uint32_t dsparb = I915_READ(DSPARB);
2938 int size;
2939
2940 size = dsparb & 0x7f;
2941 size >>= 1; /* Convert to cachelines */
2942
2943 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2944 plane ? "B" : "A", size);
2945
2946 return size;
2947 }
2948
2949 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
2950 int planeb_clock, int sr_hdisplay, int unused,
2951 int pixel_size)
2952 {
2953 struct drm_i915_private *dev_priv = dev->dev_private;
2954 const struct cxsr_latency *latency;
2955 u32 reg;
2956 unsigned long wm;
2957 int sr_clock;
2958
2959 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2960 dev_priv->fsb_freq, dev_priv->mem_freq);
2961 if (!latency) {
2962 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2963 pineview_disable_cxsr(dev);
2964 return;
2965 }
2966
2967 if (!planea_clock || !planeb_clock) {
2968 sr_clock = planea_clock ? planea_clock : planeb_clock;
2969
2970 /* Display SR */
2971 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2972 pixel_size, latency->display_sr);
2973 reg = I915_READ(DSPFW1);
2974 reg &= ~DSPFW_SR_MASK;
2975 reg |= wm << DSPFW_SR_SHIFT;
2976 I915_WRITE(DSPFW1, reg);
2977 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2978
2979 /* cursor SR */
2980 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2981 pixel_size, latency->cursor_sr);
2982 reg = I915_READ(DSPFW3);
2983 reg &= ~DSPFW_CURSOR_SR_MASK;
2984 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2985 I915_WRITE(DSPFW3, reg);
2986
2987 /* Display HPLL off SR */
2988 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2989 pixel_size, latency->display_hpll_disable);
2990 reg = I915_READ(DSPFW3);
2991 reg &= ~DSPFW_HPLL_SR_MASK;
2992 reg |= wm & DSPFW_HPLL_SR_MASK;
2993 I915_WRITE(DSPFW3, reg);
2994
2995 /* cursor HPLL off SR */
2996 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2997 pixel_size, latency->cursor_hpll_disable);
2998 reg = I915_READ(DSPFW3);
2999 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3000 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3001 I915_WRITE(DSPFW3, reg);
3002 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3003
3004 /* activate cxsr */
3005 I915_WRITE(DSPFW3,
3006 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3007 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3008 } else {
3009 pineview_disable_cxsr(dev);
3010 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3011 }
3012 }
3013
3014 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3015 int planeb_clock, int sr_hdisplay, int sr_htotal,
3016 int pixel_size)
3017 {
3018 struct drm_i915_private *dev_priv = dev->dev_private;
3019 int total_size, cacheline_size;
3020 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3021 struct intel_watermark_params planea_params, planeb_params;
3022 unsigned long line_time_us;
3023 int sr_clock, sr_entries = 0, entries_required;
3024
3025 /* Create copies of the base settings for each pipe */
3026 planea_params = planeb_params = g4x_wm_info;
3027
3028 /* Grab a couple of global values before we overwrite them */
3029 total_size = planea_params.fifo_size;
3030 cacheline_size = planea_params.cacheline_size;
3031
3032 /*
3033 * Note: we need to make sure we don't overflow for various clock &
3034 * latency values.
3035 * clocks go from a few thousand to several hundred thousand.
3036 * latency is usually a few thousand
3037 */
3038 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3039 1000;
3040 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3041 planea_wm = entries_required + planea_params.guard_size;
3042
3043 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3044 1000;
3045 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3046 planeb_wm = entries_required + planeb_params.guard_size;
3047
3048 cursora_wm = cursorb_wm = 16;
3049 cursor_sr = 32;
3050
3051 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3052
3053 /* Calc sr entries for one plane configs */
3054 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3055 /* self-refresh has much higher latency */
3056 static const int sr_latency_ns = 12000;
3057
3058 sr_clock = planea_clock ? planea_clock : planeb_clock;
3059 line_time_us = ((sr_htotal * 1000) / sr_clock);
3060
3061 /* Use ns/us then divide to preserve precision */
3062 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3063 pixel_size * sr_hdisplay;
3064 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3065
3066 entries_required = (((sr_latency_ns / line_time_us) +
3067 1000) / 1000) * pixel_size * 64;
3068 entries_required = DIV_ROUND_UP(entries_required,
3069 g4x_cursor_wm_info.cacheline_size);
3070 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3071
3072 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3073 cursor_sr = g4x_cursor_wm_info.max_wm;
3074 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3075 "cursor %d\n", sr_entries, cursor_sr);
3076
3077 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3078 } else {
3079 /* Turn off self refresh if both pipes are enabled */
3080 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3081 & ~FW_BLC_SELF_EN);
3082 }
3083
3084 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3085 planea_wm, planeb_wm, sr_entries);
3086
3087 planea_wm &= 0x3f;
3088 planeb_wm &= 0x3f;
3089
3090 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3091 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3092 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3093 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3094 (cursora_wm << DSPFW_CURSORA_SHIFT));
3095 /* HPLL off in SR has some issues on G4x... disable it */
3096 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3097 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3098 }
3099
3100 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3101 int planeb_clock, int sr_hdisplay, int sr_htotal,
3102 int pixel_size)
3103 {
3104 struct drm_i915_private *dev_priv = dev->dev_private;
3105 unsigned long line_time_us;
3106 int sr_clock, sr_entries, srwm = 1;
3107 int cursor_sr = 16;
3108
3109 /* Calc sr entries for one plane configs */
3110 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3111 /* self-refresh has much higher latency */
3112 static const int sr_latency_ns = 12000;
3113
3114 sr_clock = planea_clock ? planea_clock : planeb_clock;
3115 line_time_us = ((sr_htotal * 1000) / sr_clock);
3116
3117 /* Use ns/us then divide to preserve precision */
3118 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3119 pixel_size * sr_hdisplay;
3120 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3121 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3122 srwm = I965_FIFO_SIZE - sr_entries;
3123 if (srwm < 0)
3124 srwm = 1;
3125 srwm &= 0x1ff;
3126
3127 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3128 pixel_size * 64;
3129 sr_entries = DIV_ROUND_UP(sr_entries,
3130 i965_cursor_wm_info.cacheline_size);
3131 cursor_sr = i965_cursor_wm_info.fifo_size -
3132 (sr_entries + i965_cursor_wm_info.guard_size);
3133
3134 if (cursor_sr > i965_cursor_wm_info.max_wm)
3135 cursor_sr = i965_cursor_wm_info.max_wm;
3136
3137 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3138 "cursor %d\n", srwm, cursor_sr);
3139
3140 if (IS_I965GM(dev))
3141 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3142 } else {
3143 /* Turn off self refresh if both pipes are enabled */
3144 if (IS_I965GM(dev))
3145 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3146 & ~FW_BLC_SELF_EN);
3147 }
3148
3149 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3150 srwm);
3151
3152 /* 965 has limitations... */
3153 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3154 (8 << 0));
3155 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3156 /* update cursor SR watermark */
3157 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3158 }
3159
3160 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3161 int planeb_clock, int sr_hdisplay, int sr_htotal,
3162 int pixel_size)
3163 {
3164 struct drm_i915_private *dev_priv = dev->dev_private;
3165 uint32_t fwater_lo;
3166 uint32_t fwater_hi;
3167 int total_size, cacheline_size, cwm, srwm = 1;
3168 int planea_wm, planeb_wm;
3169 struct intel_watermark_params planea_params, planeb_params;
3170 unsigned long line_time_us;
3171 int sr_clock, sr_entries = 0;
3172
3173 /* Create copies of the base settings for each pipe */
3174 if (IS_I965GM(dev) || IS_I945GM(dev))
3175 planea_params = planeb_params = i945_wm_info;
3176 else if (IS_I9XX(dev))
3177 planea_params = planeb_params = i915_wm_info;
3178 else
3179 planea_params = planeb_params = i855_wm_info;
3180
3181 /* Grab a couple of global values before we overwrite them */
3182 total_size = planea_params.fifo_size;
3183 cacheline_size = planea_params.cacheline_size;
3184
3185 /* Update per-plane FIFO sizes */
3186 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3187 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3188
3189 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3190 pixel_size, latency_ns);
3191 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3192 pixel_size, latency_ns);
3193 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3194
3195 /*
3196 * Overlay gets an aggressive default since video jitter is bad.
3197 */
3198 cwm = 2;
3199
3200 /* Calc sr entries for one plane configs */
3201 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3202 (!planea_clock || !planeb_clock)) {
3203 /* self-refresh has much higher latency */
3204 static const int sr_latency_ns = 6000;
3205
3206 sr_clock = planea_clock ? planea_clock : planeb_clock;
3207 line_time_us = ((sr_htotal * 1000) / sr_clock);
3208
3209 /* Use ns/us then divide to preserve precision */
3210 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3211 pixel_size * sr_hdisplay;
3212 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3213 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3214 srwm = total_size - sr_entries;
3215 if (srwm < 0)
3216 srwm = 1;
3217
3218 if (IS_I945G(dev) || IS_I945GM(dev))
3219 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3220 else if (IS_I915GM(dev)) {
3221 /* 915M has a smaller SRWM field */
3222 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3223 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3224 }
3225 } else {
3226 /* Turn off self refresh if both pipes are enabled */
3227 if (IS_I945G(dev) || IS_I945GM(dev)) {
3228 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3229 & ~FW_BLC_SELF_EN);
3230 } else if (IS_I915GM(dev)) {
3231 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3232 }
3233 }
3234
3235 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3236 planea_wm, planeb_wm, cwm, srwm);
3237
3238 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3239 fwater_hi = (cwm & 0x1f);
3240
3241 /* Set request length to 8 cachelines per fetch */
3242 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3243 fwater_hi = fwater_hi | (1 << 8);
3244
3245 I915_WRITE(FW_BLC, fwater_lo);
3246 I915_WRITE(FW_BLC2, fwater_hi);
3247 }
3248
3249 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3250 int unused2, int unused3, int pixel_size)
3251 {
3252 struct drm_i915_private *dev_priv = dev->dev_private;
3253 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3254 int planea_wm;
3255
3256 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3257
3258 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3259 pixel_size, latency_ns);
3260 fwater_lo |= (3<<8) | planea_wm;
3261
3262 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3263
3264 I915_WRITE(FW_BLC, fwater_lo);
3265 }
3266
3267 #define ILK_LP0_PLANE_LATENCY 700
3268 #define ILK_LP0_CURSOR_LATENCY 1300
3269
3270 static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3271 int planeb_clock, int sr_hdisplay, int sr_htotal,
3272 int pixel_size)
3273 {
3274 struct drm_i915_private *dev_priv = dev->dev_private;
3275 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3276 int sr_wm, cursor_wm;
3277 unsigned long line_time_us;
3278 int sr_clock, entries_required;
3279 u32 reg_value;
3280 int line_count;
3281 int planea_htotal = 0, planeb_htotal = 0;
3282 struct drm_crtc *crtc;
3283
3284 /* Need htotal for all active display plane */
3285 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3287 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3288 if (intel_crtc->plane == 0)
3289 planea_htotal = crtc->mode.htotal;
3290 else
3291 planeb_htotal = crtc->mode.htotal;
3292 }
3293 }
3294
3295 /* Calculate and update the watermark for plane A */
3296 if (planea_clock) {
3297 entries_required = ((planea_clock / 1000) * pixel_size *
3298 ILK_LP0_PLANE_LATENCY) / 1000;
3299 entries_required = DIV_ROUND_UP(entries_required,
3300 ironlake_display_wm_info.cacheline_size);
3301 planea_wm = entries_required +
3302 ironlake_display_wm_info.guard_size;
3303
3304 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3305 planea_wm = ironlake_display_wm_info.max_wm;
3306
3307 /* Use the large buffer method to calculate cursor watermark */
3308 line_time_us = (planea_htotal * 1000) / planea_clock;
3309
3310 /* Use ns/us then divide to preserve precision */
3311 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3312
3313 /* calculate the cursor watermark for cursor A */
3314 entries_required = line_count * 64 * pixel_size;
3315 entries_required = DIV_ROUND_UP(entries_required,
3316 ironlake_cursor_wm_info.cacheline_size);
3317 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3318 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3319 cursora_wm = ironlake_cursor_wm_info.max_wm;
3320
3321 reg_value = I915_READ(WM0_PIPEA_ILK);
3322 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3323 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3324 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3325 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3326 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3327 "cursor: %d\n", planea_wm, cursora_wm);
3328 }
3329 /* Calculate and update the watermark for plane B */
3330 if (planeb_clock) {
3331 entries_required = ((planeb_clock / 1000) * pixel_size *
3332 ILK_LP0_PLANE_LATENCY) / 1000;
3333 entries_required = DIV_ROUND_UP(entries_required,
3334 ironlake_display_wm_info.cacheline_size);
3335 planeb_wm = entries_required +
3336 ironlake_display_wm_info.guard_size;
3337
3338 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3339 planeb_wm = ironlake_display_wm_info.max_wm;
3340
3341 /* Use the large buffer method to calculate cursor watermark */
3342 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3343
3344 /* Use ns/us then divide to preserve precision */
3345 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3346
3347 /* calculate the cursor watermark for cursor B */
3348 entries_required = line_count * 64 * pixel_size;
3349 entries_required = DIV_ROUND_UP(entries_required,
3350 ironlake_cursor_wm_info.cacheline_size);
3351 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3352 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3353 cursorb_wm = ironlake_cursor_wm_info.max_wm;
3354
3355 reg_value = I915_READ(WM0_PIPEB_ILK);
3356 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3357 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3358 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3359 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3360 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3361 "cursor: %d\n", planeb_wm, cursorb_wm);
3362 }
3363
3364 /*
3365 * Calculate and update the self-refresh watermark only when one
3366 * display plane is used.
3367 */
3368 if (!planea_clock || !planeb_clock) {
3369
3370 /* Read the self-refresh latency. The unit is 0.5us */
3371 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3372
3373 sr_clock = planea_clock ? planea_clock : planeb_clock;
3374 line_time_us = ((sr_htotal * 1000) / sr_clock);
3375
3376 /* Use ns/us then divide to preserve precision */
3377 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3378 / 1000;
3379
3380 /* calculate the self-refresh watermark for display plane */
3381 entries_required = line_count * sr_hdisplay * pixel_size;
3382 entries_required = DIV_ROUND_UP(entries_required,
3383 ironlake_display_srwm_info.cacheline_size);
3384 sr_wm = entries_required +
3385 ironlake_display_srwm_info.guard_size;
3386
3387 /* calculate the self-refresh watermark for display cursor */
3388 entries_required = line_count * pixel_size * 64;
3389 entries_required = DIV_ROUND_UP(entries_required,
3390 ironlake_cursor_srwm_info.cacheline_size);
3391 cursor_wm = entries_required +
3392 ironlake_cursor_srwm_info.guard_size;
3393
3394 /* configure watermark and enable self-refresh */
3395 reg_value = I915_READ(WM1_LP_ILK);
3396 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3397 WM1_LP_CURSOR_MASK);
3398 reg_value |= WM1_LP_SR_EN |
3399 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3400 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3401
3402 I915_WRITE(WM1_LP_ILK, reg_value);
3403 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3404 "cursor %d\n", sr_wm, cursor_wm);
3405
3406 } else {
3407 /* Turn off self refresh if both pipes are enabled */
3408 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3409 }
3410 }
3411 /**
3412 * intel_update_watermarks - update FIFO watermark values based on current modes
3413 *
3414 * Calculate watermark values for the various WM regs based on current mode
3415 * and plane configuration.
3416 *
3417 * There are several cases to deal with here:
3418 * - normal (i.e. non-self-refresh)
3419 * - self-refresh (SR) mode
3420 * - lines are large relative to FIFO size (buffer can hold up to 2)
3421 * - lines are small relative to FIFO size (buffer can hold more than 2
3422 * lines), so need to account for TLB latency
3423 *
3424 * The normal calculation is:
3425 * watermark = dotclock * bytes per pixel * latency
3426 * where latency is platform & configuration dependent (we assume pessimal
3427 * values here).
3428 *
3429 * The SR calculation is:
3430 * watermark = (trunc(latency/line time)+1) * surface width *
3431 * bytes per pixel
3432 * where
3433 * line time = htotal / dotclock
3434 * surface width = hdisplay for normal plane and 64 for cursor
3435 * and latency is assumed to be high, as above.
3436 *
3437 * The final value programmed to the register should always be rounded up,
3438 * and include an extra 2 entries to account for clock crossings.
3439 *
3440 * We don't use the sprite, so we can ignore that. And on Crestline we have
3441 * to set the non-SR watermarks to 8.
3442 */
3443 static void intel_update_watermarks(struct drm_device *dev)
3444 {
3445 struct drm_i915_private *dev_priv = dev->dev_private;
3446 struct drm_crtc *crtc;
3447 int sr_hdisplay = 0;
3448 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3449 int enabled = 0, pixel_size = 0;
3450 int sr_htotal = 0;
3451
3452 if (!dev_priv->display.update_wm)
3453 return;
3454
3455 /* Get the clock config from both planes */
3456 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3458 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3459 enabled++;
3460 if (intel_crtc->plane == 0) {
3461 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3462 intel_crtc->pipe, crtc->mode.clock);
3463 planea_clock = crtc->mode.clock;
3464 } else {
3465 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3466 intel_crtc->pipe, crtc->mode.clock);
3467 planeb_clock = crtc->mode.clock;
3468 }
3469 sr_hdisplay = crtc->mode.hdisplay;
3470 sr_clock = crtc->mode.clock;
3471 sr_htotal = crtc->mode.htotal;
3472 if (crtc->fb)
3473 pixel_size = crtc->fb->bits_per_pixel / 8;
3474 else
3475 pixel_size = 4; /* by default */
3476 }
3477 }
3478
3479 if (enabled <= 0)
3480 return;
3481
3482 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3483 sr_hdisplay, sr_htotal, pixel_size);
3484 }
3485
3486 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3487 struct drm_display_mode *mode,
3488 struct drm_display_mode *adjusted_mode,
3489 int x, int y,
3490 struct drm_framebuffer *old_fb)
3491 {
3492 struct drm_device *dev = crtc->dev;
3493 struct drm_i915_private *dev_priv = dev->dev_private;
3494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3495 int pipe = intel_crtc->pipe;
3496 int plane = intel_crtc->plane;
3497 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3498 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3499 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3500 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3501 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3502 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3503 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3504 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3505 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3506 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3507 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3508 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3509 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3510 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3511 int refclk, num_connectors = 0;
3512 intel_clock_t clock, reduced_clock;
3513 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3514 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3515 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3516 struct intel_encoder *has_edp_encoder = NULL;
3517 struct drm_mode_config *mode_config = &dev->mode_config;
3518 struct drm_encoder *encoder;
3519 const intel_limit_t *limit;
3520 int ret;
3521 struct fdi_m_n m_n = {0};
3522 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3523 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3524 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3525 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3526 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3527 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3528 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3529 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3530 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3531 int lvds_reg = LVDS;
3532 u32 temp;
3533 int target_clock;
3534
3535 drm_vblank_pre_modeset(dev, pipe);
3536
3537 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3538 struct intel_encoder *intel_encoder;
3539
3540 if (encoder->crtc != crtc)
3541 continue;
3542
3543 intel_encoder = enc_to_intel_encoder(encoder);
3544 switch (intel_encoder->type) {
3545 case INTEL_OUTPUT_LVDS:
3546 is_lvds = true;
3547 break;
3548 case INTEL_OUTPUT_SDVO:
3549 case INTEL_OUTPUT_HDMI:
3550 is_sdvo = true;
3551 if (intel_encoder->needs_tv_clock)
3552 is_tv = true;
3553 break;
3554 case INTEL_OUTPUT_DVO:
3555 is_dvo = true;
3556 break;
3557 case INTEL_OUTPUT_TVOUT:
3558 is_tv = true;
3559 break;
3560 case INTEL_OUTPUT_ANALOG:
3561 is_crt = true;
3562 break;
3563 case INTEL_OUTPUT_DISPLAYPORT:
3564 is_dp = true;
3565 break;
3566 case INTEL_OUTPUT_EDP:
3567 has_edp_encoder = intel_encoder;
3568 break;
3569 }
3570
3571 num_connectors++;
3572 }
3573
3574 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3575 refclk = dev_priv->lvds_ssc_freq * 1000;
3576 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3577 refclk / 1000);
3578 } else if (IS_I9XX(dev)) {
3579 refclk = 96000;
3580 if (HAS_PCH_SPLIT(dev))
3581 refclk = 120000; /* 120Mhz refclk */
3582 } else {
3583 refclk = 48000;
3584 }
3585
3586
3587 /*
3588 * Returns a set of divisors for the desired target clock with the given
3589 * refclk, or FALSE. The returned values represent the clock equation:
3590 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3591 */
3592 limit = intel_limit(crtc);
3593 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3594 if (!ok) {
3595 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3596 drm_vblank_post_modeset(dev, pipe);
3597 return -EINVAL;
3598 }
3599
3600 /* Ensure that the cursor is valid for the new mode before changing... */
3601 intel_crtc_update_cursor(crtc);
3602
3603 if (is_lvds && dev_priv->lvds_downclock_avail) {
3604 has_reduced_clock = limit->find_pll(limit, crtc,
3605 dev_priv->lvds_downclock,
3606 refclk,
3607 &reduced_clock);
3608 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3609 /*
3610 * If the different P is found, it means that we can't
3611 * switch the display clock by using the FP0/FP1.
3612 * In such case we will disable the LVDS downclock
3613 * feature.
3614 */
3615 DRM_DEBUG_KMS("Different P is found for "
3616 "LVDS clock/downclock\n");
3617 has_reduced_clock = 0;
3618 }
3619 }
3620 /* SDVO TV has fixed PLL values depend on its clock range,
3621 this mirrors vbios setting. */
3622 if (is_sdvo && is_tv) {
3623 if (adjusted_mode->clock >= 100000
3624 && adjusted_mode->clock < 140500) {
3625 clock.p1 = 2;
3626 clock.p2 = 10;
3627 clock.n = 3;
3628 clock.m1 = 16;
3629 clock.m2 = 8;
3630 } else if (adjusted_mode->clock >= 140500
3631 && adjusted_mode->clock <= 200000) {
3632 clock.p1 = 1;
3633 clock.p2 = 10;
3634 clock.n = 6;
3635 clock.m1 = 12;
3636 clock.m2 = 8;
3637 }
3638 }
3639
3640 /* FDI link */
3641 if (HAS_PCH_SPLIT(dev)) {
3642 int lane = 0, link_bw, bpp;
3643 /* eDP doesn't require FDI link, so just set DP M/N
3644 according to current link config */
3645 if (has_edp_encoder) {
3646 target_clock = mode->clock;
3647 intel_edp_link_config(has_edp_encoder,
3648 &lane, &link_bw);
3649 } else {
3650 /* DP over FDI requires target mode clock
3651 instead of link clock */
3652 if (is_dp)
3653 target_clock = mode->clock;
3654 else
3655 target_clock = adjusted_mode->clock;
3656 link_bw = 270000;
3657 }
3658
3659 /* determine panel color depth */
3660 temp = I915_READ(pipeconf_reg);
3661 temp &= ~PIPE_BPC_MASK;
3662 if (is_lvds) {
3663 int lvds_reg = I915_READ(PCH_LVDS);
3664 /* the BPC will be 6 if it is 18-bit LVDS panel */
3665 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3666 temp |= PIPE_8BPC;
3667 else
3668 temp |= PIPE_6BPC;
3669 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3670 switch (dev_priv->edp_bpp/3) {
3671 case 8:
3672 temp |= PIPE_8BPC;
3673 break;
3674 case 10:
3675 temp |= PIPE_10BPC;
3676 break;
3677 case 6:
3678 temp |= PIPE_6BPC;
3679 break;
3680 case 12:
3681 temp |= PIPE_12BPC;
3682 break;
3683 }
3684 } else
3685 temp |= PIPE_8BPC;
3686 I915_WRITE(pipeconf_reg, temp);
3687 I915_READ(pipeconf_reg);
3688
3689 switch (temp & PIPE_BPC_MASK) {
3690 case PIPE_8BPC:
3691 bpp = 24;
3692 break;
3693 case PIPE_10BPC:
3694 bpp = 30;
3695 break;
3696 case PIPE_6BPC:
3697 bpp = 18;
3698 break;
3699 case PIPE_12BPC:
3700 bpp = 36;
3701 break;
3702 default:
3703 DRM_ERROR("unknown pipe bpc value\n");
3704 bpp = 24;
3705 }
3706
3707 if (!lane) {
3708 /*
3709 * Account for spread spectrum to avoid
3710 * oversubscribing the link. Max center spread
3711 * is 2.5%; use 5% for safety's sake.
3712 */
3713 u32 bps = target_clock * bpp * 21 / 20;
3714 lane = bps / (link_bw * 8) + 1;
3715 }
3716
3717 intel_crtc->fdi_lanes = lane;
3718
3719 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3720 }
3721
3722 /* Ironlake: try to setup display ref clock before DPLL
3723 * enabling. This is only under driver's control after
3724 * PCH B stepping, previous chipset stepping should be
3725 * ignoring this setting.
3726 */
3727 if (HAS_PCH_SPLIT(dev)) {
3728 temp = I915_READ(PCH_DREF_CONTROL);
3729 /* Always enable nonspread source */
3730 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3731 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3732 I915_WRITE(PCH_DREF_CONTROL, temp);
3733 POSTING_READ(PCH_DREF_CONTROL);
3734
3735 temp &= ~DREF_SSC_SOURCE_MASK;
3736 temp |= DREF_SSC_SOURCE_ENABLE;
3737 I915_WRITE(PCH_DREF_CONTROL, temp);
3738 POSTING_READ(PCH_DREF_CONTROL);
3739
3740 udelay(200);
3741
3742 if (has_edp_encoder) {
3743 if (dev_priv->lvds_use_ssc) {
3744 temp |= DREF_SSC1_ENABLE;
3745 I915_WRITE(PCH_DREF_CONTROL, temp);
3746 POSTING_READ(PCH_DREF_CONTROL);
3747
3748 udelay(200);
3749
3750 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3751 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3752 I915_WRITE(PCH_DREF_CONTROL, temp);
3753 POSTING_READ(PCH_DREF_CONTROL);
3754 } else {
3755 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3756 I915_WRITE(PCH_DREF_CONTROL, temp);
3757 POSTING_READ(PCH_DREF_CONTROL);
3758 }
3759 }
3760 }
3761
3762 if (IS_PINEVIEW(dev)) {
3763 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3764 if (has_reduced_clock)
3765 fp2 = (1 << reduced_clock.n) << 16 |
3766 reduced_clock.m1 << 8 | reduced_clock.m2;
3767 } else {
3768 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3769 if (has_reduced_clock)
3770 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3771 reduced_clock.m2;
3772 }
3773
3774 if (!HAS_PCH_SPLIT(dev))
3775 dpll = DPLL_VGA_MODE_DIS;
3776
3777 if (IS_I9XX(dev)) {
3778 if (is_lvds)
3779 dpll |= DPLLB_MODE_LVDS;
3780 else
3781 dpll |= DPLLB_MODE_DAC_SERIAL;
3782 if (is_sdvo) {
3783 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3784 if (pixel_multiplier > 1) {
3785 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3786 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3787 else if (HAS_PCH_SPLIT(dev))
3788 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3789 }
3790 dpll |= DPLL_DVO_HIGH_SPEED;
3791 }
3792 if (is_dp)
3793 dpll |= DPLL_DVO_HIGH_SPEED;
3794
3795 /* compute bitmask from p1 value */
3796 if (IS_PINEVIEW(dev))
3797 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3798 else {
3799 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3800 /* also FPA1 */
3801 if (HAS_PCH_SPLIT(dev))
3802 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3803 if (IS_G4X(dev) && has_reduced_clock)
3804 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3805 }
3806 switch (clock.p2) {
3807 case 5:
3808 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3809 break;
3810 case 7:
3811 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3812 break;
3813 case 10:
3814 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3815 break;
3816 case 14:
3817 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3818 break;
3819 }
3820 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3821 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3822 } else {
3823 if (is_lvds) {
3824 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3825 } else {
3826 if (clock.p1 == 2)
3827 dpll |= PLL_P1_DIVIDE_BY_TWO;
3828 else
3829 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3830 if (clock.p2 == 4)
3831 dpll |= PLL_P2_DIVIDE_BY_4;
3832 }
3833 }
3834
3835 if (is_sdvo && is_tv)
3836 dpll |= PLL_REF_INPUT_TVCLKINBC;
3837 else if (is_tv)
3838 /* XXX: just matching BIOS for now */
3839 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3840 dpll |= 3;
3841 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3842 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3843 else
3844 dpll |= PLL_REF_INPUT_DREFCLK;
3845
3846 /* setup pipeconf */
3847 pipeconf = I915_READ(pipeconf_reg);
3848
3849 /* Set up the display plane register */
3850 dspcntr = DISPPLANE_GAMMA_ENABLE;
3851
3852 /* Ironlake's plane is forced to pipe, bit 24 is to
3853 enable color space conversion */
3854 if (!HAS_PCH_SPLIT(dev)) {
3855 if (pipe == 0)
3856 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3857 else
3858 dspcntr |= DISPPLANE_SEL_PIPE_B;
3859 }
3860
3861 if (pipe == 0 && !IS_I965G(dev)) {
3862 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3863 * core speed.
3864 *
3865 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3866 * pipe == 0 check?
3867 */
3868 if (mode->clock >
3869 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3870 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3871 else
3872 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3873 }
3874
3875 dspcntr |= DISPLAY_PLANE_ENABLE;
3876 pipeconf |= PIPEACONF_ENABLE;
3877 dpll |= DPLL_VCO_ENABLE;
3878
3879
3880 /* Disable the panel fitter if it was on our pipe */
3881 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3882 I915_WRITE(PFIT_CONTROL, 0);
3883
3884 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3885 drm_mode_debug_printmodeline(mode);
3886
3887 /* assign to Ironlake registers */
3888 if (HAS_PCH_SPLIT(dev)) {
3889 fp_reg = pch_fp_reg;
3890 dpll_reg = pch_dpll_reg;
3891 }
3892
3893 if (!has_edp_encoder) {
3894 I915_WRITE(fp_reg, fp);
3895 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3896 I915_READ(dpll_reg);
3897 udelay(150);
3898 }
3899
3900 /* enable transcoder DPLL */
3901 if (HAS_PCH_CPT(dev)) {
3902 temp = I915_READ(PCH_DPLL_SEL);
3903 if (trans_dpll_sel == 0)
3904 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3905 else
3906 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3907 I915_WRITE(PCH_DPLL_SEL, temp);
3908 I915_READ(PCH_DPLL_SEL);
3909 udelay(150);
3910 }
3911
3912 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3913 * This is an exception to the general rule that mode_set doesn't turn
3914 * things on.
3915 */
3916 if (is_lvds) {
3917 u32 lvds;
3918
3919 if (HAS_PCH_SPLIT(dev))
3920 lvds_reg = PCH_LVDS;
3921
3922 lvds = I915_READ(lvds_reg);
3923 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3924 if (pipe == 1) {
3925 if (HAS_PCH_CPT(dev))
3926 lvds |= PORT_TRANS_B_SEL_CPT;
3927 else
3928 lvds |= LVDS_PIPEB_SELECT;
3929 } else {
3930 if (HAS_PCH_CPT(dev))
3931 lvds &= ~PORT_TRANS_SEL_MASK;
3932 else
3933 lvds &= ~LVDS_PIPEB_SELECT;
3934 }
3935 /* set the corresponsding LVDS_BORDER bit */
3936 lvds |= dev_priv->lvds_border_bits;
3937 /* Set the B0-B3 data pairs corresponding to whether we're going to
3938 * set the DPLLs for dual-channel mode or not.
3939 */
3940 if (clock.p2 == 7)
3941 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3942 else
3943 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3944
3945 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3946 * appropriately here, but we need to look more thoroughly into how
3947 * panels behave in the two modes.
3948 */
3949 /* set the dithering flag on non-PCH LVDS as needed */
3950 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3951 if (dev_priv->lvds_dither)
3952 lvds |= LVDS_ENABLE_DITHER;
3953 else
3954 lvds &= ~LVDS_ENABLE_DITHER;
3955 }
3956 I915_WRITE(lvds_reg, lvds);
3957 I915_READ(lvds_reg);
3958 }
3959
3960 /* set the dithering flag and clear for anything other than a panel. */
3961 if (HAS_PCH_SPLIT(dev)) {
3962 pipeconf &= ~PIPECONF_DITHER_EN;
3963 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
3964 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
3965 pipeconf |= PIPECONF_DITHER_EN;
3966 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
3967 }
3968 }
3969
3970 if (is_dp)
3971 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3972 else if (HAS_PCH_SPLIT(dev)) {
3973 /* For non-DP output, clear any trans DP clock recovery setting.*/
3974 if (pipe == 0) {
3975 I915_WRITE(TRANSA_DATA_M1, 0);
3976 I915_WRITE(TRANSA_DATA_N1, 0);
3977 I915_WRITE(TRANSA_DP_LINK_M1, 0);
3978 I915_WRITE(TRANSA_DP_LINK_N1, 0);
3979 } else {
3980 I915_WRITE(TRANSB_DATA_M1, 0);
3981 I915_WRITE(TRANSB_DATA_N1, 0);
3982 I915_WRITE(TRANSB_DP_LINK_M1, 0);
3983 I915_WRITE(TRANSB_DP_LINK_N1, 0);
3984 }
3985 }
3986
3987 if (!has_edp_encoder) {
3988 I915_WRITE(fp_reg, fp);
3989 I915_WRITE(dpll_reg, dpll);
3990 I915_READ(dpll_reg);
3991 /* Wait for the clocks to stabilize. */
3992 udelay(150);
3993
3994 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3995 if (is_sdvo) {
3996 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3997 if (pixel_multiplier > 1)
3998 pixel_multiplier = (pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3999 else
4000 pixel_multiplier = 0;
4001
4002 I915_WRITE(dpll_md_reg,
4003 (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
4004 pixel_multiplier);
4005 } else
4006 I915_WRITE(dpll_md_reg, 0);
4007 } else {
4008 /* write it again -- the BIOS does, after all */
4009 I915_WRITE(dpll_reg, dpll);
4010 }
4011 I915_READ(dpll_reg);
4012 /* Wait for the clocks to stabilize. */
4013 udelay(150);
4014 }
4015
4016 if (is_lvds && has_reduced_clock && i915_powersave) {
4017 I915_WRITE(fp_reg + 4, fp2);
4018 intel_crtc->lowfreq_avail = true;
4019 if (HAS_PIPE_CXSR(dev)) {
4020 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4021 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4022 }
4023 } else {
4024 I915_WRITE(fp_reg + 4, fp);
4025 intel_crtc->lowfreq_avail = false;
4026 if (HAS_PIPE_CXSR(dev)) {
4027 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4028 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4029 }
4030 }
4031
4032 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4033 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4034 /* the chip adds 2 halflines automatically */
4035 adjusted_mode->crtc_vdisplay -= 1;
4036 adjusted_mode->crtc_vtotal -= 1;
4037 adjusted_mode->crtc_vblank_start -= 1;
4038 adjusted_mode->crtc_vblank_end -= 1;
4039 adjusted_mode->crtc_vsync_end -= 1;
4040 adjusted_mode->crtc_vsync_start -= 1;
4041 } else
4042 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4043
4044 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4045 ((adjusted_mode->crtc_htotal - 1) << 16));
4046 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4047 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4048 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4049 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4050 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4051 ((adjusted_mode->crtc_vtotal - 1) << 16));
4052 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4053 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4054 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4055 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4056 /* pipesrc and dspsize control the size that is scaled from, which should
4057 * always be the user's requested size.
4058 */
4059 if (!HAS_PCH_SPLIT(dev)) {
4060 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4061 (mode->hdisplay - 1));
4062 I915_WRITE(dsppos_reg, 0);
4063 }
4064 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4065
4066 if (HAS_PCH_SPLIT(dev)) {
4067 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4068 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4069 I915_WRITE(link_m1_reg, m_n.link_m);
4070 I915_WRITE(link_n1_reg, m_n.link_n);
4071
4072 if (has_edp_encoder) {
4073 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4074 } else {
4075 /* enable FDI RX PLL too */
4076 temp = I915_READ(fdi_rx_reg);
4077 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4078 I915_READ(fdi_rx_reg);
4079 udelay(200);
4080
4081 /* enable FDI TX PLL too */
4082 temp = I915_READ(fdi_tx_reg);
4083 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4084 I915_READ(fdi_tx_reg);
4085
4086 /* enable FDI RX PCDCLK */
4087 temp = I915_READ(fdi_rx_reg);
4088 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4089 I915_READ(fdi_rx_reg);
4090 udelay(200);
4091 }
4092 }
4093
4094 I915_WRITE(pipeconf_reg, pipeconf);
4095 I915_READ(pipeconf_reg);
4096
4097 intel_wait_for_vblank(dev, pipe);
4098
4099 if (IS_IRONLAKE(dev)) {
4100 /* enable address swizzle for tiling buffer */
4101 temp = I915_READ(DISP_ARB_CTL);
4102 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4103 }
4104
4105 I915_WRITE(dspcntr_reg, dspcntr);
4106
4107 /* Flush the plane changes */
4108 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4109
4110 intel_update_watermarks(dev);
4111
4112 drm_vblank_post_modeset(dev, pipe);
4113
4114 return ret;
4115 }
4116
4117 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4118 void intel_crtc_load_lut(struct drm_crtc *crtc)
4119 {
4120 struct drm_device *dev = crtc->dev;
4121 struct drm_i915_private *dev_priv = dev->dev_private;
4122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4123 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4124 int i;
4125
4126 /* The clocks have to be on to load the palette. */
4127 if (!crtc->enabled)
4128 return;
4129
4130 /* use legacy palette for Ironlake */
4131 if (HAS_PCH_SPLIT(dev))
4132 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4133 LGC_PALETTE_B;
4134
4135 for (i = 0; i < 256; i++) {
4136 I915_WRITE(palreg + 4 * i,
4137 (intel_crtc->lut_r[i] << 16) |
4138 (intel_crtc->lut_g[i] << 8) |
4139 intel_crtc->lut_b[i]);
4140 }
4141 }
4142
4143 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4144 {
4145 struct drm_device *dev = crtc->dev;
4146 struct drm_i915_private *dev_priv = dev->dev_private;
4147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4148 bool visible = base != 0;
4149 u32 cntl;
4150
4151 if (intel_crtc->cursor_visible == visible)
4152 return;
4153
4154 cntl = I915_READ(CURACNTR);
4155 if (visible) {
4156 /* On these chipsets we can only modify the base whilst
4157 * the cursor is disabled.
4158 */
4159 I915_WRITE(CURABASE, base);
4160
4161 cntl &= ~(CURSOR_FORMAT_MASK);
4162 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4163 cntl |= CURSOR_ENABLE |
4164 CURSOR_GAMMA_ENABLE |
4165 CURSOR_FORMAT_ARGB;
4166 } else
4167 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4168 I915_WRITE(CURACNTR, cntl);
4169
4170 intel_crtc->cursor_visible = visible;
4171 }
4172
4173 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4174 {
4175 struct drm_device *dev = crtc->dev;
4176 struct drm_i915_private *dev_priv = dev->dev_private;
4177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4178 int pipe = intel_crtc->pipe;
4179 bool visible = base != 0;
4180
4181 if (intel_crtc->cursor_visible != visible) {
4182 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4183 if (base) {
4184 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4185 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4186 cntl |= pipe << 28; /* Connect to correct pipe */
4187 } else {
4188 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4189 cntl |= CURSOR_MODE_DISABLE;
4190 }
4191 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4192
4193 intel_crtc->cursor_visible = visible;
4194 }
4195 /* and commit changes on next vblank */
4196 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4197 }
4198
4199 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4200 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4201 {
4202 struct drm_device *dev = crtc->dev;
4203 struct drm_i915_private *dev_priv = dev->dev_private;
4204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4205 int pipe = intel_crtc->pipe;
4206 int x = intel_crtc->cursor_x;
4207 int y = intel_crtc->cursor_y;
4208 u32 base, pos;
4209 bool visible;
4210
4211 pos = 0;
4212
4213 if (intel_crtc->cursor_on && crtc->fb) {
4214 base = intel_crtc->cursor_addr;
4215 if (x > (int) crtc->fb->width)
4216 base = 0;
4217
4218 if (y > (int) crtc->fb->height)
4219 base = 0;
4220 } else
4221 base = 0;
4222
4223 if (x < 0) {
4224 if (x + intel_crtc->cursor_width < 0)
4225 base = 0;
4226
4227 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4228 x = -x;
4229 }
4230 pos |= x << CURSOR_X_SHIFT;
4231
4232 if (y < 0) {
4233 if (y + intel_crtc->cursor_height < 0)
4234 base = 0;
4235
4236 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4237 y = -y;
4238 }
4239 pos |= y << CURSOR_Y_SHIFT;
4240
4241 visible = base != 0;
4242 if (!visible && !intel_crtc->cursor_visible)
4243 return;
4244
4245 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4246 if (IS_845G(dev) || IS_I865G(dev))
4247 i845_update_cursor(crtc, base);
4248 else
4249 i9xx_update_cursor(crtc, base);
4250
4251 if (visible)
4252 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4253 }
4254
4255 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4256 struct drm_file *file_priv,
4257 uint32_t handle,
4258 uint32_t width, uint32_t height)
4259 {
4260 struct drm_device *dev = crtc->dev;
4261 struct drm_i915_private *dev_priv = dev->dev_private;
4262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4263 struct drm_gem_object *bo;
4264 struct drm_i915_gem_object *obj_priv;
4265 uint32_t addr;
4266 int ret;
4267
4268 DRM_DEBUG_KMS("\n");
4269
4270 /* if we want to turn off the cursor ignore width and height */
4271 if (!handle) {
4272 DRM_DEBUG_KMS("cursor off\n");
4273 addr = 0;
4274 bo = NULL;
4275 mutex_lock(&dev->struct_mutex);
4276 goto finish;
4277 }
4278
4279 /* Currently we only support 64x64 cursors */
4280 if (width != 64 || height != 64) {
4281 DRM_ERROR("we currently only support 64x64 cursors\n");
4282 return -EINVAL;
4283 }
4284
4285 bo = drm_gem_object_lookup(dev, file_priv, handle);
4286 if (!bo)
4287 return -ENOENT;
4288
4289 obj_priv = to_intel_bo(bo);
4290
4291 if (bo->size < width * height * 4) {
4292 DRM_ERROR("buffer is to small\n");
4293 ret = -ENOMEM;
4294 goto fail;
4295 }
4296
4297 /* we only need to pin inside GTT if cursor is non-phy */
4298 mutex_lock(&dev->struct_mutex);
4299 if (!dev_priv->info->cursor_needs_physical) {
4300 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4301 if (ret) {
4302 DRM_ERROR("failed to pin cursor bo\n");
4303 goto fail_locked;
4304 }
4305
4306 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4307 if (ret) {
4308 DRM_ERROR("failed to move cursor bo into the GTT\n");
4309 goto fail_unpin;
4310 }
4311
4312 addr = obj_priv->gtt_offset;
4313 } else {
4314 int align = IS_I830(dev) ? 16 * 1024 : 256;
4315 ret = i915_gem_attach_phys_object(dev, bo,
4316 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4317 align);
4318 if (ret) {
4319 DRM_ERROR("failed to attach phys object\n");
4320 goto fail_locked;
4321 }
4322 addr = obj_priv->phys_obj->handle->busaddr;
4323 }
4324
4325 if (!IS_I9XX(dev))
4326 I915_WRITE(CURSIZE, (height << 12) | width);
4327
4328 finish:
4329 if (intel_crtc->cursor_bo) {
4330 if (dev_priv->info->cursor_needs_physical) {
4331 if (intel_crtc->cursor_bo != bo)
4332 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4333 } else
4334 i915_gem_object_unpin(intel_crtc->cursor_bo);
4335 drm_gem_object_unreference(intel_crtc->cursor_bo);
4336 }
4337
4338 mutex_unlock(&dev->struct_mutex);
4339
4340 intel_crtc->cursor_addr = addr;
4341 intel_crtc->cursor_bo = bo;
4342 intel_crtc->cursor_width = width;
4343 intel_crtc->cursor_height = height;
4344
4345 intel_crtc_update_cursor(crtc);
4346
4347 return 0;
4348 fail_unpin:
4349 i915_gem_object_unpin(bo);
4350 fail_locked:
4351 mutex_unlock(&dev->struct_mutex);
4352 fail:
4353 drm_gem_object_unreference_unlocked(bo);
4354 return ret;
4355 }
4356
4357 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4358 {
4359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4360
4361 intel_crtc->cursor_x = x;
4362 intel_crtc->cursor_y = y;
4363
4364 intel_crtc_update_cursor(crtc);
4365
4366 return 0;
4367 }
4368
4369 /** Sets the color ramps on behalf of RandR */
4370 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4371 u16 blue, int regno)
4372 {
4373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4374
4375 intel_crtc->lut_r[regno] = red >> 8;
4376 intel_crtc->lut_g[regno] = green >> 8;
4377 intel_crtc->lut_b[regno] = blue >> 8;
4378 }
4379
4380 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4381 u16 *blue, int regno)
4382 {
4383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4384
4385 *red = intel_crtc->lut_r[regno] << 8;
4386 *green = intel_crtc->lut_g[regno] << 8;
4387 *blue = intel_crtc->lut_b[regno] << 8;
4388 }
4389
4390 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4391 u16 *blue, uint32_t start, uint32_t size)
4392 {
4393 int end = (start + size > 256) ? 256 : start + size, i;
4394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4395
4396 for (i = start; i < end; i++) {
4397 intel_crtc->lut_r[i] = red[i] >> 8;
4398 intel_crtc->lut_g[i] = green[i] >> 8;
4399 intel_crtc->lut_b[i] = blue[i] >> 8;
4400 }
4401
4402 intel_crtc_load_lut(crtc);
4403 }
4404
4405 /**
4406 * Get a pipe with a simple mode set on it for doing load-based monitor
4407 * detection.
4408 *
4409 * It will be up to the load-detect code to adjust the pipe as appropriate for
4410 * its requirements. The pipe will be connected to no other encoders.
4411 *
4412 * Currently this code will only succeed if there is a pipe with no encoders
4413 * configured for it. In the future, it could choose to temporarily disable
4414 * some outputs to free up a pipe for its use.
4415 *
4416 * \return crtc, or NULL if no pipes are available.
4417 */
4418
4419 /* VESA 640x480x72Hz mode to set on the pipe */
4420 static struct drm_display_mode load_detect_mode = {
4421 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4422 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4423 };
4424
4425 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4426 struct drm_connector *connector,
4427 struct drm_display_mode *mode,
4428 int *dpms_mode)
4429 {
4430 struct intel_crtc *intel_crtc;
4431 struct drm_crtc *possible_crtc;
4432 struct drm_crtc *supported_crtc =NULL;
4433 struct drm_encoder *encoder = &intel_encoder->enc;
4434 struct drm_crtc *crtc = NULL;
4435 struct drm_device *dev = encoder->dev;
4436 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4437 struct drm_crtc_helper_funcs *crtc_funcs;
4438 int i = -1;
4439
4440 /*
4441 * Algorithm gets a little messy:
4442 * - if the connector already has an assigned crtc, use it (but make
4443 * sure it's on first)
4444 * - try to find the first unused crtc that can drive this connector,
4445 * and use that if we find one
4446 * - if there are no unused crtcs available, try to use the first
4447 * one we found that supports the connector
4448 */
4449
4450 /* See if we already have a CRTC for this connector */
4451 if (encoder->crtc) {
4452 crtc = encoder->crtc;
4453 /* Make sure the crtc and connector are running */
4454 intel_crtc = to_intel_crtc(crtc);
4455 *dpms_mode = intel_crtc->dpms_mode;
4456 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4457 crtc_funcs = crtc->helper_private;
4458 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4459 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4460 }
4461 return crtc;
4462 }
4463
4464 /* Find an unused one (if possible) */
4465 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4466 i++;
4467 if (!(encoder->possible_crtcs & (1 << i)))
4468 continue;
4469 if (!possible_crtc->enabled) {
4470 crtc = possible_crtc;
4471 break;
4472 }
4473 if (!supported_crtc)
4474 supported_crtc = possible_crtc;
4475 }
4476
4477 /*
4478 * If we didn't find an unused CRTC, don't use any.
4479 */
4480 if (!crtc) {
4481 return NULL;
4482 }
4483
4484 encoder->crtc = crtc;
4485 connector->encoder = encoder;
4486 intel_encoder->load_detect_temp = true;
4487
4488 intel_crtc = to_intel_crtc(crtc);
4489 *dpms_mode = intel_crtc->dpms_mode;
4490
4491 if (!crtc->enabled) {
4492 if (!mode)
4493 mode = &load_detect_mode;
4494 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4495 } else {
4496 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4497 crtc_funcs = crtc->helper_private;
4498 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4499 }
4500
4501 /* Add this connector to the crtc */
4502 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4503 encoder_funcs->commit(encoder);
4504 }
4505 /* let the connector get through one full cycle before testing */
4506 intel_wait_for_vblank(dev, intel_crtc->pipe);
4507
4508 return crtc;
4509 }
4510
4511 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4512 struct drm_connector *connector, int dpms_mode)
4513 {
4514 struct drm_encoder *encoder = &intel_encoder->enc;
4515 struct drm_device *dev = encoder->dev;
4516 struct drm_crtc *crtc = encoder->crtc;
4517 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4518 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4519
4520 if (intel_encoder->load_detect_temp) {
4521 encoder->crtc = NULL;
4522 connector->encoder = NULL;
4523 intel_encoder->load_detect_temp = false;
4524 crtc->enabled = drm_helper_crtc_in_use(crtc);
4525 drm_helper_disable_unused_functions(dev);
4526 }
4527
4528 /* Switch crtc and encoder back off if necessary */
4529 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4530 if (encoder->crtc == crtc)
4531 encoder_funcs->dpms(encoder, dpms_mode);
4532 crtc_funcs->dpms(crtc, dpms_mode);
4533 }
4534 }
4535
4536 /* Returns the clock of the currently programmed mode of the given pipe. */
4537 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4538 {
4539 struct drm_i915_private *dev_priv = dev->dev_private;
4540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4541 int pipe = intel_crtc->pipe;
4542 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4543 u32 fp;
4544 intel_clock_t clock;
4545
4546 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4547 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4548 else
4549 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4550
4551 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4552 if (IS_PINEVIEW(dev)) {
4553 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4554 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4555 } else {
4556 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4557 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4558 }
4559
4560 if (IS_I9XX(dev)) {
4561 if (IS_PINEVIEW(dev))
4562 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4563 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4564 else
4565 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4566 DPLL_FPA01_P1_POST_DIV_SHIFT);
4567
4568 switch (dpll & DPLL_MODE_MASK) {
4569 case DPLLB_MODE_DAC_SERIAL:
4570 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4571 5 : 10;
4572 break;
4573 case DPLLB_MODE_LVDS:
4574 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4575 7 : 14;
4576 break;
4577 default:
4578 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4579 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4580 return 0;
4581 }
4582
4583 /* XXX: Handle the 100Mhz refclk */
4584 intel_clock(dev, 96000, &clock);
4585 } else {
4586 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4587
4588 if (is_lvds) {
4589 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4590 DPLL_FPA01_P1_POST_DIV_SHIFT);
4591 clock.p2 = 14;
4592
4593 if ((dpll & PLL_REF_INPUT_MASK) ==
4594 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4595 /* XXX: might not be 66MHz */
4596 intel_clock(dev, 66000, &clock);
4597 } else
4598 intel_clock(dev, 48000, &clock);
4599 } else {
4600 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4601 clock.p1 = 2;
4602 else {
4603 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4604 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4605 }
4606 if (dpll & PLL_P2_DIVIDE_BY_4)
4607 clock.p2 = 4;
4608 else
4609 clock.p2 = 2;
4610
4611 intel_clock(dev, 48000, &clock);
4612 }
4613 }
4614
4615 /* XXX: It would be nice to validate the clocks, but we can't reuse
4616 * i830PllIsValid() because it relies on the xf86_config connector
4617 * configuration being accurate, which it isn't necessarily.
4618 */
4619
4620 return clock.dot;
4621 }
4622
4623 /** Returns the currently programmed mode of the given pipe. */
4624 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4625 struct drm_crtc *crtc)
4626 {
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4629 int pipe = intel_crtc->pipe;
4630 struct drm_display_mode *mode;
4631 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4632 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4633 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4634 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4635
4636 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4637 if (!mode)
4638 return NULL;
4639
4640 mode->clock = intel_crtc_clock_get(dev, crtc);
4641 mode->hdisplay = (htot & 0xffff) + 1;
4642 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4643 mode->hsync_start = (hsync & 0xffff) + 1;
4644 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4645 mode->vdisplay = (vtot & 0xffff) + 1;
4646 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4647 mode->vsync_start = (vsync & 0xffff) + 1;
4648 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4649
4650 drm_mode_set_name(mode);
4651 drm_mode_set_crtcinfo(mode, 0);
4652
4653 return mode;
4654 }
4655
4656 #define GPU_IDLE_TIMEOUT 500 /* ms */
4657
4658 /* When this timer fires, we've been idle for awhile */
4659 static void intel_gpu_idle_timer(unsigned long arg)
4660 {
4661 struct drm_device *dev = (struct drm_device *)arg;
4662 drm_i915_private_t *dev_priv = dev->dev_private;
4663
4664 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4665
4666 dev_priv->busy = false;
4667
4668 queue_work(dev_priv->wq, &dev_priv->idle_work);
4669 }
4670
4671 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4672
4673 static void intel_crtc_idle_timer(unsigned long arg)
4674 {
4675 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4676 struct drm_crtc *crtc = &intel_crtc->base;
4677 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4678
4679 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4680
4681 intel_crtc->busy = false;
4682
4683 queue_work(dev_priv->wq, &dev_priv->idle_work);
4684 }
4685
4686 static void intel_increase_pllclock(struct drm_crtc *crtc)
4687 {
4688 struct drm_device *dev = crtc->dev;
4689 drm_i915_private_t *dev_priv = dev->dev_private;
4690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4691 int pipe = intel_crtc->pipe;
4692 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4693 int dpll = I915_READ(dpll_reg);
4694
4695 if (HAS_PCH_SPLIT(dev))
4696 return;
4697
4698 if (!dev_priv->lvds_downclock_avail)
4699 return;
4700
4701 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4702 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4703
4704 /* Unlock panel regs */
4705 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4706 PANEL_UNLOCK_REGS);
4707
4708 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4709 I915_WRITE(dpll_reg, dpll);
4710 dpll = I915_READ(dpll_reg);
4711 intel_wait_for_vblank(dev, pipe);
4712 dpll = I915_READ(dpll_reg);
4713 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4714 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4715
4716 /* ...and lock them again */
4717 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4718 }
4719
4720 /* Schedule downclock */
4721 mod_timer(&intel_crtc->idle_timer, jiffies +
4722 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4723 }
4724
4725 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4726 {
4727 struct drm_device *dev = crtc->dev;
4728 drm_i915_private_t *dev_priv = dev->dev_private;
4729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4730 int pipe = intel_crtc->pipe;
4731 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4732 int dpll = I915_READ(dpll_reg);
4733
4734 if (HAS_PCH_SPLIT(dev))
4735 return;
4736
4737 if (!dev_priv->lvds_downclock_avail)
4738 return;
4739
4740 /*
4741 * Since this is called by a timer, we should never get here in
4742 * the manual case.
4743 */
4744 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4745 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4746
4747 /* Unlock panel regs */
4748 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4749 PANEL_UNLOCK_REGS);
4750
4751 dpll |= DISPLAY_RATE_SELECT_FPA1;
4752 I915_WRITE(dpll_reg, dpll);
4753 dpll = I915_READ(dpll_reg);
4754 intel_wait_for_vblank(dev, pipe);
4755 dpll = I915_READ(dpll_reg);
4756 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4757 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4758
4759 /* ...and lock them again */
4760 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4761 }
4762
4763 }
4764
4765 /**
4766 * intel_idle_update - adjust clocks for idleness
4767 * @work: work struct
4768 *
4769 * Either the GPU or display (or both) went idle. Check the busy status
4770 * here and adjust the CRTC and GPU clocks as necessary.
4771 */
4772 static void intel_idle_update(struct work_struct *work)
4773 {
4774 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4775 idle_work);
4776 struct drm_device *dev = dev_priv->dev;
4777 struct drm_crtc *crtc;
4778 struct intel_crtc *intel_crtc;
4779 int enabled = 0;
4780
4781 if (!i915_powersave)
4782 return;
4783
4784 mutex_lock(&dev->struct_mutex);
4785
4786 i915_update_gfx_val(dev_priv);
4787
4788 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4789 /* Skip inactive CRTCs */
4790 if (!crtc->fb)
4791 continue;
4792
4793 enabled++;
4794 intel_crtc = to_intel_crtc(crtc);
4795 if (!intel_crtc->busy)
4796 intel_decrease_pllclock(crtc);
4797 }
4798
4799 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4800 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4801 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4802 }
4803
4804 mutex_unlock(&dev->struct_mutex);
4805 }
4806
4807 /**
4808 * intel_mark_busy - mark the GPU and possibly the display busy
4809 * @dev: drm device
4810 * @obj: object we're operating on
4811 *
4812 * Callers can use this function to indicate that the GPU is busy processing
4813 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4814 * buffer), we'll also mark the display as busy, so we know to increase its
4815 * clock frequency.
4816 */
4817 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4818 {
4819 drm_i915_private_t *dev_priv = dev->dev_private;
4820 struct drm_crtc *crtc = NULL;
4821 struct intel_framebuffer *intel_fb;
4822 struct intel_crtc *intel_crtc;
4823
4824 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4825 return;
4826
4827 if (!dev_priv->busy) {
4828 if (IS_I945G(dev) || IS_I945GM(dev)) {
4829 u32 fw_blc_self;
4830
4831 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4832 fw_blc_self = I915_READ(FW_BLC_SELF);
4833 fw_blc_self &= ~FW_BLC_SELF_EN;
4834 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4835 }
4836 dev_priv->busy = true;
4837 } else
4838 mod_timer(&dev_priv->idle_timer, jiffies +
4839 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4840
4841 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4842 if (!crtc->fb)
4843 continue;
4844
4845 intel_crtc = to_intel_crtc(crtc);
4846 intel_fb = to_intel_framebuffer(crtc->fb);
4847 if (intel_fb->obj == obj) {
4848 if (!intel_crtc->busy) {
4849 if (IS_I945G(dev) || IS_I945GM(dev)) {
4850 u32 fw_blc_self;
4851
4852 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4853 fw_blc_self = I915_READ(FW_BLC_SELF);
4854 fw_blc_self &= ~FW_BLC_SELF_EN;
4855 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4856 }
4857 /* Non-busy -> busy, upclock */
4858 intel_increase_pllclock(crtc);
4859 intel_crtc->busy = true;
4860 } else {
4861 /* Busy -> busy, put off timer */
4862 mod_timer(&intel_crtc->idle_timer, jiffies +
4863 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4864 }
4865 }
4866 }
4867 }
4868
4869 static void intel_crtc_destroy(struct drm_crtc *crtc)
4870 {
4871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4872 struct drm_device *dev = crtc->dev;
4873 struct intel_unpin_work *work;
4874 unsigned long flags;
4875
4876 spin_lock_irqsave(&dev->event_lock, flags);
4877 work = intel_crtc->unpin_work;
4878 intel_crtc->unpin_work = NULL;
4879 spin_unlock_irqrestore(&dev->event_lock, flags);
4880
4881 if (work) {
4882 cancel_work_sync(&work->work);
4883 kfree(work);
4884 }
4885
4886 drm_crtc_cleanup(crtc);
4887
4888 kfree(intel_crtc);
4889 }
4890
4891 static void intel_unpin_work_fn(struct work_struct *__work)
4892 {
4893 struct intel_unpin_work *work =
4894 container_of(__work, struct intel_unpin_work, work);
4895
4896 mutex_lock(&work->dev->struct_mutex);
4897 i915_gem_object_unpin(work->old_fb_obj);
4898 drm_gem_object_unreference(work->pending_flip_obj);
4899 drm_gem_object_unreference(work->old_fb_obj);
4900 mutex_unlock(&work->dev->struct_mutex);
4901 kfree(work);
4902 }
4903
4904 static void do_intel_finish_page_flip(struct drm_device *dev,
4905 struct drm_crtc *crtc)
4906 {
4907 drm_i915_private_t *dev_priv = dev->dev_private;
4908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4909 struct intel_unpin_work *work;
4910 struct drm_i915_gem_object *obj_priv;
4911 struct drm_pending_vblank_event *e;
4912 struct timeval now;
4913 unsigned long flags;
4914
4915 /* Ignore early vblank irqs */
4916 if (intel_crtc == NULL)
4917 return;
4918
4919 spin_lock_irqsave(&dev->event_lock, flags);
4920 work = intel_crtc->unpin_work;
4921 if (work == NULL || !work->pending) {
4922 spin_unlock_irqrestore(&dev->event_lock, flags);
4923 return;
4924 }
4925
4926 intel_crtc->unpin_work = NULL;
4927 drm_vblank_put(dev, intel_crtc->pipe);
4928
4929 if (work->event) {
4930 e = work->event;
4931 do_gettimeofday(&now);
4932 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4933 e->event.tv_sec = now.tv_sec;
4934 e->event.tv_usec = now.tv_usec;
4935 list_add_tail(&e->base.link,
4936 &e->base.file_priv->event_list);
4937 wake_up_interruptible(&e->base.file_priv->event_wait);
4938 }
4939
4940 spin_unlock_irqrestore(&dev->event_lock, flags);
4941
4942 obj_priv = to_intel_bo(work->pending_flip_obj);
4943
4944 /* Initial scanout buffer will have a 0 pending flip count */
4945 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4946 atomic_dec_and_test(&obj_priv->pending_flip))
4947 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4948 schedule_work(&work->work);
4949
4950 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4951 }
4952
4953 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4954 {
4955 drm_i915_private_t *dev_priv = dev->dev_private;
4956 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4957
4958 do_intel_finish_page_flip(dev, crtc);
4959 }
4960
4961 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4962 {
4963 drm_i915_private_t *dev_priv = dev->dev_private;
4964 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4965
4966 do_intel_finish_page_flip(dev, crtc);
4967 }
4968
4969 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4970 {
4971 drm_i915_private_t *dev_priv = dev->dev_private;
4972 struct intel_crtc *intel_crtc =
4973 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4974 unsigned long flags;
4975
4976 spin_lock_irqsave(&dev->event_lock, flags);
4977 if (intel_crtc->unpin_work) {
4978 if ((++intel_crtc->unpin_work->pending) > 1)
4979 DRM_ERROR("Prepared flip multiple times\n");
4980 } else {
4981 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4982 }
4983 spin_unlock_irqrestore(&dev->event_lock, flags);
4984 }
4985
4986 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4987 struct drm_framebuffer *fb,
4988 struct drm_pending_vblank_event *event)
4989 {
4990 struct drm_device *dev = crtc->dev;
4991 struct drm_i915_private *dev_priv = dev->dev_private;
4992 struct intel_framebuffer *intel_fb;
4993 struct drm_i915_gem_object *obj_priv;
4994 struct drm_gem_object *obj;
4995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4996 struct intel_unpin_work *work;
4997 unsigned long flags, offset;
4998 int pipe = intel_crtc->pipe;
4999 u32 pf, pipesrc;
5000 int ret;
5001
5002 work = kzalloc(sizeof *work, GFP_KERNEL);
5003 if (work == NULL)
5004 return -ENOMEM;
5005
5006 work->event = event;
5007 work->dev = crtc->dev;
5008 intel_fb = to_intel_framebuffer(crtc->fb);
5009 work->old_fb_obj = intel_fb->obj;
5010 INIT_WORK(&work->work, intel_unpin_work_fn);
5011
5012 /* We borrow the event spin lock for protecting unpin_work */
5013 spin_lock_irqsave(&dev->event_lock, flags);
5014 if (intel_crtc->unpin_work) {
5015 spin_unlock_irqrestore(&dev->event_lock, flags);
5016 kfree(work);
5017
5018 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5019 return -EBUSY;
5020 }
5021 intel_crtc->unpin_work = work;
5022 spin_unlock_irqrestore(&dev->event_lock, flags);
5023
5024 intel_fb = to_intel_framebuffer(fb);
5025 obj = intel_fb->obj;
5026
5027 mutex_lock(&dev->struct_mutex);
5028 ret = intel_pin_and_fence_fb_obj(dev, obj);
5029 if (ret)
5030 goto cleanup_work;
5031
5032 /* Reference the objects for the scheduled work. */
5033 drm_gem_object_reference(work->old_fb_obj);
5034 drm_gem_object_reference(obj);
5035
5036 crtc->fb = fb;
5037 ret = i915_gem_object_flush_write_domain(obj);
5038 if (ret)
5039 goto cleanup_objs;
5040
5041 ret = drm_vblank_get(dev, intel_crtc->pipe);
5042 if (ret)
5043 goto cleanup_objs;
5044
5045 obj_priv = to_intel_bo(obj);
5046 atomic_inc(&obj_priv->pending_flip);
5047 work->pending_flip_obj = obj;
5048
5049 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5050 u32 flip_mask;
5051
5052 if (intel_crtc->plane)
5053 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5054 else
5055 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5056
5057 BEGIN_LP_RING(2);
5058 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5059 OUT_RING(0);
5060 ADVANCE_LP_RING();
5061 }
5062
5063 work->enable_stall_check = true;
5064
5065 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5066 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5067
5068 BEGIN_LP_RING(4);
5069 switch(INTEL_INFO(dev)->gen) {
5070 case 2:
5071 OUT_RING(MI_DISPLAY_FLIP |
5072 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5073 OUT_RING(fb->pitch);
5074 OUT_RING(obj_priv->gtt_offset + offset);
5075 OUT_RING(MI_NOOP);
5076 break;
5077
5078 case 3:
5079 OUT_RING(MI_DISPLAY_FLIP_I915 |
5080 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5081 OUT_RING(fb->pitch);
5082 OUT_RING(obj_priv->gtt_offset + offset);
5083 OUT_RING(MI_NOOP);
5084 break;
5085
5086 case 4:
5087 case 5:
5088 /* i965+ uses the linear or tiled offsets from the
5089 * Display Registers (which do not change across a page-flip)
5090 * so we need only reprogram the base address.
5091 */
5092 OUT_RING(MI_DISPLAY_FLIP |
5093 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5094 OUT_RING(fb->pitch);
5095 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5096
5097 /* XXX Enabling the panel-fitter across page-flip is so far
5098 * untested on non-native modes, so ignore it for now.
5099 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5100 */
5101 pf = 0;
5102 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5103 OUT_RING(pf | pipesrc);
5104 break;
5105
5106 case 6:
5107 OUT_RING(MI_DISPLAY_FLIP |
5108 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5109 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5110 OUT_RING(obj_priv->gtt_offset);
5111
5112 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5113 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5114 OUT_RING(pf | pipesrc);
5115 break;
5116 }
5117 ADVANCE_LP_RING();
5118
5119 mutex_unlock(&dev->struct_mutex);
5120
5121 trace_i915_flip_request(intel_crtc->plane, obj);
5122
5123 return 0;
5124
5125 cleanup_objs:
5126 drm_gem_object_unreference(work->old_fb_obj);
5127 drm_gem_object_unreference(obj);
5128 cleanup_work:
5129 mutex_unlock(&dev->struct_mutex);
5130
5131 spin_lock_irqsave(&dev->event_lock, flags);
5132 intel_crtc->unpin_work = NULL;
5133 spin_unlock_irqrestore(&dev->event_lock, flags);
5134
5135 kfree(work);
5136
5137 return ret;
5138 }
5139
5140 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5141 .dpms = intel_crtc_dpms,
5142 .mode_fixup = intel_crtc_mode_fixup,
5143 .mode_set = intel_crtc_mode_set,
5144 .mode_set_base = intel_pipe_set_base,
5145 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5146 .prepare = intel_crtc_prepare,
5147 .commit = intel_crtc_commit,
5148 .load_lut = intel_crtc_load_lut,
5149 };
5150
5151 static const struct drm_crtc_funcs intel_crtc_funcs = {
5152 .cursor_set = intel_crtc_cursor_set,
5153 .cursor_move = intel_crtc_cursor_move,
5154 .gamma_set = intel_crtc_gamma_set,
5155 .set_config = drm_crtc_helper_set_config,
5156 .destroy = intel_crtc_destroy,
5157 .page_flip = intel_crtc_page_flip,
5158 };
5159
5160
5161 static void intel_crtc_init(struct drm_device *dev, int pipe)
5162 {
5163 drm_i915_private_t *dev_priv = dev->dev_private;
5164 struct intel_crtc *intel_crtc;
5165 int i;
5166
5167 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5168 if (intel_crtc == NULL)
5169 return;
5170
5171 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5172
5173 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5174 intel_crtc->pipe = pipe;
5175 intel_crtc->plane = pipe;
5176 for (i = 0; i < 256; i++) {
5177 intel_crtc->lut_r[i] = i;
5178 intel_crtc->lut_g[i] = i;
5179 intel_crtc->lut_b[i] = i;
5180 }
5181
5182 /* Swap pipes & planes for FBC on pre-965 */
5183 intel_crtc->pipe = pipe;
5184 intel_crtc->plane = pipe;
5185 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5186 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5187 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5188 }
5189
5190 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5191 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5192 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5193 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5194
5195 intel_crtc->cursor_addr = 0;
5196 intel_crtc->dpms_mode = -1;
5197 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5198
5199 intel_crtc->busy = false;
5200
5201 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5202 (unsigned long)intel_crtc);
5203 }
5204
5205 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5206 struct drm_file *file_priv)
5207 {
5208 drm_i915_private_t *dev_priv = dev->dev_private;
5209 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5210 struct drm_mode_object *drmmode_obj;
5211 struct intel_crtc *crtc;
5212
5213 if (!dev_priv) {
5214 DRM_ERROR("called with no initialization\n");
5215 return -EINVAL;
5216 }
5217
5218 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5219 DRM_MODE_OBJECT_CRTC);
5220
5221 if (!drmmode_obj) {
5222 DRM_ERROR("no such CRTC id\n");
5223 return -EINVAL;
5224 }
5225
5226 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5227 pipe_from_crtc_id->pipe = crtc->pipe;
5228
5229 return 0;
5230 }
5231
5232 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5233 {
5234 struct drm_crtc *crtc = NULL;
5235
5236 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5238 if (intel_crtc->pipe == pipe)
5239 break;
5240 }
5241 return crtc;
5242 }
5243
5244 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5245 {
5246 int index_mask = 0;
5247 struct drm_encoder *encoder;
5248 int entry = 0;
5249
5250 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5251 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5252 if (type_mask & intel_encoder->clone_mask)
5253 index_mask |= (1 << entry);
5254 entry++;
5255 }
5256 return index_mask;
5257 }
5258
5259
5260 static void intel_setup_outputs(struct drm_device *dev)
5261 {
5262 struct drm_i915_private *dev_priv = dev->dev_private;
5263 struct drm_encoder *encoder;
5264 bool dpd_is_edp = false;
5265
5266 if (IS_MOBILE(dev) && !IS_I830(dev))
5267 intel_lvds_init(dev);
5268
5269 if (HAS_PCH_SPLIT(dev)) {
5270 dpd_is_edp = intel_dpd_is_edp(dev);
5271
5272 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5273 intel_dp_init(dev, DP_A);
5274
5275 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5276 intel_dp_init(dev, PCH_DP_D);
5277 }
5278
5279 intel_crt_init(dev);
5280
5281 if (HAS_PCH_SPLIT(dev)) {
5282 int found;
5283
5284 if (I915_READ(HDMIB) & PORT_DETECTED) {
5285 /* PCH SDVOB multiplex with HDMIB */
5286 found = intel_sdvo_init(dev, PCH_SDVOB);
5287 if (!found)
5288 intel_hdmi_init(dev, HDMIB);
5289 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5290 intel_dp_init(dev, PCH_DP_B);
5291 }
5292
5293 if (I915_READ(HDMIC) & PORT_DETECTED)
5294 intel_hdmi_init(dev, HDMIC);
5295
5296 if (I915_READ(HDMID) & PORT_DETECTED)
5297 intel_hdmi_init(dev, HDMID);
5298
5299 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5300 intel_dp_init(dev, PCH_DP_C);
5301
5302 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5303 intel_dp_init(dev, PCH_DP_D);
5304
5305 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5306 bool found = false;
5307
5308 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5309 DRM_DEBUG_KMS("probing SDVOB\n");
5310 found = intel_sdvo_init(dev, SDVOB);
5311 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5312 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5313 intel_hdmi_init(dev, SDVOB);
5314 }
5315
5316 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5317 DRM_DEBUG_KMS("probing DP_B\n");
5318 intel_dp_init(dev, DP_B);
5319 }
5320 }
5321
5322 /* Before G4X SDVOC doesn't have its own detect register */
5323
5324 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5325 DRM_DEBUG_KMS("probing SDVOC\n");
5326 found = intel_sdvo_init(dev, SDVOC);
5327 }
5328
5329 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5330
5331 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5332 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5333 intel_hdmi_init(dev, SDVOC);
5334 }
5335 if (SUPPORTS_INTEGRATED_DP(dev)) {
5336 DRM_DEBUG_KMS("probing DP_C\n");
5337 intel_dp_init(dev, DP_C);
5338 }
5339 }
5340
5341 if (SUPPORTS_INTEGRATED_DP(dev) &&
5342 (I915_READ(DP_D) & DP_DETECTED)) {
5343 DRM_DEBUG_KMS("probing DP_D\n");
5344 intel_dp_init(dev, DP_D);
5345 }
5346 } else if (IS_GEN2(dev))
5347 intel_dvo_init(dev);
5348
5349 if (SUPPORTS_TV(dev))
5350 intel_tv_init(dev);
5351
5352 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5353 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5354
5355 encoder->possible_crtcs = intel_encoder->crtc_mask;
5356 encoder->possible_clones = intel_encoder_clones(dev,
5357 intel_encoder->clone_mask);
5358 }
5359 }
5360
5361 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5362 {
5363 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5364
5365 drm_framebuffer_cleanup(fb);
5366 drm_gem_object_unreference_unlocked(intel_fb->obj);
5367
5368 kfree(intel_fb);
5369 }
5370
5371 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5372 struct drm_file *file_priv,
5373 unsigned int *handle)
5374 {
5375 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5376 struct drm_gem_object *object = intel_fb->obj;
5377
5378 return drm_gem_handle_create(file_priv, object, handle);
5379 }
5380
5381 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5382 .destroy = intel_user_framebuffer_destroy,
5383 .create_handle = intel_user_framebuffer_create_handle,
5384 };
5385
5386 int intel_framebuffer_init(struct drm_device *dev,
5387 struct intel_framebuffer *intel_fb,
5388 struct drm_mode_fb_cmd *mode_cmd,
5389 struct drm_gem_object *obj)
5390 {
5391 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5392 int ret;
5393
5394 if (obj_priv->tiling_mode == I915_TILING_Y)
5395 return -EINVAL;
5396
5397 if (mode_cmd->pitch & 63)
5398 return -EINVAL;
5399
5400 switch (mode_cmd->bpp) {
5401 case 8:
5402 case 16:
5403 case 24:
5404 case 32:
5405 break;
5406 default:
5407 return -EINVAL;
5408 }
5409
5410 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5411 if (ret) {
5412 DRM_ERROR("framebuffer init failed %d\n", ret);
5413 return ret;
5414 }
5415
5416 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5417 intel_fb->obj = obj;
5418 return 0;
5419 }
5420
5421 static struct drm_framebuffer *
5422 intel_user_framebuffer_create(struct drm_device *dev,
5423 struct drm_file *filp,
5424 struct drm_mode_fb_cmd *mode_cmd)
5425 {
5426 struct drm_gem_object *obj;
5427 struct intel_framebuffer *intel_fb;
5428 int ret;
5429
5430 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5431 if (!obj)
5432 return ERR_PTR(-ENOENT);
5433
5434 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5435 if (!intel_fb)
5436 return ERR_PTR(-ENOMEM);
5437
5438 ret = intel_framebuffer_init(dev, intel_fb,
5439 mode_cmd, obj);
5440 if (ret) {
5441 drm_gem_object_unreference_unlocked(obj);
5442 kfree(intel_fb);
5443 return ERR_PTR(ret);
5444 }
5445
5446 return &intel_fb->base;
5447 }
5448
5449 static const struct drm_mode_config_funcs intel_mode_funcs = {
5450 .fb_create = intel_user_framebuffer_create,
5451 .output_poll_changed = intel_fb_output_poll_changed,
5452 };
5453
5454 static struct drm_gem_object *
5455 intel_alloc_context_page(struct drm_device *dev)
5456 {
5457 struct drm_gem_object *ctx;
5458 int ret;
5459
5460 ctx = i915_gem_alloc_object(dev, 4096);
5461 if (!ctx) {
5462 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5463 return NULL;
5464 }
5465
5466 mutex_lock(&dev->struct_mutex);
5467 ret = i915_gem_object_pin(ctx, 4096);
5468 if (ret) {
5469 DRM_ERROR("failed to pin power context: %d\n", ret);
5470 goto err_unref;
5471 }
5472
5473 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5474 if (ret) {
5475 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5476 goto err_unpin;
5477 }
5478 mutex_unlock(&dev->struct_mutex);
5479
5480 return ctx;
5481
5482 err_unpin:
5483 i915_gem_object_unpin(ctx);
5484 err_unref:
5485 drm_gem_object_unreference(ctx);
5486 mutex_unlock(&dev->struct_mutex);
5487 return NULL;
5488 }
5489
5490 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5491 {
5492 struct drm_i915_private *dev_priv = dev->dev_private;
5493 u16 rgvswctl;
5494
5495 rgvswctl = I915_READ16(MEMSWCTL);
5496 if (rgvswctl & MEMCTL_CMD_STS) {
5497 DRM_DEBUG("gpu busy, RCS change rejected\n");
5498 return false; /* still busy with another command */
5499 }
5500
5501 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5502 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5503 I915_WRITE16(MEMSWCTL, rgvswctl);
5504 POSTING_READ16(MEMSWCTL);
5505
5506 rgvswctl |= MEMCTL_CMD_STS;
5507 I915_WRITE16(MEMSWCTL, rgvswctl);
5508
5509 return true;
5510 }
5511
5512 void ironlake_enable_drps(struct drm_device *dev)
5513 {
5514 struct drm_i915_private *dev_priv = dev->dev_private;
5515 u32 rgvmodectl = I915_READ(MEMMODECTL);
5516 u8 fmax, fmin, fstart, vstart;
5517
5518 /* 100ms RC evaluation intervals */
5519 I915_WRITE(RCUPEI, 100000);
5520 I915_WRITE(RCDNEI, 100000);
5521
5522 /* Set max/min thresholds to 90ms and 80ms respectively */
5523 I915_WRITE(RCBMAXAVG, 90000);
5524 I915_WRITE(RCBMINAVG, 80000);
5525
5526 I915_WRITE(MEMIHYST, 1);
5527
5528 /* Set up min, max, and cur for interrupt handling */
5529 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5530 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5531 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5532 MEMMODE_FSTART_SHIFT;
5533 fstart = fmax;
5534
5535 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5536 PXVFREQ_PX_SHIFT;
5537
5538 dev_priv->fmax = fstart; /* IPS callback will increase this */
5539 dev_priv->fstart = fstart;
5540
5541 dev_priv->max_delay = fmax;
5542 dev_priv->min_delay = fmin;
5543 dev_priv->cur_delay = fstart;
5544
5545 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5546 fstart);
5547
5548 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5549
5550 /*
5551 * Interrupts will be enabled in ironlake_irq_postinstall
5552 */
5553
5554 I915_WRITE(VIDSTART, vstart);
5555 POSTING_READ(VIDSTART);
5556
5557 rgvmodectl |= MEMMODE_SWMODE_EN;
5558 I915_WRITE(MEMMODECTL, rgvmodectl);
5559
5560 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5561 DRM_ERROR("stuck trying to change perf mode\n");
5562 msleep(1);
5563
5564 ironlake_set_drps(dev, fstart);
5565
5566 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5567 I915_READ(0x112e0);
5568 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5569 dev_priv->last_count2 = I915_READ(0x112f4);
5570 getrawmonotonic(&dev_priv->last_time2);
5571 }
5572
5573 void ironlake_disable_drps(struct drm_device *dev)
5574 {
5575 struct drm_i915_private *dev_priv = dev->dev_private;
5576 u16 rgvswctl = I915_READ16(MEMSWCTL);
5577
5578 /* Ack interrupts, disable EFC interrupt */
5579 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5580 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5581 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5582 I915_WRITE(DEIIR, DE_PCU_EVENT);
5583 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5584
5585 /* Go back to the starting frequency */
5586 ironlake_set_drps(dev, dev_priv->fstart);
5587 msleep(1);
5588 rgvswctl |= MEMCTL_CMD_STS;
5589 I915_WRITE(MEMSWCTL, rgvswctl);
5590 msleep(1);
5591
5592 }
5593
5594 static unsigned long intel_pxfreq(u32 vidfreq)
5595 {
5596 unsigned long freq;
5597 int div = (vidfreq & 0x3f0000) >> 16;
5598 int post = (vidfreq & 0x3000) >> 12;
5599 int pre = (vidfreq & 0x7);
5600
5601 if (!pre)
5602 return 0;
5603
5604 freq = ((div * 133333) / ((1<<post) * pre));
5605
5606 return freq;
5607 }
5608
5609 void intel_init_emon(struct drm_device *dev)
5610 {
5611 struct drm_i915_private *dev_priv = dev->dev_private;
5612 u32 lcfuse;
5613 u8 pxw[16];
5614 int i;
5615
5616 /* Disable to program */
5617 I915_WRITE(ECR, 0);
5618 POSTING_READ(ECR);
5619
5620 /* Program energy weights for various events */
5621 I915_WRITE(SDEW, 0x15040d00);
5622 I915_WRITE(CSIEW0, 0x007f0000);
5623 I915_WRITE(CSIEW1, 0x1e220004);
5624 I915_WRITE(CSIEW2, 0x04000004);
5625
5626 for (i = 0; i < 5; i++)
5627 I915_WRITE(PEW + (i * 4), 0);
5628 for (i = 0; i < 3; i++)
5629 I915_WRITE(DEW + (i * 4), 0);
5630
5631 /* Program P-state weights to account for frequency power adjustment */
5632 for (i = 0; i < 16; i++) {
5633 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5634 unsigned long freq = intel_pxfreq(pxvidfreq);
5635 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5636 PXVFREQ_PX_SHIFT;
5637 unsigned long val;
5638
5639 val = vid * vid;
5640 val *= (freq / 1000);
5641 val *= 255;
5642 val /= (127*127*900);
5643 if (val > 0xff)
5644 DRM_ERROR("bad pxval: %ld\n", val);
5645 pxw[i] = val;
5646 }
5647 /* Render standby states get 0 weight */
5648 pxw[14] = 0;
5649 pxw[15] = 0;
5650
5651 for (i = 0; i < 4; i++) {
5652 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5653 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5654 I915_WRITE(PXW + (i * 4), val);
5655 }
5656
5657 /* Adjust magic regs to magic values (more experimental results) */
5658 I915_WRITE(OGW0, 0);
5659 I915_WRITE(OGW1, 0);
5660 I915_WRITE(EG0, 0x00007f00);
5661 I915_WRITE(EG1, 0x0000000e);
5662 I915_WRITE(EG2, 0x000e0000);
5663 I915_WRITE(EG3, 0x68000300);
5664 I915_WRITE(EG4, 0x42000000);
5665 I915_WRITE(EG5, 0x00140031);
5666 I915_WRITE(EG6, 0);
5667 I915_WRITE(EG7, 0);
5668
5669 for (i = 0; i < 8; i++)
5670 I915_WRITE(PXWL + (i * 4), 0);
5671
5672 /* Enable PMON + select events */
5673 I915_WRITE(ECR, 0x80000019);
5674
5675 lcfuse = I915_READ(LCFUSE02);
5676
5677 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5678 }
5679
5680 void intel_init_clock_gating(struct drm_device *dev)
5681 {
5682 struct drm_i915_private *dev_priv = dev->dev_private;
5683
5684 /*
5685 * Disable clock gating reported to work incorrectly according to the
5686 * specs, but enable as much else as we can.
5687 */
5688 if (HAS_PCH_SPLIT(dev)) {
5689 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5690
5691 if (IS_IRONLAKE(dev)) {
5692 /* Required for FBC */
5693 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5694 /* Required for CxSR */
5695 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5696
5697 I915_WRITE(PCH_3DCGDIS0,
5698 MARIUNIT_CLOCK_GATE_DISABLE |
5699 SVSMUNIT_CLOCK_GATE_DISABLE);
5700 }
5701
5702 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5703
5704 /*
5705 * According to the spec the following bits should be set in
5706 * order to enable memory self-refresh
5707 * The bit 22/21 of 0x42004
5708 * The bit 5 of 0x42020
5709 * The bit 15 of 0x45000
5710 */
5711 if (IS_IRONLAKE(dev)) {
5712 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5713 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5714 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5715 I915_WRITE(ILK_DSPCLK_GATE,
5716 (I915_READ(ILK_DSPCLK_GATE) |
5717 ILK_DPARB_CLK_GATE));
5718 I915_WRITE(DISP_ARB_CTL,
5719 (I915_READ(DISP_ARB_CTL) |
5720 DISP_FBC_WM_DIS));
5721 }
5722 /*
5723 * Based on the document from hardware guys the following bits
5724 * should be set unconditionally in order to enable FBC.
5725 * The bit 22 of 0x42000
5726 * The bit 22 of 0x42004
5727 * The bit 7,8,9 of 0x42020.
5728 */
5729 if (IS_IRONLAKE_M(dev)) {
5730 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5731 I915_READ(ILK_DISPLAY_CHICKEN1) |
5732 ILK_FBCQ_DIS);
5733 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5734 I915_READ(ILK_DISPLAY_CHICKEN2) |
5735 ILK_DPARB_GATE);
5736 I915_WRITE(ILK_DSPCLK_GATE,
5737 I915_READ(ILK_DSPCLK_GATE) |
5738 ILK_DPFC_DIS1 |
5739 ILK_DPFC_DIS2 |
5740 ILK_CLK_FBC);
5741 }
5742 return;
5743 } else if (IS_G4X(dev)) {
5744 uint32_t dspclk_gate;
5745 I915_WRITE(RENCLK_GATE_D1, 0);
5746 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5747 GS_UNIT_CLOCK_GATE_DISABLE |
5748 CL_UNIT_CLOCK_GATE_DISABLE);
5749 I915_WRITE(RAMCLK_GATE_D, 0);
5750 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5751 OVRUNIT_CLOCK_GATE_DISABLE |
5752 OVCUNIT_CLOCK_GATE_DISABLE;
5753 if (IS_GM45(dev))
5754 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5755 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5756 } else if (IS_I965GM(dev)) {
5757 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5758 I915_WRITE(RENCLK_GATE_D2, 0);
5759 I915_WRITE(DSPCLK_GATE_D, 0);
5760 I915_WRITE(RAMCLK_GATE_D, 0);
5761 I915_WRITE16(DEUC, 0);
5762 } else if (IS_I965G(dev)) {
5763 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5764 I965_RCC_CLOCK_GATE_DISABLE |
5765 I965_RCPB_CLOCK_GATE_DISABLE |
5766 I965_ISC_CLOCK_GATE_DISABLE |
5767 I965_FBC_CLOCK_GATE_DISABLE);
5768 I915_WRITE(RENCLK_GATE_D2, 0);
5769 } else if (IS_I9XX(dev)) {
5770 u32 dstate = I915_READ(D_STATE);
5771
5772 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5773 DSTATE_DOT_CLOCK_GATING;
5774 I915_WRITE(D_STATE, dstate);
5775 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5776 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5777 } else if (IS_I830(dev)) {
5778 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5779 }
5780
5781 /*
5782 * GPU can automatically power down the render unit if given a page
5783 * to save state.
5784 */
5785 if (IS_IRONLAKE_M(dev)) {
5786 if (dev_priv->renderctx == NULL)
5787 dev_priv->renderctx = intel_alloc_context_page(dev);
5788 if (dev_priv->renderctx) {
5789 struct drm_i915_gem_object *obj_priv;
5790 obj_priv = to_intel_bo(dev_priv->renderctx);
5791 if (obj_priv) {
5792 BEGIN_LP_RING(4);
5793 OUT_RING(MI_SET_CONTEXT);
5794 OUT_RING(obj_priv->gtt_offset |
5795 MI_MM_SPACE_GTT |
5796 MI_SAVE_EXT_STATE_EN |
5797 MI_RESTORE_EXT_STATE_EN |
5798 MI_RESTORE_INHIBIT);
5799 OUT_RING(MI_NOOP);
5800 OUT_RING(MI_FLUSH);
5801 ADVANCE_LP_RING();
5802 }
5803 } else
5804 DRM_DEBUG_KMS("Failed to allocate render context."
5805 "Disable RC6\n");
5806 }
5807
5808 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5809 struct drm_i915_gem_object *obj_priv = NULL;
5810
5811 if (dev_priv->pwrctx) {
5812 obj_priv = to_intel_bo(dev_priv->pwrctx);
5813 } else {
5814 struct drm_gem_object *pwrctx;
5815
5816 pwrctx = intel_alloc_context_page(dev);
5817 if (pwrctx) {
5818 dev_priv->pwrctx = pwrctx;
5819 obj_priv = to_intel_bo(pwrctx);
5820 }
5821 }
5822
5823 if (obj_priv) {
5824 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5825 I915_WRITE(MCHBAR_RENDER_STANDBY,
5826 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5827 }
5828 }
5829 }
5830
5831 /* Set up chip specific display functions */
5832 static void intel_init_display(struct drm_device *dev)
5833 {
5834 struct drm_i915_private *dev_priv = dev->dev_private;
5835
5836 /* We always want a DPMS function */
5837 if (HAS_PCH_SPLIT(dev))
5838 dev_priv->display.dpms = ironlake_crtc_dpms;
5839 else
5840 dev_priv->display.dpms = i9xx_crtc_dpms;
5841
5842 if (I915_HAS_FBC(dev)) {
5843 if (IS_IRONLAKE_M(dev)) {
5844 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5845 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5846 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5847 } else if (IS_GM45(dev)) {
5848 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5849 dev_priv->display.enable_fbc = g4x_enable_fbc;
5850 dev_priv->display.disable_fbc = g4x_disable_fbc;
5851 } else if (IS_I965GM(dev)) {
5852 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5853 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5854 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5855 }
5856 /* 855GM needs testing */
5857 }
5858
5859 /* Returns the core display clock speed */
5860 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5861 dev_priv->display.get_display_clock_speed =
5862 i945_get_display_clock_speed;
5863 else if (IS_I915G(dev))
5864 dev_priv->display.get_display_clock_speed =
5865 i915_get_display_clock_speed;
5866 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5867 dev_priv->display.get_display_clock_speed =
5868 i9xx_misc_get_display_clock_speed;
5869 else if (IS_I915GM(dev))
5870 dev_priv->display.get_display_clock_speed =
5871 i915gm_get_display_clock_speed;
5872 else if (IS_I865G(dev))
5873 dev_priv->display.get_display_clock_speed =
5874 i865_get_display_clock_speed;
5875 else if (IS_I85X(dev))
5876 dev_priv->display.get_display_clock_speed =
5877 i855_get_display_clock_speed;
5878 else /* 852, 830 */
5879 dev_priv->display.get_display_clock_speed =
5880 i830_get_display_clock_speed;
5881
5882 /* For FIFO watermark updates */
5883 if (HAS_PCH_SPLIT(dev)) {
5884 if (IS_IRONLAKE(dev)) {
5885 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5886 dev_priv->display.update_wm = ironlake_update_wm;
5887 else {
5888 DRM_DEBUG_KMS("Failed to get proper latency. "
5889 "Disable CxSR\n");
5890 dev_priv->display.update_wm = NULL;
5891 }
5892 } else
5893 dev_priv->display.update_wm = NULL;
5894 } else if (IS_PINEVIEW(dev)) {
5895 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5896 dev_priv->is_ddr3,
5897 dev_priv->fsb_freq,
5898 dev_priv->mem_freq)) {
5899 DRM_INFO("failed to find known CxSR latency "
5900 "(found ddr%s fsb freq %d, mem freq %d), "
5901 "disabling CxSR\n",
5902 (dev_priv->is_ddr3 == 1) ? "3": "2",
5903 dev_priv->fsb_freq, dev_priv->mem_freq);
5904 /* Disable CxSR and never update its watermark again */
5905 pineview_disable_cxsr(dev);
5906 dev_priv->display.update_wm = NULL;
5907 } else
5908 dev_priv->display.update_wm = pineview_update_wm;
5909 } else if (IS_G4X(dev))
5910 dev_priv->display.update_wm = g4x_update_wm;
5911 else if (IS_I965G(dev))
5912 dev_priv->display.update_wm = i965_update_wm;
5913 else if (IS_I9XX(dev)) {
5914 dev_priv->display.update_wm = i9xx_update_wm;
5915 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5916 } else if (IS_I85X(dev)) {
5917 dev_priv->display.update_wm = i9xx_update_wm;
5918 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5919 } else {
5920 dev_priv->display.update_wm = i830_update_wm;
5921 if (IS_845G(dev))
5922 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5923 else
5924 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5925 }
5926 }
5927
5928 /*
5929 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5930 * resume, or other times. This quirk makes sure that's the case for
5931 * affected systems.
5932 */
5933 static void quirk_pipea_force (struct drm_device *dev)
5934 {
5935 struct drm_i915_private *dev_priv = dev->dev_private;
5936
5937 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5938 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5939 }
5940
5941 struct intel_quirk {
5942 int device;
5943 int subsystem_vendor;
5944 int subsystem_device;
5945 void (*hook)(struct drm_device *dev);
5946 };
5947
5948 struct intel_quirk intel_quirks[] = {
5949 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5950 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5951 /* HP Mini needs pipe A force quirk (LP: #322104) */
5952 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5953
5954 /* Thinkpad R31 needs pipe A force quirk */
5955 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5956 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5957 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5958
5959 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5960 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
5961 /* ThinkPad X40 needs pipe A force quirk */
5962
5963 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5964 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5965
5966 /* 855 & before need to leave pipe A & dpll A up */
5967 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5968 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5969 };
5970
5971 static void intel_init_quirks(struct drm_device *dev)
5972 {
5973 struct pci_dev *d = dev->pdev;
5974 int i;
5975
5976 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5977 struct intel_quirk *q = &intel_quirks[i];
5978
5979 if (d->device == q->device &&
5980 (d->subsystem_vendor == q->subsystem_vendor ||
5981 q->subsystem_vendor == PCI_ANY_ID) &&
5982 (d->subsystem_device == q->subsystem_device ||
5983 q->subsystem_device == PCI_ANY_ID))
5984 q->hook(dev);
5985 }
5986 }
5987
5988 /* Disable the VGA plane that we never use */
5989 static void i915_disable_vga(struct drm_device *dev)
5990 {
5991 struct drm_i915_private *dev_priv = dev->dev_private;
5992 u8 sr1;
5993 u32 vga_reg;
5994
5995 if (HAS_PCH_SPLIT(dev))
5996 vga_reg = CPU_VGACNTRL;
5997 else
5998 vga_reg = VGACNTRL;
5999
6000 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6001 outb(1, VGA_SR_INDEX);
6002 sr1 = inb(VGA_SR_DATA);
6003 outb(sr1 | 1<<5, VGA_SR_DATA);
6004 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6005 udelay(300);
6006
6007 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6008 POSTING_READ(vga_reg);
6009 }
6010
6011 void intel_modeset_init(struct drm_device *dev)
6012 {
6013 struct drm_i915_private *dev_priv = dev->dev_private;
6014 int i;
6015
6016 drm_mode_config_init(dev);
6017
6018 dev->mode_config.min_width = 0;
6019 dev->mode_config.min_height = 0;
6020
6021 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6022
6023 intel_init_quirks(dev);
6024
6025 intel_init_display(dev);
6026
6027 if (IS_I965G(dev)) {
6028 dev->mode_config.max_width = 8192;
6029 dev->mode_config.max_height = 8192;
6030 } else if (IS_I9XX(dev)) {
6031 dev->mode_config.max_width = 4096;
6032 dev->mode_config.max_height = 4096;
6033 } else {
6034 dev->mode_config.max_width = 2048;
6035 dev->mode_config.max_height = 2048;
6036 }
6037
6038 /* set memory base */
6039 if (IS_I9XX(dev))
6040 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6041 else
6042 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6043
6044 if (IS_MOBILE(dev) || IS_I9XX(dev))
6045 dev_priv->num_pipe = 2;
6046 else
6047 dev_priv->num_pipe = 1;
6048 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6049 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6050
6051 for (i = 0; i < dev_priv->num_pipe; i++) {
6052 intel_crtc_init(dev, i);
6053 }
6054
6055 intel_setup_outputs(dev);
6056
6057 intel_init_clock_gating(dev);
6058
6059 /* Just disable it once at startup */
6060 i915_disable_vga(dev);
6061
6062 if (IS_IRONLAKE_M(dev)) {
6063 ironlake_enable_drps(dev);
6064 intel_init_emon(dev);
6065 }
6066
6067 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6068 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6069 (unsigned long)dev);
6070
6071 intel_setup_overlay(dev);
6072 }
6073
6074 void intel_modeset_cleanup(struct drm_device *dev)
6075 {
6076 struct drm_i915_private *dev_priv = dev->dev_private;
6077 struct drm_crtc *crtc;
6078 struct intel_crtc *intel_crtc;
6079
6080 mutex_lock(&dev->struct_mutex);
6081
6082 drm_kms_helper_poll_fini(dev);
6083 intel_fbdev_fini(dev);
6084
6085 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6086 /* Skip inactive CRTCs */
6087 if (!crtc->fb)
6088 continue;
6089
6090 intel_crtc = to_intel_crtc(crtc);
6091 intel_increase_pllclock(crtc);
6092 }
6093
6094 if (dev_priv->display.disable_fbc)
6095 dev_priv->display.disable_fbc(dev);
6096
6097 if (dev_priv->renderctx) {
6098 struct drm_i915_gem_object *obj_priv;
6099
6100 obj_priv = to_intel_bo(dev_priv->renderctx);
6101 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6102 I915_READ(CCID);
6103 i915_gem_object_unpin(dev_priv->renderctx);
6104 drm_gem_object_unreference(dev_priv->renderctx);
6105 }
6106
6107 if (dev_priv->pwrctx) {
6108 struct drm_i915_gem_object *obj_priv;
6109
6110 obj_priv = to_intel_bo(dev_priv->pwrctx);
6111 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6112 I915_READ(PWRCTXA);
6113 i915_gem_object_unpin(dev_priv->pwrctx);
6114 drm_gem_object_unreference(dev_priv->pwrctx);
6115 }
6116
6117 if (IS_IRONLAKE_M(dev))
6118 ironlake_disable_drps(dev);
6119
6120 mutex_unlock(&dev->struct_mutex);
6121
6122 /* Disable the irq before mode object teardown, for the irq might
6123 * enqueue unpin/hotplug work. */
6124 drm_irq_uninstall(dev);
6125 cancel_work_sync(&dev_priv->hotplug_work);
6126
6127 /* Shut off idle work before the crtcs get freed. */
6128 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6129 intel_crtc = to_intel_crtc(crtc);
6130 del_timer_sync(&intel_crtc->idle_timer);
6131 }
6132 del_timer_sync(&dev_priv->idle_timer);
6133 cancel_work_sync(&dev_priv->idle_work);
6134
6135 drm_mode_config_cleanup(dev);
6136 }
6137
6138 /*
6139 * Return which encoder is currently attached for connector.
6140 */
6141 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
6142 {
6143 struct drm_mode_object *obj;
6144 struct drm_encoder *encoder;
6145 int i;
6146
6147 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
6148 if (connector->encoder_ids[i] == 0)
6149 break;
6150
6151 obj = drm_mode_object_find(connector->dev,
6152 connector->encoder_ids[i],
6153 DRM_MODE_OBJECT_ENCODER);
6154 if (!obj)
6155 continue;
6156
6157 encoder = obj_to_encoder(obj);
6158 return encoder;
6159 }
6160 return NULL;
6161 }
6162
6163 /*
6164 * set vga decode state - true == enable VGA decode
6165 */
6166 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6167 {
6168 struct drm_i915_private *dev_priv = dev->dev_private;
6169 u16 gmch_ctrl;
6170
6171 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6172 if (state)
6173 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6174 else
6175 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6176 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6177 return 0;
6178 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree