drivers/pci/probe.c

   1 /*
   2  * probe.c - PCI detection and setup code
   3  */
   4
   5 #include <linux/kernel.h>
   6 #include <linux/delay.h>
   7 #include <linux/init.h>
   8 #include <linux/pci.h>
   9 #include <linux/slab.h>
  10 #include <linux/module.h>
  11 #include <linux/cpumask.h>
  12 #include "pci.h"
  13
  14 #define CARDBUS_LATENCY_TIMER   176     /* secondary latency timer */
  15 #define CARDBUS_RESERVE_BUSNR   3
  16 #define PCI_CFG_SPACE_SIZE      256
  17 #define PCI_CFG_SPACE_EXP_SIZE  4096
  18
  19 /* Ugh.  Need to stop exporting this to modules. */
  20 LIST_HEAD(pci_root_buses);
  21 EXPORT_SYMBOL(pci_root_buses);
  22
  23 LIST_HEAD(pci_devices);
  24
  25 #ifdef HAVE_PCI_LEGACY
  26 /**
  27  * pci_create_legacy_files - create legacy I/O port and memory files
  28  * @b: bus to create files under
  29  *
  30  * Some platforms allow access to legacy I/O port and ISA memory space on
  31  * a per-bus basis.  This routine creates the files and ties them into
  32  * their associated read, write and mmap files from pci-sysfs.c
  33  */
  34 static void pci_create_legacy_files(struct pci_bus *b)
  35 {
  36         b->legacy_io = kmalloc(sizeof(struct bin_attribute) * 2,
  37                                GFP_ATOMIC);
  38         if (b->legacy_io) {
  39                 memset(b->legacy_io, 0, sizeof(struct bin_attribute) * 2);
  40                 b->legacy_io->attr.name = "legacy_io";
  41                 b->legacy_io->size = 0xffff;
  42                 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
  43                 b->legacy_io->attr.owner = THIS_MODULE;
  44                 b->legacy_io->read = pci_read_legacy_io;
  45                 b->legacy_io->write = pci_write_legacy_io;
  46                 class_device_create_bin_file(&b->class_dev, b->legacy_io);
  47
  48                 /* Allocated above after the legacy_io struct */
  49                 b->legacy_mem = b->legacy_io + 1;
  50                 b->legacy_mem->attr.name = "legacy_mem";
  51                 b->legacy_mem->size = 1024*1024;
  52                 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
  53                 b->legacy_mem->attr.owner = THIS_MODULE;
  54                 b->legacy_mem->mmap = pci_mmap_legacy_mem;
  55                 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
  56         }
  57 }
  58
  59 void pci_remove_legacy_files(struct pci_bus *b)
  60 {
  61         if (b->legacy_io) {
  62                 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
  63                 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
  64                 kfree(b->legacy_io); /* both are allocated here */
  65         }
  66 }
  67 #else /* !HAVE_PCI_LEGACY */
  68 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
  69 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
  70 #endif /* HAVE_PCI_LEGACY */
  71
  72 /*
  73  * PCI Bus Class Devices
  74  */
  75 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev,
  76                                         char *buf)
  77 {
  78         int ret;
  79         cpumask_t cpumask;
  80
  81         cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
  82         ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
  83         if (ret < PAGE_SIZE)
  84                 buf[ret++] = '\n';
  85         return ret;
  86 }
  87 CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
  88
  89 /*
  90  * PCI Bus Class
  91  */
  92 static void release_pcibus_dev(struct class_device *class_dev)
  93 {
  94         struct pci_bus *pci_bus = to_pci_bus(class_dev);
  95
  96         if (pci_bus->bridge)
  97                 put_device(pci_bus->bridge);
  98         kfree(pci_bus);
  99 }
 100
 101 static struct class pcibus_class = {
 102         .name           = "pci_bus",
 103         .release        = &release_pcibus_dev,
 104 };
 105
 106 static int __init pcibus_class_init(void)
 107 {
 108         return class_register(&pcibus_class);
 109 }
 110 postcore_initcall(pcibus_class_init);
 111
 112 /*
 113  * Translate the low bits of the PCI base
 114  * to the resource type
 115  */
 116 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
 117 {
 118         if (flags & PCI_BASE_ADDRESS_SPACE_IO)
 119                 return IORESOURCE_IO;
 120
 121         if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
 122                 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
 123
 124         return IORESOURCE_MEM;
 125 }
 126
 127 /*
 128  * Find the extent of a PCI decode..
 129  */
 130 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
 131 {
 132         u32 size = mask & maxbase;      /* Find the significant bits */
 133         if (!size)
 134                 return 0;
 135
 136         /* Get the lowest of them to find the decode size, and
 137            from that the extent.  */
 138         size = (size & ~(size-1)) - 1;
 139
 140         /* base == maxbase can be valid only if the BAR has
 141            already been programmed with all 1s.  */
 142         if (base == maxbase && ((base | size) & mask) != mask)
 143                 return 0;
 144
 145         return size;
 146 }
 147
 148 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
 149 {
 150         unsigned int pos, reg, next;
 151         u32 l, sz;
 152         struct resource *res;
 153
 154         for(pos=0; pos<howmany; pos = next) {
 155                 next = pos+1;
 156                 res = &dev->resource[pos];
 157                 res->name = pci_name(dev);
 158                 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
 159                 pci_read_config_dword(dev, reg, &l);
 160                 pci_write_config_dword(dev, reg, ~0);
 161                 pci_read_config_dword(dev, reg, &sz);
 162                 pci_write_config_dword(dev, reg, l);
 163                 if (!sz || sz == 0xffffffff)
 164                         continue;
 165                 if (l == 0xffffffff)
 166                         l = 0;
 167                 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
 168                         sz = pci_size(l, sz, PCI_BASE_ADDRESS_MEM_MASK);
 169                         if (!sz)
 170                                 continue;
 171                         res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
 172                         res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
 173                 } else {
 174                         sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
 175                         if (!sz)
 176                                 continue;
 177                         res->start = l & PCI_BASE_ADDRESS_IO_MASK;
 178                         res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
 179                 }
 180                 res->end = res->start + (unsigned long) sz;
 181                 res->flags |= pci_calc_resource_flags(l);
 182                 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
 183                     == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
 184                         pci_read_config_dword(dev, reg+4, &l);
 185                         next++;
 186 #if BITS_PER_LONG == 64
 187                         res->start |= ((unsigned long) l) << 32;
 188                         res->end = res->start + sz;
 189                         pci_write_config_dword(dev, reg+4, ~0);
 190                         pci_read_config_dword(dev, reg+4, &sz);
 191                         pci_write_config_dword(dev, reg+4, l);
 192                         sz = pci_size(l, sz, 0xffffffff);
 193                         if (sz) {
 194                                 /* This BAR needs > 4GB?  Wow. */
 195                                 res->end |= (unsigned long)sz<<32;
 196                         }
 197 #else
 198                         if (l) {
 199                                 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev));
 200                                 res->start = 0;
 201                                 res->flags = 0;
 202                                 continue;
 203                         }
 204 #endif
 205                 }
 206         }
 207         if (rom) {
 208                 dev->rom_base_reg = rom;
 209                 res = &dev->resource[PCI_ROM_RESOURCE];
 210                 res->name = pci_name(dev);
 211                 pci_read_config_dword(dev, rom, &l);
 212                 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
 213                 pci_read_config_dword(dev, rom, &sz);
 214                 pci_write_config_dword(dev, rom, l);
 215                 if (l == 0xffffffff)
 216                         l = 0;
 217                 if (sz && sz != 0xffffffff) {
 218                         sz = pci_size(l, sz, PCI_ROM_ADDRESS_MASK);
 219                         if (sz) {
 220                                 res->flags = (l & IORESOURCE_ROM_ENABLE) |
 221                                   IORESOURCE_MEM | IORESOURCE_PREFETCH |
 222                                   IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
 223                                 res->start = l & PCI_ROM_ADDRESS_MASK;
 224                                 res->end = res->start + (unsigned long) sz;
 225                         }
 226                 }
 227         }
 228 }
 229
 230 void __devinit pci_read_bridge_bases(struct pci_bus *child)
 231 {
 232         struct pci_dev *dev = child->self;
 233         u8 io_base_lo, io_limit_lo;
 234         u16 mem_base_lo, mem_limit_lo;
 235         unsigned long base, limit;
 236         struct resource *res;
 237         int i;
 238
 239         if (!dev)               /* It's a host bus, nothing to read */
 240                 return;
 241
 242         if (dev->transparent) {
 243                 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
 244                 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
 245                         child->resource[i] = child->parent->resource[i - 3];
 246         }
 247
 248         for(i=0; i<3; i++)
 249                 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
 250
 251         res = child->resource[0];
 252         pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
 253         pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
 254         base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
 255         limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
 256
 257         if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
 258                 u16 io_base_hi, io_limit_hi;
 259                 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
 260                 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
 261                 base |= (io_base_hi << 16);
 262                 limit |= (io_limit_hi << 16);
 263         }
 264
 265         if (base <= limit) {
 266                 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
 267                 res->start = base;
 268                 res->end = limit + 0xfff;
 269         }
 270
 271         res = child->resource[1];
 272         pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
 273         pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
 274         base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
 275         limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
 276         if (base <= limit) {
 277                 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
 278                 res->start = base;
 279                 res->end = limit + 0xfffff;
 280         }
 281
 282         res = child->resource[2];
 283         pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
 284         pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
 285         base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
 286         limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
 287
 288         if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
 289                 u32 mem_base_hi, mem_limit_hi;
 290                 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
 291                 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
 292
 293                 /*
 294                  * Some bridges set the base > limit by default, and some
 295                  * (broken) BIOSes do not initialize them.  If we find
 296                  * this, just assume they are not being used.
 297                  */
 298                 if (mem_base_hi <= mem_limit_hi) {
 299 #if BITS_PER_LONG == 64
 300                         base |= ((long) mem_base_hi) << 32;
 301                         limit |= ((long) mem_limit_hi) << 32;
 302 #else
 303                         if (mem_base_hi || mem_limit_hi) {
 304                                 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
 305                                 return;
 306                         }
 307 #endif
 308                 }
 309         }
 310         if (base <= limit) {
 311                 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
 312                 res->start = base;
 313                 res->end = limit + 0xfffff;
 314         }
 315 }
 316
 317 static struct pci_bus * __devinit pci_alloc_bus(void)
 318 {
 319         struct pci_bus *b;
 320
 321         b = kmalloc(sizeof(*b), GFP_KERNEL);
 322         if (b) {
 323                 memset(b, 0, sizeof(*b));
 324                 INIT_LIST_HEAD(&b->node);
 325                 INIT_LIST_HEAD(&b->children);
 326                 INIT_LIST_HEAD(&b->devices);
 327         }
 328         return b;
 329 }
 330
 331 static struct pci_bus * __devinit
 332 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
 333 {
 334         struct pci_bus *child;
 335         int i;
 336
 337         /*
 338          * Allocate a new bus, and inherit stuff from the parent..
 339          */
 340         child = pci_alloc_bus();
 341         if (!child)
 342                 return NULL;
 343
 344         child->self = bridge;
 345         child->parent = parent;
 346         child->ops = parent->ops;
 347         child->sysdata = parent->sysdata;
 348         child->bridge = get_device(&bridge->dev);
 349
 350         child->class_dev.class = &pcibus_class;
 351         sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
 352         class_device_register(&child->class_dev);
 353         class_device_create_file(&child->class_dev, &class_device_attr_cpuaffinity);
 354
 355         /*
 356          * Set up the primary, secondary and subordinate
 357          * bus numbers.
 358          */
 359         child->number = child->secondary = busnr;
 360         child->primary = parent->secondary;
 361         child->subordinate = 0xff;
 362
 363         /* Set up default resource pointers and names.. */
 364         for (i = 0; i < 4; i++) {
 365                 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
 366                 child->resource[i]->name = child->name;
 367         }
 368         bridge->subordinate = child;
 369
 370         return child;
 371 }
 372
 373 struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
 374 {
 375         struct pci_bus *child;
 376
 377         child = pci_alloc_child_bus(parent, dev, busnr);
 378         if (child) {
 379                 spin_lock(&pci_bus_lock);
 380                 list_add_tail(&child->node, &parent->children);
 381                 spin_unlock(&pci_bus_lock);
 382         }
 383         return child;
 384 }
 385
 386 static void pci_enable_crs(struct pci_dev *dev)
 387 {
 388         u16 cap, rpctl;
 389         int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
 390         if (!rpcap)
 391                 return;
 392
 393         pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
 394         if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
 395                 return;
 396
 397         pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
 398         rpctl |= PCI_EXP_RTCTL_CRSSVE;
 399         pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
 400 }
 401
 402 static void __devinit pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
 403 {
 404         struct pci_bus *parent = child->parent;
 405         while (parent->parent && parent->subordinate < max) {
 406                 parent->subordinate = max;
 407                 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
 408                 parent = parent->parent;
 409         }
 410 }
 411
 412 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
 413
 414 /*
 415  * If it's a bridge, configure it and scan the bus behind it.
 416  * For CardBus bridges, we don't scan behind as the devices will
 417  * be handled by the bridge driver itself.
 418  *
 419  * We need to process bridges in two passes -- first we scan those
 420  * already configured by the BIOS and after we are done with all of
 421  * them, we proceed to assigning numbers to the remaining buses in
 422  * order to avoid overlaps between old and new bus numbers.
 423  */
 424 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
 425 {
 426         struct pci_bus *child;
 427         int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
 428         u32 buses, i;
 429         u16 bctl;
 430
 431         pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
 432
 433         pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
 434                  pci_name(dev), buses & 0xffffff, pass);
 435
 436         /* Disable MasterAbortMode during probing to avoid reporting
 437            of bus errors (in some architectures) */
 438         pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
 439         pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
 440                               bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
 441
 442         pci_enable_crs(dev);
 443
 444         if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
 445                 unsigned int cmax, busnr;
 446                 /*
 447                  * Bus already configured by firmware, process it in the first
 448                  * pass and just note the configuration.
 449                  */
 450                 if (pass)
 451                         return max;
 452                 busnr = (buses >> 8) & 0xFF;
 453
 454                 /*
 455                  * If we already got to this bus through a different bridge,
 456                  * ignore it.  This can happen with the i450NX chipset.
 457                  */
 458                 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
 459                         printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
 460                                         pci_domain_nr(bus), busnr);
 461                         return max;
 462                 }
 463
 464                 child = pci_add_new_bus(bus, dev, busnr);
 465                 if (!child)
 466                         return max;
 467                 child->primary = buses & 0xFF;
 468                 child->subordinate = (buses >> 16) & 0xFF;
 469                 child->bridge_ctl = bctl;
 470
 471                 cmax = pci_scan_child_bus(child);
 472                 if (cmax > max)
 473                         max = cmax;
 474                 if (child->subordinate > max)
 475                         max = child->subordinate;
 476         } else {
 477                 /*
 478                  * We need to assign a number to this bus which we always
 479                  * do in the second pass.
 480                  */
 481                 if (!pass)
 482                         return max;
 483
 484                 /* Clear errors */
 485                 pci_write_config_word(dev, PCI_STATUS, 0xffff);
 486
 487                 /* Prevent assigning a bus number that already exists.
 488                  * This can happen when a bridge is hot-plugged */
 489                 if (pci_find_bus(pci_domain_nr(bus), max+1))
 490                         return max;
 491                 child = pci_add_new_bus(bus, dev, ++max);
 492                 buses = (buses & 0xff000000)
 493                       | ((unsigned int)(child->primary)     <<  0)
 494                       | ((unsigned int)(child->secondary)   <<  8)
 495                       | ((unsigned int)(child->subordinate) << 16);
 496
 497                 /*
 498                  * yenta.c forces a secondary latency timer of 176.
 499                  * Copy that behaviour here.
 500                  */
 501                 if (is_cardbus) {
 502                         buses &= ~0xff000000;
 503                         buses |= CARDBUS_LATENCY_TIMER << 24;
 504                 }
 505
 506                 /*
 507                  * We need to blast all three values with a single write.
 508                  */
 509                 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
 510
 511                 if (!is_cardbus) {
 512                         child->bridge_ctl = bctl | PCI_BRIDGE_CTL_NO_ISA;
 513                         /*
 514                          * Adjust subordinate busnr in parent buses.
 515                          * We do this before scanning for children because
 516                          * some devices may not be detected if the bios
 517                          * was lazy.
 518                          */
 519                         pci_fixup_parent_subordinate_busnr(child, max);
 520                         /* Now we can scan all subordinate buses... */
 521                         max = pci_scan_child_bus(child);
 522                 } else {
 523                         /*
 524                          * For CardBus bridges, we leave 4 bus numbers
 525                          * as cards with a PCI-to-PCI bridge can be
 526                          * inserted later.
 527                          */
 528                         for (i=0; i<CARDBUS_RESERVE_BUSNR; i++)
 529                                 if (pci_find_bus(pci_domain_nr(bus),
 530                                                         max+i+1))
 531                                         break;
 532                         max += i;
 533                         pci_fixup_parent_subordinate_busnr(child, max);
 534                 }
 535                 /*
 536                  * Set the subordinate bus number to its real value.
 537                  */
 538                 child->subordinate = max;
 539                 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
 540         }
 541
 542         pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
 543
 544         sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
 545
 546         return max;
 547 }
 548
 549 /*
 550  * Read interrupt line and base address registers.
 551  * The architecture-dependent code can tweak these, of course.
 552  */
 553 static void pci_read_irq(struct pci_dev *dev)
 554 {
 555         unsigned char irq;
 556
 557         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
 558         if (irq)
 559                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 560         dev->irq = irq;
 561 }
 562
 563 /**
 564  * pci_setup_device - fill in class and map information of a device
 565  * @dev: the device structure to fill
 566  *
 567  * Initialize the device structure with information about the device's
 568  * vendor,class,memory and IO-space addresses,IRQ lines etc.
 569  * Called at initialisation of the PCI subsystem and by CardBus services.
 570  * Returns 0 on success and -1 if unknown type of device (not normal, bridge
 571  * or CardBus).
 572  */
 573 static int pci_setup_device(struct pci_dev * dev)
 574 {
 575         u32 class;
 576
 577         sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
 578                 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
 579
 580         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
 581         class >>= 8;                                /* upper 3 bytes */
 582         dev->class = class;
 583         class >>= 8;
 584
 585         pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
 586                  dev->vendor, dev->device, class, dev->hdr_type);
 587
 588         /* "Unknown power state" */
 589         dev->current_state = PCI_UNKNOWN;
 590
 591         /* Early fixups, before probing the BARs */
 592         pci_fixup_device(pci_fixup_early, dev);
 593         class = dev->class >> 8;
 594
 595         switch (dev->hdr_type) {                    /* header type */
 596         case PCI_HEADER_TYPE_NORMAL:                /* standard header */
 597                 if (class == PCI_CLASS_BRIDGE_PCI)
 598                         goto bad;
 599                 pci_read_irq(dev);
 600                 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
 601                 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
 602                 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
 603                 break;
 604
 605         case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */
 606                 if (class != PCI_CLASS_BRIDGE_PCI)
 607                         goto bad;
 608                 /* The PCI-to-PCI bridge spec requires that subtractive
 609                    decoding (i.e. transparent) bridge must have programming
 610                    interface code of 0x01. */
 611                 dev->transparent = ((dev->class & 0xff) == 1);
 612                 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
 613                 break;
 614
 615         case PCI_HEADER_TYPE_CARDBUS:               /* CardBus bridge header */
 616                 if (class != PCI_CLASS_BRIDGE_CARDBUS)
 617                         goto bad;
 618                 pci_read_irq(dev);
 619                 pci_read_bases(dev, 1, 0);
 620                 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
 621                 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
 622                 break;
 623
 624         default:                                    /* unknown header */
 625                 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
 626                         pci_name(dev), dev->hdr_type);
 627                 return -1;
 628
 629         bad:
 630                 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
 631                        pci_name(dev), class, dev->hdr_type);
 632                 dev->class = PCI_CLASS_NOT_DEFINED;
 633         }
 634
 635         /* We found a fine healthy device, go go go... */
 636         return 0;
 637 }
 638
 639 /**
 640  * pci_release_dev - free a pci device structure when all users of it are finished.
 641  * @dev: device that's been disconnected
 642  *
 643  * Will be called only by the device core when all users of this pci device are
 644  * done.
 645  */
 646 static void pci_release_dev(struct device *dev)
 647 {
 648         struct pci_dev *pci_dev;
 649
 650         pci_dev = to_pci_dev(dev);
 651         kfree(pci_dev);
 652 }
 653
 654 /**
 655  * pci_cfg_space_size - get the configuration space size of the PCI device.
 656  *
 657  * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
 658  * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
 659  * access it.  Maybe we don't have a way to generate extended config space
 660  * accesses, or the device is behind a reverse Express bridge.  So we try
 661  * reading the dword at 0x100 which must either be 0 or a valid extended
 662  * capability header.
 663  */
 664 static int pci_cfg_space_size(struct pci_dev *dev)
 665 {
 666         int pos;
 667         u32 status;
 668
 669         pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
 670         if (!pos) {
 671                 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
 672                 if (!pos)
 673                         goto fail;
 674
 675                 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
 676                 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
 677                         goto fail;
 678         }
 679
 680         if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
 681                 goto fail;
 682         if (status == 0xffffffff)
 683                 goto fail;
 684
 685         return PCI_CFG_SPACE_EXP_SIZE;
 686
 687  fail:
 688         return PCI_CFG_SPACE_SIZE;
 689 }
 690
 691 static void pci_release_bus_bridge_dev(struct device *dev)
 692 {
 693         kfree(dev);
 694 }
 695
 696 /*
 697  * Read the config data for a PCI device, sanity-check it
 698  * and fill in the dev structure...
 699  */
 700 static struct pci_dev * __devinit
 701 pci_scan_device(struct pci_bus *bus, int devfn)
 702 {
 703         struct pci_dev *dev;
 704         u32 l;
 705         u8 hdr_type;
 706         int delay = 1;
 707
 708         if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
 709                 return NULL;
 710
 711         /* some broken boards return 0 or ~0 if a slot is empty: */
 712         if (l == 0xffffffff || l == 0x00000000 ||
 713             l == 0x0000ffff || l == 0xffff0000)
 714                 return NULL;
 715
 716         /* Configuration request Retry Status */
 717         while (l == 0xffff0001) {
 718                 msleep(delay);
 719                 delay *= 2;
 720                 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
 721                         return NULL;
 722                 /* Card hasn't responded in 60 seconds?  Must be stuck. */
 723                 if (delay > 60 * 1000) {
 724                         printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
 725                                         "responding\n", pci_domain_nr(bus),
 726                                         bus->number, PCI_SLOT(devfn),
 727                                         PCI_FUNC(devfn));
 728                         return NULL;
 729                 }
 730         }
 731
 732         if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
 733                 return NULL;
 734
 735         dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
 736         if (!dev)
 737                 return NULL;
 738
 739         memset(dev, 0, sizeof(struct pci_dev));
 740         dev->bus = bus;
 741         dev->sysdata = bus->sysdata;
 742         dev->dev.parent = bus->bridge;
 743         dev->dev.bus = &pci_bus_type;
 744         dev->devfn = devfn;
 745         dev->hdr_type = hdr_type & 0x7f;
 746         dev->multifunction = !!(hdr_type & 0x80);
 747         dev->vendor = l & 0xffff;
 748         dev->device = (l >> 16) & 0xffff;
 749         dev->cfg_size = pci_cfg_space_size(dev);
 750
 751         /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
 752            set this higher, assuming the system even supports it.  */
 753         dev->dma_mask = 0xffffffff;
 754         if (pci_setup_device(dev) < 0) {
 755                 kfree(dev);
 756                 return NULL;
 757         }
 758
 759         return dev;
 760 }
 761
 762 void __devinit pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
 763 {
 764         device_initialize(&dev->dev);
 765         dev->dev.release = pci_release_dev;
 766         pci_dev_get(dev);
 767
 768         dev->dev.dma_mask = &dev->dma_mask;
 769         dev->dev.coherent_dma_mask = 0xffffffffull;
 770
 771         /* Fix up broken headers */
 772         pci_fixup_device(pci_fixup_header, dev);
 773
 774         /*
 775          * Add the device to our list of discovered devices
 776          * and the bus list for fixup functions, etc.
 777          */
 778         INIT_LIST_HEAD(&dev->global_list);
 779         spin_lock(&pci_bus_lock);
 780         list_add_tail(&dev->bus_list, &bus->devices);
 781         spin_unlock(&pci_bus_lock);
 782 }
 783
 784 struct pci_dev * __devinit
 785 pci_scan_single_device(struct pci_bus *bus, int devfn)
 786 {
 787         struct pci_dev *dev;
 788
 789         dev = pci_scan_device(bus, devfn);
 790         if (!dev)
 791                 return NULL;
 792
 793         pci_device_add(dev, bus);
 794         pci_scan_msi_device(dev);
 795
 796         return dev;
 797 }
 798
 799 /**
 800  * pci_scan_slot - scan a PCI slot on a bus for devices.
 801  * @bus: PCI bus to scan
 802  * @devfn: slot number to scan (must have zero function.)
 803  *
 804  * Scan a PCI slot on the specified PCI bus for devices, adding
 805  * discovered devices to the @bus->devices list.  New devices
 806  * will have an empty dev->global_list head.
 807  */
 808 int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
 809 {
 810         int func, nr = 0;
 811         int scan_all_fns;
 812
 813         scan_all_fns = pcibios_scan_all_fns(bus, devfn);
 814
 815         for (func = 0; func < 8; func++, devfn++) {
 816                 struct pci_dev *dev;
 817
 818                 dev = pci_scan_single_device(bus, devfn);
 819                 if (dev) {
 820                         nr++;
 821
 822                         /*
 823                          * If this is a single function device,
 824                          * don't scan past the first function.
 825                          */
 826                         if (!dev->multifunction) {
 827                                 if (func > 0) {
 828                                         dev->multifunction = 1;
 829                                 } else {
 830                                         break;
 831                                 }
 832                         }
 833                 } else {
 834                         if (func == 0 && !scan_all_fns)
 835                                 break;
 836                 }
 837         }
 838         return nr;
 839 }
 840
 841 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
 842 {
 843         unsigned int devfn, pass, max = bus->secondary;
 844         struct pci_dev *dev;
 845
 846         pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
 847
 848         /* Go find them, Rover! */
 849         for (devfn = 0; devfn < 0x100; devfn += 8)
 850                 pci_scan_slot(bus, devfn);
 851
 852         /*
 853          * After performing arch-dependent fixup of the bus, look behind
 854          * all PCI-to-PCI bridges on this bus.
 855          */
 856         pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
 857         pcibios_fixup_bus(bus);
 858         for (pass=0; pass < 2; pass++)
 859                 list_for_each_entry(dev, &bus->devices, bus_list) {
 860                         if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
 861                             dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
 862                                 max = pci_scan_bridge(bus, dev, max, pass);
 863                 }
 864
 865         /*
 866          * We've scanned the bus and so we know all about what's on
 867          * the other side of any bridges that may be on this bus plus
 868          * any devices.
 869          *
 870          * Return how far we've got finding sub-buses.
 871          */
 872         pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
 873                 pci_domain_nr(bus), bus->number, max);
 874         return max;
 875 }
 876
 877 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
 878 {
 879         unsigned int max;
 880
 881         max = pci_scan_child_bus(bus);
 882
 883         /*
 884          * Make the discovered devices available.
 885          */
 886         pci_bus_add_devices(bus);
 887
 888         return max;
 889 }
 890
 891 struct pci_bus * __devinit pci_create_bus(struct device *parent,
 892                 int bus, struct pci_ops *ops, void *sysdata)
 893 {
 894         int error;
 895         struct pci_bus *b;
 896         struct device *dev;
 897
 898         b = pci_alloc_bus();
 899         if (!b)
 900                 return NULL;
 901
 902         dev = kmalloc(sizeof(*dev), GFP_KERNEL);
 903         if (!dev){
 904                 kfree(b);
 905                 return NULL;
 906         }
 907
 908         b->sysdata = sysdata;
 909         b->ops = ops;
 910
 911         if (pci_find_bus(pci_domain_nr(b), bus)) {
 912                 /* If we already got to this bus through a different bridge, ignore it */
 913                 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
 914                 goto err_out;
 915         }
 916         spin_lock(&pci_bus_lock);
 917         list_add_tail(&b->node, &pci_root_buses);
 918         spin_unlock(&pci_bus_lock);
 919
 920         memset(dev, 0, sizeof(*dev));
 921         dev->parent = parent;
 922         dev->release = pci_release_bus_bridge_dev;
 923         sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
 924         error = device_register(dev);
 925         if (error)
 926                 goto dev_reg_err;
 927         b->bridge = get_device(dev);
 928
 929         b->class_dev.class = &pcibus_class;
 930         sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
 931         error = class_device_register(&b->class_dev);
 932         if (error)
 933                 goto class_dev_reg_err;
 934         error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
 935         if (error)
 936                 goto class_dev_create_file_err;
 937
 938         /* Create legacy_io and legacy_mem files for this bus */
 939         pci_create_legacy_files(b);
 940
 941         error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
 942         if (error)
 943                 goto sys_create_link_err;
 944
 945         b->number = b->secondary = bus;
 946         b->resource[0] = &ioport_resource;
 947         b->resource[1] = &iomem_resource;
 948
 949         return b;
 950
 951 sys_create_link_err:
 952         class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
 953 class_dev_create_file_err:
 954         class_device_unregister(&b->class_dev);
 955 class_dev_reg_err:
 956         device_unregister(dev);
 957 dev_reg_err:
 958         spin_lock(&pci_bus_lock);
 959         list_del(&b->node);
 960         spin_unlock(&pci_bus_lock);
 961 err_out:
 962         kfree(dev);
 963         kfree(b);
 964         return NULL;
 965 }
 966 EXPORT_SYMBOL_GPL(pci_create_bus);
 967
 968 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
 969                 int bus, struct pci_ops *ops, void *sysdata)
 970 {
 971         struct pci_bus *b;
 972
 973         b = pci_create_bus(parent, bus, ops, sysdata);
 974         if (b)
 975                 b->subordinate = pci_scan_child_bus(b);
 976         return b;
 977 }
 978 EXPORT_SYMBOL(pci_scan_bus_parented);
 979
 980 #ifdef CONFIG_HOTPLUG
 981 EXPORT_SYMBOL(pci_add_new_bus);
 982 EXPORT_SYMBOL(pci_do_scan_bus);
 983 EXPORT_SYMBOL(pci_scan_slot);
 984 EXPORT_SYMBOL(pci_scan_bridge);
 985 EXPORT_SYMBOL(pci_scan_single_device);
 986 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
 987 #endif