arch/x86/include/asm/apic.h

   1 #ifndef _ASM_X86_APIC_H
   2 #define _ASM_X86_APIC_H
   3
   4 #include <linux/cpumask.h>
   5 #include <linux/delay.h>
   6 #include <linux/pm.h>
   7
   8 #include <asm/alternative.h>
   9 #include <asm/cpufeature.h>
  10 #include <asm/processor.h>
  11 #include <asm/apicdef.h>
  12 #include <asm/atomic.h>
  13 #include <asm/fixmap.h>
  14 #include <asm/mpspec.h>
  15 #include <asm/system.h>
  16 #include <asm/msr.h>
  17
  18 #define ARCH_APICTIMER_STOPS_ON_C3      1
  19
  20 /*
  21  * Debugging macros
  22  */
  23 #define APIC_QUIET   0
  24 #define APIC_VERBOSE 1
  25 #define APIC_DEBUG   2
  26
  27 /*
  28  * Define the default level of output to be very little
  29  * This can be turned up by using apic=verbose for more
  30  * information and apic=debug for _lots_ of information.
  31  * apic_verbosity is defined in apic.c
  32  */
  33 #define apic_printk(v, s, a...) do {       \
  34                 if ((v) <= apic_verbosity) \
  35                         printk(s, ##a);    \
  36         } while (0)
  37
  38
  39 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
  40 extern void generic_apic_probe(void);
  41 #else
  42 static inline void generic_apic_probe(void)
  43 {
  44 }
  45 #endif
  46
  47 #ifdef CONFIG_X86_LOCAL_APIC
  48
  49 extern unsigned int apic_verbosity;
  50 extern int local_apic_timer_c2_ok;
  51
  52 extern int disable_apic;
  53
  54 #ifdef CONFIG_SMP
  55 extern void __inquire_remote_apic(int apicid);
  56 #else /* CONFIG_SMP */
  57 static inline void __inquire_remote_apic(int apicid)
  58 {
  59 }
  60 #endif /* CONFIG_SMP */
  61
  62 static inline void default_inquire_remote_apic(int apicid)
  63 {
  64         if (apic_verbosity >= APIC_DEBUG)
  65                 __inquire_remote_apic(apicid);
  66 }
  67
  68 /*
  69  * Basic functions accessing APICs.
  70  */
  71 #ifdef CONFIG_PARAVIRT
  72 #include <asm/paravirt.h>
  73 #else
  74 #define setup_boot_clock setup_boot_APIC_clock
  75 #define setup_secondary_clock setup_secondary_APIC_clock
  76 #endif
  77
  78 #ifdef CONFIG_X86_64
  79 extern int is_vsmp_box(void);
  80 #else
  81 static inline int is_vsmp_box(void)
  82 {
  83         return 0;
  84 }
  85 #endif
  86 extern void xapic_wait_icr_idle(void);
  87 extern u32 safe_xapic_wait_icr_idle(void);
  88 extern void xapic_icr_write(u32, u32);
  89 extern int setup_profiling_timer(unsigned int);
  90
  91 static inline void native_apic_mem_write(u32 reg, u32 v)
  92 {
  93         volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
  94
  95         alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
  96                        ASM_OUTPUT2("=r" (v), "=m" (*addr)),
  97                        ASM_OUTPUT2("0" (v), "m" (*addr)));
  98 }
  99
 100 static inline u32 native_apic_mem_read(u32 reg)
 101 {
 102         return *((volatile u32 *)(APIC_BASE + reg));
 103 }
 104
 105 extern void native_apic_wait_icr_idle(void);
 106 extern u32 native_safe_apic_wait_icr_idle(void);
 107 extern void native_apic_icr_write(u32 low, u32 id);
 108 extern u64 native_apic_icr_read(void);
 109
 110 #define EIM_8BIT_APIC_ID        0
 111 #define EIM_32BIT_APIC_ID       1
 112
 113 #ifdef CONFIG_X86_X2APIC
 114 /*
 115  * Make previous memory operations globally visible before
 116  * sending the IPI through x2apic wrmsr. We need a serializing instruction or
 117  * mfence for this.
 118  */
 119 static inline void x2apic_wrmsr_fence(void)
 120 {
 121         asm volatile("mfence" : : : "memory");
 122 }
 123
 124 static inline void native_apic_msr_write(u32 reg, u32 v)
 125 {
 126         if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
 127             reg == APIC_LVR)
 128                 return;
 129
 130         wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
 131 }
 132
 133 static inline u32 native_apic_msr_read(u32 reg)
 134 {
 135         u32 low, high;
 136
 137         if (reg == APIC_DFR)
 138                 return -1;
 139
 140         rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
 141         return low;
 142 }
 143
 144 static inline void native_x2apic_wait_icr_idle(void)
 145 {
 146         /* no need to wait for icr idle in x2apic */
 147         return;
 148 }
 149
 150 static inline u32 native_safe_x2apic_wait_icr_idle(void)
 151 {
 152         /* no need to wait for icr idle in x2apic */
 153         return 0;
 154 }
 155
 156 static inline void native_x2apic_icr_write(u32 low, u32 id)
 157 {
 158         wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
 159 }
 160
 161 static inline u64 native_x2apic_icr_read(void)
 162 {
 163         unsigned long val;
 164
 165         rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
 166         return val;
 167 }
 168
 169 extern int x2apic, x2apic_phys;
 170 extern void check_x2apic(void);
 171 extern void enable_x2apic(void);
 172 extern void enable_IR_x2apic(void);
 173 extern void x2apic_icr_write(u32 low, u32 id);
 174 static inline int x2apic_enabled(void)
 175 {
 176         int msr, msr2;
 177
 178         if (!cpu_has_x2apic)
 179                 return 0;
 180
 181         rdmsr(MSR_IA32_APICBASE, msr, msr2);
 182         if (msr & X2APIC_ENABLE)
 183                 return 1;
 184         return 0;
 185 }
 186 #else
 187 static inline void check_x2apic(void)
 188 {
 189 }
 190 static inline void enable_x2apic(void)
 191 {
 192 }
 193 static inline void enable_IR_x2apic(void)
 194 {
 195 }
 196 static inline int x2apic_enabled(void)
 197 {
 198         return 0;
 199 }
 200
 201 #define x2apic  0
 202
 203 #endif
 204
 205 extern int get_physical_broadcast(void);
 206
 207 #ifdef CONFIG_X86_X2APIC
 208 static inline void ack_x2APIC_irq(void)
 209 {
 210         /* Docs say use 0 for future compatibility */
 211         native_apic_msr_write(APIC_EOI, 0);
 212 }
 213 #endif
 214
 215 extern int lapic_get_maxlvt(void);
 216 extern void clear_local_APIC(void);
 217 extern void connect_bsp_APIC(void);
 218 extern void disconnect_bsp_APIC(int virt_wire_setup);
 219 extern void disable_local_APIC(void);
 220 extern void lapic_shutdown(void);
 221 extern int verify_local_APIC(void);
 222 extern void cache_APIC_registers(void);
 223 extern void sync_Arb_IDs(void);
 224 extern void init_bsp_APIC(void);
 225 extern void setup_local_APIC(void);
 226 extern void end_local_APIC_setup(void);
 227 extern void init_apic_mappings(void);
 228 extern void setup_boot_APIC_clock(void);
 229 extern void setup_secondary_APIC_clock(void);
 230 extern int APIC_init_uniprocessor(void);
 231 extern void enable_NMI_through_LVT0(void);
 232
 233 /*
 234  * On 32bit this is mach-xxx local
 235  */
 236 #ifdef CONFIG_X86_64
 237 extern void early_init_lapic_mapping(void);
 238 extern int apic_is_clustered_box(void);
 239 #else
 240 static inline int apic_is_clustered_box(void)
 241 {
 242         return 0;
 243 }
 244 #endif
 245
 246 extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
 247 extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
 248
 249
 250 #else /* !CONFIG_X86_LOCAL_APIC */
 251 static inline void lapic_shutdown(void) { }
 252 #define local_apic_timer_c2_ok          1
 253 static inline void init_apic_mappings(void) { }
 254 static inline void disable_local_APIC(void) { }
 255
 256 #endif /* !CONFIG_X86_LOCAL_APIC */
 257
 258 #ifdef CONFIG_X86_64
 259 #define SET_APIC_ID(x)          (apic->set_apic_id(x))
 260 #else
 261
 262 #endif
 263
 264 /*
 265  * Copyright 2004 James Cleverdon, IBM.
 266  * Subject to the GNU Public License, v.2
 267  *
 268  * Generic APIC sub-arch data struct.
 269  *
 270  * Hacked for x86-64 by James Cleverdon from i386 architecture code by
 271  * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
 272  * James Cleverdon.
 273  */
 274 struct apic {
 275         char *name;
 276
 277         int (*probe)(void);
 278         int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
 279         int (*apic_id_registered)(void);
 280
 281         u32 irq_delivery_mode;
 282         u32 irq_dest_mode;
 283
 284         const struct cpumask *(*target_cpus)(void);
 285
 286         int disable_esr;
 287
 288         int dest_logical;
 289         unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid);
 290         unsigned long (*check_apicid_present)(int apicid);
 291
 292         void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
 293         void (*init_apic_ldr)(void);
 294
 295         physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map);
 296
 297         void (*setup_apic_routing)(void);
 298         int (*multi_timer_check)(int apic, int irq);
 299         int (*apicid_to_node)(int logical_apicid);
 300         int (*cpu_to_logical_apicid)(int cpu);
 301         int (*cpu_present_to_apicid)(int mps_cpu);
 302         physid_mask_t (*apicid_to_cpu_present)(int phys_apicid);
 303         void (*setup_portio_remap)(void);
 304         int (*check_phys_apicid_present)(int boot_cpu_physical_apicid);
 305         void (*enable_apic_mode)(void);
 306         int (*phys_pkg_id)(int cpuid_apic, int index_msb);
 307
 308         /*
 309          * When one of the next two hooks returns 1 the apic
 310          * is switched to this. Essentially they are additional
 311          * probe functions:
 312          */
 313         int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
 314
 315         unsigned int (*get_apic_id)(unsigned long x);
 316         unsigned long (*set_apic_id)(unsigned int id);
 317         unsigned long apic_id_mask;
 318
 319         unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
 320         unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
 321                                                const struct cpumask *andmask);
 322
 323         /* ipi */
 324         void (*send_IPI_mask)(const struct cpumask *mask, int vector);
 325         void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
 326                                          int vector);
 327         void (*send_IPI_allbutself)(int vector);
 328         void (*send_IPI_all)(int vector);
 329         void (*send_IPI_self)(int vector);
 330
 331         /* wakeup_secondary_cpu */
 332         int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
 333
 334         int trampoline_phys_low;
 335         int trampoline_phys_high;
 336
 337         void (*wait_for_init_deassert)(atomic_t *deassert);
 338         void (*smp_callin_clear_local_apic)(void);
 339         void (*inquire_remote_apic)(int apicid);
 340
 341         /* apic ops */
 342         u32 (*read)(u32 reg);
 343         void (*write)(u32 reg, u32 v);
 344         u64 (*icr_read)(void);
 345         void (*icr_write)(u32 low, u32 high);
 346         void (*wait_icr_idle)(void);
 347         u32 (*safe_wait_icr_idle)(void);
 348 };
 349
 350 /*
 351  * Pointer to the local APIC driver in use on this system (there's
 352  * always just one such driver in use - the kernel decides via an
 353  * early probing process which one it picks - and then sticks to it):
 354  */
 355 extern struct apic *apic;
 356
 357 /*
 358  * APIC functionality to boot other CPUs - only used on SMP:
 359  */
 360 #ifdef CONFIG_SMP
 361 extern atomic_t init_deasserted;
 362 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
 363 #endif
 364
 365 static inline u32 apic_read(u32 reg)
 366 {
 367         return apic->read(reg);
 368 }
 369
 370 static inline void apic_write(u32 reg, u32 val)
 371 {
 372         apic->write(reg, val);
 373 }
 374
 375 static inline u64 apic_icr_read(void)
 376 {
 377         return apic->icr_read();
 378 }
 379
 380 static inline void apic_icr_write(u32 low, u32 high)
 381 {
 382         apic->icr_write(low, high);
 383 }
 384
 385 static inline void apic_wait_icr_idle(void)
 386 {
 387         apic->wait_icr_idle();
 388 }
 389
 390 static inline u32 safe_apic_wait_icr_idle(void)
 391 {
 392         return apic->safe_wait_icr_idle();
 393 }
 394
 395
 396 static inline void ack_APIC_irq(void)
 397 {
 398 #ifdef CONFIG_X86_LOCAL_APIC
 399         /*
 400          * ack_APIC_irq() actually gets compiled as a single instruction
 401          * ... yummie.
 402          */
 403
 404         /* Docs say use 0 for future compatibility */
 405         apic_write(APIC_EOI, 0);
 406 #endif
 407 }
 408
 409 static inline unsigned default_get_apic_id(unsigned long x)
 410 {
 411         unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
 412
 413         if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
 414                 return (x >> 24) & 0xFF;
 415         else
 416                 return (x >> 24) & 0x0F;
 417 }
 418
 419 /*
 420  * Warm reset vector default position:
 421  */
 422 #define DEFAULT_TRAMPOLINE_PHYS_LOW             0x467
 423 #define DEFAULT_TRAMPOLINE_PHYS_HIGH            0x469
 424
 425 #ifdef CONFIG_X86_64
 426 extern struct apic apic_flat;
 427 extern struct apic apic_physflat;
 428 extern struct apic apic_x2apic_cluster;
 429 extern struct apic apic_x2apic_phys;
 430 extern int default_acpi_madt_oem_check(char *, char *);
 431
 432 extern void apic_send_IPI_self(int vector);
 433
 434 extern struct apic apic_x2apic_uv_x;
 435 DECLARE_PER_CPU(int, x2apic_extra_bits);
 436
 437 extern int default_cpu_present_to_apicid(int mps_cpu);
 438 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
 439 #endif
 440
 441 static inline void default_wait_for_init_deassert(atomic_t *deassert)
 442 {
 443         while (!atomic_read(deassert))
 444                 cpu_relax();
 445         return;
 446 }
 447
 448 extern void generic_bigsmp_probe(void);
 449
 450
 451 #ifdef CONFIG_X86_LOCAL_APIC
 452
 453 #include <asm/smp.h>
 454
 455 #define APIC_DFR_VALUE  (APIC_DFR_FLAT)
 456
 457 static inline const struct cpumask *default_target_cpus(void)
 458 {
 459 #ifdef CONFIG_SMP
 460         return cpu_online_mask;
 461 #else
 462         return cpumask_of(0);
 463 #endif
 464 }
 465
 466 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
 467
 468
 469 static inline unsigned int read_apic_id(void)
 470 {
 471         unsigned int reg;
 472
 473         reg = apic_read(APIC_ID);
 474
 475         return apic->get_apic_id(reg);
 476 }
 477
 478 extern void default_setup_apic_routing(void);
 479
 480 #ifdef CONFIG_X86_32
 481 /*
 482  * Set up the logical destination ID.
 483  *
 484  * Intel recommends to set DFR, LDR and TPR before enabling
 485  * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
 486  * document number 292116).  So here it goes...
 487  */
 488 extern void default_init_apic_ldr(void);
 489
 490 static inline int default_apic_id_registered(void)
 491 {
 492         return physid_isset(read_apic_id(), phys_cpu_present_map);
 493 }
 494
 495 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
 496 {
 497         return cpuid_apic >> index_msb;
 498 }
 499
 500 extern int default_apicid_to_node(int logical_apicid);
 501
 502 #endif
 503
 504 static inline unsigned int
 505 default_cpu_mask_to_apicid(const struct cpumask *cpumask)
 506 {
 507         return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
 508 }
 509
 510 static inline unsigned int
 511 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 512                                const struct cpumask *andmask)
 513 {
 514         unsigned long mask1 = cpumask_bits(cpumask)[0];
 515         unsigned long mask2 = cpumask_bits(andmask)[0];
 516         unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
 517
 518         return (unsigned int)(mask1 & mask2 & mask3);
 519 }
 520
 521 static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
 522 {
 523         return physid_isset(apicid, bitmap);
 524 }
 525
 526 static inline unsigned long default_check_apicid_present(int bit)
 527 {
 528         return physid_isset(bit, phys_cpu_present_map);
 529 }
 530
 531 static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map)
 532 {
 533         return phys_map;
 534 }
 535
 536 /* Mapping from cpu number to logical apicid */
 537 static inline int default_cpu_to_logical_apicid(int cpu)
 538 {
 539         return 1 << cpu;
 540 }
 541
 542 static inline int __default_cpu_present_to_apicid(int mps_cpu)
 543 {
 544         if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
 545                 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
 546         else
 547                 return BAD_APICID;
 548 }
 549
 550 static inline int
 551 __default_check_phys_apicid_present(int boot_cpu_physical_apicid)
 552 {
 553         return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
 554 }
 555
 556 #ifdef CONFIG_X86_32
 557 static inline int default_cpu_present_to_apicid(int mps_cpu)
 558 {
 559         return __default_cpu_present_to_apicid(mps_cpu);
 560 }
 561
 562 static inline int
 563 default_check_phys_apicid_present(int boot_cpu_physical_apicid)
 564 {
 565         return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
 566 }
 567 #else
 568 extern int default_cpu_present_to_apicid(int mps_cpu);
 569 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
 570 #endif
 571
 572 static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid)
 573 {
 574         return physid_mask_of_physid(phys_apicid);
 575 }
 576
 577 #endif /* CONFIG_X86_LOCAL_APIC */
 578
 579 #ifdef CONFIG_X86_32
 580 extern u8 cpu_2_logical_apicid[NR_CPUS];
 581 #endif
 582
 583 #endif /* _ASM_X86_APIC_H */