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fix typos concerning "initiali[zs]e"
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / scsi / pm8001 / pm8001_hwi.c
blobe81efac25fa42dbce5ca91c398ac8e10ed71a560
1 /*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm8001_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46 /**
47 * read_main_config_table - read the configure table and save it.
48 * @pm8001_ha: our hba card information
49 */
50 static void __devinit read_main_config_table(struct pm8001_hba_info *pm8001_ha)
51 {
52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
53 pm8001_ha->main_cfg_tbl.signature = pm8001_mr32(address, 0x00);
54 pm8001_ha->main_cfg_tbl.interface_rev = pm8001_mr32(address, 0x04);
55 pm8001_ha->main_cfg_tbl.firmware_rev = pm8001_mr32(address, 0x08);
56 pm8001_ha->main_cfg_tbl.max_out_io = pm8001_mr32(address, 0x0C);
57 pm8001_ha->main_cfg_tbl.max_sgl = pm8001_mr32(address, 0x10);
58 pm8001_ha->main_cfg_tbl.ctrl_cap_flag = pm8001_mr32(address, 0x14);
59 pm8001_ha->main_cfg_tbl.gst_offset = pm8001_mr32(address, 0x18);
60 pm8001_ha->main_cfg_tbl.inbound_queue_offset =
61 pm8001_mr32(address, MAIN_IBQ_OFFSET);
62 pm8001_ha->main_cfg_tbl.outbound_queue_offset =
63 pm8001_mr32(address, MAIN_OBQ_OFFSET);
64 pm8001_ha->main_cfg_tbl.hda_mode_flag =
65 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
66
67 /* read analog Setting offset from the configuration table */
68 pm8001_ha->main_cfg_tbl.anolog_setup_table_offset =
69 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
70
71 /* read Error Dump Offset and Length */
72 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset0 =
73 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
74 pm8001_ha->main_cfg_tbl.fatal_err_dump_length0 =
75 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
76 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset1 =
77 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
78 pm8001_ha->main_cfg_tbl.fatal_err_dump_length1 =
79 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
80 }
81
82 /**
83 * read_general_status_table - read the general status table and save it.
84 * @pm8001_ha: our hba card information
85 */
86 static void __devinit
87 read_general_status_table(struct pm8001_hba_info *pm8001_ha)
88 {
89 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
90 pm8001_ha->gs_tbl.gst_len_mpistate = pm8001_mr32(address, 0x00);
91 pm8001_ha->gs_tbl.iq_freeze_state0 = pm8001_mr32(address, 0x04);
92 pm8001_ha->gs_tbl.iq_freeze_state1 = pm8001_mr32(address, 0x08);
93 pm8001_ha->gs_tbl.msgu_tcnt = pm8001_mr32(address, 0x0C);
94 pm8001_ha->gs_tbl.iop_tcnt = pm8001_mr32(address, 0x10);
95 pm8001_ha->gs_tbl.reserved = pm8001_mr32(address, 0x14);
96 pm8001_ha->gs_tbl.phy_state[0] = pm8001_mr32(address, 0x18);
97 pm8001_ha->gs_tbl.phy_state[1] = pm8001_mr32(address, 0x1C);
98 pm8001_ha->gs_tbl.phy_state[2] = pm8001_mr32(address, 0x20);
99 pm8001_ha->gs_tbl.phy_state[3] = pm8001_mr32(address, 0x24);
100 pm8001_ha->gs_tbl.phy_state[4] = pm8001_mr32(address, 0x28);
101 pm8001_ha->gs_tbl.phy_state[5] = pm8001_mr32(address, 0x2C);
102 pm8001_ha->gs_tbl.phy_state[6] = pm8001_mr32(address, 0x30);
103 pm8001_ha->gs_tbl.phy_state[7] = pm8001_mr32(address, 0x34);
104 pm8001_ha->gs_tbl.reserved1 = pm8001_mr32(address, 0x38);
105 pm8001_ha->gs_tbl.reserved2 = pm8001_mr32(address, 0x3C);
106 pm8001_ha->gs_tbl.reserved3 = pm8001_mr32(address, 0x40);
107 pm8001_ha->gs_tbl.recover_err_info[0] = pm8001_mr32(address, 0x44);
108 pm8001_ha->gs_tbl.recover_err_info[1] = pm8001_mr32(address, 0x48);
109 pm8001_ha->gs_tbl.recover_err_info[2] = pm8001_mr32(address, 0x4C);
110 pm8001_ha->gs_tbl.recover_err_info[3] = pm8001_mr32(address, 0x50);
111 pm8001_ha->gs_tbl.recover_err_info[4] = pm8001_mr32(address, 0x54);
112 pm8001_ha->gs_tbl.recover_err_info[5] = pm8001_mr32(address, 0x58);
113 pm8001_ha->gs_tbl.recover_err_info[6] = pm8001_mr32(address, 0x5C);
114 pm8001_ha->gs_tbl.recover_err_info[7] = pm8001_mr32(address, 0x60);
115 }
116
117 /**
118 * read_inbnd_queue_table - read the inbound queue table and save it.
119 * @pm8001_ha: our hba card information
120 */
121 static void __devinit
122 read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
123 {
124 int inbQ_num = 1;
125 int i;
126 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
127 for (i = 0; i < inbQ_num; i++) {
128 u32 offset = i * 0x20;
129 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
130 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
131 pm8001_ha->inbnd_q_tbl[i].pi_offset =
132 pm8001_mr32(address, (offset + 0x18));
133 }
134 }
135
136 /**
137 * read_outbnd_queue_table - read the outbound queue table and save it.
138 * @pm8001_ha: our hba card information
139 */
140 static void __devinit
141 read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
142 {
143 int outbQ_num = 1;
144 int i;
145 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
146 for (i = 0; i < outbQ_num; i++) {
147 u32 offset = i * 0x24;
148 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
149 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
150 pm8001_ha->outbnd_q_tbl[i].ci_offset =
151 pm8001_mr32(address, (offset + 0x18));
152 }
153 }
154
155 /**
156 * init_default_table_values - init the default table.
157 * @pm8001_ha: our hba card information
158 */
159 static void __devinit
160 init_default_table_values(struct pm8001_hba_info *pm8001_ha)
161 {
162 int qn = 1;
163 int i;
164 u32 offsetib, offsetob;
165 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
166 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
167
168 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd = 0;
169 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3 = 0;
170 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7 = 0;
171 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3 = 0;
172 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7 = 0;
173 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3 = 0;
174 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7 = 0;
175 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
176 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
177 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3 = 0;
178 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7 = 0;
179
180 pm8001_ha->main_cfg_tbl.upper_event_log_addr =
181 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
182 pm8001_ha->main_cfg_tbl.lower_event_log_addr =
183 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
184 pm8001_ha->main_cfg_tbl.event_log_size = PM8001_EVENT_LOG_SIZE;
185 pm8001_ha->main_cfg_tbl.event_log_option = 0x01;
186 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr =
187 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
188 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr =
189 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
190 pm8001_ha->main_cfg_tbl.iop_event_log_size = PM8001_EVENT_LOG_SIZE;
191 pm8001_ha->main_cfg_tbl.iop_event_log_option = 0x01;
192 pm8001_ha->main_cfg_tbl.fatal_err_interrupt = 0x01;
193 for (i = 0; i < qn; i++) {
194 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
195 0x00000100 | (0x00000040 << 16) | (0x00<<30);
196 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
197 pm8001_ha->memoryMap.region[IB].phys_addr_hi;
198 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
199 pm8001_ha->memoryMap.region[IB].phys_addr_lo;
200 pm8001_ha->inbnd_q_tbl[i].base_virt =
201 (u8 *)pm8001_ha->memoryMap.region[IB].virt_ptr;
202 pm8001_ha->inbnd_q_tbl[i].total_length =
203 pm8001_ha->memoryMap.region[IB].total_len;
204 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
205 pm8001_ha->memoryMap.region[CI].phys_addr_hi;
206 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
207 pm8001_ha->memoryMap.region[CI].phys_addr_lo;
208 pm8001_ha->inbnd_q_tbl[i].ci_virt =
209 pm8001_ha->memoryMap.region[CI].virt_ptr;
210 offsetib = i * 0x20;
211 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
212 get_pci_bar_index(pm8001_mr32(addressib,
213 (offsetib + 0x14)));
214 pm8001_ha->inbnd_q_tbl[i].pi_offset =
215 pm8001_mr32(addressib, (offsetib + 0x18));
216 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
217 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
218 }
219 for (i = 0; i < qn; i++) {
220 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
221 256 | (64 << 16) | (1<<30);
222 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
223 pm8001_ha->memoryMap.region[OB].phys_addr_hi;
224 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
225 pm8001_ha->memoryMap.region[OB].phys_addr_lo;
226 pm8001_ha->outbnd_q_tbl[i].base_virt =
227 (u8 *)pm8001_ha->memoryMap.region[OB].virt_ptr;
228 pm8001_ha->outbnd_q_tbl[i].total_length =
229 pm8001_ha->memoryMap.region[OB].total_len;
230 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
231 pm8001_ha->memoryMap.region[PI].phys_addr_hi;
232 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
233 pm8001_ha->memoryMap.region[PI].phys_addr_lo;
234 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay =
235 0 | (10 << 16) | (0 << 24);
236 pm8001_ha->outbnd_q_tbl[i].pi_virt =
237 pm8001_ha->memoryMap.region[PI].virt_ptr;
238 offsetob = i * 0x24;
239 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
240 get_pci_bar_index(pm8001_mr32(addressob,
241 offsetob + 0x14));
242 pm8001_ha->outbnd_q_tbl[i].ci_offset =
243 pm8001_mr32(addressob, (offsetob + 0x18));
244 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
245 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
246 }
247 }
248
249 /**
250 * update_main_config_table - update the main default table to the HBA.
251 * @pm8001_ha: our hba card information
252 */
253 static void __devinit
254 update_main_config_table(struct pm8001_hba_info *pm8001_ha)
255 {
256 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
257 pm8001_mw32(address, 0x24,
258 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd);
259 pm8001_mw32(address, 0x28,
260 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3);
261 pm8001_mw32(address, 0x2C,
262 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7);
263 pm8001_mw32(address, 0x30,
264 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3);
265 pm8001_mw32(address, 0x34,
266 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7);
267 pm8001_mw32(address, 0x38,
268 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3);
269 pm8001_mw32(address, 0x3C,
270 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7);
271 pm8001_mw32(address, 0x40,
272 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3);
273 pm8001_mw32(address, 0x44,
274 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7);
275 pm8001_mw32(address, 0x48,
276 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3);
277 pm8001_mw32(address, 0x4C,
278 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7);
279 pm8001_mw32(address, 0x50,
280 pm8001_ha->main_cfg_tbl.upper_event_log_addr);
281 pm8001_mw32(address, 0x54,
282 pm8001_ha->main_cfg_tbl.lower_event_log_addr);
283 pm8001_mw32(address, 0x58, pm8001_ha->main_cfg_tbl.event_log_size);
284 pm8001_mw32(address, 0x5C, pm8001_ha->main_cfg_tbl.event_log_option);
285 pm8001_mw32(address, 0x60,
286 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr);
287 pm8001_mw32(address, 0x64,
288 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr);
289 pm8001_mw32(address, 0x68, pm8001_ha->main_cfg_tbl.iop_event_log_size);
290 pm8001_mw32(address, 0x6C,
291 pm8001_ha->main_cfg_tbl.iop_event_log_option);
292 pm8001_mw32(address, 0x70,
293 pm8001_ha->main_cfg_tbl.fatal_err_interrupt);
294 }
295
296 /**
297 * update_inbnd_queue_table - update the inbound queue table to the HBA.
298 * @pm8001_ha: our hba card information
299 */
300 static void __devinit
301 update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
302 {
303 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
304 u16 offset = number * 0x20;
305 pm8001_mw32(address, offset + 0x00,
306 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
307 pm8001_mw32(address, offset + 0x04,
308 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
309 pm8001_mw32(address, offset + 0x08,
310 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
311 pm8001_mw32(address, offset + 0x0C,
312 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
313 pm8001_mw32(address, offset + 0x10,
314 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
315 }
316
317 /**
318 * update_outbnd_queue_table - update the outbound queue table to the HBA.
319 * @pm8001_ha: our hba card information
320 */
321 static void __devinit
322 update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
323 {
324 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
325 u16 offset = number * 0x24;
326 pm8001_mw32(address, offset + 0x00,
327 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
328 pm8001_mw32(address, offset + 0x04,
329 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
330 pm8001_mw32(address, offset + 0x08,
331 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
332 pm8001_mw32(address, offset + 0x0C,
333 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
334 pm8001_mw32(address, offset + 0x10,
335 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
336 pm8001_mw32(address, offset + 0x1C,
337 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
338 }
339
340 /**
341 * bar4_shift - function is called to shift BAR base address
342 * @pm8001_ha : our hba card infomation
343 * @shiftValue : shifting value in memory bar.
344 */
345 static int bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
346 {
347 u32 regVal;
348 u32 max_wait_count;
349
350 /* program the inbound AXI translation Lower Address */
351 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
352
353 /* confirm the setting is written */
354 max_wait_count = 1 * 1000 * 1000; /* 1 sec */
355 do {
356 udelay(1);
357 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
358 } while ((regVal != shiftValue) && (--max_wait_count));
359
360 if (!max_wait_count) {
361 PM8001_INIT_DBG(pm8001_ha,
362 pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
363 " = 0x%x\n", regVal));
364 return -1;
365 }
366 return 0;
367 }
368
369 /**
370 * mpi_set_phys_g3_with_ssc
371 * @pm8001_ha: our hba card information
372 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
373 */
374 static void __devinit
375 mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, u32 SSCbit)
376 {
377 u32 value, offset, i;
378
379 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
380 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
381 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
382 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
383 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
384 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
385 #define SNW3_PHY_CAPABILITIES_PARITY 31
386
387 /*
388 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
389 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
390 */
391 if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR))
392 return;
393
394 for (i = 0; i < 4; i++) {
395 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
396 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
397 }
398 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
399 if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR))
400 return;
401 for (i = 4; i < 8; i++) {
402 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
403 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
404 }
405 /*************************************************************
406 Change the SSC upspreading value to 0x0 so that upspreading is disabled.
407 Device MABC SMOD0 Controls
408 Address: (via MEMBASE-III):
409 Using shifted destination address 0x0_0000: with Offset 0xD8
410
411 31:28 R/W Reserved Do not change
412 27:24 R/W SAS_SMOD_SPRDUP 0000
413 23:20 R/W SAS_SMOD_SPRDDN 0000
414 19:0 R/W Reserved Do not change
415 Upon power-up this register will read as 0x8990c016,
416 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
417 so that the written value will be 0x8090c016.
418 This will ensure only down-spreading SSC is enabled on the SPC.
419 *************************************************************/
420 value = pm8001_cr32(pm8001_ha, 2, 0xd8);
421 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
422
423 /*set the shifted destination address to 0x0 to avoid error operation */
424 bar4_shift(pm8001_ha, 0x0);
425 return;
426 }
427
428 /**
429 * mpi_set_open_retry_interval_reg
430 * @pm8001_ha: our hba card information
431 * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
432 */
433 static void __devinit
434 mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
435 u32 interval)
436 {
437 u32 offset;
438 u32 value;
439 u32 i;
440
441 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
442 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
443 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
444 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
445 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
446
447 value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
448 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
449 if (-1 == bar4_shift(pm8001_ha,
450 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR))
451 return;
452 for (i = 0; i < 4; i++) {
453 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
454 pm8001_cw32(pm8001_ha, 2, offset, value);
455 }
456
457 if (-1 == bar4_shift(pm8001_ha,
458 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR))
459 return;
460 for (i = 4; i < 8; i++) {
461 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
462 pm8001_cw32(pm8001_ha, 2, offset, value);
463 }
464 /*set the shifted destination address to 0x0 to avoid error operation */
465 bar4_shift(pm8001_ha, 0x0);
466 return;
467 }
468
469 /**
470 * mpi_init_check - check firmware initialization status.
471 * @pm8001_ha: our hba card information
472 */
473 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
474 {
475 u32 max_wait_count;
476 u32 value;
477 u32 gst_len_mpistate;
478 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
479 table is updated */
480 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
481 /* wait until Inbound DoorBell Clear Register toggled */
482 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
483 do {
484 udelay(1);
485 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
486 value &= SPC_MSGU_CFG_TABLE_UPDATE;
487 } while ((value != 0) && (--max_wait_count));
488
489 if (!max_wait_count)
490 return -1;
491 /* check the MPI-State for initialization */
492 gst_len_mpistate =
493 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
494 GST_GSTLEN_MPIS_OFFSET);
495 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
496 return -1;
497 /* check MPI Initialization error */
498 gst_len_mpistate = gst_len_mpistate >> 16;
499 if (0x0000 != gst_len_mpistate)
500 return -1;
501 return 0;
502 }
503
504 /**
505 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
506 * @pm8001_ha: our hba card information
507 */
508 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
509 {
510 u32 value, value1;
511 u32 max_wait_count;
512 /* check error state */
513 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
514 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
515 /* check AAP error */
516 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
517 /* error state */
518 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
519 return -1;
520 }
521
522 /* check IOP error */
523 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
524 /* error state */
525 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
526 return -1;
527 }
528
529 /* bit 4-31 of scratch pad1 should be zeros if it is not
530 in error state*/
531 if (value & SCRATCH_PAD1_STATE_MASK) {
532 /* error case */
533 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
534 return -1;
535 }
536
537 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
538 in error state */
539 if (value1 & SCRATCH_PAD2_STATE_MASK) {
540 /* error case */
541 return -1;
542 }
543
544 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
545
546 /* wait until scratch pad 1 and 2 registers in ready state */
547 do {
548 udelay(1);
549 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
550 & SCRATCH_PAD1_RDY;
551 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
552 & SCRATCH_PAD2_RDY;
553 if ((--max_wait_count) == 0)
554 return -1;
555 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
556 return 0;
557 }
558
559 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
560 {
561 void __iomem *base_addr;
562 u32 value;
563 u32 offset;
564 u32 pcibar;
565 u32 pcilogic;
566
567 value = pm8001_cr32(pm8001_ha, 0, 0x44);
568 offset = value & 0x03FFFFFF;
569 PM8001_INIT_DBG(pm8001_ha,
570 pm8001_printk("Scratchpad 0 Offset: %x \n", offset));
571 pcilogic = (value & 0xFC000000) >> 26;
572 pcibar = get_pci_bar_index(pcilogic);
573 PM8001_INIT_DBG(pm8001_ha,
574 pm8001_printk("Scratchpad 0 PCI BAR: %d \n", pcibar));
575 pm8001_ha->main_cfg_tbl_addr = base_addr =
576 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
577 pm8001_ha->general_stat_tbl_addr =
578 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
579 pm8001_ha->inbnd_q_tbl_addr =
580 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
581 pm8001_ha->outbnd_q_tbl_addr =
582 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
583 }
584
585 /**
586 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
587 * @pm8001_ha: our hba card information
588 */
589 static int __devinit pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
590 {
591 /* check the firmware status */
592 if (-1 == check_fw_ready(pm8001_ha)) {
593 PM8001_FAIL_DBG(pm8001_ha,
594 pm8001_printk("Firmware is not ready!\n"));
595 return -EBUSY;
596 }
597
598 /* Initialize pci space address eg: mpi offset */
599 init_pci_device_addresses(pm8001_ha);
600 init_default_table_values(pm8001_ha);
601 read_main_config_table(pm8001_ha);
602 read_general_status_table(pm8001_ha);
603 read_inbnd_queue_table(pm8001_ha);
604 read_outbnd_queue_table(pm8001_ha);
605 /* update main config table ,inbound table and outbound table */
606 update_main_config_table(pm8001_ha);
607 update_inbnd_queue_table(pm8001_ha, 0);
608 update_outbnd_queue_table(pm8001_ha, 0);
609 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
610 mpi_set_open_retry_interval_reg(pm8001_ha, 7);
611 /* notify firmware update finished and check initialization status */
612 if (0 == mpi_init_check(pm8001_ha)) {
613 PM8001_INIT_DBG(pm8001_ha,
614 pm8001_printk("MPI initialize successful!\n"));
615 } else
616 return -EBUSY;
617 /*This register is a 16-bit timer with a resolution of 1us. This is the
618 timer used for interrupt delay/coalescing in the PCIe Application Layer.
619 Zero is not a valid value. A value of 1 in the register will cause the
620 interrupts to be normal. A value greater than 1 will cause coalescing
621 delays.*/
622 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
623 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
624 return 0;
625 }
626
627 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
628 {
629 u32 max_wait_count;
630 u32 value;
631 u32 gst_len_mpistate;
632 init_pci_device_addresses(pm8001_ha);
633 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
634 table is stop */
635 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
636
637 /* wait until Inbound DoorBell Clear Register toggled */
638 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
639 do {
640 udelay(1);
641 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
642 value &= SPC_MSGU_CFG_TABLE_RESET;
643 } while ((value != 0) && (--max_wait_count));
644
645 if (!max_wait_count) {
646 PM8001_FAIL_DBG(pm8001_ha,
647 pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
648 return -1;
649 }
650
651 /* check the MPI-State for termination in progress */
652 /* wait until Inbound DoorBell Clear Register toggled */
653 max_wait_count = 1 * 1000 * 1000; /* 1 sec */
654 do {
655 udelay(1);
656 gst_len_mpistate =
657 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
658 GST_GSTLEN_MPIS_OFFSET);
659 if (GST_MPI_STATE_UNINIT ==
660 (gst_len_mpistate & GST_MPI_STATE_MASK))
661 break;
662 } while (--max_wait_count);
663 if (!max_wait_count) {
664 PM8001_FAIL_DBG(pm8001_ha,
665 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
666 gst_len_mpistate & GST_MPI_STATE_MASK));
667 return -1;
668 }
669 return 0;
670 }
671
672 /**
673 * soft_reset_ready_check - Function to check FW is ready for soft reset.
674 * @pm8001_ha: our hba card information
675 */
676 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
677 {
678 u32 regVal, regVal1, regVal2;
679 if (mpi_uninit_check(pm8001_ha) != 0) {
680 PM8001_FAIL_DBG(pm8001_ha,
681 pm8001_printk("MPI state is not ready\n"));
682 return -1;
683 }
684 /* read the scratch pad 2 register bit 2 */
685 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
686 & SCRATCH_PAD2_FWRDY_RST;
687 if (regVal == SCRATCH_PAD2_FWRDY_RST) {
688 PM8001_INIT_DBG(pm8001_ha,
689 pm8001_printk("Firmware is ready for reset .\n"));
690 } else {
691 /* Trigger NMI twice via RB6 */
692 if (-1 == bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
693 PM8001_FAIL_DBG(pm8001_ha,
694 pm8001_printk("Shift Bar4 to 0x%x failed\n",
695 RB6_ACCESS_REG));
696 return -1;
697 }
698 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
699 RB6_MAGIC_NUMBER_RST);
700 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
701 /* wait for 100 ms */
702 mdelay(100);
703 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
704 SCRATCH_PAD2_FWRDY_RST;
705 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
706 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
707 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
708 PM8001_FAIL_DBG(pm8001_ha,
709 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
710 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
711 regVal1, regVal2));
712 PM8001_FAIL_DBG(pm8001_ha,
713 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
714 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
715 PM8001_FAIL_DBG(pm8001_ha,
716 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
717 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
718 return -1;
719 }
720 }
721 return 0;
722 }
723
724 /**
725 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
726 * the FW register status to the originated status.
727 * @pm8001_ha: our hba card information
728 * @signature: signature in host scratch pad0 register.
729 */
730 static int
731 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
732 {
733 u32 regVal, toggleVal;
734 u32 max_wait_count;
735 u32 regVal1, regVal2, regVal3;
736
737 /* step1: Check FW is ready for soft reset */
738 if (soft_reset_ready_check(pm8001_ha) != 0) {
739 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
740 return -1;
741 }
742
743 /* step 2: clear NMI status register on AAP1 and IOP, write the same
744 value to clear */
745 /* map 0x60000 to BAR4(0x20), BAR2(win) */
746 if (-1 == bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
747 PM8001_FAIL_DBG(pm8001_ha,
748 pm8001_printk("Shift Bar4 to 0x%x failed\n",
749 MBIC_AAP1_ADDR_BASE));
750 return -1;
751 }
752 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
753 PM8001_INIT_DBG(pm8001_ha,
754 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
755 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
756 /* map 0x70000 to BAR4(0x20), BAR2(win) */
757 if (-1 == bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
758 PM8001_FAIL_DBG(pm8001_ha,
759 pm8001_printk("Shift Bar4 to 0x%x failed\n",
760 MBIC_IOP_ADDR_BASE));
761 return -1;
762 }
763 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
764 PM8001_INIT_DBG(pm8001_ha,
765 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
766 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
767
768 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
769 PM8001_INIT_DBG(pm8001_ha,
770 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
771 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
772
773 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
774 PM8001_INIT_DBG(pm8001_ha,
775 pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal));
776 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
777
778 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
779 PM8001_INIT_DBG(pm8001_ha,
780 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
781 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
782
783 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
784 PM8001_INIT_DBG(pm8001_ha,
785 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
786 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
787
788 /* read the scratch pad 1 register bit 2 */
789 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
790 & SCRATCH_PAD1_RST;
791 toggleVal = regVal ^ SCRATCH_PAD1_RST;
792
793 /* set signature in host scratch pad0 register to tell SPC that the
794 host performs the soft reset */
795 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
796
797 /* read required registers for confirmming */
798 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
799 if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
800 PM8001_FAIL_DBG(pm8001_ha,
801 pm8001_printk("Shift Bar4 to 0x%x failed\n",
802 GSM_ADDR_BASE));
803 return -1;
804 }
805 PM8001_INIT_DBG(pm8001_ha,
806 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
807 " Reset = 0x%x\n",
808 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
809
810 /* step 3: host read GSM Configuration and Reset register */
811 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
812 /* Put those bits to low */
813 /* GSM XCBI offset = 0x70 0000
814 0x00 Bit 13 COM_SLV_SW_RSTB 1
815 0x00 Bit 12 QSSP_SW_RSTB 1
816 0x00 Bit 11 RAAE_SW_RSTB 1
817 0x00 Bit 9 RB_1_SW_RSTB 1
818 0x00 Bit 8 SM_SW_RSTB 1
819 */
820 regVal &= ~(0x00003b00);
821 /* host write GSM Configuration and Reset register */
822 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
823 PM8001_INIT_DBG(pm8001_ha,
824 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
825 "Configuration and Reset is set to = 0x%x\n",
826 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
827
828 /* step 4: */
829 /* disable GSM - Read Address Parity Check */
830 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
831 PM8001_INIT_DBG(pm8001_ha,
832 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
833 "Enable = 0x%x\n", regVal1));
834 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
835 PM8001_INIT_DBG(pm8001_ha,
836 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
837 "is set to = 0x%x\n",
838 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
839
840 /* disable GSM - Write Address Parity Check */
841 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
842 PM8001_INIT_DBG(pm8001_ha,
843 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
844 " Enable = 0x%x\n", regVal2));
845 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
846 PM8001_INIT_DBG(pm8001_ha,
847 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
848 "Enable is set to = 0x%x\n",
849 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
850
851 /* disable GSM - Write Data Parity Check */
852 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
853 PM8001_INIT_DBG(pm8001_ha,
854 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
855 " Enable = 0x%x\n", regVal3));
856 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
857 PM8001_INIT_DBG(pm8001_ha,
858 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
859 "is set to = 0x%x\n",
860 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
861
862 /* step 5: delay 10 usec */
863 udelay(10);
864 /* step 5-b: set GPIO-0 output control to tristate anyway */
865 if (-1 == bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
866 PM8001_INIT_DBG(pm8001_ha,
867 pm8001_printk("Shift Bar4 to 0x%x failed\n",
868 GPIO_ADDR_BASE));
869 return -1;
870 }
871 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
872 PM8001_INIT_DBG(pm8001_ha,
873 pm8001_printk("GPIO Output Control Register:"
874 " = 0x%x\n", regVal));
875 /* set GPIO-0 output control to tri-state */
876 regVal &= 0xFFFFFFFC;
877 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
878
879 /* Step 6: Reset the IOP and AAP1 */
880 /* map 0x00000 to BAR4(0x20), BAR2(win) */
881 if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
882 PM8001_FAIL_DBG(pm8001_ha,
883 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
884 SPC_TOP_LEVEL_ADDR_BASE));
885 return -1;
886 }
887 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
888 PM8001_INIT_DBG(pm8001_ha,
889 pm8001_printk("Top Register before resetting IOP/AAP1"
890 ":= 0x%x\n", regVal));
891 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
892 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
893
894 /* step 7: Reset the BDMA/OSSP */
895 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
896 PM8001_INIT_DBG(pm8001_ha,
897 pm8001_printk("Top Register before resetting BDMA/OSSP"
898 ": = 0x%x\n", regVal));
899 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
900 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
901
902 /* step 8: delay 10 usec */
903 udelay(10);
904
905 /* step 9: bring the BDMA and OSSP out of reset */
906 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
907 PM8001_INIT_DBG(pm8001_ha,
908 pm8001_printk("Top Register before bringing up BDMA/OSSP"
909 ":= 0x%x\n", regVal));
910 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
911 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
912
913 /* step 10: delay 10 usec */
914 udelay(10);
915
916 /* step 11: reads and sets the GSM Configuration and Reset Register */
917 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
918 if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
919 PM8001_FAIL_DBG(pm8001_ha,
920 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
921 GSM_ADDR_BASE));
922 return -1;
923 }
924 PM8001_INIT_DBG(pm8001_ha,
925 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
926 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
927 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
928 /* Put those bits to high */
929 /* GSM XCBI offset = 0x70 0000
930 0x00 Bit 13 COM_SLV_SW_RSTB 1
931 0x00 Bit 12 QSSP_SW_RSTB 1
932 0x00 Bit 11 RAAE_SW_RSTB 1
933 0x00 Bit 9 RB_1_SW_RSTB 1
934 0x00 Bit 8 SM_SW_RSTB 1
935 */
936 regVal |= (GSM_CONFIG_RESET_VALUE);
937 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
938 PM8001_INIT_DBG(pm8001_ha,
939 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
940 " Configuration and Reset is set to = 0x%x\n",
941 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
942
943 /* step 12: Restore GSM - Read Address Parity Check */
944 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
945 /* just for debugging */
946 PM8001_INIT_DBG(pm8001_ha,
947 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
948 " = 0x%x\n", regVal));
949 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
950 PM8001_INIT_DBG(pm8001_ha,
951 pm8001_printk("GSM 0x700038 - Read Address Parity"
952 " Check Enable is set to = 0x%x\n",
953 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
954 /* Restore GSM - Write Address Parity Check */
955 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
956 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
957 PM8001_INIT_DBG(pm8001_ha,
958 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
959 " Enable is set to = 0x%x\n",
960 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
961 /* Restore GSM - Write Data Parity Check */
962 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
963 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
964 PM8001_INIT_DBG(pm8001_ha,
965 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
966 "is set to = 0x%x\n",
967 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
968
969 /* step 13: bring the IOP and AAP1 out of reset */
970 /* map 0x00000 to BAR4(0x20), BAR2(win) */
971 if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
972 PM8001_FAIL_DBG(pm8001_ha,
973 pm8001_printk("Shift Bar4 to 0x%x failed\n",
974 SPC_TOP_LEVEL_ADDR_BASE));
975 return -1;
976 }
977 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
978 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
979 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
980
981 /* step 14: delay 10 usec - Normal Mode */
982 udelay(10);
983 /* check Soft Reset Normal mode or Soft Reset HDA mode */
984 if (signature == SPC_SOFT_RESET_SIGNATURE) {
985 /* step 15 (Normal Mode): wait until scratch pad1 register
986 bit 2 toggled */
987 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
988 do {
989 udelay(1);
990 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
991 SCRATCH_PAD1_RST;
992 } while ((regVal != toggleVal) && (--max_wait_count));
993
994 if (!max_wait_count) {
995 regVal = pm8001_cr32(pm8001_ha, 0,
996 MSGU_SCRATCH_PAD_1);
997 PM8001_FAIL_DBG(pm8001_ha,
998 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
999 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1000 toggleVal, regVal));
1001 PM8001_FAIL_DBG(pm8001_ha,
1002 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1003 pm8001_cr32(pm8001_ha, 0,
1004 MSGU_SCRATCH_PAD_0)));
1005 PM8001_FAIL_DBG(pm8001_ha,
1006 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1007 pm8001_cr32(pm8001_ha, 0,
1008 MSGU_SCRATCH_PAD_2)));
1009 PM8001_FAIL_DBG(pm8001_ha,
1010 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1011 pm8001_cr32(pm8001_ha, 0,
1012 MSGU_SCRATCH_PAD_3)));
1013 return -1;
1014 }
1015
1016 /* step 16 (Normal) - Clear ODMR and ODCR */
1017 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1018 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1019
1020 /* step 17 (Normal Mode): wait for the FW and IOP to get
1021 ready - 1 sec timeout */
1022 /* Wait for the SPC Configuration Table to be ready */
1023 if (check_fw_ready(pm8001_ha) == -1) {
1024 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1025 /* return error if MPI Configuration Table not ready */
1026 PM8001_INIT_DBG(pm8001_ha,
1027 pm8001_printk("FW not ready SCRATCH_PAD1"
1028 " = 0x%x\n", regVal));
1029 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1030 /* return error if MPI Configuration Table not ready */
1031 PM8001_INIT_DBG(pm8001_ha,
1032 pm8001_printk("FW not ready SCRATCH_PAD2"
1033 " = 0x%x\n", regVal));
1034 PM8001_INIT_DBG(pm8001_ha,
1035 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1036 pm8001_cr32(pm8001_ha, 0,
1037 MSGU_SCRATCH_PAD_0)));
1038 PM8001_INIT_DBG(pm8001_ha,
1039 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1040 pm8001_cr32(pm8001_ha, 0,
1041 MSGU_SCRATCH_PAD_3)));
1042 return -1;
1043 }
1044 }
1045
1046 PM8001_INIT_DBG(pm8001_ha,
1047 pm8001_printk("SPC soft reset Complete\n"));
1048 return 0;
1049 }
1050
1051 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1052 {
1053 u32 i;
1054 u32 regVal;
1055 PM8001_INIT_DBG(pm8001_ha,
1056 pm8001_printk("chip reset start\n"));
1057
1058 /* do SPC chip reset. */
1059 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1060 regVal &= ~(SPC_REG_RESET_DEVICE);
1061 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1062
1063 /* delay 10 usec */
1064 udelay(10);
1065
1066 /* bring chip reset out of reset */
1067 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1068 regVal |= SPC_REG_RESET_DEVICE;
1069 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1070
1071 /* delay 10 usec */
1072 udelay(10);
1073
1074 /* wait for 20 msec until the firmware gets reloaded */
1075 i = 20;
1076 do {
1077 mdelay(1);
1078 } while ((--i) != 0);
1079
1080 PM8001_INIT_DBG(pm8001_ha,
1081 pm8001_printk("chip reset finished\n"));
1082 }
1083
1084 /**
1085 * pm8001_chip_iounmap - which maped when initialized.
1086 * @pm8001_ha: our hba card information
1087 */
1088 static void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1089 {
1090 s8 bar, logical = 0;
1091 for (bar = 0; bar < 6; bar++) {
1092 /*
1093 ** logical BARs for SPC:
1094 ** bar 0 and 1 - logical BAR0
1095 ** bar 2 and 3 - logical BAR1
1096 ** bar4 - logical BAR2
1097 ** bar5 - logical BAR3
1098 ** Skip the appropriate assignments:
1099 */
1100 if ((bar == 1) || (bar == 3))
1101 continue;
1102 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1103 iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1104 logical++;
1105 }
1106 }
1107 }
1108
1109 /**
1110 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1111 * @pm8001_ha: our hba card information
1112 */
1113 static void
1114 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1115 {
1116 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1117 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1118 }
1119
1120 /**
1121 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1122 * @pm8001_ha: our hba card information
1123 */
1124 static void
1125 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1126 {
1127 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1128 }
1129
1130 /**
1131 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1132 * @pm8001_ha: our hba card information
1133 */
1134 static void
1135 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1136 u32 int_vec_idx)
1137 {
1138 u32 msi_index;
1139 u32 value;
1140 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1141 msi_index += MSIX_TABLE_BASE;
1142 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1143 value = (1 << int_vec_idx);
1144 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value);
1145
1146 }
1147
1148 /**
1149 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1150 * @pm8001_ha: our hba card information
1151 */
1152 static void
1153 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1154 u32 int_vec_idx)
1155 {
1156 u32 msi_index;
1157 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1158 msi_index += MSIX_TABLE_BASE;
1159 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE);
1160
1161 }
1162 /**
1163 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1164 * @pm8001_ha: our hba card information
1165 */
1166 static void
1167 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1168 {
1169 #ifdef PM8001_USE_MSIX
1170 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1171 return;
1172 #endif
1173 pm8001_chip_intx_interrupt_enable(pm8001_ha);
1174
1175 }
1176
1177 /**
1178 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1179 * @pm8001_ha: our hba card information
1180 */
1181 static void
1182 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1183 {
1184 #ifdef PM8001_USE_MSIX
1185 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1186 return;
1187 #endif
1188 pm8001_chip_intx_interrupt_disable(pm8001_ha);
1189
1190 }
1191
1192 /**
1193 * mpi_msg_free_get- get the free message buffer for transfer inbound queue.
1194 * @circularQ: the inbound queue we want to transfer to HBA.
1195 * @messageSize: the message size of this transfer, normally it is 64 bytes
1196 * @messagePtr: the pointer to message.
1197 */
1198 static int mpi_msg_free_get(struct inbound_queue_table *circularQ,
1199 u16 messageSize, void **messagePtr)
1200 {
1201 u32 offset, consumer_index;
1202 struct mpi_msg_hdr *msgHeader;
1203 u8 bcCount = 1; /* only support single buffer */
1204
1205 /* Checks is the requested message size can be allocated in this queue*/
1206 if (messageSize > 64) {
1207 *messagePtr = NULL;
1208 return -1;
1209 }
1210
1211 /* Stores the new consumer index */
1212 consumer_index = pm8001_read_32(circularQ->ci_virt);
1213 circularQ->consumer_index = cpu_to_le32(consumer_index);
1214 if (((circularQ->producer_idx + bcCount) % 256) ==
1215 circularQ->consumer_index) {
1216 *messagePtr = NULL;
1217 return -1;
1218 }
1219 /* get memory IOMB buffer address */
1220 offset = circularQ->producer_idx * 64;
1221 /* increment to next bcCount element */
1222 circularQ->producer_idx = (circularQ->producer_idx + bcCount) % 256;
1223 /* Adds that distance to the base of the region virtual address plus
1224 the message header size*/
1225 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1226 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1227 return 0;
1228 }
1229
1230 /**
1231 * mpi_build_cmd- build the message queue for transfer, update the PI to FW
1232 * to tell the fw to get this message from IOMB.
1233 * @pm8001_ha: our hba card information
1234 * @circularQ: the inbound queue we want to transfer to HBA.
1235 * @opCode: the operation code represents commands which LLDD and fw recognized.
1236 * @payload: the command payload of each operation command.
1237 */
1238 static int mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1239 struct inbound_queue_table *circularQ,
1240 u32 opCode, void *payload)
1241 {
1242 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1243 u32 responseQueue = 0;
1244 void *pMessage;
1245
1246 if (mpi_msg_free_get(circularQ, 64, &pMessage) < 0) {
1247 PM8001_IO_DBG(pm8001_ha,
1248 pm8001_printk("No free mpi buffer \n"));
1249 return -1;
1250 }
1251 BUG_ON(!payload);
1252 /*Copy to the payload*/
1253 memcpy(pMessage, payload, (64 - sizeof(struct mpi_msg_hdr)));
1254
1255 /*Build the header*/
1256 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1257 | ((responseQueue & 0x3F) << 16)
1258 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1259
1260 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1261 /*Update the PI to the firmware*/
1262 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1263 circularQ->pi_offset, circularQ->producer_idx);
1264 PM8001_IO_DBG(pm8001_ha,
1265 pm8001_printk("after PI= %d CI= %d \n", circularQ->producer_idx,
1266 circularQ->consumer_index));
1267 return 0;
1268 }
1269
1270 static u32 mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1271 struct outbound_queue_table *circularQ, u8 bc)
1272 {
1273 u32 producer_index;
1274 struct mpi_msg_hdr *msgHeader;
1275 struct mpi_msg_hdr *pOutBoundMsgHeader;
1276
1277 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1278 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1279 circularQ->consumer_idx * 64);
1280 if (pOutBoundMsgHeader != msgHeader) {
1281 PM8001_FAIL_DBG(pm8001_ha,
1282 pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1283 circularQ->consumer_idx, msgHeader));
1284
1285 /* Update the producer index from SPC */
1286 producer_index = pm8001_read_32(circularQ->pi_virt);
1287 circularQ->producer_index = cpu_to_le32(producer_index);
1288 PM8001_FAIL_DBG(pm8001_ha,
1289 pm8001_printk("consumer_idx = %d producer_index = %d"
1290 "msgHeader = %p\n", circularQ->consumer_idx,
1291 circularQ->producer_index, msgHeader));
1292 return 0;
1293 }
1294 /* free the circular queue buffer elements associated with the message*/
1295 circularQ->consumer_idx = (circularQ->consumer_idx + bc) % 256;
1296 /* update the CI of outbound queue */
1297 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1298 circularQ->consumer_idx);
1299 /* Update the producer index from SPC*/
1300 producer_index = pm8001_read_32(circularQ->pi_virt);
1301 circularQ->producer_index = cpu_to_le32(producer_index);
1302 PM8001_IO_DBG(pm8001_ha,
1303 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1304 circularQ->producer_index));
1305 return 0;
1306 }
1307
1308 /**
1309 * mpi_msg_consume- get the MPI message from outbound queue message table.
1310 * @pm8001_ha: our hba card information
1311 * @circularQ: the outbound queue table.
1312 * @messagePtr1: the message contents of this outbound message.
1313 * @pBC: the message size.
1314 */
1315 static u32 mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1316 struct outbound_queue_table *circularQ,
1317 void **messagePtr1, u8 *pBC)
1318 {
1319 struct mpi_msg_hdr *msgHeader;
1320 __le32 msgHeader_tmp;
1321 u32 header_tmp;
1322 do {
1323 /* If there are not-yet-delivered messages ... */
1324 if (circularQ->producer_index != circularQ->consumer_idx) {
1325 /*Get the pointer to the circular queue buffer element*/
1326 msgHeader = (struct mpi_msg_hdr *)
1327 (circularQ->base_virt +
1328 circularQ->consumer_idx * 64);
1329 /* read header */
1330 header_tmp = pm8001_read_32(msgHeader);
1331 msgHeader_tmp = cpu_to_le32(header_tmp);
1332 if (0 != (msgHeader_tmp & 0x80000000)) {
1333 if (OPC_OUB_SKIP_ENTRY !=
1334 (msgHeader_tmp & 0xfff)) {
1335 *messagePtr1 =
1336 ((u8 *)msgHeader) +
1337 sizeof(struct mpi_msg_hdr);
1338 *pBC = (u8)((msgHeader_tmp >> 24) &
1339 0x1f);
1340 PM8001_IO_DBG(pm8001_ha,
1341 pm8001_printk(": CI=%d PI=%d "
1342 "msgHeader=%x\n",
1343 circularQ->consumer_idx,
1344 circularQ->producer_index,
1345 msgHeader_tmp));
1346 return MPI_IO_STATUS_SUCCESS;
1347 } else {
1348 circularQ->consumer_idx =
1349 (circularQ->consumer_idx +
1350 ((msgHeader_tmp >> 24) & 0x1f))
1351 % 256;
1352 msgHeader_tmp = 0;
1353 pm8001_write_32(msgHeader, 0, 0);
1354 /* update the CI of outbound queue */
1355 pm8001_cw32(pm8001_ha,
1356 circularQ->ci_pci_bar,
1357 circularQ->ci_offset,
1358 circularQ->consumer_idx);
1359 }
1360 } else {
1361 circularQ->consumer_idx =
1362 (circularQ->consumer_idx +
1363 ((msgHeader_tmp >> 24) & 0x1f)) % 256;
1364 msgHeader_tmp = 0;
1365 pm8001_write_32(msgHeader, 0, 0);
1366 /* update the CI of outbound queue */
1367 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1368 circularQ->ci_offset,
1369 circularQ->consumer_idx);
1370 return MPI_IO_STATUS_FAIL;
1371 }
1372 } else {
1373 u32 producer_index;
1374 void *pi_virt = circularQ->pi_virt;
1375 /* Update the producer index from SPC */
1376 producer_index = pm8001_read_32(pi_virt);
1377 circularQ->producer_index = cpu_to_le32(producer_index);
1378 }
1379 } while (circularQ->producer_index != circularQ->consumer_idx);
1380 /* while we don't have any more not-yet-delivered message */
1381 /* report empty */
1382 return MPI_IO_STATUS_BUSY;
1383 }
1384
1385 static void pm8001_work_queue(struct work_struct *work)
1386 {
1387 struct delayed_work *dw = container_of(work, struct delayed_work, work);
1388 struct pm8001_wq *wq = container_of(dw, struct pm8001_wq, work_q);
1389 struct pm8001_device *pm8001_dev;
1390 struct domain_device *dev;
1391
1392 switch (wq->handler) {
1393 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1394 pm8001_dev = wq->data;
1395 dev = pm8001_dev->sas_device;
1396 pm8001_I_T_nexus_reset(dev);
1397 break;
1398 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1399 pm8001_dev = wq->data;
1400 dev = pm8001_dev->sas_device;
1401 pm8001_I_T_nexus_reset(dev);
1402 break;
1403 case IO_DS_IN_ERROR:
1404 pm8001_dev = wq->data;
1405 dev = pm8001_dev->sas_device;
1406 pm8001_I_T_nexus_reset(dev);
1407 break;
1408 case IO_DS_NON_OPERATIONAL:
1409 pm8001_dev = wq->data;
1410 dev = pm8001_dev->sas_device;
1411 pm8001_I_T_nexus_reset(dev);
1412 break;
1413 }
1414 list_del(&wq->entry);
1415 kfree(wq);
1416 }
1417
1418 static int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1419 int handler)
1420 {
1421 struct pm8001_wq *wq;
1422 int ret = 0;
1423
1424 wq = kmalloc(sizeof(struct pm8001_wq), GFP_ATOMIC);
1425 if (wq) {
1426 wq->pm8001_ha = pm8001_ha;
1427 wq->data = data;
1428 wq->handler = handler;
1429 INIT_DELAYED_WORK(&wq->work_q, pm8001_work_queue);
1430 list_add_tail(&wq->entry, &pm8001_ha->wq_list);
1431 schedule_delayed_work(&wq->work_q, 0);
1432 } else
1433 ret = -ENOMEM;
1434
1435 return ret;
1436 }
1437
1438 /**
1439 * mpi_ssp_completion- process the event that FW response to the SSP request.
1440 * @pm8001_ha: our hba card information
1441 * @piomb: the message contents of this outbound message.
1442 *
1443 * When FW has completed a ssp request for example a IO request, after it has
1444 * filled the SG data with the data, it will trigger this event represent
1445 * that he has finished the job,please check the coresponding buffer.
1446 * So we will tell the caller who maybe waiting the result to tell upper layer
1447 * that the task has been finished.
1448 */
1449 static void
1450 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1451 {
1452 struct sas_task *t;
1453 struct pm8001_ccb_info *ccb;
1454 unsigned long flags;
1455 u32 status;
1456 u32 param;
1457 u32 tag;
1458 struct ssp_completion_resp *psspPayload;
1459 struct task_status_struct *ts;
1460 struct ssp_response_iu *iu;
1461 struct pm8001_device *pm8001_dev;
1462 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1463 status = le32_to_cpu(psspPayload->status);
1464 tag = le32_to_cpu(psspPayload->tag);
1465 ccb = &pm8001_ha->ccb_info[tag];
1466 pm8001_dev = ccb->device;
1467 param = le32_to_cpu(psspPayload->param);
1468
1469 t = ccb->task;
1470
1471 if (status && status != IO_UNDERFLOW)
1472 PM8001_FAIL_DBG(pm8001_ha,
1473 pm8001_printk("sas IO status 0x%x\n", status));
1474 if (unlikely(!t || !t->lldd_task || !t->dev))
1475 return;
1476 ts = &t->task_status;
1477 switch (status) {
1478 case IO_SUCCESS:
1479 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1480 ",param = %d \n", param));
1481 if (param == 0) {
1482 ts->resp = SAS_TASK_COMPLETE;
1483 ts->stat = SAM_GOOD;
1484 } else {
1485 ts->resp = SAS_TASK_COMPLETE;
1486 ts->stat = SAS_PROTO_RESPONSE;
1487 ts->residual = param;
1488 iu = &psspPayload->ssp_resp_iu;
1489 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1490 }
1491 if (pm8001_dev)
1492 pm8001_dev->running_req--;
1493 break;
1494 case IO_ABORTED:
1495 PM8001_IO_DBG(pm8001_ha,
1496 pm8001_printk("IO_ABORTED IOMB Tag \n"));
1497 ts->resp = SAS_TASK_COMPLETE;
1498 ts->stat = SAS_ABORTED_TASK;
1499 break;
1500 case IO_UNDERFLOW:
1501 /* SSP Completion with error */
1502 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1503 ",param = %d \n", param));
1504 ts->resp = SAS_TASK_COMPLETE;
1505 ts->stat = SAS_DATA_UNDERRUN;
1506 ts->residual = param;
1507 if (pm8001_dev)
1508 pm8001_dev->running_req--;
1509 break;
1510 case IO_NO_DEVICE:
1511 PM8001_IO_DBG(pm8001_ha,
1512 pm8001_printk("IO_NO_DEVICE\n"));
1513 ts->resp = SAS_TASK_UNDELIVERED;
1514 ts->stat = SAS_PHY_DOWN;
1515 break;
1516 case IO_XFER_ERROR_BREAK:
1517 PM8001_IO_DBG(pm8001_ha,
1518 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1519 ts->resp = SAS_TASK_COMPLETE;
1520 ts->stat = SAS_OPEN_REJECT;
1521 break;
1522 case IO_XFER_ERROR_PHY_NOT_READY:
1523 PM8001_IO_DBG(pm8001_ha,
1524 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1525 ts->resp = SAS_TASK_COMPLETE;
1526 ts->stat = SAS_OPEN_REJECT;
1527 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1528 break;
1529 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1530 PM8001_IO_DBG(pm8001_ha,
1531 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1532 ts->resp = SAS_TASK_COMPLETE;
1533 ts->stat = SAS_OPEN_REJECT;
1534 ts->open_rej_reason = SAS_OREJ_EPROTO;
1535 break;
1536 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1537 PM8001_IO_DBG(pm8001_ha,
1538 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1539 ts->resp = SAS_TASK_COMPLETE;
1540 ts->stat = SAS_OPEN_REJECT;
1541 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1542 break;
1543 case IO_OPEN_CNX_ERROR_BREAK:
1544 PM8001_IO_DBG(pm8001_ha,
1545 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1546 ts->resp = SAS_TASK_COMPLETE;
1547 ts->stat = SAS_OPEN_REJECT;
1548 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1549 break;
1550 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1551 PM8001_IO_DBG(pm8001_ha,
1552 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1553 ts->resp = SAS_TASK_COMPLETE;
1554 ts->stat = SAS_OPEN_REJECT;
1555 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1556 if (!t->uldd_task)
1557 pm8001_handle_event(pm8001_ha,
1558 pm8001_dev,
1559 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1560 break;
1561 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1562 PM8001_IO_DBG(pm8001_ha,
1563 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1564 ts->resp = SAS_TASK_COMPLETE;
1565 ts->stat = SAS_OPEN_REJECT;
1566 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1567 break;
1568 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1569 PM8001_IO_DBG(pm8001_ha,
1570 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1571 "NOT_SUPPORTED\n"));
1572 ts->resp = SAS_TASK_COMPLETE;
1573 ts->stat = SAS_OPEN_REJECT;
1574 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1575 break;
1576 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1577 PM8001_IO_DBG(pm8001_ha,
1578 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1579 ts->resp = SAS_TASK_UNDELIVERED;
1580 ts->stat = SAS_OPEN_REJECT;
1581 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1582 break;
1583 case IO_XFER_ERROR_NAK_RECEIVED:
1584 PM8001_IO_DBG(pm8001_ha,
1585 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1586 ts->resp = SAS_TASK_COMPLETE;
1587 ts->stat = SAS_OPEN_REJECT;
1588 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1589 break;
1590 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1591 PM8001_IO_DBG(pm8001_ha,
1592 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1593 ts->resp = SAS_TASK_COMPLETE;
1594 ts->stat = SAS_NAK_R_ERR;
1595 break;
1596 case IO_XFER_ERROR_DMA:
1597 PM8001_IO_DBG(pm8001_ha,
1598 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1599 ts->resp = SAS_TASK_COMPLETE;
1600 ts->stat = SAS_OPEN_REJECT;
1601 break;
1602 case IO_XFER_OPEN_RETRY_TIMEOUT:
1603 PM8001_IO_DBG(pm8001_ha,
1604 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1605 ts->resp = SAS_TASK_COMPLETE;
1606 ts->stat = SAS_OPEN_REJECT;
1607 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1608 break;
1609 case IO_XFER_ERROR_OFFSET_MISMATCH:
1610 PM8001_IO_DBG(pm8001_ha,
1611 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1612 ts->resp = SAS_TASK_COMPLETE;
1613 ts->stat = SAS_OPEN_REJECT;
1614 break;
1615 case IO_PORT_IN_RESET:
1616 PM8001_IO_DBG(pm8001_ha,
1617 pm8001_printk("IO_PORT_IN_RESET\n"));
1618 ts->resp = SAS_TASK_COMPLETE;
1619 ts->stat = SAS_OPEN_REJECT;
1620 break;
1621 case IO_DS_NON_OPERATIONAL:
1622 PM8001_IO_DBG(pm8001_ha,
1623 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1624 ts->resp = SAS_TASK_COMPLETE;
1625 ts->stat = SAS_OPEN_REJECT;
1626 if (!t->uldd_task)
1627 pm8001_handle_event(pm8001_ha,
1628 pm8001_dev,
1629 IO_DS_NON_OPERATIONAL);
1630 break;
1631 case IO_DS_IN_RECOVERY:
1632 PM8001_IO_DBG(pm8001_ha,
1633 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1634 ts->resp = SAS_TASK_COMPLETE;
1635 ts->stat = SAS_OPEN_REJECT;
1636 break;
1637 case IO_TM_TAG_NOT_FOUND:
1638 PM8001_IO_DBG(pm8001_ha,
1639 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1640 ts->resp = SAS_TASK_COMPLETE;
1641 ts->stat = SAS_OPEN_REJECT;
1642 break;
1643 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1644 PM8001_IO_DBG(pm8001_ha,
1645 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1646 ts->resp = SAS_TASK_COMPLETE;
1647 ts->stat = SAS_OPEN_REJECT;
1648 break;
1649 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1650 PM8001_IO_DBG(pm8001_ha,
1651 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1652 ts->resp = SAS_TASK_COMPLETE;
1653 ts->stat = SAS_OPEN_REJECT;
1654 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1655 default:
1656 PM8001_IO_DBG(pm8001_ha,
1657 pm8001_printk("Unknown status 0x%x\n", status));
1658 /* not allowed case. Therefore, return failed status */
1659 ts->resp = SAS_TASK_COMPLETE;
1660 ts->stat = SAS_OPEN_REJECT;
1661 break;
1662 }
1663 PM8001_IO_DBG(pm8001_ha,
1664 pm8001_printk("scsi_status = %x \n ",
1665 psspPayload->ssp_resp_iu.status));
1666 spin_lock_irqsave(&t->task_state_lock, flags);
1667 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1668 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1669 t->task_state_flags |= SAS_TASK_STATE_DONE;
1670 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1671 spin_unlock_irqrestore(&t->task_state_lock, flags);
1672 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1673 " io_status 0x%x resp 0x%x "
1674 "stat 0x%x but aborted by upper layer!\n",
1675 t, status, ts->resp, ts->stat));
1676 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1677 } else {
1678 spin_unlock_irqrestore(&t->task_state_lock, flags);
1679 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1680 mb();/* in order to force CPU ordering */
1681 t->task_done(t);
1682 }
1683 }
1684
1685 /*See the comments for mpi_ssp_completion */
1686 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1687 {
1688 struct sas_task *t;
1689 unsigned long flags;
1690 struct task_status_struct *ts;
1691 struct pm8001_ccb_info *ccb;
1692 struct pm8001_device *pm8001_dev;
1693 struct ssp_event_resp *psspPayload =
1694 (struct ssp_event_resp *)(piomb + 4);
1695 u32 event = le32_to_cpu(psspPayload->event);
1696 u32 tag = le32_to_cpu(psspPayload->tag);
1697 u32 port_id = le32_to_cpu(psspPayload->port_id);
1698 u32 dev_id = le32_to_cpu(psspPayload->device_id);
1699
1700 ccb = &pm8001_ha->ccb_info[tag];
1701 t = ccb->task;
1702 pm8001_dev = ccb->device;
1703 if (event)
1704 PM8001_FAIL_DBG(pm8001_ha,
1705 pm8001_printk("sas IO status 0x%x\n", event));
1706 if (unlikely(!t || !t->lldd_task || !t->dev))
1707 return;
1708 ts = &t->task_status;
1709 PM8001_IO_DBG(pm8001_ha,
1710 pm8001_printk("port_id = %x,device_id = %x\n",
1711 port_id, dev_id));
1712 switch (event) {
1713 case IO_OVERFLOW:
1714 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1715 ts->resp = SAS_TASK_COMPLETE;
1716 ts->stat = SAS_DATA_OVERRUN;
1717 ts->residual = 0;
1718 if (pm8001_dev)
1719 pm8001_dev->running_req--;
1720 break;
1721 case IO_XFER_ERROR_BREAK:
1722 PM8001_IO_DBG(pm8001_ha,
1723 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1724 ts->resp = SAS_TASK_COMPLETE;
1725 ts->stat = SAS_INTERRUPTED;
1726 break;
1727 case IO_XFER_ERROR_PHY_NOT_READY:
1728 PM8001_IO_DBG(pm8001_ha,
1729 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1730 ts->resp = SAS_TASK_COMPLETE;
1731 ts->stat = SAS_OPEN_REJECT;
1732 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1733 break;
1734 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1735 PM8001_IO_DBG(pm8001_ha,
1736 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1737 "_SUPPORTED\n"));
1738 ts->resp = SAS_TASK_COMPLETE;
1739 ts->stat = SAS_OPEN_REJECT;
1740 ts->open_rej_reason = SAS_OREJ_EPROTO;
1741 break;
1742 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1743 PM8001_IO_DBG(pm8001_ha,
1744 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1745 ts->resp = SAS_TASK_COMPLETE;
1746 ts->stat = SAS_OPEN_REJECT;
1747 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1748 break;
1749 case IO_OPEN_CNX_ERROR_BREAK:
1750 PM8001_IO_DBG(pm8001_ha,
1751 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1752 ts->resp = SAS_TASK_COMPLETE;
1753 ts->stat = SAS_OPEN_REJECT;
1754 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1755 break;
1756 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1757 PM8001_IO_DBG(pm8001_ha,
1758 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1759 ts->resp = SAS_TASK_COMPLETE;
1760 ts->stat = SAS_OPEN_REJECT;
1761 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1762 if (!t->uldd_task)
1763 pm8001_handle_event(pm8001_ha,
1764 pm8001_dev,
1765 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1766 break;
1767 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1768 PM8001_IO_DBG(pm8001_ha,
1769 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1770 ts->resp = SAS_TASK_COMPLETE;
1771 ts->stat = SAS_OPEN_REJECT;
1772 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1773 break;
1774 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1775 PM8001_IO_DBG(pm8001_ha,
1776 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1777 "NOT_SUPPORTED\n"));
1778 ts->resp = SAS_TASK_COMPLETE;
1779 ts->stat = SAS_OPEN_REJECT;
1780 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1781 break;
1782 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1783 PM8001_IO_DBG(pm8001_ha,
1784 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1785 ts->resp = SAS_TASK_COMPLETE;
1786 ts->stat = SAS_OPEN_REJECT;
1787 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1788 break;
1789 case IO_XFER_ERROR_NAK_RECEIVED:
1790 PM8001_IO_DBG(pm8001_ha,
1791 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1792 ts->resp = SAS_TASK_COMPLETE;
1793 ts->stat = SAS_OPEN_REJECT;
1794 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1795 break;
1796 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1797 PM8001_IO_DBG(pm8001_ha,
1798 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1799 ts->resp = SAS_TASK_COMPLETE;
1800 ts->stat = SAS_NAK_R_ERR;
1801 break;
1802 case IO_XFER_OPEN_RETRY_TIMEOUT:
1803 PM8001_IO_DBG(pm8001_ha,
1804 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1805 ts->resp = SAS_TASK_COMPLETE;
1806 ts->stat = SAS_OPEN_REJECT;
1807 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1808 break;
1809 case IO_XFER_ERROR_UNEXPECTED_PHASE:
1810 PM8001_IO_DBG(pm8001_ha,
1811 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1812 ts->resp = SAS_TASK_COMPLETE;
1813 ts->stat = SAS_DATA_OVERRUN;
1814 break;
1815 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1816 PM8001_IO_DBG(pm8001_ha,
1817 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1818 ts->resp = SAS_TASK_COMPLETE;
1819 ts->stat = SAS_DATA_OVERRUN;
1820 break;
1821 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1822 PM8001_IO_DBG(pm8001_ha,
1823 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1824 ts->resp = SAS_TASK_COMPLETE;
1825 ts->stat = SAS_DATA_OVERRUN;
1826 break;
1827 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1828 PM8001_IO_DBG(pm8001_ha,
1829 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1830 ts->resp = SAS_TASK_COMPLETE;
1831 ts->stat = SAS_DATA_OVERRUN;
1832 break;
1833 case IO_XFER_ERROR_OFFSET_MISMATCH:
1834 PM8001_IO_DBG(pm8001_ha,
1835 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1836 ts->resp = SAS_TASK_COMPLETE;
1837 ts->stat = SAS_DATA_OVERRUN;
1838 break;
1839 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1840 PM8001_IO_DBG(pm8001_ha,
1841 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1842 ts->resp = SAS_TASK_COMPLETE;
1843 ts->stat = SAS_DATA_OVERRUN;
1844 break;
1845 case IO_XFER_CMD_FRAME_ISSUED:
1846 PM8001_IO_DBG(pm8001_ha,
1847 pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n"));
1848 return;
1849 default:
1850 PM8001_IO_DBG(pm8001_ha,
1851 pm8001_printk("Unknown status 0x%x\n", event));
1852 /* not allowed case. Therefore, return failed status */
1853 ts->resp = SAS_TASK_COMPLETE;
1854 ts->stat = SAS_DATA_OVERRUN;
1855 break;
1856 }
1857 spin_lock_irqsave(&t->task_state_lock, flags);
1858 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1859 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1860 t->task_state_flags |= SAS_TASK_STATE_DONE;
1861 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1862 spin_unlock_irqrestore(&t->task_state_lock, flags);
1863 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1864 " event 0x%x resp 0x%x "
1865 "stat 0x%x but aborted by upper layer!\n",
1866 t, event, ts->resp, ts->stat));
1867 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1868 } else {
1869 spin_unlock_irqrestore(&t->task_state_lock, flags);
1870 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1871 mb();/* in order to force CPU ordering */
1872 t->task_done(t);
1873 }
1874 }
1875
1876 /*See the comments for mpi_ssp_completion */
1877 static void
1878 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1879 {
1880 struct sas_task *t;
1881 struct pm8001_ccb_info *ccb;
1882 unsigned long flags = 0;
1883 u32 param;
1884 u32 status;
1885 u32 tag;
1886 struct sata_completion_resp *psataPayload;
1887 struct task_status_struct *ts;
1888 struct ata_task_resp *resp ;
1889 u32 *sata_resp;
1890 struct pm8001_device *pm8001_dev;
1891
1892 psataPayload = (struct sata_completion_resp *)(piomb + 4);
1893 status = le32_to_cpu(psataPayload->status);
1894 tag = le32_to_cpu(psataPayload->tag);
1895
1896 ccb = &pm8001_ha->ccb_info[tag];
1897 param = le32_to_cpu(psataPayload->param);
1898 t = ccb->task;
1899 ts = &t->task_status;
1900 pm8001_dev = ccb->device;
1901 if (status)
1902 PM8001_FAIL_DBG(pm8001_ha,
1903 pm8001_printk("sata IO status 0x%x\n", status));
1904 if (unlikely(!t || !t->lldd_task || !t->dev))
1905 return;
1906
1907 switch (status) {
1908 case IO_SUCCESS:
1909 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
1910 if (param == 0) {
1911 ts->resp = SAS_TASK_COMPLETE;
1912 ts->stat = SAM_GOOD;
1913 } else {
1914 u8 len;
1915 ts->resp = SAS_TASK_COMPLETE;
1916 ts->stat = SAS_PROTO_RESPONSE;
1917 ts->residual = param;
1918 PM8001_IO_DBG(pm8001_ha,
1919 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
1920 param));
1921 sata_resp = &psataPayload->sata_resp[0];
1922 resp = (struct ata_task_resp *)ts->buf;
1923 if (t->ata_task.dma_xfer == 0 &&
1924 t->data_dir == PCI_DMA_FROMDEVICE) {
1925 len = sizeof(struct pio_setup_fis);
1926 PM8001_IO_DBG(pm8001_ha,
1927 pm8001_printk("PIO read len = %d\n", len));
1928 } else if (t->ata_task.use_ncq) {
1929 len = sizeof(struct set_dev_bits_fis);
1930 PM8001_IO_DBG(pm8001_ha,
1931 pm8001_printk("FPDMA len = %d\n", len));
1932 } else {
1933 len = sizeof(struct dev_to_host_fis);
1934 PM8001_IO_DBG(pm8001_ha,
1935 pm8001_printk("other len = %d\n", len));
1936 }
1937 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
1938 resp->frame_len = len;
1939 memcpy(&resp->ending_fis[0], sata_resp, len);
1940 ts->buf_valid_size = sizeof(*resp);
1941 } else
1942 PM8001_IO_DBG(pm8001_ha,
1943 pm8001_printk("response to large \n"));
1944 }
1945 if (pm8001_dev)
1946 pm8001_dev->running_req--;
1947 break;
1948 case IO_ABORTED:
1949 PM8001_IO_DBG(pm8001_ha,
1950 pm8001_printk("IO_ABORTED IOMB Tag \n"));
1951 ts->resp = SAS_TASK_COMPLETE;
1952 ts->stat = SAS_ABORTED_TASK;
1953 if (pm8001_dev)
1954 pm8001_dev->running_req--;
1955 break;
1956 /* following cases are to do cases */
1957 case IO_UNDERFLOW:
1958 /* SATA Completion with error */
1959 PM8001_IO_DBG(pm8001_ha,
1960 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
1961 ts->resp = SAS_TASK_COMPLETE;
1962 ts->stat = SAS_DATA_UNDERRUN;
1963 ts->residual = param;
1964 if (pm8001_dev)
1965 pm8001_dev->running_req--;
1966 break;
1967 case IO_NO_DEVICE:
1968 PM8001_IO_DBG(pm8001_ha,
1969 pm8001_printk("IO_NO_DEVICE\n"));
1970 ts->resp = SAS_TASK_UNDELIVERED;
1971 ts->stat = SAS_PHY_DOWN;
1972 break;
1973 case IO_XFER_ERROR_BREAK:
1974 PM8001_IO_DBG(pm8001_ha,
1975 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1976 ts->resp = SAS_TASK_COMPLETE;
1977 ts->stat = SAS_INTERRUPTED;
1978 break;
1979 case IO_XFER_ERROR_PHY_NOT_READY:
1980 PM8001_IO_DBG(pm8001_ha,
1981 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1982 ts->resp = SAS_TASK_COMPLETE;
1983 ts->stat = SAS_OPEN_REJECT;
1984 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1985 break;
1986 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1987 PM8001_IO_DBG(pm8001_ha,
1988 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1989 "_SUPPORTED\n"));
1990 ts->resp = SAS_TASK_COMPLETE;
1991 ts->stat = SAS_OPEN_REJECT;
1992 ts->open_rej_reason = SAS_OREJ_EPROTO;
1993 break;
1994 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1995 PM8001_IO_DBG(pm8001_ha,
1996 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1997 ts->resp = SAS_TASK_COMPLETE;
1998 ts->stat = SAS_OPEN_REJECT;
1999 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2000 break;
2001 case IO_OPEN_CNX_ERROR_BREAK:
2002 PM8001_IO_DBG(pm8001_ha,
2003 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2004 ts->resp = SAS_TASK_COMPLETE;
2005 ts->stat = SAS_OPEN_REJECT;
2006 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2007 break;
2008 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2009 PM8001_IO_DBG(pm8001_ha,
2010 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2011 ts->resp = SAS_TASK_COMPLETE;
2012 ts->stat = SAS_DEV_NO_RESPONSE;
2013 if (!t->uldd_task) {
2014 pm8001_handle_event(pm8001_ha,
2015 pm8001_dev,
2016 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2017 ts->resp = SAS_TASK_UNDELIVERED;
2018 ts->stat = SAS_QUEUE_FULL;
2019 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2020 mb();/*in order to force CPU ordering*/
2021 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2022 t->task_done(t);
2023 spin_lock_irqsave(&pm8001_ha->lock, flags);
2024 return;
2025 }
2026 break;
2027 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2028 PM8001_IO_DBG(pm8001_ha,
2029 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2030 ts->resp = SAS_TASK_UNDELIVERED;
2031 ts->stat = SAS_OPEN_REJECT;
2032 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2033 if (!t->uldd_task) {
2034 pm8001_handle_event(pm8001_ha,
2035 pm8001_dev,
2036 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2037 ts->resp = SAS_TASK_UNDELIVERED;
2038 ts->stat = SAS_QUEUE_FULL;
2039 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2040 mb();/*ditto*/
2041 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2042 t->task_done(t);
2043 spin_lock_irqsave(&pm8001_ha->lock, flags);
2044 return;
2045 }
2046 break;
2047 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2048 PM8001_IO_DBG(pm8001_ha,
2049 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2050 "NOT_SUPPORTED\n"));
2051 ts->resp = SAS_TASK_COMPLETE;
2052 ts->stat = SAS_OPEN_REJECT;
2053 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2054 break;
2055 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2056 PM8001_IO_DBG(pm8001_ha,
2057 pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2058 "_BUSY\n"));
2059 ts->resp = SAS_TASK_COMPLETE;
2060 ts->stat = SAS_DEV_NO_RESPONSE;
2061 if (!t->uldd_task) {
2062 pm8001_handle_event(pm8001_ha,
2063 pm8001_dev,
2064 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2065 ts->resp = SAS_TASK_UNDELIVERED;
2066 ts->stat = SAS_QUEUE_FULL;
2067 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2068 mb();/* ditto*/
2069 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2070 t->task_done(t);
2071 spin_lock_irqsave(&pm8001_ha->lock, flags);
2072 return;
2073 }
2074 break;
2075 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2076 PM8001_IO_DBG(pm8001_ha,
2077 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2078 ts->resp = SAS_TASK_COMPLETE;
2079 ts->stat = SAS_OPEN_REJECT;
2080 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2081 break;
2082 case IO_XFER_ERROR_NAK_RECEIVED:
2083 PM8001_IO_DBG(pm8001_ha,
2084 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2085 ts->resp = SAS_TASK_COMPLETE;
2086 ts->stat = SAS_NAK_R_ERR;
2087 break;
2088 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2089 PM8001_IO_DBG(pm8001_ha,
2090 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2091 ts->resp = SAS_TASK_COMPLETE;
2092 ts->stat = SAS_NAK_R_ERR;
2093 break;
2094 case IO_XFER_ERROR_DMA:
2095 PM8001_IO_DBG(pm8001_ha,
2096 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2097 ts->resp = SAS_TASK_COMPLETE;
2098 ts->stat = SAS_ABORTED_TASK;
2099 break;
2100 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2101 PM8001_IO_DBG(pm8001_ha,
2102 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2103 ts->resp = SAS_TASK_UNDELIVERED;
2104 ts->stat = SAS_DEV_NO_RESPONSE;
2105 break;
2106 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2107 PM8001_IO_DBG(pm8001_ha,
2108 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2109 ts->resp = SAS_TASK_COMPLETE;
2110 ts->stat = SAS_DATA_UNDERRUN;
2111 break;
2112 case IO_XFER_OPEN_RETRY_TIMEOUT:
2113 PM8001_IO_DBG(pm8001_ha,
2114 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2115 ts->resp = SAS_TASK_COMPLETE;
2116 ts->stat = SAS_OPEN_TO;
2117 break;
2118 case IO_PORT_IN_RESET:
2119 PM8001_IO_DBG(pm8001_ha,
2120 pm8001_printk("IO_PORT_IN_RESET\n"));
2121 ts->resp = SAS_TASK_COMPLETE;
2122 ts->stat = SAS_DEV_NO_RESPONSE;
2123 break;
2124 case IO_DS_NON_OPERATIONAL:
2125 PM8001_IO_DBG(pm8001_ha,
2126 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2127 ts->resp = SAS_TASK_COMPLETE;
2128 ts->stat = SAS_DEV_NO_RESPONSE;
2129 if (!t->uldd_task) {
2130 pm8001_handle_event(pm8001_ha, pm8001_dev,
2131 IO_DS_NON_OPERATIONAL);
2132 ts->resp = SAS_TASK_UNDELIVERED;
2133 ts->stat = SAS_QUEUE_FULL;
2134 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2135 mb();/*ditto*/
2136 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2137 t->task_done(t);
2138 spin_lock_irqsave(&pm8001_ha->lock, flags);
2139 return;
2140 }
2141 break;
2142 case IO_DS_IN_RECOVERY:
2143 PM8001_IO_DBG(pm8001_ha,
2144 pm8001_printk(" IO_DS_IN_RECOVERY\n"));
2145 ts->resp = SAS_TASK_COMPLETE;
2146 ts->stat = SAS_DEV_NO_RESPONSE;
2147 break;
2148 case IO_DS_IN_ERROR:
2149 PM8001_IO_DBG(pm8001_ha,
2150 pm8001_printk("IO_DS_IN_ERROR\n"));
2151 ts->resp = SAS_TASK_COMPLETE;
2152 ts->stat = SAS_DEV_NO_RESPONSE;
2153 if (!t->uldd_task) {
2154 pm8001_handle_event(pm8001_ha, pm8001_dev,
2155 IO_DS_IN_ERROR);
2156 ts->resp = SAS_TASK_UNDELIVERED;
2157 ts->stat = SAS_QUEUE_FULL;
2158 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2159 mb();/*ditto*/
2160 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2161 t->task_done(t);
2162 spin_lock_irqsave(&pm8001_ha->lock, flags);
2163 return;
2164 }
2165 break;
2166 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2167 PM8001_IO_DBG(pm8001_ha,
2168 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2169 ts->resp = SAS_TASK_COMPLETE;
2170 ts->stat = SAS_OPEN_REJECT;
2171 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2172 default:
2173 PM8001_IO_DBG(pm8001_ha,
2174 pm8001_printk("Unknown status 0x%x\n", status));
2175 /* not allowed case. Therefore, return failed status */
2176 ts->resp = SAS_TASK_COMPLETE;
2177 ts->stat = SAS_DEV_NO_RESPONSE;
2178 break;
2179 }
2180 spin_lock_irqsave(&t->task_state_lock, flags);
2181 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2182 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2183 t->task_state_flags |= SAS_TASK_STATE_DONE;
2184 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2185 spin_unlock_irqrestore(&t->task_state_lock, flags);
2186 PM8001_FAIL_DBG(pm8001_ha,
2187 pm8001_printk("task 0x%p done with io_status 0x%x"
2188 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2189 t, status, ts->resp, ts->stat));
2190 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2191 } else if (t->uldd_task) {
2192 spin_unlock_irqrestore(&t->task_state_lock, flags);
2193 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2194 mb();/* ditto */
2195 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2196 t->task_done(t);
2197 spin_lock_irqsave(&pm8001_ha->lock, flags);
2198 } else if (!t->uldd_task) {
2199 spin_unlock_irqrestore(&t->task_state_lock, flags);
2200 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2201 mb();/*ditto*/
2202 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2203 t->task_done(t);
2204 spin_lock_irqsave(&pm8001_ha->lock, flags);
2205 }
2206 }
2207
2208 /*See the comments for mpi_ssp_completion */
2209 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2210 {
2211 struct sas_task *t;
2212 unsigned long flags = 0;
2213 struct task_status_struct *ts;
2214 struct pm8001_ccb_info *ccb;
2215 struct pm8001_device *pm8001_dev;
2216 struct sata_event_resp *psataPayload =
2217 (struct sata_event_resp *)(piomb + 4);
2218 u32 event = le32_to_cpu(psataPayload->event);
2219 u32 tag = le32_to_cpu(psataPayload->tag);
2220 u32 port_id = le32_to_cpu(psataPayload->port_id);
2221 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2222
2223 ccb = &pm8001_ha->ccb_info[tag];
2224 t = ccb->task;
2225 pm8001_dev = ccb->device;
2226 if (event)
2227 PM8001_FAIL_DBG(pm8001_ha,
2228 pm8001_printk("sata IO status 0x%x\n", event));
2229 if (unlikely(!t || !t->lldd_task || !t->dev))
2230 return;
2231 ts = &t->task_status;
2232 PM8001_IO_DBG(pm8001_ha,
2233 pm8001_printk("port_id = %x,device_id = %x\n",
2234 port_id, dev_id));
2235 switch (event) {
2236 case IO_OVERFLOW:
2237 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2238 ts->resp = SAS_TASK_COMPLETE;
2239 ts->stat = SAS_DATA_OVERRUN;
2240 ts->residual = 0;
2241 if (pm8001_dev)
2242 pm8001_dev->running_req--;
2243 break;
2244 case IO_XFER_ERROR_BREAK:
2245 PM8001_IO_DBG(pm8001_ha,
2246 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2247 ts->resp = SAS_TASK_COMPLETE;
2248 ts->stat = SAS_INTERRUPTED;
2249 break;
2250 case IO_XFER_ERROR_PHY_NOT_READY:
2251 PM8001_IO_DBG(pm8001_ha,
2252 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2253 ts->resp = SAS_TASK_COMPLETE;
2254 ts->stat = SAS_OPEN_REJECT;
2255 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2256 break;
2257 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2258 PM8001_IO_DBG(pm8001_ha,
2259 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2260 "_SUPPORTED\n"));
2261 ts->resp = SAS_TASK_COMPLETE;
2262 ts->stat = SAS_OPEN_REJECT;
2263 ts->open_rej_reason = SAS_OREJ_EPROTO;
2264 break;
2265 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2266 PM8001_IO_DBG(pm8001_ha,
2267 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2268 ts->resp = SAS_TASK_COMPLETE;
2269 ts->stat = SAS_OPEN_REJECT;
2270 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2271 break;
2272 case IO_OPEN_CNX_ERROR_BREAK:
2273 PM8001_IO_DBG(pm8001_ha,
2274 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2275 ts->resp = SAS_TASK_COMPLETE;
2276 ts->stat = SAS_OPEN_REJECT;
2277 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2278 break;
2279 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2280 PM8001_IO_DBG(pm8001_ha,
2281 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2282 ts->resp = SAS_TASK_UNDELIVERED;
2283 ts->stat = SAS_DEV_NO_RESPONSE;
2284 if (!t->uldd_task) {
2285 pm8001_handle_event(pm8001_ha,
2286 pm8001_dev,
2287 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2288 ts->resp = SAS_TASK_COMPLETE;
2289 ts->stat = SAS_QUEUE_FULL;
2290 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2291 mb();/*ditto*/
2292 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2293 t->task_done(t);
2294 spin_lock_irqsave(&pm8001_ha->lock, flags);
2295 return;
2296 }
2297 break;
2298 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2299 PM8001_IO_DBG(pm8001_ha,
2300 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2301 ts->resp = SAS_TASK_UNDELIVERED;
2302 ts->stat = SAS_OPEN_REJECT;
2303 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2304 break;
2305 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2306 PM8001_IO_DBG(pm8001_ha,
2307 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2308 "NOT_SUPPORTED\n"));
2309 ts->resp = SAS_TASK_COMPLETE;
2310 ts->stat = SAS_OPEN_REJECT;
2311 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2312 break;
2313 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2314 PM8001_IO_DBG(pm8001_ha,
2315 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2316 ts->resp = SAS_TASK_COMPLETE;
2317 ts->stat = SAS_OPEN_REJECT;
2318 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2319 break;
2320 case IO_XFER_ERROR_NAK_RECEIVED:
2321 PM8001_IO_DBG(pm8001_ha,
2322 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2323 ts->resp = SAS_TASK_COMPLETE;
2324 ts->stat = SAS_NAK_R_ERR;
2325 break;
2326 case IO_XFER_ERROR_PEER_ABORTED:
2327 PM8001_IO_DBG(pm8001_ha,
2328 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2329 ts->resp = SAS_TASK_COMPLETE;
2330 ts->stat = SAS_NAK_R_ERR;
2331 break;
2332 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2333 PM8001_IO_DBG(pm8001_ha,
2334 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2335 ts->resp = SAS_TASK_COMPLETE;
2336 ts->stat = SAS_DATA_UNDERRUN;
2337 break;
2338 case IO_XFER_OPEN_RETRY_TIMEOUT:
2339 PM8001_IO_DBG(pm8001_ha,
2340 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2341 ts->resp = SAS_TASK_COMPLETE;
2342 ts->stat = SAS_OPEN_TO;
2343 break;
2344 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2345 PM8001_IO_DBG(pm8001_ha,
2346 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2347 ts->resp = SAS_TASK_COMPLETE;
2348 ts->stat = SAS_OPEN_TO;
2349 break;
2350 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2351 PM8001_IO_DBG(pm8001_ha,
2352 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2353 ts->resp = SAS_TASK_COMPLETE;
2354 ts->stat = SAS_OPEN_TO;
2355 break;
2356 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2357 PM8001_IO_DBG(pm8001_ha,
2358 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2359 ts->resp = SAS_TASK_COMPLETE;
2360 ts->stat = SAS_OPEN_TO;
2361 break;
2362 case IO_XFER_ERROR_OFFSET_MISMATCH:
2363 PM8001_IO_DBG(pm8001_ha,
2364 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2365 ts->resp = SAS_TASK_COMPLETE;
2366 ts->stat = SAS_OPEN_TO;
2367 break;
2368 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2369 PM8001_IO_DBG(pm8001_ha,
2370 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2371 ts->resp = SAS_TASK_COMPLETE;
2372 ts->stat = SAS_OPEN_TO;
2373 break;
2374 case IO_XFER_CMD_FRAME_ISSUED:
2375 PM8001_IO_DBG(pm8001_ha,
2376 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2377 break;
2378 case IO_XFER_PIO_SETUP_ERROR:
2379 PM8001_IO_DBG(pm8001_ha,
2380 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2381 ts->resp = SAS_TASK_COMPLETE;
2382 ts->stat = SAS_OPEN_TO;
2383 break;
2384 default:
2385 PM8001_IO_DBG(pm8001_ha,
2386 pm8001_printk("Unknown status 0x%x\n", event));
2387 /* not allowed case. Therefore, return failed status */
2388 ts->resp = SAS_TASK_COMPLETE;
2389 ts->stat = SAS_OPEN_TO;
2390 break;
2391 }
2392 spin_lock_irqsave(&t->task_state_lock, flags);
2393 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2394 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2395 t->task_state_flags |= SAS_TASK_STATE_DONE;
2396 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2397 spin_unlock_irqrestore(&t->task_state_lock, flags);
2398 PM8001_FAIL_DBG(pm8001_ha,
2399 pm8001_printk("task 0x%p done with io_status 0x%x"
2400 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2401 t, event, ts->resp, ts->stat));
2402 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2403 } else if (t->uldd_task) {
2404 spin_unlock_irqrestore(&t->task_state_lock, flags);
2405 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2406 mb();/* ditto */
2407 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2408 t->task_done(t);
2409 spin_lock_irqsave(&pm8001_ha->lock, flags);
2410 } else if (!t->uldd_task) {
2411 spin_unlock_irqrestore(&t->task_state_lock, flags);
2412 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2413 mb();/*ditto*/
2414 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2415 t->task_done(t);
2416 spin_lock_irqsave(&pm8001_ha->lock, flags);
2417 }
2418 }
2419
2420 /*See the comments for mpi_ssp_completion */
2421 static void
2422 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2423 {
2424 u32 param;
2425 struct sas_task *t;
2426 struct pm8001_ccb_info *ccb;
2427 unsigned long flags;
2428 u32 status;
2429 u32 tag;
2430 struct smp_completion_resp *psmpPayload;
2431 struct task_status_struct *ts;
2432 struct pm8001_device *pm8001_dev;
2433
2434 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2435 status = le32_to_cpu(psmpPayload->status);
2436 tag = le32_to_cpu(psmpPayload->tag);
2437
2438 ccb = &pm8001_ha->ccb_info[tag];
2439 param = le32_to_cpu(psmpPayload->param);
2440 t = ccb->task;
2441 ts = &t->task_status;
2442 pm8001_dev = ccb->device;
2443 if (status)
2444 PM8001_FAIL_DBG(pm8001_ha,
2445 pm8001_printk("smp IO status 0x%x\n", status));
2446 if (unlikely(!t || !t->lldd_task || !t->dev))
2447 return;
2448
2449 switch (status) {
2450 case IO_SUCCESS:
2451 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2452 ts->resp = SAS_TASK_COMPLETE;
2453 ts->stat = SAM_GOOD;
2454 if (pm8001_dev)
2455 pm8001_dev->running_req--;
2456 break;
2457 case IO_ABORTED:
2458 PM8001_IO_DBG(pm8001_ha,
2459 pm8001_printk("IO_ABORTED IOMB\n"));
2460 ts->resp = SAS_TASK_COMPLETE;
2461 ts->stat = SAS_ABORTED_TASK;
2462 if (pm8001_dev)
2463 pm8001_dev->running_req--;
2464 break;
2465 case IO_OVERFLOW:
2466 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2467 ts->resp = SAS_TASK_COMPLETE;
2468 ts->stat = SAS_DATA_OVERRUN;
2469 ts->residual = 0;
2470 if (pm8001_dev)
2471 pm8001_dev->running_req--;
2472 break;
2473 case IO_NO_DEVICE:
2474 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2475 ts->resp = SAS_TASK_COMPLETE;
2476 ts->stat = SAS_PHY_DOWN;
2477 break;
2478 case IO_ERROR_HW_TIMEOUT:
2479 PM8001_IO_DBG(pm8001_ha,
2480 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2481 ts->resp = SAS_TASK_COMPLETE;
2482 ts->stat = SAM_BUSY;
2483 break;
2484 case IO_XFER_ERROR_BREAK:
2485 PM8001_IO_DBG(pm8001_ha,
2486 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2487 ts->resp = SAS_TASK_COMPLETE;
2488 ts->stat = SAM_BUSY;
2489 break;
2490 case IO_XFER_ERROR_PHY_NOT_READY:
2491 PM8001_IO_DBG(pm8001_ha,
2492 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2493 ts->resp = SAS_TASK_COMPLETE;
2494 ts->stat = SAM_BUSY;
2495 break;
2496 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2497 PM8001_IO_DBG(pm8001_ha,
2498 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2499 ts->resp = SAS_TASK_COMPLETE;
2500 ts->stat = SAS_OPEN_REJECT;
2501 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2502 break;
2503 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2504 PM8001_IO_DBG(pm8001_ha,
2505 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2506 ts->resp = SAS_TASK_COMPLETE;
2507 ts->stat = SAS_OPEN_REJECT;
2508 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2509 break;
2510 case IO_OPEN_CNX_ERROR_BREAK:
2511 PM8001_IO_DBG(pm8001_ha,
2512 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2513 ts->resp = SAS_TASK_COMPLETE;
2514 ts->stat = SAS_OPEN_REJECT;
2515 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2516 break;
2517 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2518 PM8001_IO_DBG(pm8001_ha,
2519 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2520 ts->resp = SAS_TASK_COMPLETE;
2521 ts->stat = SAS_OPEN_REJECT;
2522 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2523 pm8001_handle_event(pm8001_ha,
2524 pm8001_dev,
2525 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2526 break;
2527 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2528 PM8001_IO_DBG(pm8001_ha,
2529 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2530 ts->resp = SAS_TASK_COMPLETE;
2531 ts->stat = SAS_OPEN_REJECT;
2532 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2533 break;
2534 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2535 PM8001_IO_DBG(pm8001_ha,
2536 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2537 "NOT_SUPPORTED\n"));
2538 ts->resp = SAS_TASK_COMPLETE;
2539 ts->stat = SAS_OPEN_REJECT;
2540 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2541 break;
2542 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2543 PM8001_IO_DBG(pm8001_ha,
2544 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2545 ts->resp = SAS_TASK_COMPLETE;
2546 ts->stat = SAS_OPEN_REJECT;
2547 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2548 break;
2549 case IO_XFER_ERROR_RX_FRAME:
2550 PM8001_IO_DBG(pm8001_ha,
2551 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2552 ts->resp = SAS_TASK_COMPLETE;
2553 ts->stat = SAS_DEV_NO_RESPONSE;
2554 break;
2555 case IO_XFER_OPEN_RETRY_TIMEOUT:
2556 PM8001_IO_DBG(pm8001_ha,
2557 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2558 ts->resp = SAS_TASK_COMPLETE;
2559 ts->stat = SAS_OPEN_REJECT;
2560 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2561 break;
2562 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2563 PM8001_IO_DBG(pm8001_ha,
2564 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2565 ts->resp = SAS_TASK_COMPLETE;
2566 ts->stat = SAS_QUEUE_FULL;
2567 break;
2568 case IO_PORT_IN_RESET:
2569 PM8001_IO_DBG(pm8001_ha,
2570 pm8001_printk("IO_PORT_IN_RESET\n"));
2571 ts->resp = SAS_TASK_COMPLETE;
2572 ts->stat = SAS_OPEN_REJECT;
2573 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2574 break;
2575 case IO_DS_NON_OPERATIONAL:
2576 PM8001_IO_DBG(pm8001_ha,
2577 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2578 ts->resp = SAS_TASK_COMPLETE;
2579 ts->stat = SAS_DEV_NO_RESPONSE;
2580 break;
2581 case IO_DS_IN_RECOVERY:
2582 PM8001_IO_DBG(pm8001_ha,
2583 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2584 ts->resp = SAS_TASK_COMPLETE;
2585 ts->stat = SAS_OPEN_REJECT;
2586 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2587 break;
2588 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2589 PM8001_IO_DBG(pm8001_ha,
2590 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2591 ts->resp = SAS_TASK_COMPLETE;
2592 ts->stat = SAS_OPEN_REJECT;
2593 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2594 break;
2595 default:
2596 PM8001_IO_DBG(pm8001_ha,
2597 pm8001_printk("Unknown status 0x%x\n", status));
2598 ts->resp = SAS_TASK_COMPLETE;
2599 ts->stat = SAS_DEV_NO_RESPONSE;
2600 /* not allowed case. Therefore, return failed status */
2601 break;
2602 }
2603 spin_lock_irqsave(&t->task_state_lock, flags);
2604 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2605 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2606 t->task_state_flags |= SAS_TASK_STATE_DONE;
2607 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2608 spin_unlock_irqrestore(&t->task_state_lock, flags);
2609 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2610 " io_status 0x%x resp 0x%x "
2611 "stat 0x%x but aborted by upper layer!\n",
2612 t, status, ts->resp, ts->stat));
2613 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2614 } else {
2615 spin_unlock_irqrestore(&t->task_state_lock, flags);
2616 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2617 mb();/* in order to force CPU ordering */
2618 t->task_done(t);
2619 }
2620 }
2621
2622 static void
2623 mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2624 {
2625 struct set_dev_state_resp *pPayload =
2626 (struct set_dev_state_resp *)(piomb + 4);
2627 u32 tag = le32_to_cpu(pPayload->tag);
2628 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2629 struct pm8001_device *pm8001_dev = ccb->device;
2630 u32 status = le32_to_cpu(pPayload->status);
2631 u32 device_id = le32_to_cpu(pPayload->device_id);
2632 u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS;
2633 u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS;
2634 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
2635 "from 0x%x to 0x%x status = 0x%x!\n",
2636 device_id, pds, nds, status));
2637 complete(pm8001_dev->setds_completion);
2638 ccb->task = NULL;
2639 ccb->ccb_tag = 0xFFFFFFFF;
2640 pm8001_ccb_free(pm8001_ha, tag);
2641 }
2642
2643 static void
2644 mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2645 {
2646 struct get_nvm_data_resp *pPayload =
2647 (struct get_nvm_data_resp *)(piomb + 4);
2648 u32 tag = le32_to_cpu(pPayload->tag);
2649 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2650 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2651 complete(pm8001_ha->nvmd_completion);
2652 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
2653 if ((dlen_status & NVMD_STAT) != 0) {
2654 PM8001_FAIL_DBG(pm8001_ha,
2655 pm8001_printk("Set nvm data error!\n"));
2656 return;
2657 }
2658 ccb->task = NULL;
2659 ccb->ccb_tag = 0xFFFFFFFF;
2660 pm8001_ccb_free(pm8001_ha, tag);
2661 }
2662
2663 static void
2664 mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2665 {
2666 struct fw_control_ex *fw_control_context;
2667 struct get_nvm_data_resp *pPayload =
2668 (struct get_nvm_data_resp *)(piomb + 4);
2669 u32 tag = le32_to_cpu(pPayload->tag);
2670 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2671 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2672 u32 ir_tds_bn_dps_das_nvm =
2673 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
2674 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
2675 fw_control_context = ccb->fw_control_context;
2676
2677 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
2678 if ((dlen_status & NVMD_STAT) != 0) {
2679 PM8001_FAIL_DBG(pm8001_ha,
2680 pm8001_printk("Get nvm data error!\n"));
2681 complete(pm8001_ha->nvmd_completion);
2682 return;
2683 }
2684
2685 if (ir_tds_bn_dps_das_nvm & IPMode) {
2686 /* indirect mode - IR bit set */
2687 PM8001_MSG_DBG(pm8001_ha,
2688 pm8001_printk("Get NVMD success, IR=1\n"));
2689 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
2690 if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
2691 memcpy(pm8001_ha->sas_addr,
2692 ((u8 *)virt_addr + 4),
2693 SAS_ADDR_SIZE);
2694 PM8001_MSG_DBG(pm8001_ha,
2695 pm8001_printk("Get SAS address"
2696 " from VPD successfully!\n"));
2697 }
2698 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
2699 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
2700 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
2701 ;
2702 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
2703 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
2704 ;
2705 } else {
2706 /* Should not be happened*/
2707 PM8001_MSG_DBG(pm8001_ha,
2708 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
2709 ir_tds_bn_dps_das_nvm));
2710 }
2711 } else /* direct mode */{
2712 PM8001_MSG_DBG(pm8001_ha,
2713 pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
2714 (dlen_status & NVMD_LEN) >> 24));
2715 }
2716 memcpy(fw_control_context->usrAddr,
2717 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
2718 fw_control_context->len);
2719 complete(pm8001_ha->nvmd_completion);
2720 ccb->task = NULL;
2721 ccb->ccb_tag = 0xFFFFFFFF;
2722 pm8001_ccb_free(pm8001_ha, tag);
2723 }
2724
2725 static int mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
2726 {
2727 struct local_phy_ctl_resp *pPayload =
2728 (struct local_phy_ctl_resp *)(piomb + 4);
2729 u32 status = le32_to_cpu(pPayload->status);
2730 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
2731 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
2732 if (status != 0) {
2733 PM8001_MSG_DBG(pm8001_ha,
2734 pm8001_printk("%x phy execute %x phy op failed! \n",
2735 phy_id, phy_op));
2736 } else
2737 PM8001_MSG_DBG(pm8001_ha,
2738 pm8001_printk("%x phy execute %x phy op success! \n",
2739 phy_id, phy_op));
2740 return 0;
2741 }
2742
2743 /**
2744 * pm8001_bytes_dmaed - one of the interface function communication with libsas
2745 * @pm8001_ha: our hba card information
2746 * @i: which phy that received the event.
2747 *
2748 * when HBA driver received the identify done event or initiate FIS received
2749 * event(for SATA), it will invoke this function to notify the sas layer that
2750 * the sas toplogy has formed, please discover the the whole sas domain,
2751 * while receive a broadcast(change) primitive just tell the sas
2752 * layer to discover the changed domain rather than the whole domain.
2753 */
2754 static void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
2755 {
2756 struct pm8001_phy *phy = &pm8001_ha->phy[i];
2757 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2758 struct sas_ha_struct *sas_ha;
2759 if (!phy->phy_attached)
2760 return;
2761
2762 sas_ha = pm8001_ha->sas;
2763 if (sas_phy->phy) {
2764 struct sas_phy *sphy = sas_phy->phy;
2765 sphy->negotiated_linkrate = sas_phy->linkrate;
2766 sphy->minimum_linkrate = phy->minimum_linkrate;
2767 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
2768 sphy->maximum_linkrate = phy->maximum_linkrate;
2769 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
2770 }
2771
2772 if (phy->phy_type & PORT_TYPE_SAS) {
2773 struct sas_identify_frame *id;
2774 id = (struct sas_identify_frame *)phy->frame_rcvd;
2775 id->dev_type = phy->identify.device_type;
2776 id->initiator_bits = SAS_PROTOCOL_ALL;
2777 id->target_bits = phy->identify.target_port_protocols;
2778 } else if (phy->phy_type & PORT_TYPE_SATA) {
2779 /*Nothing*/
2780 }
2781 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
2782
2783 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
2784 pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
2785 }
2786
2787 /* Get the link rate speed */
2788 static void get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
2789 {
2790 struct sas_phy *sas_phy = phy->sas_phy.phy;
2791
2792 switch (link_rate) {
2793 case PHY_SPEED_60:
2794 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
2795 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
2796 break;
2797 case PHY_SPEED_30:
2798 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
2799 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
2800 break;
2801 case PHY_SPEED_15:
2802 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
2803 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
2804 break;
2805 }
2806 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
2807 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
2808 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
2809 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
2810 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
2811 }
2812
2813 /**
2814 * asd_get_attached_sas_addr -- extract/generate attached SAS address
2815 * @phy: pointer to asd_phy
2816 * @sas_addr: pointer to buffer where the SAS address is to be written
2817 *
2818 * This function extracts the SAS address from an IDENTIFY frame
2819 * received. If OOB is SATA, then a SAS address is generated from the
2820 * HA tables.
2821 *
2822 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
2823 * buffer.
2824 */
2825 static void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
2826 u8 *sas_addr)
2827 {
2828 if (phy->sas_phy.frame_rcvd[0] == 0x34
2829 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
2830 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
2831 /* FIS device-to-host */
2832 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
2833 addr += phy->sas_phy.id;
2834 *(__be64 *)sas_addr = cpu_to_be64(addr);
2835 } else {
2836 struct sas_identify_frame *idframe =
2837 (void *) phy->sas_phy.frame_rcvd;
2838 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
2839 }
2840 }
2841
2842 /**
2843 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2844 * @pm8001_ha: our hba card information
2845 * @Qnum: the outbound queue message number.
2846 * @SEA: source of event to ack
2847 * @port_id: port id.
2848 * @phyId: phy id.
2849 * @param0: parameter 0.
2850 * @param1: parameter 1.
2851 */
2852 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2853 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2854 {
2855 struct hw_event_ack_req payload;
2856 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2857
2858 struct inbound_queue_table *circularQ;
2859
2860 memset((u8 *)&payload, 0, sizeof(payload));
2861 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2862 payload.tag = 1;
2863 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2864 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
2865 payload.param0 = cpu_to_le32(param0);
2866 payload.param1 = cpu_to_le32(param1);
2867 mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
2868 }
2869
2870 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2871 u32 phyId, u32 phy_op);
2872
2873 /**
2874 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2875 * @pm8001_ha: our hba card information
2876 * @piomb: IO message buffer
2877 */
2878 static void
2879 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2880 {
2881 struct hw_event_resp *pPayload =
2882 (struct hw_event_resp *)(piomb + 4);
2883 u32 lr_evt_status_phyid_portid =
2884 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
2885 u8 link_rate =
2886 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
2887 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
2888 u8 phy_id =
2889 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
2890 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
2891 u8 portstate = (u8)(npip_portstate & 0x0000000F);
2892 struct pm8001_port *port = &pm8001_ha->port[port_id];
2893 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2894 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2895 unsigned long flags;
2896 u8 deviceType = pPayload->sas_identify.dev_type;
2897 port->port_state = portstate;
2898 PM8001_MSG_DBG(pm8001_ha,
2899 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
2900 port_id, phy_id));
2901
2902 switch (deviceType) {
2903 case SAS_PHY_UNUSED:
2904 PM8001_MSG_DBG(pm8001_ha,
2905 pm8001_printk("device type no device.\n"));
2906 break;
2907 case SAS_END_DEVICE:
2908 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2909 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
2910 PHY_NOTIFY_ENABLE_SPINUP);
2911 port->port_attached = 1;
2912 get_lrate_mode(phy, link_rate);
2913 break;
2914 case SAS_EDGE_EXPANDER_DEVICE:
2915 PM8001_MSG_DBG(pm8001_ha,
2916 pm8001_printk("expander device.\n"));
2917 port->port_attached = 1;
2918 get_lrate_mode(phy, link_rate);
2919 break;
2920 case SAS_FANOUT_EXPANDER_DEVICE:
2921 PM8001_MSG_DBG(pm8001_ha,
2922 pm8001_printk("fanout expander device.\n"));
2923 port->port_attached = 1;
2924 get_lrate_mode(phy, link_rate);
2925 break;
2926 default:
2927 PM8001_MSG_DBG(pm8001_ha,
2928 pm8001_printk("unknown device type(%x)\n", deviceType));
2929 break;
2930 }
2931 phy->phy_type |= PORT_TYPE_SAS;
2932 phy->identify.device_type = deviceType;
2933 phy->phy_attached = 1;
2934 if (phy->identify.device_type == SAS_END_DEV)
2935 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2936 else if (phy->identify.device_type != NO_DEVICE)
2937 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2938 phy->sas_phy.oob_mode = SAS_OOB_MODE;
2939 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2940 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2941 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2942 sizeof(struct sas_identify_frame)-4);
2943 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2944 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2945 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2946 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2947 mdelay(200);/*delay a moment to wait disk to spinup*/
2948 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2949 }
2950
2951 /**
2952 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2953 * @pm8001_ha: our hba card information
2954 * @piomb: IO message buffer
2955 */
2956 static void
2957 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2958 {
2959 struct hw_event_resp *pPayload =
2960 (struct hw_event_resp *)(piomb + 4);
2961 u32 lr_evt_status_phyid_portid =
2962 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
2963 u8 link_rate =
2964 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
2965 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
2966 u8 phy_id =
2967 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
2968 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
2969 u8 portstate = (u8)(npip_portstate & 0x0000000F);
2970 struct pm8001_port *port = &pm8001_ha->port[port_id];
2971 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2972 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2973 unsigned long flags;
2974 PM8001_MSG_DBG(pm8001_ha,
2975 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
2976 " phy id = %d\n", port_id, phy_id));
2977 port->port_state = portstate;
2978 port->port_attached = 1;
2979 get_lrate_mode(phy, link_rate);
2980 phy->phy_type |= PORT_TYPE_SATA;
2981 phy->phy_attached = 1;
2982 phy->sas_phy.oob_mode = SATA_OOB_MODE;
2983 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2984 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2985 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
2986 sizeof(struct dev_to_host_fis));
2987 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2988 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2989 phy->identify.device_type = SATA_DEV;
2990 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2991 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2992 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2993 }
2994
2995 /**
2996 * hw_event_phy_down -we should notify the libsas the phy is down.
2997 * @pm8001_ha: our hba card information
2998 * @piomb: IO message buffer
2999 */
3000 static void
3001 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3002 {
3003 struct hw_event_resp *pPayload =
3004 (struct hw_event_resp *)(piomb + 4);
3005 u32 lr_evt_status_phyid_portid =
3006 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3007 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3008 u8 phy_id =
3009 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3010 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3011 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3012 struct pm8001_port *port = &pm8001_ha->port[port_id];
3013 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3014 port->port_state = portstate;
3015 phy->phy_type = 0;
3016 phy->identify.device_type = 0;
3017 phy->phy_attached = 0;
3018 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3019 switch (portstate) {
3020 case PORT_VALID:
3021 break;
3022 case PORT_INVALID:
3023 PM8001_MSG_DBG(pm8001_ha,
3024 pm8001_printk(" PortInvalid portID %d \n", port_id));
3025 PM8001_MSG_DBG(pm8001_ha,
3026 pm8001_printk(" Last phy Down and port invalid\n"));
3027 port->port_attached = 0;
3028 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3029 port_id, phy_id, 0, 0);
3030 break;
3031 case PORT_IN_RESET:
3032 PM8001_MSG_DBG(pm8001_ha,
3033 pm8001_printk(" Port In Reset portID %d \n", port_id));
3034 break;
3035 case PORT_NOT_ESTABLISHED:
3036 PM8001_MSG_DBG(pm8001_ha,
3037 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3038 port->port_attached = 0;
3039 break;
3040 case PORT_LOSTCOMM:
3041 PM8001_MSG_DBG(pm8001_ha,
3042 pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3043 PM8001_MSG_DBG(pm8001_ha,
3044 pm8001_printk(" Last phy Down and port invalid\n"));
3045 port->port_attached = 0;
3046 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3047 port_id, phy_id, 0, 0);
3048 break;
3049 default:
3050 port->port_attached = 0;
3051 PM8001_MSG_DBG(pm8001_ha,
3052 pm8001_printk(" phy Down and(default) = %x\n",
3053 portstate));
3054 break;
3055
3056 }
3057 }
3058
3059 /**
3060 * mpi_reg_resp -process register device ID response.
3061 * @pm8001_ha: our hba card information
3062 * @piomb: IO message buffer
3063 *
3064 * when sas layer find a device it will notify LLDD, then the driver register
3065 * the domain device to FW, this event is the return device ID which the FW
3066 * has assigned, from now,inter-communication with FW is no longer using the
3067 * SAS address, use device ID which FW assigned.
3068 */
3069 static int mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3070 {
3071 u32 status;
3072 u32 device_id;
3073 u32 htag;
3074 struct pm8001_ccb_info *ccb;
3075 struct pm8001_device *pm8001_dev;
3076 struct dev_reg_resp *registerRespPayload =
3077 (struct dev_reg_resp *)(piomb + 4);
3078
3079 htag = le32_to_cpu(registerRespPayload->tag);
3080 ccb = &pm8001_ha->ccb_info[registerRespPayload->tag];
3081 pm8001_dev = ccb->device;
3082 status = le32_to_cpu(registerRespPayload->status);
3083 device_id = le32_to_cpu(registerRespPayload->device_id);
3084 PM8001_MSG_DBG(pm8001_ha,
3085 pm8001_printk(" register device is status = %d\n", status));
3086 switch (status) {
3087 case DEVREG_SUCCESS:
3088 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3089 pm8001_dev->device_id = device_id;
3090 break;
3091 case DEVREG_FAILURE_OUT_OF_RESOURCE:
3092 PM8001_MSG_DBG(pm8001_ha,
3093 pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3094 break;
3095 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3096 PM8001_MSG_DBG(pm8001_ha,
3097 pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3098 break;
3099 case DEVREG_FAILURE_INVALID_PHY_ID:
3100 PM8001_MSG_DBG(pm8001_ha,
3101 pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3102 break;
3103 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3104 PM8001_MSG_DBG(pm8001_ha,
3105 pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3106 break;
3107 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3108 PM8001_MSG_DBG(pm8001_ha,
3109 pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3110 break;
3111 case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3112 PM8001_MSG_DBG(pm8001_ha,
3113 pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3114 break;
3115 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3116 PM8001_MSG_DBG(pm8001_ha,
3117 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3118 break;
3119 default:
3120 PM8001_MSG_DBG(pm8001_ha,
3121 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
3122 break;
3123 }
3124 complete(pm8001_dev->dcompletion);
3125 ccb->task = NULL;
3126 ccb->ccb_tag = 0xFFFFFFFF;
3127 pm8001_ccb_free(pm8001_ha, htag);
3128 return 0;
3129 }
3130
3131 static int mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3132 {
3133 u32 status;
3134 u32 device_id;
3135 struct dev_reg_resp *registerRespPayload =
3136 (struct dev_reg_resp *)(piomb + 4);
3137
3138 status = le32_to_cpu(registerRespPayload->status);
3139 device_id = le32_to_cpu(registerRespPayload->device_id);
3140 if (status != 0)
3141 PM8001_MSG_DBG(pm8001_ha,
3142 pm8001_printk(" deregister device failed ,status = %x"
3143 ", device_id = %x\n", status, device_id));
3144 return 0;
3145 }
3146
3147 static int
3148 mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3149 {
3150 u32 status;
3151 struct fw_control_ex fw_control_context;
3152 struct fw_flash_Update_resp *ppayload =
3153 (struct fw_flash_Update_resp *)(piomb + 4);
3154 u32 tag = le32_to_cpu(ppayload->tag);
3155 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3156 status = le32_to_cpu(ppayload->status);
3157 memcpy(&fw_control_context,
3158 ccb->fw_control_context,
3159 sizeof(fw_control_context));
3160 switch (status) {
3161 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3162 PM8001_MSG_DBG(pm8001_ha,
3163 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3164 break;
3165 case FLASH_UPDATE_IN_PROGRESS:
3166 PM8001_MSG_DBG(pm8001_ha,
3167 pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3168 break;
3169 case FLASH_UPDATE_HDR_ERR:
3170 PM8001_MSG_DBG(pm8001_ha,
3171 pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3172 break;
3173 case FLASH_UPDATE_OFFSET_ERR:
3174 PM8001_MSG_DBG(pm8001_ha,
3175 pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3176 break;
3177 case FLASH_UPDATE_CRC_ERR:
3178 PM8001_MSG_DBG(pm8001_ha,
3179 pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3180 break;
3181 case FLASH_UPDATE_LENGTH_ERR:
3182 PM8001_MSG_DBG(pm8001_ha,
3183 pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3184 break;
3185 case FLASH_UPDATE_HW_ERR:
3186 PM8001_MSG_DBG(pm8001_ha,
3187 pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3188 break;
3189 case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3190 PM8001_MSG_DBG(pm8001_ha,
3191 pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3192 break;
3193 case FLASH_UPDATE_DISABLED:
3194 PM8001_MSG_DBG(pm8001_ha,
3195 pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3196 break;
3197 default:
3198 PM8001_MSG_DBG(pm8001_ha,
3199 pm8001_printk("No matched status = %d\n", status));
3200 break;
3201 }
3202 ccb->fw_control_context->fw_control->retcode = status;
3203 pci_free_consistent(pm8001_ha->pdev,
3204 fw_control_context.len,
3205 fw_control_context.virtAddr,
3206 fw_control_context.phys_addr);
3207 complete(pm8001_ha->nvmd_completion);
3208 ccb->task = NULL;
3209 ccb->ccb_tag = 0xFFFFFFFF;
3210 pm8001_ccb_free(pm8001_ha, tag);
3211 return 0;
3212 }
3213
3214 static int
3215 mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3216 {
3217 u32 status;
3218 int i;
3219 struct general_event_resp *pPayload =
3220 (struct general_event_resp *)(piomb + 4);
3221 status = le32_to_cpu(pPayload->status);
3222 PM8001_MSG_DBG(pm8001_ha,
3223 pm8001_printk(" status = 0x%x\n", status));
3224 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3225 PM8001_MSG_DBG(pm8001_ha,
3226 pm8001_printk("inb_IOMB_payload[0x%x] 0x%x, \n", i,
3227 pPayload->inb_IOMB_payload[i]));
3228 return 0;
3229 }
3230
3231 static int
3232 mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3233 {
3234 struct sas_task *t;
3235 struct pm8001_ccb_info *ccb;
3236 unsigned long flags;
3237 u32 status ;
3238 u32 tag, scp;
3239 struct task_status_struct *ts;
3240
3241 struct task_abort_resp *pPayload =
3242 (struct task_abort_resp *)(piomb + 4);
3243 ccb = &pm8001_ha->ccb_info[pPayload->tag];
3244 t = ccb->task;
3245
3246
3247 status = le32_to_cpu(pPayload->status);
3248 tag = le32_to_cpu(pPayload->tag);
3249 scp = le32_to_cpu(pPayload->scp);
3250 PM8001_IO_DBG(pm8001_ha,
3251 pm8001_printk(" status = 0x%x\n", status));
3252 if (t == NULL)
3253 return -1;
3254 ts = &t->task_status;
3255 if (status != 0)
3256 PM8001_FAIL_DBG(pm8001_ha,
3257 pm8001_printk("task abort failed status 0x%x ,"
3258 "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
3259 switch (status) {
3260 case IO_SUCCESS:
3261 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3262 ts->resp = SAS_TASK_COMPLETE;
3263 ts->stat = SAM_GOOD;
3264 break;
3265 case IO_NOT_VALID:
3266 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3267 ts->resp = TMF_RESP_FUNC_FAILED;
3268 break;
3269 }
3270 spin_lock_irqsave(&t->task_state_lock, flags);
3271 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3272 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3273 t->task_state_flags |= SAS_TASK_STATE_DONE;
3274 spin_unlock_irqrestore(&t->task_state_lock, flags);
3275 pm8001_ccb_task_free(pm8001_ha, t, ccb, pPayload->tag);
3276 mb();
3277 t->task_done(t);
3278 return 0;
3279 }
3280
3281 /**
3282 * mpi_hw_event -The hw event has come.
3283 * @pm8001_ha: our hba card information
3284 * @piomb: IO message buffer
3285 */
3286 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3287 {
3288 unsigned long flags;
3289 struct hw_event_resp *pPayload =
3290 (struct hw_event_resp *)(piomb + 4);
3291 u32 lr_evt_status_phyid_portid =
3292 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3293 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3294 u8 phy_id =
3295 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3296 u16 eventType =
3297 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3298 u8 status =
3299 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3300 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3301 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3302 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3303 PM8001_MSG_DBG(pm8001_ha,
3304 pm8001_printk("outbound queue HW event & event type : "));
3305 switch (eventType) {
3306 case HW_EVENT_PHY_START_STATUS:
3307 PM8001_MSG_DBG(pm8001_ha,
3308 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3309 " status = %x\n", status));
3310 if (status == 0) {
3311 phy->phy_state = 1;
3312 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3313 complete(phy->enable_completion);
3314 }
3315 break;
3316 case HW_EVENT_SAS_PHY_UP:
3317 PM8001_MSG_DBG(pm8001_ha,
3318 pm8001_printk("HW_EVENT_PHY_START_STATUS \n"));
3319 hw_event_sas_phy_up(pm8001_ha, piomb);
3320 break;
3321 case HW_EVENT_SATA_PHY_UP:
3322 PM8001_MSG_DBG(pm8001_ha,
3323 pm8001_printk("HW_EVENT_SATA_PHY_UP \n"));
3324 hw_event_sata_phy_up(pm8001_ha, piomb);
3325 break;
3326 case HW_EVENT_PHY_STOP_STATUS:
3327 PM8001_MSG_DBG(pm8001_ha,
3328 pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3329 "status = %x\n", status));
3330 if (status == 0)
3331 phy->phy_state = 0;
3332 break;
3333 case HW_EVENT_SATA_SPINUP_HOLD:
3334 PM8001_MSG_DBG(pm8001_ha,
3335 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD \n"));
3336 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3337 break;
3338 case HW_EVENT_PHY_DOWN:
3339 PM8001_MSG_DBG(pm8001_ha,
3340 pm8001_printk("HW_EVENT_PHY_DOWN \n"));
3341 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3342 phy->phy_attached = 0;
3343 phy->phy_state = 0;
3344 hw_event_phy_down(pm8001_ha, piomb);
3345 break;
3346 case HW_EVENT_PORT_INVALID:
3347 PM8001_MSG_DBG(pm8001_ha,
3348 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3349 sas_phy_disconnected(sas_phy);
3350 phy->phy_attached = 0;
3351 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3352 break;
3353 /* the broadcast change primitive received, tell the LIBSAS this event
3354 to revalidate the sas domain*/
3355 case HW_EVENT_BROADCAST_CHANGE:
3356 PM8001_MSG_DBG(pm8001_ha,
3357 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3358 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3359 port_id, phy_id, 1, 0);
3360 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3361 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3362 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3363 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3364 break;
3365 case HW_EVENT_PHY_ERROR:
3366 PM8001_MSG_DBG(pm8001_ha,
3367 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3368 sas_phy_disconnected(&phy->sas_phy);
3369 phy->phy_attached = 0;
3370 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3371 break;
3372 case HW_EVENT_BROADCAST_EXP:
3373 PM8001_MSG_DBG(pm8001_ha,
3374 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3375 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3376 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3377 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3378 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3379 break;
3380 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3381 PM8001_MSG_DBG(pm8001_ha,
3382 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3383 pm8001_hw_event_ack_req(pm8001_ha, 0,
3384 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3385 sas_phy_disconnected(sas_phy);
3386 phy->phy_attached = 0;
3387 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3388 break;
3389 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3390 PM8001_MSG_DBG(pm8001_ha,
3391 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3392 pm8001_hw_event_ack_req(pm8001_ha, 0,
3393 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3394 port_id, phy_id, 0, 0);
3395 sas_phy_disconnected(sas_phy);
3396 phy->phy_attached = 0;
3397 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3398 break;
3399 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3400 PM8001_MSG_DBG(pm8001_ha,
3401 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3402 pm8001_hw_event_ack_req(pm8001_ha, 0,
3403 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3404 port_id, phy_id, 0, 0);
3405 sas_phy_disconnected(sas_phy);
3406 phy->phy_attached = 0;
3407 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3408 break;
3409 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3410 PM8001_MSG_DBG(pm8001_ha,
3411 pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3412 pm8001_hw_event_ack_req(pm8001_ha, 0,
3413 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3414 port_id, phy_id, 0, 0);
3415 sas_phy_disconnected(sas_phy);
3416 phy->phy_attached = 0;
3417 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3418 break;
3419 case HW_EVENT_MALFUNCTION:
3420 PM8001_MSG_DBG(pm8001_ha,
3421 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3422 break;
3423 case HW_EVENT_BROADCAST_SES:
3424 PM8001_MSG_DBG(pm8001_ha,
3425 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3426 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3427 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3428 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3429 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3430 break;
3431 case HW_EVENT_INBOUND_CRC_ERROR:
3432 PM8001_MSG_DBG(pm8001_ha,
3433 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3434 pm8001_hw_event_ack_req(pm8001_ha, 0,
3435 HW_EVENT_INBOUND_CRC_ERROR,
3436 port_id, phy_id, 0, 0);
3437 break;
3438 case HW_EVENT_HARD_RESET_RECEIVED:
3439 PM8001_MSG_DBG(pm8001_ha,
3440 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3441 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3442 break;
3443 case HW_EVENT_ID_FRAME_TIMEOUT:
3444 PM8001_MSG_DBG(pm8001_ha,
3445 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3446 sas_phy_disconnected(sas_phy);
3447 phy->phy_attached = 0;
3448 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3449 break;
3450 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3451 PM8001_MSG_DBG(pm8001_ha,
3452 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED \n"));
3453 pm8001_hw_event_ack_req(pm8001_ha, 0,
3454 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3455 port_id, phy_id, 0, 0);
3456 sas_phy_disconnected(sas_phy);
3457 phy->phy_attached = 0;
3458 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3459 break;
3460 case HW_EVENT_PORT_RESET_TIMER_TMO:
3461 PM8001_MSG_DBG(pm8001_ha,
3462 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO \n"));
3463 sas_phy_disconnected(sas_phy);
3464 phy->phy_attached = 0;
3465 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3466 break;
3467 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3468 PM8001_MSG_DBG(pm8001_ha,
3469 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO \n"));
3470 sas_phy_disconnected(sas_phy);
3471 phy->phy_attached = 0;
3472 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3473 break;
3474 case HW_EVENT_PORT_RECOVER:
3475 PM8001_MSG_DBG(pm8001_ha,
3476 pm8001_printk("HW_EVENT_PORT_RECOVER \n"));
3477 break;
3478 case HW_EVENT_PORT_RESET_COMPLETE:
3479 PM8001_MSG_DBG(pm8001_ha,
3480 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE \n"));
3481 break;
3482 case EVENT_BROADCAST_ASYNCH_EVENT:
3483 PM8001_MSG_DBG(pm8001_ha,
3484 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3485 break;
3486 default:
3487 PM8001_MSG_DBG(pm8001_ha,
3488 pm8001_printk("Unknown event type = %x\n", eventType));
3489 break;
3490 }
3491 return 0;
3492 }
3493
3494 /**
3495 * process_one_iomb - process one outbound Queue memory block
3496 * @pm8001_ha: our hba card information
3497 * @piomb: IO message buffer
3498 */
3499 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3500 {
3501 u32 pHeader = (u32)*(u32 *)piomb;
3502 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3503
3504 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
3505
3506 switch (opc) {
3507 case OPC_OUB_ECHO:
3508 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO \n"));
3509 break;
3510 case OPC_OUB_HW_EVENT:
3511 PM8001_MSG_DBG(pm8001_ha,
3512 pm8001_printk("OPC_OUB_HW_EVENT \n"));
3513 mpi_hw_event(pm8001_ha, piomb);
3514 break;
3515 case OPC_OUB_SSP_COMP:
3516 PM8001_MSG_DBG(pm8001_ha,
3517 pm8001_printk("OPC_OUB_SSP_COMP \n"));
3518 mpi_ssp_completion(pm8001_ha, piomb);
3519 break;
3520 case OPC_OUB_SMP_COMP:
3521 PM8001_MSG_DBG(pm8001_ha,
3522 pm8001_printk("OPC_OUB_SMP_COMP \n"));
3523 mpi_smp_completion(pm8001_ha, piomb);
3524 break;
3525 case OPC_OUB_LOCAL_PHY_CNTRL:
3526 PM8001_MSG_DBG(pm8001_ha,
3527 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3528 mpi_local_phy_ctl(pm8001_ha, piomb);
3529 break;
3530 case OPC_OUB_DEV_REGIST:
3531 PM8001_MSG_DBG(pm8001_ha,
3532 pm8001_printk("OPC_OUB_DEV_REGIST \n"));
3533 mpi_reg_resp(pm8001_ha, piomb);
3534 break;
3535 case OPC_OUB_DEREG_DEV:
3536 PM8001_MSG_DBG(pm8001_ha,
3537 pm8001_printk("unresgister the deviece \n"));
3538 mpi_dereg_resp(pm8001_ha, piomb);
3539 break;
3540 case OPC_OUB_GET_DEV_HANDLE:
3541 PM8001_MSG_DBG(pm8001_ha,
3542 pm8001_printk("OPC_OUB_GET_DEV_HANDLE \n"));
3543 break;
3544 case OPC_OUB_SATA_COMP:
3545 PM8001_MSG_DBG(pm8001_ha,
3546 pm8001_printk("OPC_OUB_SATA_COMP \n"));
3547 mpi_sata_completion(pm8001_ha, piomb);
3548 break;
3549 case OPC_OUB_SATA_EVENT:
3550 PM8001_MSG_DBG(pm8001_ha,
3551 pm8001_printk("OPC_OUB_SATA_EVENT \n"));
3552 mpi_sata_event(pm8001_ha, piomb);
3553 break;
3554 case OPC_OUB_SSP_EVENT:
3555 PM8001_MSG_DBG(pm8001_ha,
3556 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3557 mpi_ssp_event(pm8001_ha, piomb);
3558 break;
3559 case OPC_OUB_DEV_HANDLE_ARRIV:
3560 PM8001_MSG_DBG(pm8001_ha,
3561 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3562 /*This is for target*/
3563 break;
3564 case OPC_OUB_SSP_RECV_EVENT:
3565 PM8001_MSG_DBG(pm8001_ha,
3566 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3567 /*This is for target*/
3568 break;
3569 case OPC_OUB_DEV_INFO:
3570 PM8001_MSG_DBG(pm8001_ha,
3571 pm8001_printk("OPC_OUB_DEV_INFO\n"));
3572 break;
3573 case OPC_OUB_FW_FLASH_UPDATE:
3574 PM8001_MSG_DBG(pm8001_ha,
3575 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3576 mpi_fw_flash_update_resp(pm8001_ha, piomb);
3577 break;
3578 case OPC_OUB_GPIO_RESPONSE:
3579 PM8001_MSG_DBG(pm8001_ha,
3580 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3581 break;
3582 case OPC_OUB_GPIO_EVENT:
3583 PM8001_MSG_DBG(pm8001_ha,
3584 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3585 break;
3586 case OPC_OUB_GENERAL_EVENT:
3587 PM8001_MSG_DBG(pm8001_ha,
3588 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3589 mpi_general_event(pm8001_ha, piomb);
3590 break;
3591 case OPC_OUB_SSP_ABORT_RSP:
3592 PM8001_MSG_DBG(pm8001_ha,
3593 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3594 mpi_task_abort_resp(pm8001_ha, piomb);
3595 break;
3596 case OPC_OUB_SATA_ABORT_RSP:
3597 PM8001_MSG_DBG(pm8001_ha,
3598 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3599 mpi_task_abort_resp(pm8001_ha, piomb);
3600 break;
3601 case OPC_OUB_SAS_DIAG_MODE_START_END:
3602 PM8001_MSG_DBG(pm8001_ha,
3603 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3604 break;
3605 case OPC_OUB_SAS_DIAG_EXECUTE:
3606 PM8001_MSG_DBG(pm8001_ha,
3607 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3608 break;
3609 case OPC_OUB_GET_TIME_STAMP:
3610 PM8001_MSG_DBG(pm8001_ha,
3611 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3612 break;
3613 case OPC_OUB_SAS_HW_EVENT_ACK:
3614 PM8001_MSG_DBG(pm8001_ha,
3615 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3616 break;
3617 case OPC_OUB_PORT_CONTROL:
3618 PM8001_MSG_DBG(pm8001_ha,
3619 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3620 break;
3621 case OPC_OUB_SMP_ABORT_RSP:
3622 PM8001_MSG_DBG(pm8001_ha,
3623 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3624 mpi_task_abort_resp(pm8001_ha, piomb);
3625 break;
3626 case OPC_OUB_GET_NVMD_DATA:
3627 PM8001_MSG_DBG(pm8001_ha,
3628 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3629 mpi_get_nvmd_resp(pm8001_ha, piomb);
3630 break;
3631 case OPC_OUB_SET_NVMD_DATA:
3632 PM8001_MSG_DBG(pm8001_ha,
3633 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3634 mpi_set_nvmd_resp(pm8001_ha, piomb);
3635 break;
3636 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3637 PM8001_MSG_DBG(pm8001_ha,
3638 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3639 break;
3640 case OPC_OUB_SET_DEVICE_STATE:
3641 PM8001_MSG_DBG(pm8001_ha,
3642 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3643 mpi_set_dev_state_resp(pm8001_ha, piomb);
3644 break;
3645 case OPC_OUB_GET_DEVICE_STATE:
3646 PM8001_MSG_DBG(pm8001_ha,
3647 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3648 break;
3649 case OPC_OUB_SET_DEV_INFO:
3650 PM8001_MSG_DBG(pm8001_ha,
3651 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3652 break;
3653 case OPC_OUB_SAS_RE_INITIALIZE:
3654 PM8001_MSG_DBG(pm8001_ha,
3655 pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
3656 break;
3657 default:
3658 PM8001_MSG_DBG(pm8001_ha,
3659 pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
3660 opc));
3661 break;
3662 }
3663 }
3664
3665 static int process_oq(struct pm8001_hba_info *pm8001_ha)
3666 {
3667 struct outbound_queue_table *circularQ;
3668 void *pMsg1 = NULL;
3669 u8 bc = 0;
3670 u32 ret = MPI_IO_STATUS_FAIL;
3671
3672 circularQ = &pm8001_ha->outbnd_q_tbl[0];
3673 do {
3674 ret = mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3675 if (MPI_IO_STATUS_SUCCESS == ret) {
3676 /* process the outbound message */
3677 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3678 /* free the message from the outbound circular buffer */
3679 mpi_msg_free_set(pm8001_ha, pMsg1, circularQ, bc);
3680 }
3681 if (MPI_IO_STATUS_BUSY == ret) {
3682 u32 producer_idx;
3683 /* Update the producer index from SPC */
3684 producer_idx = pm8001_read_32(circularQ->pi_virt);
3685 circularQ->producer_index = cpu_to_le32(producer_idx);
3686 if (circularQ->producer_index ==
3687 circularQ->consumer_idx)
3688 /* OQ is empty */
3689 break;
3690 }
3691 } while (1);
3692 return ret;
3693 }
3694
3695 /* PCI_DMA_... to our direction translation. */
3696 static const u8 data_dir_flags[] = {
3697 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3698 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
3699 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
3700 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
3701 };
3702 static void
3703 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
3704 {
3705 int i;
3706 struct scatterlist *sg;
3707 struct pm8001_prd *buf_prd = prd;
3708
3709 for_each_sg(scatter, sg, nr, i) {
3710 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
3711 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
3712 buf_prd->im_len.e = 0;
3713 buf_prd++;
3714 }
3715 }
3716
3717 static void build_smp_cmd(u32 deviceID, u32 hTag, struct smp_req *psmp_cmd)
3718 {
3719 psmp_cmd->tag = cpu_to_le32(hTag);
3720 psmp_cmd->device_id = cpu_to_le32(deviceID);
3721 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3722 }
3723
3724 /**
3725 * pm8001_chip_smp_req - send a SMP task to FW
3726 * @pm8001_ha: our hba card information.
3727 * @ccb: the ccb information this request used.
3728 */
3729 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3730 struct pm8001_ccb_info *ccb)
3731 {
3732 int elem, rc;
3733 struct sas_task *task = ccb->task;
3734 struct domain_device *dev = task->dev;
3735 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3736 struct scatterlist *sg_req, *sg_resp;
3737 u32 req_len, resp_len;
3738 struct smp_req smp_cmd;
3739 u32 opc;
3740 struct inbound_queue_table *circularQ;
3741
3742 memset(&smp_cmd, 0, sizeof(smp_cmd));
3743 /*
3744 * DMA-map SMP request, response buffers
3745 */
3746 sg_req = &task->smp_task.smp_req;
3747 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3748 if (!elem)
3749 return -ENOMEM;
3750 req_len = sg_dma_len(sg_req);
3751
3752 sg_resp = &task->smp_task.smp_resp;
3753 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3754 if (!elem) {
3755 rc = -ENOMEM;
3756 goto err_out;
3757 }
3758 resp_len = sg_dma_len(sg_resp);
3759 /* must be in dwords */
3760 if ((req_len & 0x3) || (resp_len & 0x3)) {
3761 rc = -EINVAL;
3762 goto err_out_2;
3763 }
3764
3765 opc = OPC_INB_SMP_REQUEST;
3766 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3767 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3768 smp_cmd.long_smp_req.long_req_addr =
3769 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3770 smp_cmd.long_smp_req.long_req_size =
3771 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3772 smp_cmd.long_smp_req.long_resp_addr =
3773 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
3774 smp_cmd.long_smp_req.long_resp_size =
3775 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3776 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
3777 mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd);
3778 return 0;
3779
3780 err_out_2:
3781 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3782 PCI_DMA_FROMDEVICE);
3783 err_out:
3784 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3785 PCI_DMA_TODEVICE);
3786 return rc;
3787 }
3788
3789 /**
3790 * pm8001_chip_ssp_io_req - send a SSP task to FW
3791 * @pm8001_ha: our hba card information.
3792 * @ccb: the ccb information this request used.
3793 */
3794 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3795 struct pm8001_ccb_info *ccb)
3796 {
3797 struct sas_task *task = ccb->task;
3798 struct domain_device *dev = task->dev;
3799 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3800 struct ssp_ini_io_start_req ssp_cmd;
3801 u32 tag = ccb->ccb_tag;
3802 int ret;
3803 __le64 phys_addr;
3804 struct inbound_queue_table *circularQ;
3805 u32 opc = OPC_INB_SSPINIIOSTART;
3806 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3807 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3808 ssp_cmd.dir_m_tlr =
3809 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
3810 SAS 1.1 compatible TLR*/
3811 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3812 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
3813 ssp_cmd.tag = cpu_to_le32(tag);
3814 if (task->ssp_task.enable_first_burst)
3815 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
3816 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
3817 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
3818 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16);
3819 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3820
3821 /* fill in PRD (scatter/gather) table, if any */
3822 if (task->num_scatter > 1) {
3823 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
3824 phys_addr = cpu_to_le64(ccb->ccb_dma_handle +
3825 offsetof(struct pm8001_ccb_info, buf_prd[0]));
3826 ssp_cmd.addr_low = lower_32_bits(phys_addr);
3827 ssp_cmd.addr_high = upper_32_bits(phys_addr);
3828 ssp_cmd.esgl = cpu_to_le32(1<<31);
3829 } else if (task->num_scatter == 1) {
3830 __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter));
3831 ssp_cmd.addr_low = lower_32_bits(dma_addr);
3832 ssp_cmd.addr_high = upper_32_bits(dma_addr);
3833 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3834 ssp_cmd.esgl = 0;
3835 } else if (task->num_scatter == 0) {
3836 ssp_cmd.addr_low = 0;
3837 ssp_cmd.addr_high = 0;
3838 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3839 ssp_cmd.esgl = 0;
3840 }
3841 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd);
3842 return ret;
3843 }
3844
3845 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
3846 struct pm8001_ccb_info *ccb)
3847 {
3848 struct sas_task *task = ccb->task;
3849 struct domain_device *dev = task->dev;
3850 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
3851 u32 tag = ccb->ccb_tag;
3852 int ret;
3853 struct sata_start_req sata_cmd;
3854 u32 hdr_tag, ncg_tag = 0;
3855 __le64 phys_addr;
3856 u32 ATAP = 0x0;
3857 u32 dir;
3858 struct inbound_queue_table *circularQ;
3859 u32 opc = OPC_INB_SATA_HOST_OPSTART;
3860 memset(&sata_cmd, 0, sizeof(sata_cmd));
3861 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3862 if (task->data_dir == PCI_DMA_NONE) {
3863 ATAP = 0x04; /* no data*/
3864 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data \n"));
3865 } else if (likely(!task->ata_task.device_control_reg_update)) {
3866 if (task->ata_task.dma_xfer) {
3867 ATAP = 0x06; /* DMA */
3868 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA \n"));
3869 } else {
3870 ATAP = 0x05; /* PIO*/
3871 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO \n"));
3872 }
3873 if (task->ata_task.use_ncq &&
3874 dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
3875 ATAP = 0x07; /* FPDMA */
3876 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA \n"));
3877 }
3878 }
3879 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag))
3880 ncg_tag = hdr_tag;
3881 dir = data_dir_flags[task->data_dir] << 8;
3882 sata_cmd.tag = cpu_to_le32(tag);
3883 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
3884 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3885 sata_cmd.ncqtag_atap_dir_m =
3886 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
3887 sata_cmd.sata_fis = task->ata_task.fis;
3888 if (likely(!task->ata_task.device_control_reg_update))
3889 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
3890 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
3891 /* fill in PRD (scatter/gather) table, if any */
3892 if (task->num_scatter > 1) {
3893 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
3894 phys_addr = cpu_to_le64(ccb->ccb_dma_handle +
3895 offsetof(struct pm8001_ccb_info, buf_prd[0]));
3896 sata_cmd.addr_low = lower_32_bits(phys_addr);
3897 sata_cmd.addr_high = upper_32_bits(phys_addr);
3898 sata_cmd.esgl = cpu_to_le32(1 << 31);
3899 } else if (task->num_scatter == 1) {
3900 __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter));
3901 sata_cmd.addr_low = lower_32_bits(dma_addr);
3902 sata_cmd.addr_high = upper_32_bits(dma_addr);
3903 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3904 sata_cmd.esgl = 0;
3905 } else if (task->num_scatter == 0) {
3906 sata_cmd.addr_low = 0;
3907 sata_cmd.addr_high = 0;
3908 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3909 sata_cmd.esgl = 0;
3910 }
3911 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd);
3912 return ret;
3913 }
3914
3915 /**
3916 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
3917 * @pm8001_ha: our hba card information.
3918 * @num: the inbound queue number
3919 * @phy_id: the phy id which we wanted to start up.
3920 */
3921 static int
3922 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
3923 {
3924 struct phy_start_req payload;
3925 struct inbound_queue_table *circularQ;
3926 int ret;
3927 u32 tag = 0x01;
3928 u32 opcode = OPC_INB_PHYSTART;
3929 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3930 memset(&payload, 0, sizeof(payload));
3931 payload.tag = cpu_to_le32(tag);
3932 /*
3933 ** [0:7] PHY Identifier
3934 ** [8:11] link rate 1.5G, 3G, 6G
3935 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
3936 ** [14] 0b disable spin up hold; 1b enable spin up hold
3937 */
3938 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
3939 LINKMODE_AUTO | LINKRATE_15 |
3940 LINKRATE_30 | LINKRATE_60 | phy_id);
3941 payload.sas_identify.dev_type = SAS_END_DEV;
3942 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
3943 memcpy(payload.sas_identify.sas_addr,
3944 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
3945 payload.sas_identify.phy_id = phy_id;
3946 ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
3947 return ret;
3948 }
3949
3950 /**
3951 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
3952 * @pm8001_ha: our hba card information.
3953 * @num: the inbound queue number
3954 * @phy_id: the phy id which we wanted to start up.
3955 */
3956 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
3957 u8 phy_id)
3958 {
3959 struct phy_stop_req payload;
3960 struct inbound_queue_table *circularQ;
3961 int ret;
3962 u32 tag = 0x01;
3963 u32 opcode = OPC_INB_PHYSTOP;
3964 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3965 memset(&payload, 0, sizeof(payload));
3966 payload.tag = cpu_to_le32(tag);
3967 payload.phy_id = cpu_to_le32(phy_id);
3968 ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
3969 return ret;
3970 }
3971
3972 /**
3973 * see comments on mpi_reg_resp.
3974 */
3975 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
3976 struct pm8001_device *pm8001_dev, u32 flag)
3977 {
3978 struct reg_dev_req payload;
3979 u32 opc;
3980 u32 stp_sspsmp_sata = 0x4;
3981 struct inbound_queue_table *circularQ;
3982 u32 linkrate, phy_id;
3983 int rc, tag = 0xdeadbeef;
3984 struct pm8001_ccb_info *ccb;
3985 u8 retryFlag = 0x1;
3986 u16 firstBurstSize = 0;
3987 u16 ITNT = 2000;
3988 struct domain_device *dev = pm8001_dev->sas_device;
3989 struct domain_device *parent_dev = dev->parent;
3990 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3991
3992 memset(&payload, 0, sizeof(payload));
3993 rc = pm8001_tag_alloc(pm8001_ha, &tag);
3994 if (rc)
3995 return rc;
3996 ccb = &pm8001_ha->ccb_info[tag];
3997 ccb->device = pm8001_dev;
3998 ccb->ccb_tag = tag;
3999 payload.tag = cpu_to_le32(tag);
4000 if (flag == 1)
4001 stp_sspsmp_sata = 0x02; /*direct attached sata */
4002 else {
4003 if (pm8001_dev->dev_type == SATA_DEV)
4004 stp_sspsmp_sata = 0x00; /* stp*/
4005 else if (pm8001_dev->dev_type == SAS_END_DEV ||
4006 pm8001_dev->dev_type == EDGE_DEV ||
4007 pm8001_dev->dev_type == FANOUT_DEV)
4008 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4009 }
4010 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4011 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4012 else
4013 phy_id = pm8001_dev->attached_phy;
4014 opc = OPC_INB_REG_DEV;
4015 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4016 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4017 payload.phyid_portid =
4018 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4019 ((phy_id & 0x0F) << 4));
4020 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4021 ((linkrate & 0x0F) * 0x1000000) |
4022 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4023 payload.firstburstsize_ITNexustimeout =
4024 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4025 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4026 SAS_ADDR_SIZE);
4027 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4028 return rc;
4029 }
4030
4031 /**
4032 * see comments on mpi_reg_resp.
4033 */
4034 static int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4035 u32 device_id)
4036 {
4037 struct dereg_dev_req payload;
4038 u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4039 int ret;
4040 struct inbound_queue_table *circularQ;
4041
4042 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4043 memset(&payload, 0, sizeof(payload));
4044 payload.tag = 1;
4045 payload.device_id = cpu_to_le32(device_id);
4046 PM8001_MSG_DBG(pm8001_ha,
4047 pm8001_printk("unregister device device_id = %d\n", device_id));
4048 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4049 return ret;
4050 }
4051
4052 /**
4053 * pm8001_chip_phy_ctl_req - support the local phy operation
4054 * @pm8001_ha: our hba card information.
4055 * @num: the inbound queue number
4056 * @phy_id: the phy id which we wanted to operate
4057 * @phy_op:
4058 */
4059 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4060 u32 phyId, u32 phy_op)
4061 {
4062 struct local_phy_ctl_req payload;
4063 struct inbound_queue_table *circularQ;
4064 int ret;
4065 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4066 memset(&payload, 0, sizeof(payload));
4067 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4068 payload.tag = 1;
4069 payload.phyop_phyid =
4070 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4071 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4072 return ret;
4073 }
4074
4075 static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4076 {
4077 u32 value;
4078 #ifdef PM8001_USE_MSIX
4079 return 1;
4080 #endif
4081 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4082 if (value)
4083 return 1;
4084 return 0;
4085
4086 }
4087
4088 /**
4089 * pm8001_chip_isr - PM8001 isr handler.
4090 * @pm8001_ha: our hba card information.
4091 * @irq: irq number.
4092 * @stat: stat.
4093 */
4094 static irqreturn_t
4095 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha)
4096 {
4097 unsigned long flags;
4098 spin_lock_irqsave(&pm8001_ha->lock, flags);
4099 pm8001_chip_interrupt_disable(pm8001_ha);
4100 process_oq(pm8001_ha);
4101 pm8001_chip_interrupt_enable(pm8001_ha);
4102 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4103 return IRQ_HANDLED;
4104 }
4105
4106 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4107 u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4108 {
4109 struct task_abort_req task_abort;
4110 struct inbound_queue_table *circularQ;
4111 int ret;
4112 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4113 memset(&task_abort, 0, sizeof(task_abort));
4114 if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4115 task_abort.abort_all = 0;
4116 task_abort.device_id = cpu_to_le32(dev_id);
4117 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4118 task_abort.tag = cpu_to_le32(cmd_tag);
4119 } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4120 task_abort.abort_all = cpu_to_le32(1);
4121 task_abort.device_id = cpu_to_le32(dev_id);
4122 task_abort.tag = cpu_to_le32(cmd_tag);
4123 }
4124 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort);
4125 return ret;
4126 }
4127
4128 /**
4129 * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4130 * @task: the task we wanted to aborted.
4131 * @flag: the abort flag.
4132 */
4133 static int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4134 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4135 {
4136 u32 opc, device_id;
4137 int rc = TMF_RESP_FUNC_FAILED;
4138 PM8001_EH_DBG(pm8001_ha, pm8001_printk("cmd_tag = %x, abort task tag"
4139 " = %x", cmd_tag, task_tag));
4140 if (pm8001_dev->dev_type == SAS_END_DEV)
4141 opc = OPC_INB_SSP_ABORT;
4142 else if (pm8001_dev->dev_type == SATA_DEV)
4143 opc = OPC_INB_SATA_ABORT;
4144 else
4145 opc = OPC_INB_SMP_ABORT;/* SMP */
4146 device_id = pm8001_dev->device_id;
4147 rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4148 task_tag, cmd_tag);
4149 if (rc != TMF_RESP_FUNC_COMPLETE)
4150 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4151 return rc;
4152 }
4153
4154 /**
4155 * pm8001_chip_ssp_tm_req - built the task management command.
4156 * @pm8001_ha: our hba card information.
4157 * @ccb: the ccb information.
4158 * @tmf: task management function.
4159 */
4160 static int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4161 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4162 {
4163 struct sas_task *task = ccb->task;
4164 struct domain_device *dev = task->dev;
4165 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4166 u32 opc = OPC_INB_SSPINITMSTART;
4167 struct inbound_queue_table *circularQ;
4168 struct ssp_ini_tm_start_req sspTMCmd;
4169 int ret;
4170
4171 memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4172 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4173 sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4174 sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4175 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4176 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4177 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4178 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd);
4179 return ret;
4180 }
4181
4182 static int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4183 void *payload)
4184 {
4185 u32 opc = OPC_INB_GET_NVMD_DATA;
4186 u32 nvmd_type;
4187 int rc;
4188 u32 tag;
4189 struct pm8001_ccb_info *ccb;
4190 struct inbound_queue_table *circularQ;
4191 struct get_nvm_data_req nvmd_req;
4192 struct fw_control_ex *fw_control_context;
4193 struct pm8001_ioctl_payload *ioctl_payload = payload;
4194
4195 nvmd_type = ioctl_payload->minor_function;
4196 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4197 fw_control_context->usrAddr = (u8 *)&ioctl_payload->func_specific[0];
4198 fw_control_context->len = ioctl_payload->length;
4199 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4200 memset(&nvmd_req, 0, sizeof(nvmd_req));
4201 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4202 if (rc)
4203 return rc;
4204 ccb = &pm8001_ha->ccb_info[tag];
4205 ccb->ccb_tag = tag;
4206 ccb->fw_control_context = fw_control_context;
4207 nvmd_req.tag = cpu_to_le32(tag);
4208
4209 switch (nvmd_type) {
4210 case TWI_DEVICE: {
4211 u32 twi_addr, twi_page_size;
4212 twi_addr = 0xa8;
4213 twi_page_size = 2;
4214
4215 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4216 twi_page_size << 8 | TWI_DEVICE);
4217 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4218 nvmd_req.resp_addr_hi =
4219 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4220 nvmd_req.resp_addr_lo =
4221 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4222 break;
4223 }
4224 case C_SEEPROM: {
4225 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4226 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4227 nvmd_req.resp_addr_hi =
4228 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4229 nvmd_req.resp_addr_lo =
4230 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4231 break;
4232 }
4233 case VPD_FLASH: {
4234 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4235 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4236 nvmd_req.resp_addr_hi =
4237 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4238 nvmd_req.resp_addr_lo =
4239 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4240 break;
4241 }
4242 case EXPAN_ROM: {
4243 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4244 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4245 nvmd_req.resp_addr_hi =
4246 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4247 nvmd_req.resp_addr_lo =
4248 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4249 break;
4250 }
4251 default:
4252 break;
4253 }
4254 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4255 return rc;
4256 }
4257
4258 static int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4259 void *payload)
4260 {
4261 u32 opc = OPC_INB_SET_NVMD_DATA;
4262 u32 nvmd_type;
4263 int rc;
4264 u32 tag;
4265 struct pm8001_ccb_info *ccb;
4266 struct inbound_queue_table *circularQ;
4267 struct set_nvm_data_req nvmd_req;
4268 struct fw_control_ex *fw_control_context;
4269 struct pm8001_ioctl_payload *ioctl_payload = payload;
4270
4271 nvmd_type = ioctl_payload->minor_function;
4272 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4273 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4274 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4275 ioctl_payload->func_specific,
4276 ioctl_payload->length);
4277 memset(&nvmd_req, 0, sizeof(nvmd_req));
4278 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4279 if (rc)
4280 return rc;
4281 ccb = &pm8001_ha->ccb_info[tag];
4282 ccb->fw_control_context = fw_control_context;
4283 ccb->ccb_tag = tag;
4284 nvmd_req.tag = cpu_to_le32(tag);
4285 switch (nvmd_type) {
4286 case TWI_DEVICE: {
4287 u32 twi_addr, twi_page_size;
4288 twi_addr = 0xa8;
4289 twi_page_size = 2;
4290 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4291 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4292 twi_page_size << 8 | TWI_DEVICE);
4293 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4294 nvmd_req.resp_addr_hi =
4295 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4296 nvmd_req.resp_addr_lo =
4297 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4298 break;
4299 }
4300 case C_SEEPROM:
4301 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4302 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4303 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4304 nvmd_req.resp_addr_hi =
4305 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4306 nvmd_req.resp_addr_lo =
4307 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4308 break;
4309 case VPD_FLASH:
4310 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4311 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4312 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4313 nvmd_req.resp_addr_hi =
4314 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4315 nvmd_req.resp_addr_lo =
4316 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4317 break;
4318 case EXPAN_ROM:
4319 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4320 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4321 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4322 nvmd_req.resp_addr_hi =
4323 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4324 nvmd_req.resp_addr_lo =
4325 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4326 break;
4327 default:
4328 break;
4329 }
4330 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4331 return rc;
4332 }
4333
4334 /**
4335 * pm8001_chip_fw_flash_update_build - support the firmware update operation
4336 * @pm8001_ha: our hba card information.
4337 * @fw_flash_updata_info: firmware flash update param
4338 */
4339 static int
4340 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4341 void *fw_flash_updata_info, u32 tag)
4342 {
4343 struct fw_flash_Update_req payload;
4344 struct fw_flash_updata_info *info;
4345 struct inbound_queue_table *circularQ;
4346 int ret;
4347 u32 opc = OPC_INB_FW_FLASH_UPDATE;
4348
4349 memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4350 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4351 info = fw_flash_updata_info;
4352 payload.tag = cpu_to_le32(tag);
4353 payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4354 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4355 payload.total_image_len = cpu_to_le32(info->total_image_len);
4356 payload.len = info->sgl.im_len.len ;
4357 payload.sgl_addr_lo = lower_32_bits(info->sgl.addr);
4358 payload.sgl_addr_hi = upper_32_bits(info->sgl.addr);
4359 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4360 return ret;
4361 }
4362
4363 static int
4364 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4365 void *payload)
4366 {
4367 struct fw_flash_updata_info flash_update_info;
4368 struct fw_control_info *fw_control;
4369 struct fw_control_ex *fw_control_context;
4370 int rc;
4371 u32 tag;
4372 struct pm8001_ccb_info *ccb;
4373 void *buffer = NULL;
4374 dma_addr_t phys_addr;
4375 u32 phys_addr_hi;
4376 u32 phys_addr_lo;
4377 struct pm8001_ioctl_payload *ioctl_payload = payload;
4378
4379 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4380 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific[0];
4381 if (fw_control->len != 0) {
4382 if (pm8001_mem_alloc(pm8001_ha->pdev,
4383 (void **)&buffer,
4384 &phys_addr,
4385 &phys_addr_hi,
4386 &phys_addr_lo,
4387 fw_control->len, 0) != 0) {
4388 PM8001_FAIL_DBG(pm8001_ha,
4389 pm8001_printk("Mem alloc failure\n"));
4390 return -ENOMEM;
4391 }
4392 }
4393 memcpy(buffer, fw_control->buffer, fw_control->len);
4394 flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4395 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4396 flash_update_info.sgl.im_len.e = 0;
4397 flash_update_info.cur_image_offset = fw_control->offset;
4398 flash_update_info.cur_image_len = fw_control->len;
4399 flash_update_info.total_image_len = fw_control->size;
4400 fw_control_context->fw_control = fw_control;
4401 fw_control_context->virtAddr = buffer;
4402 fw_control_context->len = fw_control->len;
4403 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4404 if (rc)
4405 return rc;
4406 ccb = &pm8001_ha->ccb_info[tag];
4407 ccb->fw_control_context = fw_control_context;
4408 ccb->ccb_tag = tag;
4409 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4410 tag);
4411 return rc;
4412 }
4413
4414 static int
4415 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4416 struct pm8001_device *pm8001_dev, u32 state)
4417 {
4418 struct set_dev_state_req payload;
4419 struct inbound_queue_table *circularQ;
4420 struct pm8001_ccb_info *ccb;
4421 int rc;
4422 u32 tag;
4423 u32 opc = OPC_INB_SET_DEVICE_STATE;
4424 memset(&payload, 0, sizeof(payload));
4425 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4426 if (rc)
4427 return -1;
4428 ccb = &pm8001_ha->ccb_info[tag];
4429 ccb->ccb_tag = tag;
4430 ccb->device = pm8001_dev;
4431 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4432 payload.tag = cpu_to_le32(tag);
4433 payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4434 payload.nds = cpu_to_le32(state);
4435 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4436 return rc;
4437
4438 }
4439
4440 static int
4441 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4442 {
4443 struct sas_re_initialization_req payload;
4444 struct inbound_queue_table *circularQ;
4445 struct pm8001_ccb_info *ccb;
4446 int rc;
4447 u32 tag;
4448 u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4449 memset(&payload, 0, sizeof(payload));
4450 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4451 if (rc)
4452 return -1;
4453 ccb = &pm8001_ha->ccb_info[tag];
4454 ccb->ccb_tag = tag;
4455 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4456 payload.tag = cpu_to_le32(tag);
4457 payload.SSAHOLT = cpu_to_le32(0xd << 25);
4458 payload.sata_hol_tmo = cpu_to_le32(80);
4459 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
4460 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4461 return rc;
4462
4463 }
4464
4465 const struct pm8001_dispatch pm8001_8001_dispatch = {
4466 .name = "pmc8001",
4467 .chip_init = pm8001_chip_init,
4468 .chip_soft_rst = pm8001_chip_soft_rst,
4469 .chip_rst = pm8001_hw_chip_rst,
4470 .chip_iounmap = pm8001_chip_iounmap,
4471 .isr = pm8001_chip_isr,
4472 .is_our_interupt = pm8001_chip_is_our_interupt,
4473 .isr_process_oq = process_oq,
4474 .interrupt_enable = pm8001_chip_interrupt_enable,
4475 .interrupt_disable = pm8001_chip_interrupt_disable,
4476 .make_prd = pm8001_chip_make_sg,
4477 .smp_req = pm8001_chip_smp_req,
4478 .ssp_io_req = pm8001_chip_ssp_io_req,
4479 .sata_req = pm8001_chip_sata_req,
4480 .phy_start_req = pm8001_chip_phy_start_req,
4481 .phy_stop_req = pm8001_chip_phy_stop_req,
4482 .reg_dev_req = pm8001_chip_reg_dev_req,
4483 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4484 .phy_ctl_req = pm8001_chip_phy_ctl_req,
4485 .task_abort = pm8001_chip_abort_task,
4486 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4487 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4488 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4489 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4490 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4491 .sas_re_init_req = pm8001_chip_sas_re_initialization,
4492 };
4493
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree