2 * linux/arch/arm/mach-tegra/platsmp.c
4 * Copyright (C) 2002 ARM Ltd.
7 * Copyright (C) 2009 Palm
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/errno.h>
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/jiffies.h>
19 #include <linux/smp.h>
22 #include <asm/cacheflush.h>
23 #include <mach/hardware.h>
24 #include <asm/mach-types.h>
25 #include <asm/localtimer.h>
26 #include <asm/smp_scu.h>
28 #include <mach/iomap.h>
30 extern void tegra_secondary_startup(void);
32 static DEFINE_SPINLOCK(boot_lock
);
33 static void __iomem
*scu_base
= IO_ADDRESS(TEGRA_ARM_PERIF_BASE
);
35 #define EVP_CPU_RESET_VECTOR \
36 (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
37 #define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
38 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
39 #define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
40 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
42 void __cpuinit
platform_secondary_init(unsigned int cpu
)
47 * if any interrupts are already enabled for the primary
48 * core (e.g. timer irq), then they will not have been enabled
51 gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE
) + 0x100);
54 * Synchronise with the boot thread.
56 spin_lock(&boot_lock
);
57 spin_unlock(&boot_lock
);
60 int __cpuinit
boot_secondary(unsigned int cpu
, struct task_struct
*idle
)
62 unsigned long old_boot_vector
;
63 unsigned long boot_vector
;
64 unsigned long timeout
;
68 * set synchronisation state between this boot processor
69 * and the secondary one
71 spin_lock(&boot_lock
);
74 /* set the reset vector to point to the secondary_startup routine */
76 boot_vector
= virt_to_phys(tegra_secondary_startup
);
77 old_boot_vector
= readl(EVP_CPU_RESET_VECTOR
);
78 writel(boot_vector
, EVP_CPU_RESET_VECTOR
);
80 /* enable cpu clock on cpu1 */
81 reg
= readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX
);
82 writel(reg
& ~(1<<9), CLK_RST_CONTROLLER_CLK_CPU_CMPLX
);
84 reg
= (1<<13) | (1<<9) | (1<<5) | (1<<1);
85 writel(reg
, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR
);
91 writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE
) + 0x14);
93 timeout
= jiffies
+ (1 * HZ
);
94 while (time_before(jiffies
, timeout
)) {
95 if (readl(EVP_CPU_RESET_VECTOR
) != boot_vector
)
100 /* put the old boot vector back */
101 writel(old_boot_vector
, EVP_CPU_RESET_VECTOR
);
104 * now the secondary core is starting up let it run its
105 * calibrations, then wait for it to finish
107 spin_unlock(&boot_lock
);
113 * Initialise the CPU possible map early - this describes the CPUs
114 * which may be present or become present in the system.
116 void __init
smp_init_cpus(void)
118 unsigned int i
, ncores
= scu_get_core_count(scu_base
);
120 for (i
= 0; i
< ncores
; i
++)
121 cpu_set(i
, cpu_possible_map
);
124 void __init
smp_prepare_cpus(unsigned int max_cpus
)
126 unsigned int ncores
= scu_get_core_count(scu_base
);
127 unsigned int cpu
= smp_processor_id();
130 smp_store_cpu_info(cpu
);
133 * are we trying to boot more cores than exist?
135 if (max_cpus
> ncores
)
139 * Initialise the present map, which describes the set of CPUs
140 * actually populated at the present time.
142 for (i
= 0; i
< max_cpus
; i
++)
143 set_cpu_present(i
, true);
146 * Initialise the SCU if there are more than one CPU and let
147 * them know where to start. Note that, on modern versions of
148 * MILO, the "poke" doesn't actually do anything until each
149 * individual core is sent a soft interrupt to get it out of
153 percpu_timer_setup();
154 scu_enable(scu_base
);