1 /* linux/arch/arm/mach-s5pv310/platsmp.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
8 * Copyright (C) 2002 ARM Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/jiffies.h>
21 #include <linux/smp.h>
24 #include <asm/cacheflush.h>
25 #include <asm/localtimer.h>
26 #include <asm/smp_scu.h>
27 #include <asm/unified.h>
29 #include <mach/hardware.h>
30 #include <mach/regs-clock.h>
32 extern void s5pv310_secondary_startup(void);
35 * control for which core is the next to come out of the secondary
39 volatile int __cpuinitdata pen_release
= -1;
41 static void __iomem
*scu_base_addr(void)
43 return (void __iomem
*)(S5P_VA_SCU
);
46 static DEFINE_SPINLOCK(boot_lock
);
48 void __cpuinit
platform_secondary_init(unsigned int cpu
)
53 * if any interrupts are already enabled for the primary
54 * core (e.g. timer irq), then they will not have been enabled
57 gic_cpu_init(0, gic_cpu_base_addr
);
60 * let the primary processor know we're out of the
61 * pen, then head off into the C entry point
67 * Synchronise with the boot thread.
69 spin_lock(&boot_lock
);
70 spin_unlock(&boot_lock
);
73 int __cpuinit
boot_secondary(unsigned int cpu
, struct task_struct
*idle
)
75 unsigned long timeout
;
78 * Set synchronisation state between this boot processor
79 * and the secondary one
81 spin_lock(&boot_lock
);
84 * The secondary processor is waiting to be released from
85 * the holding pen - release it, then wait for it to flag
86 * that it has been released by resetting pen_release.
88 * Note that "pen_release" is the hardware CPU ID, whereas
89 * "cpu" is Linux's internal ID.
92 __cpuc_flush_dcache_area((void *)&pen_release
, sizeof(pen_release
));
93 outer_clean_range(__pa(&pen_release
), __pa(&pen_release
+ 1));
96 * Send the secondary CPU a soft interrupt, thereby causing
97 * the boot monitor to read the system wide flags register,
98 * and branch to the address found there.
100 smp_cross_call(cpumask_of(cpu
));
102 timeout
= jiffies
+ (1 * HZ
);
103 while (time_before(jiffies
, timeout
)) {
105 if (pen_release
== -1)
112 * now the secondary core is starting up let it run its
113 * calibrations, then wait for it to finish
115 spin_unlock(&boot_lock
);
117 return pen_release
!= -1 ? -ENOSYS
: 0;
121 * Initialise the CPU possible map early - this describes the CPUs
122 * which may be present or become present in the system.
125 void __init
smp_init_cpus(void)
127 void __iomem
*scu_base
= scu_base_addr();
128 unsigned int i
, ncores
;
130 ncores
= scu_base
? scu_get_core_count(scu_base
) : 1;
135 "S5PV310: strange CM count of 0? Default to 1\n");
140 if (ncores
> NR_CPUS
) {
142 "S5PV310: no. of cores (%d) greater than configured "
143 "maximum of %d - clipping\n",
148 for (i
= 0; i
< ncores
; i
++)
149 set_cpu_possible(i
, true);
152 void __init
smp_prepare_cpus(unsigned int max_cpus
)
154 unsigned int ncores
= num_possible_cpus();
155 unsigned int cpu
= smp_processor_id();
158 smp_store_cpu_info(cpu
);
160 /* are we trying to boot more cores than exist? */
161 if (max_cpus
> ncores
)
165 * Initialise the present map, which describes the set of CPUs
166 * actually populated at the present time.
168 for (i
= 0; i
< max_cpus
; i
++)
169 set_cpu_present(i
, true);
172 * Initialise the SCU if there are more than one CPU and let
173 * them know where to start.
177 * Enable the local timer or broadcast device for the
178 * boot CPU, but only if we have more than one CPU.
180 percpu_timer_setup();
182 scu_enable(scu_base_addr());
185 * Write the address of secondary startup into the
186 * system-wide flags register. The boot monitor waits
187 * until it receives a soft interrupt, and then the
188 * secondary CPU branches to this address.
190 __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup
)), S5P_VA_SYSRAM
);